1 //===-- NativeRegisterContextLinux_arm64.cpp --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #if defined(__arm64__) || defined(__aarch64__) 11 12 #include "NativeRegisterContextLinux_arm.h" 13 #include "NativeRegisterContextLinux_arm64.h" 14 15 // C Includes 16 // C++ Includes 17 18 // Other libraries and framework includes 19 #include "lldb/Core/DataBufferHeap.h" 20 #include "lldb/Core/Log.h" 21 #include "lldb/Core/RegisterValue.h" 22 #include "lldb/Host/common/NativeProcessProtocol.h" 23 #include "lldb/Utility/Error.h" 24 25 #include "Plugins/Process/Linux/NativeProcessLinux.h" 26 #include "Plugins/Process/Linux/Procfs.h" 27 #include "Plugins/Process/POSIX/ProcessPOSIXLog.h" 28 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" 29 30 // System includes - They have to be included after framework includes because 31 // they define some 32 // macros which collide with variable names in other modules 33 #include <sys/socket.h> 34 // NT_PRSTATUS and NT_FPREGSET definition 35 #include <elf.h> 36 // user_hwdebug_state definition 37 #include <asm/ptrace.h> 38 39 #define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize()) 40 41 using namespace lldb; 42 using namespace lldb_private; 43 using namespace lldb_private::process_linux; 44 45 // ARM64 general purpose registers. 46 static const uint32_t g_gpr_regnums_arm64[] = { 47 gpr_x0_arm64, gpr_x1_arm64, gpr_x2_arm64, gpr_x3_arm64, 48 gpr_x4_arm64, gpr_x5_arm64, gpr_x6_arm64, gpr_x7_arm64, 49 gpr_x8_arm64, gpr_x9_arm64, gpr_x10_arm64, gpr_x11_arm64, 50 gpr_x12_arm64, gpr_x13_arm64, gpr_x14_arm64, gpr_x15_arm64, 51 gpr_x16_arm64, gpr_x17_arm64, gpr_x18_arm64, gpr_x19_arm64, 52 gpr_x20_arm64, gpr_x21_arm64, gpr_x22_arm64, gpr_x23_arm64, 53 gpr_x24_arm64, gpr_x25_arm64, gpr_x26_arm64, gpr_x27_arm64, 54 gpr_x28_arm64, gpr_fp_arm64, gpr_lr_arm64, gpr_sp_arm64, 55 gpr_pc_arm64, gpr_cpsr_arm64, gpr_w0_arm64, gpr_w1_arm64, 56 gpr_w2_arm64, gpr_w3_arm64, gpr_w4_arm64, gpr_w5_arm64, 57 gpr_w6_arm64, gpr_w7_arm64, gpr_w8_arm64, gpr_w9_arm64, 58 gpr_w10_arm64, gpr_w11_arm64, gpr_w12_arm64, gpr_w13_arm64, 59 gpr_w14_arm64, gpr_w15_arm64, gpr_w16_arm64, gpr_w17_arm64, 60 gpr_w18_arm64, gpr_w19_arm64, gpr_w20_arm64, gpr_w21_arm64, 61 gpr_w22_arm64, gpr_w23_arm64, gpr_w24_arm64, gpr_w25_arm64, 62 gpr_w26_arm64, gpr_w27_arm64, gpr_w28_arm64, 63 LLDB_INVALID_REGNUM // register sets need to end with this flag 64 }; 65 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 66 1) == k_num_gpr_registers_arm64, 67 "g_gpr_regnums_arm64 has wrong number of register infos"); 68 69 // ARM64 floating point registers. 70 static const uint32_t g_fpu_regnums_arm64[] = { 71 fpu_v0_arm64, fpu_v1_arm64, fpu_v2_arm64, fpu_v3_arm64, 72 fpu_v4_arm64, fpu_v5_arm64, fpu_v6_arm64, fpu_v7_arm64, 73 fpu_v8_arm64, fpu_v9_arm64, fpu_v10_arm64, fpu_v11_arm64, 74 fpu_v12_arm64, fpu_v13_arm64, fpu_v14_arm64, fpu_v15_arm64, 75 fpu_v16_arm64, fpu_v17_arm64, fpu_v18_arm64, fpu_v19_arm64, 76 fpu_v20_arm64, fpu_v21_arm64, fpu_v22_arm64, fpu_v23_arm64, 77 fpu_v24_arm64, fpu_v25_arm64, fpu_v26_arm64, fpu_v27_arm64, 78 fpu_v28_arm64, fpu_v29_arm64, fpu_v30_arm64, fpu_v31_arm64, 79 fpu_s0_arm64, fpu_s1_arm64, fpu_s2_arm64, fpu_s3_arm64, 80 fpu_s4_arm64, fpu_s5_arm64, fpu_s6_arm64, fpu_s7_arm64, 81 fpu_s8_arm64, fpu_s9_arm64, fpu_s10_arm64, fpu_s11_arm64, 82 fpu_s12_arm64, fpu_s13_arm64, fpu_s14_arm64, fpu_s15_arm64, 83 fpu_s16_arm64, fpu_s17_arm64, fpu_s18_arm64, fpu_s19_arm64, 84 fpu_s20_arm64, fpu_s21_arm64, fpu_s22_arm64, fpu_s23_arm64, 85 fpu_s24_arm64, fpu_s25_arm64, fpu_s26_arm64, fpu_s27_arm64, 86 fpu_s28_arm64, fpu_s29_arm64, fpu_s30_arm64, fpu_s31_arm64, 87 88 fpu_d0_arm64, fpu_d1_arm64, fpu_d2_arm64, fpu_d3_arm64, 89 fpu_d4_arm64, fpu_d5_arm64, fpu_d6_arm64, fpu_d7_arm64, 90 fpu_d8_arm64, fpu_d9_arm64, fpu_d10_arm64, fpu_d11_arm64, 91 fpu_d12_arm64, fpu_d13_arm64, fpu_d14_arm64, fpu_d15_arm64, 92 fpu_d16_arm64, fpu_d17_arm64, fpu_d18_arm64, fpu_d19_arm64, 93 fpu_d20_arm64, fpu_d21_arm64, fpu_d22_arm64, fpu_d23_arm64, 94 fpu_d24_arm64, fpu_d25_arm64, fpu_d26_arm64, fpu_d27_arm64, 95 fpu_d28_arm64, fpu_d29_arm64, fpu_d30_arm64, fpu_d31_arm64, 96 fpu_fpsr_arm64, fpu_fpcr_arm64, 97 LLDB_INVALID_REGNUM // register sets need to end with this flag 98 }; 99 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 100 1) == k_num_fpr_registers_arm64, 101 "g_fpu_regnums_arm64 has wrong number of register infos"); 102 103 namespace { 104 // Number of register sets provided by this context. 105 enum { k_num_register_sets = 2 }; 106 } 107 108 // Register sets for ARM64. 109 static const RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 110 {"General Purpose Registers", "gpr", k_num_gpr_registers_arm64, 111 g_gpr_regnums_arm64}, 112 {"Floating Point Registers", "fpu", k_num_fpr_registers_arm64, 113 g_fpu_regnums_arm64}}; 114 115 NativeRegisterContextLinux * 116 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux( 117 const ArchSpec &target_arch, NativeThreadProtocol &native_thread, 118 uint32_t concrete_frame_idx) { 119 switch (target_arch.GetMachine()) { 120 case llvm::Triple::arm: 121 return new NativeRegisterContextLinux_arm(target_arch, native_thread, 122 concrete_frame_idx); 123 case llvm::Triple::aarch64: 124 return new NativeRegisterContextLinux_arm64(target_arch, native_thread, 125 concrete_frame_idx); 126 default: 127 llvm_unreachable("have no register context for architecture"); 128 } 129 } 130 131 NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64( 132 const ArchSpec &target_arch, NativeThreadProtocol &native_thread, 133 uint32_t concrete_frame_idx) 134 : NativeRegisterContextLinux(native_thread, concrete_frame_idx, 135 new RegisterInfoPOSIX_arm64(target_arch)) { 136 switch (target_arch.GetMachine()) { 137 case llvm::Triple::aarch64: 138 m_reg_info.num_registers = k_num_registers_arm64; 139 m_reg_info.num_gpr_registers = k_num_gpr_registers_arm64; 140 m_reg_info.num_fpr_registers = k_num_fpr_registers_arm64; 141 m_reg_info.last_gpr = k_last_gpr_arm64; 142 m_reg_info.first_fpr = k_first_fpr_arm64; 143 m_reg_info.last_fpr = k_last_fpr_arm64; 144 m_reg_info.first_fpr_v = fpu_v0_arm64; 145 m_reg_info.last_fpr_v = fpu_v31_arm64; 146 m_reg_info.gpr_flags = gpr_cpsr_arm64; 147 break; 148 default: 149 llvm_unreachable("Unhandled target architecture."); 150 break; 151 } 152 153 ::memset(&m_fpr, 0, sizeof(m_fpr)); 154 ::memset(&m_gpr_arm64, 0, sizeof(m_gpr_arm64)); 155 ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs)); 156 ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs)); 157 158 // 16 is just a maximum value, query hardware for actual watchpoint count 159 m_max_hwp_supported = 16; 160 m_max_hbp_supported = 16; 161 m_refresh_hwdebug_info = true; 162 } 163 164 uint32_t NativeRegisterContextLinux_arm64::GetRegisterSetCount() const { 165 return k_num_register_sets; 166 } 167 168 const RegisterSet * 169 NativeRegisterContextLinux_arm64::GetRegisterSet(uint32_t set_index) const { 170 if (set_index < k_num_register_sets) 171 return &g_reg_sets_arm64[set_index]; 172 173 return nullptr; 174 } 175 176 uint32_t NativeRegisterContextLinux_arm64::GetUserRegisterCount() const { 177 uint32_t count = 0; 178 for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index) 179 count += g_reg_sets_arm64[set_index].num_registers; 180 return count; 181 } 182 183 Error NativeRegisterContextLinux_arm64::ReadRegister( 184 const RegisterInfo *reg_info, RegisterValue ®_value) { 185 Error error; 186 187 if (!reg_info) { 188 error.SetErrorString("reg_info NULL"); 189 return error; 190 } 191 192 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; 193 194 if (IsFPR(reg)) { 195 error = ReadFPR(); 196 if (error.Fail()) 197 return error; 198 } else { 199 uint32_t full_reg = reg; 200 bool is_subreg = reg_info->invalidate_regs && 201 (reg_info->invalidate_regs[0] != LLDB_INVALID_REGNUM); 202 203 if (is_subreg) { 204 // Read the full aligned 64-bit register. 205 full_reg = reg_info->invalidate_regs[0]; 206 } 207 208 error = ReadRegisterRaw(full_reg, reg_value); 209 210 if (error.Success()) { 211 // If our read was not aligned (for ah,bh,ch,dh), shift our returned value 212 // one byte to the right. 213 if (is_subreg && (reg_info->byte_offset & 0x1)) 214 reg_value.SetUInt64(reg_value.GetAsUInt64() >> 8); 215 216 // If our return byte size was greater than the return value reg size, 217 // then 218 // use the type specified by reg_info rather than the uint64_t default 219 if (reg_value.GetByteSize() > reg_info->byte_size) 220 reg_value.SetType(reg_info); 221 } 222 return error; 223 } 224 225 // Get pointer to m_fpr variable and set the data from it. 226 uint32_t fpr_offset = CalculateFprOffset(reg_info); 227 assert(fpr_offset < sizeof m_fpr); 228 uint8_t *src = (uint8_t *)&m_fpr + fpr_offset; 229 reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size, 230 eByteOrderLittle, error); 231 232 return error; 233 } 234 235 Error NativeRegisterContextLinux_arm64::WriteRegister( 236 const RegisterInfo *reg_info, const RegisterValue ®_value) { 237 if (!reg_info) 238 return Error("reg_info NULL"); 239 240 const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB]; 241 if (reg_index == LLDB_INVALID_REGNUM) 242 return Error("no lldb regnum for %s", reg_info && reg_info->name 243 ? reg_info->name 244 : "<unknown register>"); 245 246 if (IsGPR(reg_index)) 247 return WriteRegisterRaw(reg_index, reg_value); 248 249 if (IsFPR(reg_index)) { 250 // Get pointer to m_fpr variable and set the data to it. 251 uint32_t fpr_offset = CalculateFprOffset(reg_info); 252 assert(fpr_offset < sizeof m_fpr); 253 uint8_t *dst = (uint8_t *)&m_fpr + fpr_offset; 254 switch (reg_info->byte_size) { 255 case 2: 256 *(uint16_t *)dst = reg_value.GetAsUInt16(); 257 break; 258 case 4: 259 *(uint32_t *)dst = reg_value.GetAsUInt32(); 260 break; 261 case 8: 262 *(uint64_t *)dst = reg_value.GetAsUInt64(); 263 break; 264 default: 265 assert(false && "Unhandled data size."); 266 return Error("unhandled register data size %" PRIu32, 267 reg_info->byte_size); 268 } 269 270 Error error = WriteFPR(); 271 if (error.Fail()) 272 return error; 273 274 return Error(); 275 } 276 277 return Error("failed - register wasn't recognized to be a GPR or an FPR, " 278 "write strategy unknown"); 279 } 280 281 Error NativeRegisterContextLinux_arm64::ReadAllRegisterValues( 282 lldb::DataBufferSP &data_sp) { 283 Error error; 284 285 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 286 if (!data_sp) 287 return Error("failed to allocate DataBufferHeap instance of size %" PRIu64, 288 REG_CONTEXT_SIZE); 289 290 error = ReadGPR(); 291 if (error.Fail()) 292 return error; 293 294 error = ReadFPR(); 295 if (error.Fail()) 296 return error; 297 298 uint8_t *dst = data_sp->GetBytes(); 299 if (dst == nullptr) { 300 error.SetErrorStringWithFormat("DataBufferHeap instance of size %" PRIu64 301 " returned a null pointer", 302 REG_CONTEXT_SIZE); 303 return error; 304 } 305 306 ::memcpy(dst, &m_gpr_arm64, GetGPRSize()); 307 dst += GetGPRSize(); 308 ::memcpy(dst, &m_fpr, sizeof(m_fpr)); 309 310 return error; 311 } 312 313 Error NativeRegisterContextLinux_arm64::WriteAllRegisterValues( 314 const lldb::DataBufferSP &data_sp) { 315 Error error; 316 317 if (!data_sp) { 318 error.SetErrorStringWithFormat( 319 "NativeRegisterContextLinux_x86_64::%s invalid data_sp provided", 320 __FUNCTION__); 321 return error; 322 } 323 324 if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) { 325 error.SetErrorStringWithFormat( 326 "NativeRegisterContextLinux_x86_64::%s data_sp contained mismatched " 327 "data size, expected %" PRIu64 ", actual %" PRIu64, 328 __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize()); 329 return error; 330 } 331 332 uint8_t *src = data_sp->GetBytes(); 333 if (src == nullptr) { 334 error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s " 335 "DataBuffer::GetBytes() returned a null " 336 "pointer", 337 __FUNCTION__); 338 return error; 339 } 340 ::memcpy(&m_gpr_arm64, src, GetRegisterInfoInterface().GetGPRSize()); 341 342 error = WriteGPR(); 343 if (error.Fail()) 344 return error; 345 346 src += GetRegisterInfoInterface().GetGPRSize(); 347 ::memcpy(&m_fpr, src, sizeof(m_fpr)); 348 349 error = WriteFPR(); 350 if (error.Fail()) 351 return error; 352 353 return error; 354 } 355 356 bool NativeRegisterContextLinux_arm64::IsGPR(unsigned reg) const { 357 return reg <= m_reg_info.last_gpr; // GPR's come first. 358 } 359 360 bool NativeRegisterContextLinux_arm64::IsFPR(unsigned reg) const { 361 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr); 362 } 363 364 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareBreakpoints() { 365 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 366 367 if (log) 368 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 369 370 Error error; 371 372 // Read hardware breakpoint and watchpoint information. 373 error = ReadHardwareDebugInfo(); 374 375 if (error.Fail()) 376 return 0; 377 378 return m_max_hbp_supported; 379 } 380 381 uint32_t 382 NativeRegisterContextLinux_arm64::SetHardwareBreakpoint(lldb::addr_t addr, 383 size_t size) { 384 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 385 LLDB_LOG(log, "addr: {0:x}, size: {1:x}", addr, size); 386 387 // Read hardware breakpoint and watchpoint information. 388 Error error = ReadHardwareDebugInfo(); 389 390 if (error.Fail()) 391 return LLDB_INVALID_INDEX32; 392 393 uint32_t control_value = 0, bp_index = 0; 394 395 // Check if size has a valid hardware breakpoint length. 396 if (size != 4) 397 return LLDB_INVALID_INDEX32; // Invalid size for a AArch64 hardware 398 // breakpoint 399 400 // Check 4-byte alignment for hardware breakpoint target address. 401 if (addr & 0x03) 402 return LLDB_INVALID_INDEX32; // Invalid address, should be 4-byte aligned. 403 404 // Setup control value 405 control_value = 0; 406 control_value |= ((1 << size) - 1) << 5; 407 control_value |= (2 << 1) | 1; 408 409 // Iterate over stored breakpoints and find a free bp_index 410 bp_index = LLDB_INVALID_INDEX32; 411 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 412 if ((m_hbr_regs[i].control & 1) == 0) { 413 bp_index = i; // Mark last free slot 414 } else if (m_hbr_regs[i].address == addr) { 415 return LLDB_INVALID_INDEX32; // We do not support duplicate breakpoints. 416 } 417 } 418 419 if (bp_index == LLDB_INVALID_INDEX32) 420 return LLDB_INVALID_INDEX32; 421 422 // Update breakpoint in local cache 423 m_hbr_regs[bp_index].real_addr = addr; 424 m_hbr_regs[bp_index].address = addr; 425 m_hbr_regs[bp_index].control = control_value; 426 427 // PTRACE call to set corresponding hardware breakpoint register. 428 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 429 430 if (error.Fail()) { 431 m_hbr_regs[bp_index].address = 0; 432 m_hbr_regs[bp_index].control &= ~1; 433 434 return LLDB_INVALID_INDEX32; 435 } 436 437 return bp_index; 438 } 439 440 bool NativeRegisterContextLinux_arm64::ClearHardwareBreakpoint( 441 uint32_t hw_idx) { 442 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 443 LLDB_LOG(log, "hw_idx: {0}", hw_idx); 444 445 // Read hardware breakpoint and watchpoint information. 446 Error error = ReadHardwareDebugInfo(); 447 448 if (error.Fail()) 449 return false; 450 451 if (hw_idx >= m_max_hbp_supported) 452 return false; 453 454 // Create a backup we can revert to in case of failure. 455 lldb::addr_t tempAddr = m_hbr_regs[hw_idx].address; 456 uint32_t tempControl = m_hbr_regs[hw_idx].control; 457 458 m_hbr_regs[hw_idx].control &= ~1; 459 m_hbr_regs[hw_idx].address = 0; 460 461 // PTRACE call to clear corresponding hardware breakpoint register. 462 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 463 464 if (error.Fail()) { 465 m_hbr_regs[hw_idx].control = tempControl; 466 m_hbr_regs[hw_idx].address = tempAddr; 467 468 return false; 469 } 470 471 return true; 472 } 473 474 Error NativeRegisterContextLinux_arm64::GetHardwareBreakHitIndex( 475 uint32_t &bp_index, lldb::addr_t trap_addr) { 476 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 477 478 if (log) 479 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 480 481 lldb::addr_t break_addr; 482 483 for (bp_index = 0; bp_index < m_max_hbp_supported; ++bp_index) { 484 break_addr = m_hbr_regs[bp_index].address; 485 486 if ((m_hbr_regs[bp_index].control & 0x1) && (trap_addr == break_addr)) { 487 m_hbr_regs[bp_index].hit_addr = trap_addr; 488 return Error(); 489 } 490 } 491 492 bp_index = LLDB_INVALID_INDEX32; 493 return Error(); 494 } 495 496 Error NativeRegisterContextLinux_arm64::ClearAllHardwareBreakpoints() { 497 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 498 499 if (log) 500 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 501 502 Error error; 503 504 // Read hardware breakpoint and watchpoint information. 505 error = ReadHardwareDebugInfo(); 506 507 if (error.Fail()) 508 return error; 509 510 lldb::addr_t tempAddr = 0; 511 uint32_t tempControl = 0; 512 513 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 514 if (m_hbr_regs[i].control & 0x01) { 515 // Create a backup we can revert to in case of failure. 516 tempAddr = m_hbr_regs[i].address; 517 tempControl = m_hbr_regs[i].control; 518 519 // Clear watchpoints in local cache 520 m_hbr_regs[i].control &= ~1; 521 m_hbr_regs[i].address = 0; 522 523 // Ptrace call to update hardware debug registers 524 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 525 526 if (error.Fail()) { 527 m_hbr_regs[i].control = tempControl; 528 m_hbr_regs[i].address = tempAddr; 529 530 return error; 531 } 532 } 533 } 534 535 return Error(); 536 } 537 538 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareWatchpoints() { 539 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 540 541 // Read hardware breakpoint and watchpoint information. 542 Error error = ReadHardwareDebugInfo(); 543 544 if (error.Fail()) 545 return 0; 546 547 LLDB_LOG(log, "{0}", m_max_hwp_supported); 548 return m_max_hwp_supported; 549 } 550 551 uint32_t NativeRegisterContextLinux_arm64::SetHardwareWatchpoint( 552 lldb::addr_t addr, size_t size, uint32_t watch_flags) { 553 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 554 LLDB_LOG(log, "addr: {0:x}, size: {1:x} watch_flags: {2:x}", addr, size, 555 watch_flags); 556 557 // Read hardware breakpoint and watchpoint information. 558 Error error = ReadHardwareDebugInfo(); 559 560 if (error.Fail()) 561 return LLDB_INVALID_INDEX32; 562 563 uint32_t control_value = 0, wp_index = 0; 564 lldb::addr_t real_addr = addr; 565 566 // Check if we are setting watchpoint other than read/write/access 567 // Also update watchpoint flag to match AArch64 write-read bit configuration. 568 switch (watch_flags) { 569 case 1: 570 watch_flags = 2; 571 break; 572 case 2: 573 watch_flags = 1; 574 break; 575 case 3: 576 break; 577 default: 578 return LLDB_INVALID_INDEX32; 579 } 580 581 // Check if size has a valid hardware watchpoint length. 582 if (size != 1 && size != 2 && size != 4 && size != 8) 583 return LLDB_INVALID_INDEX32; 584 585 // Check 8-byte alignment for hardware watchpoint target address. 586 // Below is a hack to recalculate address and size in order to 587 // make sure we can watch non 8-byte alligned addresses as well. 588 if (addr & 0x07) { 589 uint8_t watch_mask = (addr & 0x07) + size; 590 591 if (watch_mask > 0x08) 592 return LLDB_INVALID_INDEX32; 593 else if (watch_mask <= 0x02) 594 size = 2; 595 else if (watch_mask <= 0x04) 596 size = 4; 597 else 598 size = 8; 599 600 addr = addr & (~0x07); 601 } 602 603 // Setup control value 604 control_value = watch_flags << 3; 605 control_value |= ((1 << size) - 1) << 5; 606 control_value |= (2 << 1) | 1; 607 608 // Iterate over stored watchpoints and find a free wp_index 609 wp_index = LLDB_INVALID_INDEX32; 610 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 611 if ((m_hwp_regs[i].control & 1) == 0) { 612 wp_index = i; // Mark last free slot 613 } else if (m_hwp_regs[i].address == addr) { 614 return LLDB_INVALID_INDEX32; // We do not support duplicate watchpoints. 615 } 616 } 617 618 if (wp_index == LLDB_INVALID_INDEX32) 619 return LLDB_INVALID_INDEX32; 620 621 // Update watchpoint in local cache 622 m_hwp_regs[wp_index].real_addr = real_addr; 623 m_hwp_regs[wp_index].address = addr; 624 m_hwp_regs[wp_index].control = control_value; 625 626 // PTRACE call to set corresponding watchpoint register. 627 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 628 629 if (error.Fail()) { 630 m_hwp_regs[wp_index].address = 0; 631 m_hwp_regs[wp_index].control &= ~1; 632 633 return LLDB_INVALID_INDEX32; 634 } 635 636 return wp_index; 637 } 638 639 bool NativeRegisterContextLinux_arm64::ClearHardwareWatchpoint( 640 uint32_t wp_index) { 641 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 642 LLDB_LOG(log, "wp_index: {0}", wp_index); 643 644 // Read hardware breakpoint and watchpoint information. 645 Error error = ReadHardwareDebugInfo(); 646 647 if (error.Fail()) 648 return false; 649 650 if (wp_index >= m_max_hwp_supported) 651 return false; 652 653 // Create a backup we can revert to in case of failure. 654 lldb::addr_t tempAddr = m_hwp_regs[wp_index].address; 655 uint32_t tempControl = m_hwp_regs[wp_index].control; 656 657 // Update watchpoint in local cache 658 m_hwp_regs[wp_index].control &= ~1; 659 m_hwp_regs[wp_index].address = 0; 660 661 // Ptrace call to update hardware debug registers 662 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 663 664 if (error.Fail()) { 665 m_hwp_regs[wp_index].control = tempControl; 666 m_hwp_regs[wp_index].address = tempAddr; 667 668 return false; 669 } 670 671 return true; 672 } 673 674 Error NativeRegisterContextLinux_arm64::ClearAllHardwareWatchpoints() { 675 // Read hardware breakpoint and watchpoint information. 676 Error error = ReadHardwareDebugInfo(); 677 678 if (error.Fail()) 679 return error; 680 681 lldb::addr_t tempAddr = 0; 682 uint32_t tempControl = 0, tempRefCount = 0; 683 684 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 685 if (m_hwp_regs[i].control & 0x01) { 686 // Create a backup we can revert to in case of failure. 687 tempAddr = m_hwp_regs[i].address; 688 tempControl = m_hwp_regs[i].control; 689 690 // Clear watchpoints in local cache 691 m_hwp_regs[i].control &= ~1; 692 m_hwp_regs[i].address = 0; 693 694 // Ptrace call to update hardware debug registers 695 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 696 697 if (error.Fail()) { 698 m_hwp_regs[i].control = tempControl; 699 m_hwp_regs[i].address = tempAddr; 700 701 return error; 702 } 703 } 704 } 705 706 return Error(); 707 } 708 709 uint32_t 710 NativeRegisterContextLinux_arm64::GetWatchpointSize(uint32_t wp_index) { 711 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 712 LLDB_LOG(log, "wp_index: {0}", wp_index); 713 714 switch ((m_hwp_regs[wp_index].control >> 5) & 0xff) { 715 case 0x01: 716 return 1; 717 case 0x03: 718 return 2; 719 case 0x0f: 720 return 4; 721 case 0xff: 722 return 8; 723 default: 724 return 0; 725 } 726 } 727 bool NativeRegisterContextLinux_arm64::WatchpointIsEnabled(uint32_t wp_index) { 728 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 729 LLDB_LOG(log, "wp_index: {0}", wp_index); 730 731 if ((m_hwp_regs[wp_index].control & 0x1) == 0x1) 732 return true; 733 else 734 return false; 735 } 736 737 Error NativeRegisterContextLinux_arm64::GetWatchpointHitIndex( 738 uint32_t &wp_index, lldb::addr_t trap_addr) { 739 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 740 LLDB_LOG(log, "wp_index: {0}, trap_addr: {1:x}", wp_index, trap_addr); 741 742 uint32_t watch_size; 743 lldb::addr_t watch_addr; 744 745 for (wp_index = 0; wp_index < m_max_hwp_supported; ++wp_index) { 746 watch_size = GetWatchpointSize(wp_index); 747 watch_addr = m_hwp_regs[wp_index].address; 748 749 if (WatchpointIsEnabled(wp_index) && trap_addr >= watch_addr && 750 trap_addr < watch_addr + watch_size) { 751 m_hwp_regs[wp_index].hit_addr = trap_addr; 752 return Error(); 753 } 754 } 755 756 wp_index = LLDB_INVALID_INDEX32; 757 return Error(); 758 } 759 760 lldb::addr_t 761 NativeRegisterContextLinux_arm64::GetWatchpointAddress(uint32_t wp_index) { 762 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 763 LLDB_LOG(log, "wp_index: {0}", wp_index); 764 765 if (wp_index >= m_max_hwp_supported) 766 return LLDB_INVALID_ADDRESS; 767 768 if (WatchpointIsEnabled(wp_index)) 769 return m_hwp_regs[wp_index].real_addr; 770 else 771 return LLDB_INVALID_ADDRESS; 772 } 773 774 lldb::addr_t 775 NativeRegisterContextLinux_arm64::GetWatchpointHitAddress(uint32_t wp_index) { 776 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 777 LLDB_LOG(log, "wp_index: {0}", wp_index); 778 779 if (wp_index >= m_max_hwp_supported) 780 return LLDB_INVALID_ADDRESS; 781 782 if (WatchpointIsEnabled(wp_index)) 783 return m_hwp_regs[wp_index].hit_addr; 784 else 785 return LLDB_INVALID_ADDRESS; 786 } 787 788 Error NativeRegisterContextLinux_arm64::ReadHardwareDebugInfo() { 789 if (!m_refresh_hwdebug_info) { 790 return Error(); 791 } 792 793 ::pid_t tid = m_thread.GetID(); 794 795 int regset = NT_ARM_HW_WATCH; 796 struct iovec ioVec; 797 struct user_hwdebug_state dreg_state; 798 Error error; 799 800 ioVec.iov_base = &dreg_state; 801 ioVec.iov_len = sizeof(dreg_state); 802 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 803 &ioVec, ioVec.iov_len); 804 805 if (error.Fail()) 806 return error; 807 808 m_max_hwp_supported = dreg_state.dbg_info & 0xff; 809 810 regset = NT_ARM_HW_BREAK; 811 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 812 &ioVec, ioVec.iov_len); 813 814 if (error.Fail()) 815 return error; 816 817 m_max_hbp_supported = dreg_state.dbg_info & 0xff; 818 m_refresh_hwdebug_info = false; 819 820 return error; 821 } 822 823 Error NativeRegisterContextLinux_arm64::WriteHardwareDebugRegs(int hwbType) { 824 struct iovec ioVec; 825 struct user_hwdebug_state dreg_state; 826 Error error; 827 828 memset(&dreg_state, 0, sizeof(dreg_state)); 829 ioVec.iov_base = &dreg_state; 830 831 if (hwbType == eDREGTypeWATCH) { 832 hwbType = NT_ARM_HW_WATCH; 833 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 834 (sizeof(dreg_state.dbg_regs[0]) * m_max_hwp_supported); 835 836 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 837 dreg_state.dbg_regs[i].addr = m_hwp_regs[i].address; 838 dreg_state.dbg_regs[i].ctrl = m_hwp_regs[i].control; 839 } 840 } else { 841 hwbType = NT_ARM_HW_BREAK; 842 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 843 (sizeof(dreg_state.dbg_regs[0]) * m_max_hbp_supported); 844 845 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 846 dreg_state.dbg_regs[i].addr = m_hbr_regs[i].address; 847 dreg_state.dbg_regs[i].ctrl = m_hbr_regs[i].control; 848 } 849 } 850 851 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 852 &hwbType, &ioVec, ioVec.iov_len); 853 } 854 855 Error NativeRegisterContextLinux_arm64::DoReadRegisterValue( 856 uint32_t offset, const char *reg_name, uint32_t size, 857 RegisterValue &value) { 858 Error error; 859 if (offset > sizeof(struct user_pt_regs)) { 860 uintptr_t offset = offset - sizeof(struct user_pt_regs); 861 if (offset > sizeof(struct user_fpsimd_state)) { 862 error.SetErrorString("invalid offset value"); 863 return error; 864 } 865 elf_fpregset_t regs; 866 int regset = NT_FPREGSET; 867 struct iovec ioVec; 868 869 ioVec.iov_base = ®s; 870 ioVec.iov_len = sizeof regs; 871 error = NativeProcessLinux::PtraceWrapper( 872 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 873 if (error.Success()) { 874 ArchSpec arch; 875 if (m_thread.GetProcess()->GetArchitecture(arch)) 876 value.SetBytes((void *)(((unsigned char *)(®s)) + offset), 16, 877 arch.GetByteOrder()); 878 else 879 error.SetErrorString("failed to get architecture"); 880 } 881 } else { 882 elf_gregset_t regs; 883 int regset = NT_PRSTATUS; 884 struct iovec ioVec; 885 886 ioVec.iov_base = ®s; 887 ioVec.iov_len = sizeof regs; 888 error = NativeProcessLinux::PtraceWrapper( 889 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 890 if (error.Success()) { 891 ArchSpec arch; 892 if (m_thread.GetProcess()->GetArchitecture(arch)) 893 value.SetBytes((void *)(((unsigned char *)(regs)) + offset), 8, 894 arch.GetByteOrder()); 895 else 896 error.SetErrorString("failed to get architecture"); 897 } 898 } 899 return error; 900 } 901 902 Error NativeRegisterContextLinux_arm64::DoWriteRegisterValue( 903 uint32_t offset, const char *reg_name, const RegisterValue &value) { 904 Error error; 905 ::pid_t tid = m_thread.GetID(); 906 if (offset > sizeof(struct user_pt_regs)) { 907 uintptr_t offset = offset - sizeof(struct user_pt_regs); 908 if (offset > sizeof(struct user_fpsimd_state)) { 909 error.SetErrorString("invalid offset value"); 910 return error; 911 } 912 elf_fpregset_t regs; 913 int regset = NT_FPREGSET; 914 struct iovec ioVec; 915 916 ioVec.iov_base = ®s; 917 ioVec.iov_len = sizeof regs; 918 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 919 &ioVec, sizeof regs); 920 921 if (error.Success()) { 922 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 923 16); 924 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 925 &ioVec, sizeof regs); 926 } 927 } else { 928 elf_gregset_t regs; 929 int regset = NT_PRSTATUS; 930 struct iovec ioVec; 931 932 ioVec.iov_base = ®s; 933 ioVec.iov_len = sizeof regs; 934 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 935 &ioVec, sizeof regs); 936 if (error.Success()) { 937 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 938 8); 939 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 940 &ioVec, sizeof regs); 941 } 942 } 943 return error; 944 } 945 946 Error NativeRegisterContextLinux_arm64::DoReadGPR(void *buf, size_t buf_size) { 947 int regset = NT_PRSTATUS; 948 struct iovec ioVec; 949 Error error; 950 951 ioVec.iov_base = buf; 952 ioVec.iov_len = buf_size; 953 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 954 ®set, &ioVec, buf_size); 955 } 956 957 Error NativeRegisterContextLinux_arm64::DoWriteGPR(void *buf, size_t buf_size) { 958 int regset = NT_PRSTATUS; 959 struct iovec ioVec; 960 Error error; 961 962 ioVec.iov_base = buf; 963 ioVec.iov_len = buf_size; 964 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 965 ®set, &ioVec, buf_size); 966 } 967 968 Error NativeRegisterContextLinux_arm64::DoReadFPR(void *buf, size_t buf_size) { 969 int regset = NT_FPREGSET; 970 struct iovec ioVec; 971 Error error; 972 973 ioVec.iov_base = buf; 974 ioVec.iov_len = buf_size; 975 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 976 ®set, &ioVec, buf_size); 977 } 978 979 Error NativeRegisterContextLinux_arm64::DoWriteFPR(void *buf, size_t buf_size) { 980 int regset = NT_FPREGSET; 981 struct iovec ioVec; 982 Error error; 983 984 ioVec.iov_base = buf; 985 ioVec.iov_len = buf_size; 986 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 987 ®set, &ioVec, buf_size); 988 } 989 990 uint32_t NativeRegisterContextLinux_arm64::CalculateFprOffset( 991 const RegisterInfo *reg_info) const { 992 return reg_info->byte_offset - 993 GetRegisterInfoAtIndex(m_reg_info.first_fpr)->byte_offset; 994 } 995 996 #endif // defined (__arm64__) || defined (__aarch64__) 997