1 //===-- NativeRegisterContextLinux_arm64.cpp --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #if defined(__arm64__) || defined(__aarch64__) 11 12 #include "NativeRegisterContextLinux_arm.h" 13 #include "NativeRegisterContextLinux_arm64.h" 14 15 // C Includes 16 // C++ Includes 17 18 // Other libraries and framework includes 19 #include "lldb/Core/RegisterValue.h" 20 #include "lldb/Host/common/NativeProcessProtocol.h" 21 #include "lldb/Utility/DataBufferHeap.h" 22 #include "lldb/Utility/Log.h" 23 #include "lldb/Utility/Status.h" 24 25 #include "Plugins/Process/Linux/NativeProcessLinux.h" 26 #include "Plugins/Process/Linux/Procfs.h" 27 #include "Plugins/Process/POSIX/ProcessPOSIXLog.h" 28 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" 29 30 // System includes - They have to be included after framework includes because 31 // they define some 32 // macros which collide with variable names in other modules 33 #include <sys/socket.h> 34 // NT_PRSTATUS and NT_FPREGSET definition 35 #include <elf.h> 36 // user_hwdebug_state definition 37 #include <asm/ptrace.h> 38 39 #define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize()) 40 41 using namespace lldb; 42 using namespace lldb_private; 43 using namespace lldb_private::process_linux; 44 45 // ARM64 general purpose registers. 46 static const uint32_t g_gpr_regnums_arm64[] = { 47 gpr_x0_arm64, gpr_x1_arm64, gpr_x2_arm64, gpr_x3_arm64, 48 gpr_x4_arm64, gpr_x5_arm64, gpr_x6_arm64, gpr_x7_arm64, 49 gpr_x8_arm64, gpr_x9_arm64, gpr_x10_arm64, gpr_x11_arm64, 50 gpr_x12_arm64, gpr_x13_arm64, gpr_x14_arm64, gpr_x15_arm64, 51 gpr_x16_arm64, gpr_x17_arm64, gpr_x18_arm64, gpr_x19_arm64, 52 gpr_x20_arm64, gpr_x21_arm64, gpr_x22_arm64, gpr_x23_arm64, 53 gpr_x24_arm64, gpr_x25_arm64, gpr_x26_arm64, gpr_x27_arm64, 54 gpr_x28_arm64, gpr_fp_arm64, gpr_lr_arm64, gpr_sp_arm64, 55 gpr_pc_arm64, gpr_cpsr_arm64, gpr_w0_arm64, gpr_w1_arm64, 56 gpr_w2_arm64, gpr_w3_arm64, gpr_w4_arm64, gpr_w5_arm64, 57 gpr_w6_arm64, gpr_w7_arm64, gpr_w8_arm64, gpr_w9_arm64, 58 gpr_w10_arm64, gpr_w11_arm64, gpr_w12_arm64, gpr_w13_arm64, 59 gpr_w14_arm64, gpr_w15_arm64, gpr_w16_arm64, gpr_w17_arm64, 60 gpr_w18_arm64, gpr_w19_arm64, gpr_w20_arm64, gpr_w21_arm64, 61 gpr_w22_arm64, gpr_w23_arm64, gpr_w24_arm64, gpr_w25_arm64, 62 gpr_w26_arm64, gpr_w27_arm64, gpr_w28_arm64, 63 LLDB_INVALID_REGNUM // register sets need to end with this flag 64 }; 65 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 66 1) == k_num_gpr_registers_arm64, 67 "g_gpr_regnums_arm64 has wrong number of register infos"); 68 69 // ARM64 floating point registers. 70 static const uint32_t g_fpu_regnums_arm64[] = { 71 fpu_v0_arm64, fpu_v1_arm64, fpu_v2_arm64, fpu_v3_arm64, 72 fpu_v4_arm64, fpu_v5_arm64, fpu_v6_arm64, fpu_v7_arm64, 73 fpu_v8_arm64, fpu_v9_arm64, fpu_v10_arm64, fpu_v11_arm64, 74 fpu_v12_arm64, fpu_v13_arm64, fpu_v14_arm64, fpu_v15_arm64, 75 fpu_v16_arm64, fpu_v17_arm64, fpu_v18_arm64, fpu_v19_arm64, 76 fpu_v20_arm64, fpu_v21_arm64, fpu_v22_arm64, fpu_v23_arm64, 77 fpu_v24_arm64, fpu_v25_arm64, fpu_v26_arm64, fpu_v27_arm64, 78 fpu_v28_arm64, fpu_v29_arm64, fpu_v30_arm64, fpu_v31_arm64, 79 fpu_s0_arm64, fpu_s1_arm64, fpu_s2_arm64, fpu_s3_arm64, 80 fpu_s4_arm64, fpu_s5_arm64, fpu_s6_arm64, fpu_s7_arm64, 81 fpu_s8_arm64, fpu_s9_arm64, fpu_s10_arm64, fpu_s11_arm64, 82 fpu_s12_arm64, fpu_s13_arm64, fpu_s14_arm64, fpu_s15_arm64, 83 fpu_s16_arm64, fpu_s17_arm64, fpu_s18_arm64, fpu_s19_arm64, 84 fpu_s20_arm64, fpu_s21_arm64, fpu_s22_arm64, fpu_s23_arm64, 85 fpu_s24_arm64, fpu_s25_arm64, fpu_s26_arm64, fpu_s27_arm64, 86 fpu_s28_arm64, fpu_s29_arm64, fpu_s30_arm64, fpu_s31_arm64, 87 88 fpu_d0_arm64, fpu_d1_arm64, fpu_d2_arm64, fpu_d3_arm64, 89 fpu_d4_arm64, fpu_d5_arm64, fpu_d6_arm64, fpu_d7_arm64, 90 fpu_d8_arm64, fpu_d9_arm64, fpu_d10_arm64, fpu_d11_arm64, 91 fpu_d12_arm64, fpu_d13_arm64, fpu_d14_arm64, fpu_d15_arm64, 92 fpu_d16_arm64, fpu_d17_arm64, fpu_d18_arm64, fpu_d19_arm64, 93 fpu_d20_arm64, fpu_d21_arm64, fpu_d22_arm64, fpu_d23_arm64, 94 fpu_d24_arm64, fpu_d25_arm64, fpu_d26_arm64, fpu_d27_arm64, 95 fpu_d28_arm64, fpu_d29_arm64, fpu_d30_arm64, fpu_d31_arm64, 96 fpu_fpsr_arm64, fpu_fpcr_arm64, 97 LLDB_INVALID_REGNUM // register sets need to end with this flag 98 }; 99 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 100 1) == k_num_fpr_registers_arm64, 101 "g_fpu_regnums_arm64 has wrong number of register infos"); 102 103 namespace { 104 // Number of register sets provided by this context. 105 enum { k_num_register_sets = 2 }; 106 } 107 108 // Register sets for ARM64. 109 static const RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 110 {"General Purpose Registers", "gpr", k_num_gpr_registers_arm64, 111 g_gpr_regnums_arm64}, 112 {"Floating Point Registers", "fpu", k_num_fpr_registers_arm64, 113 g_fpu_regnums_arm64}}; 114 115 std::unique_ptr<NativeRegisterContextLinux> 116 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux( 117 const ArchSpec &target_arch, NativeThreadProtocol &native_thread) { 118 switch (target_arch.GetMachine()) { 119 case llvm::Triple::arm: 120 return llvm::make_unique<NativeRegisterContextLinux_arm>(target_arch, 121 native_thread); 122 case llvm::Triple::aarch64: 123 return llvm::make_unique<NativeRegisterContextLinux_arm64>(target_arch, 124 native_thread); 125 default: 126 llvm_unreachable("have no register context for architecture"); 127 } 128 } 129 130 NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64( 131 const ArchSpec &target_arch, NativeThreadProtocol &native_thread) 132 : NativeRegisterContextLinux(native_thread, 133 new RegisterInfoPOSIX_arm64(target_arch)) { 134 switch (target_arch.GetMachine()) { 135 case llvm::Triple::aarch64: 136 m_reg_info.num_registers = k_num_registers_arm64; 137 m_reg_info.num_gpr_registers = k_num_gpr_registers_arm64; 138 m_reg_info.num_fpr_registers = k_num_fpr_registers_arm64; 139 m_reg_info.last_gpr = k_last_gpr_arm64; 140 m_reg_info.first_fpr = k_first_fpr_arm64; 141 m_reg_info.last_fpr = k_last_fpr_arm64; 142 m_reg_info.first_fpr_v = fpu_v0_arm64; 143 m_reg_info.last_fpr_v = fpu_v31_arm64; 144 m_reg_info.gpr_flags = gpr_cpsr_arm64; 145 break; 146 default: 147 llvm_unreachable("Unhandled target architecture."); 148 break; 149 } 150 151 ::memset(&m_fpr, 0, sizeof(m_fpr)); 152 ::memset(&m_gpr_arm64, 0, sizeof(m_gpr_arm64)); 153 ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs)); 154 ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs)); 155 156 // 16 is just a maximum value, query hardware for actual watchpoint count 157 m_max_hwp_supported = 16; 158 m_max_hbp_supported = 16; 159 m_refresh_hwdebug_info = true; 160 } 161 162 uint32_t NativeRegisterContextLinux_arm64::GetRegisterSetCount() const { 163 return k_num_register_sets; 164 } 165 166 const RegisterSet * 167 NativeRegisterContextLinux_arm64::GetRegisterSet(uint32_t set_index) const { 168 if (set_index < k_num_register_sets) 169 return &g_reg_sets_arm64[set_index]; 170 171 return nullptr; 172 } 173 174 uint32_t NativeRegisterContextLinux_arm64::GetUserRegisterCount() const { 175 uint32_t count = 0; 176 for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index) 177 count += g_reg_sets_arm64[set_index].num_registers; 178 return count; 179 } 180 181 Status 182 NativeRegisterContextLinux_arm64::ReadRegister(const RegisterInfo *reg_info, 183 RegisterValue ®_value) { 184 Status error; 185 186 if (!reg_info) { 187 error.SetErrorString("reg_info NULL"); 188 return error; 189 } 190 191 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; 192 193 if (IsFPR(reg)) { 194 error = ReadFPR(); 195 if (error.Fail()) 196 return error; 197 } else { 198 uint32_t full_reg = reg; 199 bool is_subreg = reg_info->invalidate_regs && 200 (reg_info->invalidate_regs[0] != LLDB_INVALID_REGNUM); 201 202 if (is_subreg) { 203 // Read the full aligned 64-bit register. 204 full_reg = reg_info->invalidate_regs[0]; 205 } 206 207 error = ReadRegisterRaw(full_reg, reg_value); 208 209 if (error.Success()) { 210 // If our read was not aligned (for ah,bh,ch,dh), shift our returned value 211 // one byte to the right. 212 if (is_subreg && (reg_info->byte_offset & 0x1)) 213 reg_value.SetUInt64(reg_value.GetAsUInt64() >> 8); 214 215 // If our return byte size was greater than the return value reg size, 216 // then 217 // use the type specified by reg_info rather than the uint64_t default 218 if (reg_value.GetByteSize() > reg_info->byte_size) 219 reg_value.SetType(reg_info); 220 } 221 return error; 222 } 223 224 // Get pointer to m_fpr variable and set the data from it. 225 uint32_t fpr_offset = CalculateFprOffset(reg_info); 226 assert(fpr_offset < sizeof m_fpr); 227 uint8_t *src = (uint8_t *)&m_fpr + fpr_offset; 228 reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size, 229 eByteOrderLittle, error); 230 231 return error; 232 } 233 234 Status NativeRegisterContextLinux_arm64::WriteRegister( 235 const RegisterInfo *reg_info, const RegisterValue ®_value) { 236 if (!reg_info) 237 return Status("reg_info NULL"); 238 239 const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB]; 240 if (reg_index == LLDB_INVALID_REGNUM) 241 return Status("no lldb regnum for %s", reg_info && reg_info->name 242 ? reg_info->name 243 : "<unknown register>"); 244 245 if (IsGPR(reg_index)) 246 return WriteRegisterRaw(reg_index, reg_value); 247 248 if (IsFPR(reg_index)) { 249 // Get pointer to m_fpr variable and set the data to it. 250 uint32_t fpr_offset = CalculateFprOffset(reg_info); 251 assert(fpr_offset < sizeof m_fpr); 252 uint8_t *dst = (uint8_t *)&m_fpr + fpr_offset; 253 switch (reg_info->byte_size) { 254 case 2: 255 *(uint16_t *)dst = reg_value.GetAsUInt16(); 256 break; 257 case 4: 258 *(uint32_t *)dst = reg_value.GetAsUInt32(); 259 break; 260 case 8: 261 *(uint64_t *)dst = reg_value.GetAsUInt64(); 262 break; 263 default: 264 assert(false && "Unhandled data size."); 265 return Status("unhandled register data size %" PRIu32, 266 reg_info->byte_size); 267 } 268 269 Status error = WriteFPR(); 270 if (error.Fail()) 271 return error; 272 273 return Status(); 274 } 275 276 return Status("failed - register wasn't recognized to be a GPR or an FPR, " 277 "write strategy unknown"); 278 } 279 280 Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues( 281 lldb::DataBufferSP &data_sp) { 282 Status error; 283 284 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 285 if (!data_sp) 286 return Status("failed to allocate DataBufferHeap instance of size %" PRIu64, 287 REG_CONTEXT_SIZE); 288 289 error = ReadGPR(); 290 if (error.Fail()) 291 return error; 292 293 error = ReadFPR(); 294 if (error.Fail()) 295 return error; 296 297 uint8_t *dst = data_sp->GetBytes(); 298 if (dst == nullptr) { 299 error.SetErrorStringWithFormat("DataBufferHeap instance of size %" PRIu64 300 " returned a null pointer", 301 REG_CONTEXT_SIZE); 302 return error; 303 } 304 305 ::memcpy(dst, &m_gpr_arm64, GetGPRSize()); 306 dst += GetGPRSize(); 307 ::memcpy(dst, &m_fpr, sizeof(m_fpr)); 308 309 return error; 310 } 311 312 Status NativeRegisterContextLinux_arm64::WriteAllRegisterValues( 313 const lldb::DataBufferSP &data_sp) { 314 Status error; 315 316 if (!data_sp) { 317 error.SetErrorStringWithFormat( 318 "NativeRegisterContextLinux_x86_64::%s invalid data_sp provided", 319 __FUNCTION__); 320 return error; 321 } 322 323 if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) { 324 error.SetErrorStringWithFormat( 325 "NativeRegisterContextLinux_x86_64::%s data_sp contained mismatched " 326 "data size, expected %" PRIu64 ", actual %" PRIu64, 327 __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize()); 328 return error; 329 } 330 331 uint8_t *src = data_sp->GetBytes(); 332 if (src == nullptr) { 333 error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s " 334 "DataBuffer::GetBytes() returned a null " 335 "pointer", 336 __FUNCTION__); 337 return error; 338 } 339 ::memcpy(&m_gpr_arm64, src, GetRegisterInfoInterface().GetGPRSize()); 340 341 error = WriteGPR(); 342 if (error.Fail()) 343 return error; 344 345 src += GetRegisterInfoInterface().GetGPRSize(); 346 ::memcpy(&m_fpr, src, sizeof(m_fpr)); 347 348 error = WriteFPR(); 349 if (error.Fail()) 350 return error; 351 352 return error; 353 } 354 355 bool NativeRegisterContextLinux_arm64::IsGPR(unsigned reg) const { 356 return reg <= m_reg_info.last_gpr; // GPR's come first. 357 } 358 359 bool NativeRegisterContextLinux_arm64::IsFPR(unsigned reg) const { 360 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr); 361 } 362 363 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareBreakpoints() { 364 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 365 366 if (log) 367 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 368 369 Status error; 370 371 // Read hardware breakpoint and watchpoint information. 372 error = ReadHardwareDebugInfo(); 373 374 if (error.Fail()) 375 return 0; 376 377 return m_max_hbp_supported; 378 } 379 380 uint32_t 381 NativeRegisterContextLinux_arm64::SetHardwareBreakpoint(lldb::addr_t addr, 382 size_t size) { 383 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 384 LLDB_LOG(log, "addr: {0:x}, size: {1:x}", addr, size); 385 386 // Read hardware breakpoint and watchpoint information. 387 Status error = ReadHardwareDebugInfo(); 388 389 if (error.Fail()) 390 return LLDB_INVALID_INDEX32; 391 392 uint32_t control_value = 0, bp_index = 0; 393 394 // Check if size has a valid hardware breakpoint length. 395 if (size != 4) 396 return LLDB_INVALID_INDEX32; // Invalid size for a AArch64 hardware 397 // breakpoint 398 399 // Check 4-byte alignment for hardware breakpoint target address. 400 if (addr & 0x03) 401 return LLDB_INVALID_INDEX32; // Invalid address, should be 4-byte aligned. 402 403 // Setup control value 404 control_value = 0; 405 control_value |= ((1 << size) - 1) << 5; 406 control_value |= (2 << 1) | 1; 407 408 // Iterate over stored breakpoints and find a free bp_index 409 bp_index = LLDB_INVALID_INDEX32; 410 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 411 if ((m_hbr_regs[i].control & 1) == 0) { 412 bp_index = i; // Mark last free slot 413 } else if (m_hbr_regs[i].address == addr) { 414 return LLDB_INVALID_INDEX32; // We do not support duplicate breakpoints. 415 } 416 } 417 418 if (bp_index == LLDB_INVALID_INDEX32) 419 return LLDB_INVALID_INDEX32; 420 421 // Update breakpoint in local cache 422 m_hbr_regs[bp_index].real_addr = addr; 423 m_hbr_regs[bp_index].address = addr; 424 m_hbr_regs[bp_index].control = control_value; 425 426 // PTRACE call to set corresponding hardware breakpoint register. 427 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 428 429 if (error.Fail()) { 430 m_hbr_regs[bp_index].address = 0; 431 m_hbr_regs[bp_index].control &= ~1; 432 433 return LLDB_INVALID_INDEX32; 434 } 435 436 return bp_index; 437 } 438 439 bool NativeRegisterContextLinux_arm64::ClearHardwareBreakpoint( 440 uint32_t hw_idx) { 441 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 442 LLDB_LOG(log, "hw_idx: {0}", hw_idx); 443 444 // Read hardware breakpoint and watchpoint information. 445 Status error = ReadHardwareDebugInfo(); 446 447 if (error.Fail()) 448 return false; 449 450 if (hw_idx >= m_max_hbp_supported) 451 return false; 452 453 // Create a backup we can revert to in case of failure. 454 lldb::addr_t tempAddr = m_hbr_regs[hw_idx].address; 455 uint32_t tempControl = m_hbr_regs[hw_idx].control; 456 457 m_hbr_regs[hw_idx].control &= ~1; 458 m_hbr_regs[hw_idx].address = 0; 459 460 // PTRACE call to clear corresponding hardware breakpoint register. 461 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 462 463 if (error.Fail()) { 464 m_hbr_regs[hw_idx].control = tempControl; 465 m_hbr_regs[hw_idx].address = tempAddr; 466 467 return false; 468 } 469 470 return true; 471 } 472 473 Status NativeRegisterContextLinux_arm64::GetHardwareBreakHitIndex( 474 uint32_t &bp_index, lldb::addr_t trap_addr) { 475 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 476 477 if (log) 478 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 479 480 lldb::addr_t break_addr; 481 482 for (bp_index = 0; bp_index < m_max_hbp_supported; ++bp_index) { 483 break_addr = m_hbr_regs[bp_index].address; 484 485 if ((m_hbr_regs[bp_index].control & 0x1) && (trap_addr == break_addr)) { 486 m_hbr_regs[bp_index].hit_addr = trap_addr; 487 return Status(); 488 } 489 } 490 491 bp_index = LLDB_INVALID_INDEX32; 492 return Status(); 493 } 494 495 Status NativeRegisterContextLinux_arm64::ClearAllHardwareBreakpoints() { 496 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 497 498 if (log) 499 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 500 501 Status error; 502 503 // Read hardware breakpoint and watchpoint information. 504 error = ReadHardwareDebugInfo(); 505 506 if (error.Fail()) 507 return error; 508 509 lldb::addr_t tempAddr = 0; 510 uint32_t tempControl = 0; 511 512 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 513 if (m_hbr_regs[i].control & 0x01) { 514 // Create a backup we can revert to in case of failure. 515 tempAddr = m_hbr_regs[i].address; 516 tempControl = m_hbr_regs[i].control; 517 518 // Clear watchpoints in local cache 519 m_hbr_regs[i].control &= ~1; 520 m_hbr_regs[i].address = 0; 521 522 // Ptrace call to update hardware debug registers 523 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 524 525 if (error.Fail()) { 526 m_hbr_regs[i].control = tempControl; 527 m_hbr_regs[i].address = tempAddr; 528 529 return error; 530 } 531 } 532 } 533 534 return Status(); 535 } 536 537 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareWatchpoints() { 538 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 539 540 // Read hardware breakpoint and watchpoint information. 541 Status error = ReadHardwareDebugInfo(); 542 543 if (error.Fail()) 544 return 0; 545 546 LLDB_LOG(log, "{0}", m_max_hwp_supported); 547 return m_max_hwp_supported; 548 } 549 550 uint32_t NativeRegisterContextLinux_arm64::SetHardwareWatchpoint( 551 lldb::addr_t addr, size_t size, uint32_t watch_flags) { 552 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 553 LLDB_LOG(log, "addr: {0:x}, size: {1:x} watch_flags: {2:x}", addr, size, 554 watch_flags); 555 556 // Read hardware breakpoint and watchpoint information. 557 Status error = ReadHardwareDebugInfo(); 558 559 if (error.Fail()) 560 return LLDB_INVALID_INDEX32; 561 562 uint32_t control_value = 0, wp_index = 0; 563 lldb::addr_t real_addr = addr; 564 565 // Check if we are setting watchpoint other than read/write/access 566 // Also update watchpoint flag to match AArch64 write-read bit configuration. 567 switch (watch_flags) { 568 case 1: 569 watch_flags = 2; 570 break; 571 case 2: 572 watch_flags = 1; 573 break; 574 case 3: 575 break; 576 default: 577 return LLDB_INVALID_INDEX32; 578 } 579 580 // Check if size has a valid hardware watchpoint length. 581 if (size != 1 && size != 2 && size != 4 && size != 8) 582 return LLDB_INVALID_INDEX32; 583 584 // Check 8-byte alignment for hardware watchpoint target address. 585 // Below is a hack to recalculate address and size in order to 586 // make sure we can watch non 8-byte alligned addresses as well. 587 if (addr & 0x07) { 588 uint8_t watch_mask = (addr & 0x07) + size; 589 590 if (watch_mask > 0x08) 591 return LLDB_INVALID_INDEX32; 592 else if (watch_mask <= 0x02) 593 size = 2; 594 else if (watch_mask <= 0x04) 595 size = 4; 596 else 597 size = 8; 598 599 addr = addr & (~0x07); 600 } 601 602 // Setup control value 603 control_value = watch_flags << 3; 604 control_value |= ((1 << size) - 1) << 5; 605 control_value |= (2 << 1) | 1; 606 607 // Iterate over stored watchpoints and find a free wp_index 608 wp_index = LLDB_INVALID_INDEX32; 609 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 610 if ((m_hwp_regs[i].control & 1) == 0) { 611 wp_index = i; // Mark last free slot 612 } else if (m_hwp_regs[i].address == addr) { 613 return LLDB_INVALID_INDEX32; // We do not support duplicate watchpoints. 614 } 615 } 616 617 if (wp_index == LLDB_INVALID_INDEX32) 618 return LLDB_INVALID_INDEX32; 619 620 // Update watchpoint in local cache 621 m_hwp_regs[wp_index].real_addr = real_addr; 622 m_hwp_regs[wp_index].address = addr; 623 m_hwp_regs[wp_index].control = control_value; 624 625 // PTRACE call to set corresponding watchpoint register. 626 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 627 628 if (error.Fail()) { 629 m_hwp_regs[wp_index].address = 0; 630 m_hwp_regs[wp_index].control &= ~1; 631 632 return LLDB_INVALID_INDEX32; 633 } 634 635 return wp_index; 636 } 637 638 bool NativeRegisterContextLinux_arm64::ClearHardwareWatchpoint( 639 uint32_t wp_index) { 640 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 641 LLDB_LOG(log, "wp_index: {0}", wp_index); 642 643 // Read hardware breakpoint and watchpoint information. 644 Status error = ReadHardwareDebugInfo(); 645 646 if (error.Fail()) 647 return false; 648 649 if (wp_index >= m_max_hwp_supported) 650 return false; 651 652 // Create a backup we can revert to in case of failure. 653 lldb::addr_t tempAddr = m_hwp_regs[wp_index].address; 654 uint32_t tempControl = m_hwp_regs[wp_index].control; 655 656 // Update watchpoint in local cache 657 m_hwp_regs[wp_index].control &= ~1; 658 m_hwp_regs[wp_index].address = 0; 659 660 // Ptrace call to update hardware debug registers 661 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 662 663 if (error.Fail()) { 664 m_hwp_regs[wp_index].control = tempControl; 665 m_hwp_regs[wp_index].address = tempAddr; 666 667 return false; 668 } 669 670 return true; 671 } 672 673 Status NativeRegisterContextLinux_arm64::ClearAllHardwareWatchpoints() { 674 // Read hardware breakpoint and watchpoint information. 675 Status error = ReadHardwareDebugInfo(); 676 677 if (error.Fail()) 678 return error; 679 680 lldb::addr_t tempAddr = 0; 681 uint32_t tempControl = 0; 682 683 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 684 if (m_hwp_regs[i].control & 0x01) { 685 // Create a backup we can revert to in case of failure. 686 tempAddr = m_hwp_regs[i].address; 687 tempControl = m_hwp_regs[i].control; 688 689 // Clear watchpoints in local cache 690 m_hwp_regs[i].control &= ~1; 691 m_hwp_regs[i].address = 0; 692 693 // Ptrace call to update hardware debug registers 694 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 695 696 if (error.Fail()) { 697 m_hwp_regs[i].control = tempControl; 698 m_hwp_regs[i].address = tempAddr; 699 700 return error; 701 } 702 } 703 } 704 705 return Status(); 706 } 707 708 uint32_t 709 NativeRegisterContextLinux_arm64::GetWatchpointSize(uint32_t wp_index) { 710 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 711 LLDB_LOG(log, "wp_index: {0}", wp_index); 712 713 switch ((m_hwp_regs[wp_index].control >> 5) & 0xff) { 714 case 0x01: 715 return 1; 716 case 0x03: 717 return 2; 718 case 0x0f: 719 return 4; 720 case 0xff: 721 return 8; 722 default: 723 return 0; 724 } 725 } 726 bool NativeRegisterContextLinux_arm64::WatchpointIsEnabled(uint32_t wp_index) { 727 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 728 LLDB_LOG(log, "wp_index: {0}", wp_index); 729 730 if ((m_hwp_regs[wp_index].control & 0x1) == 0x1) 731 return true; 732 else 733 return false; 734 } 735 736 Status NativeRegisterContextLinux_arm64::GetWatchpointHitIndex( 737 uint32_t &wp_index, lldb::addr_t trap_addr) { 738 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 739 LLDB_LOG(log, "wp_index: {0}, trap_addr: {1:x}", wp_index, trap_addr); 740 741 uint32_t watch_size; 742 lldb::addr_t watch_addr; 743 744 for (wp_index = 0; wp_index < m_max_hwp_supported; ++wp_index) { 745 watch_size = GetWatchpointSize(wp_index); 746 watch_addr = m_hwp_regs[wp_index].address; 747 748 if (WatchpointIsEnabled(wp_index) && trap_addr >= watch_addr && 749 trap_addr < watch_addr + watch_size) { 750 m_hwp_regs[wp_index].hit_addr = trap_addr; 751 return Status(); 752 } 753 } 754 755 wp_index = LLDB_INVALID_INDEX32; 756 return Status(); 757 } 758 759 lldb::addr_t 760 NativeRegisterContextLinux_arm64::GetWatchpointAddress(uint32_t wp_index) { 761 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 762 LLDB_LOG(log, "wp_index: {0}", wp_index); 763 764 if (wp_index >= m_max_hwp_supported) 765 return LLDB_INVALID_ADDRESS; 766 767 if (WatchpointIsEnabled(wp_index)) 768 return m_hwp_regs[wp_index].real_addr; 769 else 770 return LLDB_INVALID_ADDRESS; 771 } 772 773 lldb::addr_t 774 NativeRegisterContextLinux_arm64::GetWatchpointHitAddress(uint32_t wp_index) { 775 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 776 LLDB_LOG(log, "wp_index: {0}", wp_index); 777 778 if (wp_index >= m_max_hwp_supported) 779 return LLDB_INVALID_ADDRESS; 780 781 if (WatchpointIsEnabled(wp_index)) 782 return m_hwp_regs[wp_index].hit_addr; 783 else 784 return LLDB_INVALID_ADDRESS; 785 } 786 787 Status NativeRegisterContextLinux_arm64::ReadHardwareDebugInfo() { 788 if (!m_refresh_hwdebug_info) { 789 return Status(); 790 } 791 792 ::pid_t tid = m_thread.GetID(); 793 794 int regset = NT_ARM_HW_WATCH; 795 struct iovec ioVec; 796 struct user_hwdebug_state dreg_state; 797 Status error; 798 799 ioVec.iov_base = &dreg_state; 800 ioVec.iov_len = sizeof(dreg_state); 801 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 802 &ioVec, ioVec.iov_len); 803 804 if (error.Fail()) 805 return error; 806 807 m_max_hwp_supported = dreg_state.dbg_info & 0xff; 808 809 regset = NT_ARM_HW_BREAK; 810 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 811 &ioVec, ioVec.iov_len); 812 813 if (error.Fail()) 814 return error; 815 816 m_max_hbp_supported = dreg_state.dbg_info & 0xff; 817 m_refresh_hwdebug_info = false; 818 819 return error; 820 } 821 822 Status NativeRegisterContextLinux_arm64::WriteHardwareDebugRegs(int hwbType) { 823 struct iovec ioVec; 824 struct user_hwdebug_state dreg_state; 825 Status error; 826 827 memset(&dreg_state, 0, sizeof(dreg_state)); 828 ioVec.iov_base = &dreg_state; 829 830 if (hwbType == eDREGTypeWATCH) { 831 hwbType = NT_ARM_HW_WATCH; 832 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 833 (sizeof(dreg_state.dbg_regs[0]) * m_max_hwp_supported); 834 835 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 836 dreg_state.dbg_regs[i].addr = m_hwp_regs[i].address; 837 dreg_state.dbg_regs[i].ctrl = m_hwp_regs[i].control; 838 } 839 } else { 840 hwbType = NT_ARM_HW_BREAK; 841 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 842 (sizeof(dreg_state.dbg_regs[0]) * m_max_hbp_supported); 843 844 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 845 dreg_state.dbg_regs[i].addr = m_hbr_regs[i].address; 846 dreg_state.dbg_regs[i].ctrl = m_hbr_regs[i].control; 847 } 848 } 849 850 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 851 &hwbType, &ioVec, ioVec.iov_len); 852 } 853 854 Status NativeRegisterContextLinux_arm64::DoReadRegisterValue( 855 uint32_t offset, const char *reg_name, uint32_t size, 856 RegisterValue &value) { 857 Status error; 858 if (offset > sizeof(struct user_pt_regs)) { 859 offset -= sizeof(struct user_pt_regs); 860 if (offset > sizeof(struct user_fpsimd_state)) { 861 error.SetErrorString("invalid offset value"); 862 return error; 863 } 864 elf_fpregset_t regs; 865 int regset = NT_FPREGSET; 866 struct iovec ioVec; 867 868 ioVec.iov_base = ®s; 869 ioVec.iov_len = sizeof regs; 870 error = NativeProcessLinux::PtraceWrapper( 871 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 872 if (error.Success()) { 873 value.SetBytes((void *)(((unsigned char *)(®s)) + offset), 16, 874 m_thread.GetProcess().GetByteOrder()); 875 } 876 } else { 877 elf_gregset_t regs; 878 int regset = NT_PRSTATUS; 879 struct iovec ioVec; 880 881 ioVec.iov_base = ®s; 882 ioVec.iov_len = sizeof regs; 883 error = NativeProcessLinux::PtraceWrapper( 884 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 885 if (error.Success()) { 886 value.SetBytes((void *)(((unsigned char *)(regs)) + offset), 8, 887 m_thread.GetProcess().GetByteOrder()); 888 } 889 } 890 return error; 891 } 892 893 Status NativeRegisterContextLinux_arm64::DoWriteRegisterValue( 894 uint32_t offset, const char *reg_name, const RegisterValue &value) { 895 Status error; 896 ::pid_t tid = m_thread.GetID(); 897 if (offset > sizeof(struct user_pt_regs)) { 898 offset -= sizeof(struct user_pt_regs); 899 if (offset > sizeof(struct user_fpsimd_state)) { 900 error.SetErrorString("invalid offset value"); 901 return error; 902 } 903 elf_fpregset_t regs; 904 int regset = NT_FPREGSET; 905 struct iovec ioVec; 906 907 ioVec.iov_base = ®s; 908 ioVec.iov_len = sizeof regs; 909 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 910 &ioVec, sizeof regs); 911 912 if (error.Success()) { 913 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 914 16); 915 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 916 &ioVec, sizeof regs); 917 } 918 } else { 919 elf_gregset_t regs; 920 int regset = NT_PRSTATUS; 921 struct iovec ioVec; 922 923 ioVec.iov_base = ®s; 924 ioVec.iov_len = sizeof regs; 925 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 926 &ioVec, sizeof regs); 927 if (error.Success()) { 928 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 929 8); 930 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 931 &ioVec, sizeof regs); 932 } 933 } 934 return error; 935 } 936 937 Status NativeRegisterContextLinux_arm64::DoReadGPR(void *buf, size_t buf_size) { 938 int regset = NT_PRSTATUS; 939 struct iovec ioVec; 940 Status error; 941 942 ioVec.iov_base = buf; 943 ioVec.iov_len = buf_size; 944 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 945 ®set, &ioVec, buf_size); 946 } 947 948 Status NativeRegisterContextLinux_arm64::DoWriteGPR(void *buf, 949 size_t buf_size) { 950 int regset = NT_PRSTATUS; 951 struct iovec ioVec; 952 Status error; 953 954 ioVec.iov_base = buf; 955 ioVec.iov_len = buf_size; 956 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 957 ®set, &ioVec, buf_size); 958 } 959 960 Status NativeRegisterContextLinux_arm64::DoReadFPR(void *buf, size_t buf_size) { 961 int regset = NT_FPREGSET; 962 struct iovec ioVec; 963 Status error; 964 965 ioVec.iov_base = buf; 966 ioVec.iov_len = buf_size; 967 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 968 ®set, &ioVec, buf_size); 969 } 970 971 Status NativeRegisterContextLinux_arm64::DoWriteFPR(void *buf, 972 size_t buf_size) { 973 int regset = NT_FPREGSET; 974 struct iovec ioVec; 975 Status error; 976 977 ioVec.iov_base = buf; 978 ioVec.iov_len = buf_size; 979 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 980 ®set, &ioVec, buf_size); 981 } 982 983 uint32_t NativeRegisterContextLinux_arm64::CalculateFprOffset( 984 const RegisterInfo *reg_info) const { 985 return reg_info->byte_offset - 986 GetRegisterInfoAtIndex(m_reg_info.first_fpr)->byte_offset; 987 } 988 989 #endif // defined (__arm64__) || defined (__aarch64__) 990