1 //===-- NativeRegisterContextLinux_arm64.cpp --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #if defined(__arm64__) || defined(__aarch64__) 11 12 #include "NativeRegisterContextLinux_arm.h" 13 #include "NativeRegisterContextLinux_arm64.h" 14 15 // C Includes 16 // C++ Includes 17 18 // Other libraries and framework includes 19 #include "lldb/Core/DataBufferHeap.h" 20 #include "lldb/Core/Error.h" 21 #include "lldb/Core/Log.h" 22 #include "lldb/Core/RegisterValue.h" 23 #include "lldb/Host/common/NativeProcessProtocol.h" 24 25 #include "Plugins/Process/Linux/NativeProcessLinux.h" 26 #include "Plugins/Process/Linux/Procfs.h" 27 #include "Plugins/Process/POSIX/ProcessPOSIXLog.h" 28 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" 29 30 // System includes - They have to be included after framework includes because 31 // they define some 32 // macros which collide with variable names in other modules 33 #include <sys/socket.h> 34 // NT_PRSTATUS and NT_FPREGSET definition 35 #include <elf.h> 36 // user_hwdebug_state definition 37 #include <asm/ptrace.h> 38 39 #define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize()) 40 41 using namespace lldb; 42 using namespace lldb_private; 43 using namespace lldb_private::process_linux; 44 45 // ARM64 general purpose registers. 46 static const uint32_t g_gpr_regnums_arm64[] = { 47 gpr_x0_arm64, gpr_x1_arm64, gpr_x2_arm64, gpr_x3_arm64, 48 gpr_x4_arm64, gpr_x5_arm64, gpr_x6_arm64, gpr_x7_arm64, 49 gpr_x8_arm64, gpr_x9_arm64, gpr_x10_arm64, gpr_x11_arm64, 50 gpr_x12_arm64, gpr_x13_arm64, gpr_x14_arm64, gpr_x15_arm64, 51 gpr_x16_arm64, gpr_x17_arm64, gpr_x18_arm64, gpr_x19_arm64, 52 gpr_x20_arm64, gpr_x21_arm64, gpr_x22_arm64, gpr_x23_arm64, 53 gpr_x24_arm64, gpr_x25_arm64, gpr_x26_arm64, gpr_x27_arm64, 54 gpr_x28_arm64, gpr_fp_arm64, gpr_lr_arm64, gpr_sp_arm64, 55 gpr_pc_arm64, gpr_cpsr_arm64, gpr_w0_arm64, gpr_w1_arm64, 56 gpr_w2_arm64, gpr_w3_arm64, gpr_w4_arm64, gpr_w5_arm64, 57 gpr_w6_arm64, gpr_w7_arm64, gpr_w8_arm64, gpr_w9_arm64, 58 gpr_w10_arm64, gpr_w11_arm64, gpr_w12_arm64, gpr_w13_arm64, 59 gpr_w14_arm64, gpr_w15_arm64, gpr_w16_arm64, gpr_w17_arm64, 60 gpr_w18_arm64, gpr_w19_arm64, gpr_w20_arm64, gpr_w21_arm64, 61 gpr_w22_arm64, gpr_w23_arm64, gpr_w24_arm64, gpr_w25_arm64, 62 gpr_w26_arm64, gpr_w27_arm64, gpr_w28_arm64, 63 LLDB_INVALID_REGNUM // register sets need to end with this flag 64 }; 65 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 66 1) == k_num_gpr_registers_arm64, 67 "g_gpr_regnums_arm64 has wrong number of register infos"); 68 69 // ARM64 floating point registers. 70 static const uint32_t g_fpu_regnums_arm64[] = { 71 fpu_v0_arm64, fpu_v1_arm64, fpu_v2_arm64, fpu_v3_arm64, 72 fpu_v4_arm64, fpu_v5_arm64, fpu_v6_arm64, fpu_v7_arm64, 73 fpu_v8_arm64, fpu_v9_arm64, fpu_v10_arm64, fpu_v11_arm64, 74 fpu_v12_arm64, fpu_v13_arm64, fpu_v14_arm64, fpu_v15_arm64, 75 fpu_v16_arm64, fpu_v17_arm64, fpu_v18_arm64, fpu_v19_arm64, 76 fpu_v20_arm64, fpu_v21_arm64, fpu_v22_arm64, fpu_v23_arm64, 77 fpu_v24_arm64, fpu_v25_arm64, fpu_v26_arm64, fpu_v27_arm64, 78 fpu_v28_arm64, fpu_v29_arm64, fpu_v30_arm64, fpu_v31_arm64, 79 fpu_s0_arm64, fpu_s1_arm64, fpu_s2_arm64, fpu_s3_arm64, 80 fpu_s4_arm64, fpu_s5_arm64, fpu_s6_arm64, fpu_s7_arm64, 81 fpu_s8_arm64, fpu_s9_arm64, fpu_s10_arm64, fpu_s11_arm64, 82 fpu_s12_arm64, fpu_s13_arm64, fpu_s14_arm64, fpu_s15_arm64, 83 fpu_s16_arm64, fpu_s17_arm64, fpu_s18_arm64, fpu_s19_arm64, 84 fpu_s20_arm64, fpu_s21_arm64, fpu_s22_arm64, fpu_s23_arm64, 85 fpu_s24_arm64, fpu_s25_arm64, fpu_s26_arm64, fpu_s27_arm64, 86 fpu_s28_arm64, fpu_s29_arm64, fpu_s30_arm64, fpu_s31_arm64, 87 88 fpu_d0_arm64, fpu_d1_arm64, fpu_d2_arm64, fpu_d3_arm64, 89 fpu_d4_arm64, fpu_d5_arm64, fpu_d6_arm64, fpu_d7_arm64, 90 fpu_d8_arm64, fpu_d9_arm64, fpu_d10_arm64, fpu_d11_arm64, 91 fpu_d12_arm64, fpu_d13_arm64, fpu_d14_arm64, fpu_d15_arm64, 92 fpu_d16_arm64, fpu_d17_arm64, fpu_d18_arm64, fpu_d19_arm64, 93 fpu_d20_arm64, fpu_d21_arm64, fpu_d22_arm64, fpu_d23_arm64, 94 fpu_d24_arm64, fpu_d25_arm64, fpu_d26_arm64, fpu_d27_arm64, 95 fpu_d28_arm64, fpu_d29_arm64, fpu_d30_arm64, fpu_d31_arm64, 96 fpu_fpsr_arm64, fpu_fpcr_arm64, 97 LLDB_INVALID_REGNUM // register sets need to end with this flag 98 }; 99 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 100 1) == k_num_fpr_registers_arm64, 101 "g_fpu_regnums_arm64 has wrong number of register infos"); 102 103 namespace { 104 // Number of register sets provided by this context. 105 enum { k_num_register_sets = 2 }; 106 } 107 108 // Register sets for ARM64. 109 static const RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 110 {"General Purpose Registers", "gpr", k_num_gpr_registers_arm64, 111 g_gpr_regnums_arm64}, 112 {"Floating Point Registers", "fpu", k_num_fpr_registers_arm64, 113 g_fpu_regnums_arm64}}; 114 115 NativeRegisterContextLinux * 116 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux( 117 const ArchSpec &target_arch, NativeThreadProtocol &native_thread, 118 uint32_t concrete_frame_idx) { 119 Log *log = ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_REGISTERS); 120 switch (target_arch.GetMachine()) { 121 case llvm::Triple::arm: 122 return new NativeRegisterContextLinux_arm(target_arch, native_thread, 123 concrete_frame_idx); 124 case llvm::Triple::aarch64: 125 return new NativeRegisterContextLinux_arm64(target_arch, native_thread, 126 concrete_frame_idx); 127 default: 128 if (log) 129 log->Printf("NativeRegisterContextLinux::%s() have no register context " 130 "for architecture: %s\n", 131 __FUNCTION__, 132 target_arch.GetTriple().getArchName().str().c_str()); 133 return nullptr; 134 } 135 } 136 137 NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64( 138 const ArchSpec &target_arch, NativeThreadProtocol &native_thread, 139 uint32_t concrete_frame_idx) 140 : NativeRegisterContextLinux(native_thread, concrete_frame_idx, 141 new RegisterInfoPOSIX_arm64(target_arch)) { 142 switch (target_arch.GetMachine()) { 143 case llvm::Triple::aarch64: 144 m_reg_info.num_registers = k_num_registers_arm64; 145 m_reg_info.num_gpr_registers = k_num_gpr_registers_arm64; 146 m_reg_info.num_fpr_registers = k_num_fpr_registers_arm64; 147 m_reg_info.last_gpr = k_last_gpr_arm64; 148 m_reg_info.first_fpr = k_first_fpr_arm64; 149 m_reg_info.last_fpr = k_last_fpr_arm64; 150 m_reg_info.first_fpr_v = fpu_v0_arm64; 151 m_reg_info.last_fpr_v = fpu_v31_arm64; 152 m_reg_info.gpr_flags = gpr_cpsr_arm64; 153 break; 154 default: 155 assert(false && "Unhandled target architecture."); 156 break; 157 } 158 159 ::memset(&m_fpr, 0, sizeof(m_fpr)); 160 ::memset(&m_gpr_arm64, 0, sizeof(m_gpr_arm64)); 161 ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs)); 162 163 // 16 is just a maximum value, query hardware for actual watchpoint count 164 m_max_hwp_supported = 16; 165 m_max_hbp_supported = 16; 166 m_refresh_hwdebug_info = true; 167 } 168 169 uint32_t NativeRegisterContextLinux_arm64::GetRegisterSetCount() const { 170 return k_num_register_sets; 171 } 172 173 const RegisterSet * 174 NativeRegisterContextLinux_arm64::GetRegisterSet(uint32_t set_index) const { 175 if (set_index < k_num_register_sets) 176 return &g_reg_sets_arm64[set_index]; 177 178 return nullptr; 179 } 180 181 uint32_t NativeRegisterContextLinux_arm64::GetUserRegisterCount() const { 182 uint32_t count = 0; 183 for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index) 184 count += g_reg_sets_arm64[set_index].num_registers; 185 return count; 186 } 187 188 Error NativeRegisterContextLinux_arm64::ReadRegister( 189 const RegisterInfo *reg_info, RegisterValue ®_value) { 190 Error error; 191 192 if (!reg_info) { 193 error.SetErrorString("reg_info NULL"); 194 return error; 195 } 196 197 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; 198 199 if (IsFPR(reg)) { 200 error = ReadFPR(); 201 if (error.Fail()) 202 return error; 203 } else { 204 uint32_t full_reg = reg; 205 bool is_subreg = reg_info->invalidate_regs && 206 (reg_info->invalidate_regs[0] != LLDB_INVALID_REGNUM); 207 208 if (is_subreg) { 209 // Read the full aligned 64-bit register. 210 full_reg = reg_info->invalidate_regs[0]; 211 } 212 213 error = ReadRegisterRaw(full_reg, reg_value); 214 215 if (error.Success()) { 216 // If our read was not aligned (for ah,bh,ch,dh), shift our returned value 217 // one byte to the right. 218 if (is_subreg && (reg_info->byte_offset & 0x1)) 219 reg_value.SetUInt64(reg_value.GetAsUInt64() >> 8); 220 221 // If our return byte size was greater than the return value reg size, 222 // then 223 // use the type specified by reg_info rather than the uint64_t default 224 if (reg_value.GetByteSize() > reg_info->byte_size) 225 reg_value.SetType(reg_info); 226 } 227 return error; 228 } 229 230 // Get pointer to m_fpr variable and set the data from it. 231 uint32_t fpr_offset = CalculateFprOffset(reg_info); 232 assert(fpr_offset < sizeof m_fpr); 233 uint8_t *src = (uint8_t *)&m_fpr + fpr_offset; 234 reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size, 235 eByteOrderLittle, error); 236 237 return error; 238 } 239 240 Error NativeRegisterContextLinux_arm64::WriteRegister( 241 const RegisterInfo *reg_info, const RegisterValue ®_value) { 242 if (!reg_info) 243 return Error("reg_info NULL"); 244 245 const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB]; 246 if (reg_index == LLDB_INVALID_REGNUM) 247 return Error("no lldb regnum for %s", reg_info && reg_info->name 248 ? reg_info->name 249 : "<unknown register>"); 250 251 if (IsGPR(reg_index)) 252 return WriteRegisterRaw(reg_index, reg_value); 253 254 if (IsFPR(reg_index)) { 255 // Get pointer to m_fpr variable and set the data to it. 256 uint32_t fpr_offset = CalculateFprOffset(reg_info); 257 assert(fpr_offset < sizeof m_fpr); 258 uint8_t *dst = (uint8_t *)&m_fpr + fpr_offset; 259 switch (reg_info->byte_size) { 260 case 2: 261 *(uint16_t *)dst = reg_value.GetAsUInt16(); 262 break; 263 case 4: 264 *(uint32_t *)dst = reg_value.GetAsUInt32(); 265 break; 266 case 8: 267 *(uint64_t *)dst = reg_value.GetAsUInt64(); 268 break; 269 default: 270 assert(false && "Unhandled data size."); 271 return Error("unhandled register data size %" PRIu32, 272 reg_info->byte_size); 273 } 274 275 Error error = WriteFPR(); 276 if (error.Fail()) 277 return error; 278 279 return Error(); 280 } 281 282 return Error("failed - register wasn't recognized to be a GPR or an FPR, " 283 "write strategy unknown"); 284 } 285 286 Error NativeRegisterContextLinux_arm64::ReadAllRegisterValues( 287 lldb::DataBufferSP &data_sp) { 288 Error error; 289 290 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 291 if (!data_sp) 292 return Error("failed to allocate DataBufferHeap instance of size %" PRIu64, 293 REG_CONTEXT_SIZE); 294 295 error = ReadGPR(); 296 if (error.Fail()) 297 return error; 298 299 error = ReadFPR(); 300 if (error.Fail()) 301 return error; 302 303 uint8_t *dst = data_sp->GetBytes(); 304 if (dst == nullptr) { 305 error.SetErrorStringWithFormat("DataBufferHeap instance of size %" PRIu64 306 " returned a null pointer", 307 REG_CONTEXT_SIZE); 308 return error; 309 } 310 311 ::memcpy(dst, &m_gpr_arm64, GetGPRSize()); 312 dst += GetGPRSize(); 313 ::memcpy(dst, &m_fpr, sizeof(m_fpr)); 314 315 return error; 316 } 317 318 Error NativeRegisterContextLinux_arm64::WriteAllRegisterValues( 319 const lldb::DataBufferSP &data_sp) { 320 Error error; 321 322 if (!data_sp) { 323 error.SetErrorStringWithFormat( 324 "NativeRegisterContextLinux_x86_64::%s invalid data_sp provided", 325 __FUNCTION__); 326 return error; 327 } 328 329 if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) { 330 error.SetErrorStringWithFormat( 331 "NativeRegisterContextLinux_x86_64::%s data_sp contained mismatched " 332 "data size, expected %" PRIu64 ", actual %" PRIu64, 333 __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize()); 334 return error; 335 } 336 337 uint8_t *src = data_sp->GetBytes(); 338 if (src == nullptr) { 339 error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s " 340 "DataBuffer::GetBytes() returned a null " 341 "pointer", 342 __FUNCTION__); 343 return error; 344 } 345 ::memcpy(&m_gpr_arm64, src, GetRegisterInfoInterface().GetGPRSize()); 346 347 error = WriteGPR(); 348 if (error.Fail()) 349 return error; 350 351 src += GetRegisterInfoInterface().GetGPRSize(); 352 ::memcpy(&m_fpr, src, sizeof(m_fpr)); 353 354 error = WriteFPR(); 355 if (error.Fail()) 356 return error; 357 358 return error; 359 } 360 361 bool NativeRegisterContextLinux_arm64::IsGPR(unsigned reg) const { 362 return reg <= m_reg_info.last_gpr; // GPR's come first. 363 } 364 365 bool NativeRegisterContextLinux_arm64::IsFPR(unsigned reg) const { 366 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr); 367 } 368 369 uint32_t 370 NativeRegisterContextLinux_arm64::SetHardwareBreakpoint(lldb::addr_t addr, 371 size_t size) { 372 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 373 374 if (log) 375 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 376 377 Error error; 378 379 // Read hardware breakpoint and watchpoint information. 380 error = ReadHardwareDebugInfo(); 381 382 if (error.Fail()) 383 return LLDB_INVALID_INDEX32; 384 385 uint32_t control_value = 0, bp_index = 0; 386 387 // Check if size has a valid hardware breakpoint length. 388 if (size != 4) 389 return LLDB_INVALID_INDEX32; // Invalid size for a AArch64 hardware 390 // breakpoint 391 392 // Check 4-byte alignment for hardware breakpoint target address. 393 if (addr & 0x03) 394 return LLDB_INVALID_INDEX32; // Invalid address, should be 4-byte aligned. 395 396 // Setup control value 397 control_value = 0; 398 control_value |= ((1 << size) - 1) << 5; 399 control_value |= (2 << 1) | 1; 400 401 // Iterate over stored hardware breakpoints 402 // Find a free bp_index or update reference count if duplicate. 403 bp_index = LLDB_INVALID_INDEX32; 404 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 405 if ((m_hbr_regs[i].control & 1) == 0) { 406 bp_index = i; // Mark last free slot 407 } else if (m_hbr_regs[i].address == addr && 408 m_hbr_regs[i].control == control_value) { 409 bp_index = i; // Mark duplicate index 410 break; // Stop searching here 411 } 412 } 413 414 if (bp_index == LLDB_INVALID_INDEX32) 415 return LLDB_INVALID_INDEX32; 416 417 // Add new or update existing breakpoint 418 if ((m_hbr_regs[bp_index].control & 1) == 0) { 419 m_hbr_regs[bp_index].address = addr; 420 m_hbr_regs[bp_index].control = control_value; 421 m_hbr_regs[bp_index].refcount = 1; 422 423 // PTRACE call to set corresponding hardware breakpoint register. 424 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 425 426 if (error.Fail()) { 427 m_hbr_regs[bp_index].address = 0; 428 m_hbr_regs[bp_index].control &= ~1; 429 m_hbr_regs[bp_index].refcount = 0; 430 431 return LLDB_INVALID_INDEX32; 432 } 433 } else 434 m_hbr_regs[bp_index].refcount++; 435 436 return bp_index; 437 } 438 439 bool NativeRegisterContextLinux_arm64::ClearHardwareBreakpoint( 440 uint32_t hw_idx) { 441 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 442 443 if (log) 444 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 445 446 Error error; 447 448 // Read hardware breakpoint and watchpoint information. 449 error = ReadHardwareDebugInfo(); 450 451 if (error.Fail()) 452 return false; 453 454 if (hw_idx >= m_max_hbp_supported) 455 return false; 456 457 // Update reference count if multiple references. 458 if (m_hbr_regs[hw_idx].refcount > 1) { 459 m_hbr_regs[hw_idx].refcount--; 460 return true; 461 } else if (m_hbr_regs[hw_idx].refcount == 1) { 462 // Create a backup we can revert to in case of failure. 463 lldb::addr_t tempAddr = m_hbr_regs[hw_idx].address; 464 uint32_t tempControl = m_hbr_regs[hw_idx].control; 465 uint32_t tempRefCount = m_hbr_regs[hw_idx].refcount; 466 467 m_hbr_regs[hw_idx].control &= ~1; 468 m_hbr_regs[hw_idx].address = 0; 469 m_hbr_regs[hw_idx].refcount = 0; 470 471 // PTRACE call to clear corresponding hardware breakpoint register. 472 WriteHardwareDebugRegs(eDREGTypeBREAK); 473 474 if (error.Fail()) { 475 m_hbr_regs[hw_idx].control = tempControl; 476 m_hbr_regs[hw_idx].address = tempAddr; 477 m_hbr_regs[hw_idx].refcount = tempRefCount; 478 479 return false; 480 } 481 482 return true; 483 } 484 485 return false; 486 } 487 488 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareWatchpoints() { 489 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 490 491 if (log) 492 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 493 494 Error error; 495 496 // Read hardware breakpoint and watchpoint information. 497 error = ReadHardwareDebugInfo(); 498 499 if (error.Fail()) 500 return 0; 501 502 return m_max_hwp_supported; 503 } 504 505 uint32_t NativeRegisterContextLinux_arm64::SetHardwareWatchpoint( 506 lldb::addr_t addr, size_t size, uint32_t watch_flags) { 507 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 508 509 if (log) 510 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 511 512 Error error; 513 514 // Read hardware breakpoint and watchpoint information. 515 error = ReadHardwareDebugInfo(); 516 517 if (error.Fail()) 518 return LLDB_INVALID_INDEX32; 519 520 uint32_t control_value = 0, wp_index = 0; 521 lldb::addr_t real_addr = addr; 522 523 // Check if we are setting watchpoint other than read/write/access 524 // Also update watchpoint flag to match AArch64 write-read bit configuration. 525 switch (watch_flags) { 526 case 1: 527 watch_flags = 2; 528 break; 529 case 2: 530 watch_flags = 1; 531 break; 532 case 3: 533 break; 534 default: 535 return LLDB_INVALID_INDEX32; 536 } 537 538 // Check if size has a valid hardware watchpoint length. 539 if (size != 1 && size != 2 && size != 4 && size != 8) 540 return LLDB_INVALID_INDEX32; 541 542 // Check 8-byte alignment for hardware watchpoint target address. 543 // Below is a hack to recalculate address and size in order to 544 // make sure we can watch non 8-byte alligned addresses as well. 545 if (addr & 0x07) { 546 uint8_t watch_mask = (addr & 0x07) + size; 547 548 if (watch_mask > 0x08) 549 return LLDB_INVALID_INDEX32; 550 else if (watch_mask <= 0x02) 551 size = 2; 552 else if (watch_mask <= 0x04) 553 size = 4; 554 else 555 size = 8; 556 557 addr = addr & (~0x07); 558 } 559 560 // Setup control value 561 control_value = watch_flags << 3; 562 control_value |= ((1 << size) - 1) << 5; 563 control_value |= (2 << 1) | 1; 564 565 // Iterate over stored watchpoints and find a free wp_index 566 wp_index = LLDB_INVALID_INDEX32; 567 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 568 if ((m_hwp_regs[i].control & 1) == 0) { 569 wp_index = i; // Mark last free slot 570 } else if (m_hwp_regs[i].address == addr) { 571 return LLDB_INVALID_INDEX32; // We do not support duplicate watchpoints. 572 } 573 } 574 575 if (wp_index == LLDB_INVALID_INDEX32) 576 return LLDB_INVALID_INDEX32; 577 578 // Update watchpoint in local cache 579 m_hwp_regs[wp_index].real_addr = real_addr; 580 m_hwp_regs[wp_index].address = addr; 581 m_hwp_regs[wp_index].control = control_value; 582 583 // PTRACE call to set corresponding watchpoint register. 584 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 585 586 if (error.Fail()) { 587 m_hwp_regs[wp_index].address = 0; 588 m_hwp_regs[wp_index].control &= ~1; 589 590 return LLDB_INVALID_INDEX32; 591 } 592 593 return wp_index; 594 } 595 596 bool NativeRegisterContextLinux_arm64::ClearHardwareWatchpoint( 597 uint32_t wp_index) { 598 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 599 600 if (log) 601 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 602 603 Error error; 604 605 // Read hardware breakpoint and watchpoint information. 606 error = ReadHardwareDebugInfo(); 607 608 if (error.Fail()) 609 return false; 610 611 if (wp_index >= m_max_hwp_supported) 612 return false; 613 614 // Create a backup we can revert to in case of failure. 615 lldb::addr_t tempAddr = m_hwp_regs[wp_index].address; 616 uint32_t tempControl = m_hwp_regs[wp_index].control; 617 618 // Update watchpoint in local cache 619 m_hwp_regs[wp_index].control &= ~1; 620 m_hwp_regs[wp_index].address = 0; 621 622 // Ptrace call to update hardware debug registers 623 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 624 625 if (error.Fail()) { 626 m_hwp_regs[wp_index].control = tempControl; 627 m_hwp_regs[wp_index].address = tempAddr; 628 629 return false; 630 } 631 632 return true; 633 } 634 635 Error NativeRegisterContextLinux_arm64::ClearAllHardwareWatchpoints() { 636 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 637 638 if (log) 639 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 640 641 Error error; 642 643 // Read hardware breakpoint and watchpoint information. 644 error = ReadHardwareDebugInfo(); 645 646 if (error.Fail()) 647 return error; 648 649 lldb::addr_t tempAddr = 0; 650 uint32_t tempControl = 0, tempRefCount = 0; 651 652 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 653 if (m_hwp_regs[i].control & 0x01) { 654 // Create a backup we can revert to in case of failure. 655 tempAddr = m_hwp_regs[i].address; 656 tempControl = m_hwp_regs[i].control; 657 658 // Clear watchpoints in local cache 659 m_hwp_regs[i].control &= ~1; 660 m_hwp_regs[i].address = 0; 661 662 // Ptrace call to update hardware debug registers 663 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 664 665 if (error.Fail()) { 666 m_hwp_regs[i].control = tempControl; 667 m_hwp_regs[i].address = tempAddr; 668 669 return error; 670 } 671 } 672 } 673 674 return Error(); 675 } 676 677 uint32_t 678 NativeRegisterContextLinux_arm64::GetWatchpointSize(uint32_t wp_index) { 679 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 680 681 if (log) 682 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 683 switch ((m_hwp_regs[wp_index].control >> 5) & 0xff) { 684 case 0x01: 685 return 1; 686 case 0x03: 687 return 2; 688 case 0x0f: 689 return 4; 690 case 0xff: 691 return 8; 692 default: 693 return 0; 694 } 695 } 696 bool NativeRegisterContextLinux_arm64::WatchpointIsEnabled(uint32_t wp_index) { 697 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 698 699 if (log) 700 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 701 702 if ((m_hwp_regs[wp_index].control & 0x1) == 0x1) 703 return true; 704 else 705 return false; 706 } 707 708 Error NativeRegisterContextLinux_arm64::GetWatchpointHitIndex( 709 uint32_t &wp_index, lldb::addr_t trap_addr) { 710 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 711 712 if (log) 713 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 714 715 uint32_t watch_size; 716 lldb::addr_t watch_addr; 717 718 for (wp_index = 0; wp_index < m_max_hwp_supported; ++wp_index) { 719 watch_size = GetWatchpointSize(wp_index); 720 watch_addr = m_hwp_regs[wp_index].address; 721 722 if (WatchpointIsEnabled(wp_index) && trap_addr >= watch_addr && 723 trap_addr < watch_addr + watch_size) { 724 m_hwp_regs[wp_index].hit_addr = trap_addr; 725 return Error(); 726 } 727 } 728 729 wp_index = LLDB_INVALID_INDEX32; 730 return Error(); 731 } 732 733 lldb::addr_t 734 NativeRegisterContextLinux_arm64::GetWatchpointAddress(uint32_t wp_index) { 735 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 736 737 if (log) 738 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 739 740 if (wp_index >= m_max_hwp_supported) 741 return LLDB_INVALID_ADDRESS; 742 743 if (WatchpointIsEnabled(wp_index)) 744 return m_hwp_regs[wp_index].real_addr; 745 else 746 return LLDB_INVALID_ADDRESS; 747 } 748 749 lldb::addr_t 750 NativeRegisterContextLinux_arm64::GetWatchpointHitAddress(uint32_t wp_index) { 751 Log *log(lldb_private::GetLogIfAllCategoriesSet(LIBLLDB_LOG_WATCHPOINTS)); 752 753 if (log) 754 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 755 756 if (wp_index >= m_max_hwp_supported) 757 return LLDB_INVALID_ADDRESS; 758 759 if (WatchpointIsEnabled(wp_index)) 760 return m_hwp_regs[wp_index].hit_addr; 761 else 762 return LLDB_INVALID_ADDRESS; 763 } 764 765 Error NativeRegisterContextLinux_arm64::ReadHardwareDebugInfo() { 766 if (!m_refresh_hwdebug_info) { 767 return Error(); 768 } 769 770 ::pid_t tid = m_thread.GetID(); 771 772 int regset = NT_ARM_HW_WATCH; 773 struct iovec ioVec; 774 struct user_hwdebug_state dreg_state; 775 Error error; 776 777 ioVec.iov_base = &dreg_state; 778 ioVec.iov_len = sizeof(dreg_state); 779 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 780 &ioVec, ioVec.iov_len); 781 782 if (error.Fail()) 783 return error; 784 785 m_max_hwp_supported = dreg_state.dbg_info & 0xff; 786 787 regset = NT_ARM_HW_BREAK; 788 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 789 &ioVec, ioVec.iov_len); 790 791 if (error.Fail()) 792 return error; 793 794 m_max_hbp_supported = dreg_state.dbg_info & 0xff; 795 m_refresh_hwdebug_info = false; 796 797 return error; 798 } 799 800 Error NativeRegisterContextLinux_arm64::WriteHardwareDebugRegs(int hwbType) { 801 struct iovec ioVec; 802 struct user_hwdebug_state dreg_state; 803 Error error; 804 805 memset(&dreg_state, 0, sizeof(dreg_state)); 806 ioVec.iov_base = &dreg_state; 807 808 if (hwbType == eDREGTypeWATCH) { 809 hwbType = NT_ARM_HW_WATCH; 810 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 811 (sizeof(dreg_state.dbg_regs[0]) * m_max_hwp_supported); 812 813 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 814 dreg_state.dbg_regs[i].addr = m_hwp_regs[i].address; 815 dreg_state.dbg_regs[i].ctrl = m_hwp_regs[i].control; 816 } 817 } else { 818 hwbType = NT_ARM_HW_BREAK; 819 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 820 (sizeof(dreg_state.dbg_regs[0]) * m_max_hbp_supported); 821 822 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 823 dreg_state.dbg_regs[i].addr = m_hbr_regs[i].address; 824 dreg_state.dbg_regs[i].ctrl = m_hbr_regs[i].control; 825 } 826 } 827 828 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 829 &hwbType, &ioVec, ioVec.iov_len); 830 } 831 832 Error NativeRegisterContextLinux_arm64::DoReadRegisterValue( 833 uint32_t offset, const char *reg_name, uint32_t size, 834 RegisterValue &value) { 835 Error error; 836 if (offset > sizeof(struct user_pt_regs)) { 837 uintptr_t offset = offset - sizeof(struct user_pt_regs); 838 if (offset > sizeof(struct user_fpsimd_state)) { 839 error.SetErrorString("invalid offset value"); 840 return error; 841 } 842 elf_fpregset_t regs; 843 int regset = NT_FPREGSET; 844 struct iovec ioVec; 845 846 ioVec.iov_base = ®s; 847 ioVec.iov_len = sizeof regs; 848 error = NativeProcessLinux::PtraceWrapper( 849 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 850 if (error.Success()) { 851 ArchSpec arch; 852 if (m_thread.GetProcess()->GetArchitecture(arch)) 853 value.SetBytes((void *)(((unsigned char *)(®s)) + offset), 16, 854 arch.GetByteOrder()); 855 else 856 error.SetErrorString("failed to get architecture"); 857 } 858 } else { 859 elf_gregset_t regs; 860 int regset = NT_PRSTATUS; 861 struct iovec ioVec; 862 863 ioVec.iov_base = ®s; 864 ioVec.iov_len = sizeof regs; 865 error = NativeProcessLinux::PtraceWrapper( 866 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 867 if (error.Success()) { 868 ArchSpec arch; 869 if (m_thread.GetProcess()->GetArchitecture(arch)) 870 value.SetBytes((void *)(((unsigned char *)(regs)) + offset), 8, 871 arch.GetByteOrder()); 872 else 873 error.SetErrorString("failed to get architecture"); 874 } 875 } 876 return error; 877 } 878 879 Error NativeRegisterContextLinux_arm64::DoWriteRegisterValue( 880 uint32_t offset, const char *reg_name, const RegisterValue &value) { 881 Error error; 882 ::pid_t tid = m_thread.GetID(); 883 if (offset > sizeof(struct user_pt_regs)) { 884 uintptr_t offset = offset - sizeof(struct user_pt_regs); 885 if (offset > sizeof(struct user_fpsimd_state)) { 886 error.SetErrorString("invalid offset value"); 887 return error; 888 } 889 elf_fpregset_t regs; 890 int regset = NT_FPREGSET; 891 struct iovec ioVec; 892 893 ioVec.iov_base = ®s; 894 ioVec.iov_len = sizeof regs; 895 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 896 &ioVec, sizeof regs); 897 898 if (error.Success()) { 899 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 900 16); 901 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 902 &ioVec, sizeof regs); 903 } 904 } else { 905 elf_gregset_t regs; 906 int regset = NT_PRSTATUS; 907 struct iovec ioVec; 908 909 ioVec.iov_base = ®s; 910 ioVec.iov_len = sizeof regs; 911 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 912 &ioVec, sizeof regs); 913 if (error.Success()) { 914 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 915 8); 916 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 917 &ioVec, sizeof regs); 918 } 919 } 920 return error; 921 } 922 923 Error NativeRegisterContextLinux_arm64::DoReadGPR(void *buf, size_t buf_size) { 924 int regset = NT_PRSTATUS; 925 struct iovec ioVec; 926 Error error; 927 928 ioVec.iov_base = buf; 929 ioVec.iov_len = buf_size; 930 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 931 ®set, &ioVec, buf_size); 932 } 933 934 Error NativeRegisterContextLinux_arm64::DoWriteGPR(void *buf, size_t buf_size) { 935 int regset = NT_PRSTATUS; 936 struct iovec ioVec; 937 Error error; 938 939 ioVec.iov_base = buf; 940 ioVec.iov_len = buf_size; 941 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 942 ®set, &ioVec, buf_size); 943 } 944 945 Error NativeRegisterContextLinux_arm64::DoReadFPR(void *buf, size_t buf_size) { 946 int regset = NT_FPREGSET; 947 struct iovec ioVec; 948 Error error; 949 950 ioVec.iov_base = buf; 951 ioVec.iov_len = buf_size; 952 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 953 ®set, &ioVec, buf_size); 954 } 955 956 Error NativeRegisterContextLinux_arm64::DoWriteFPR(void *buf, size_t buf_size) { 957 int regset = NT_FPREGSET; 958 struct iovec ioVec; 959 Error error; 960 961 ioVec.iov_base = buf; 962 ioVec.iov_len = buf_size; 963 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 964 ®set, &ioVec, buf_size); 965 } 966 967 uint32_t NativeRegisterContextLinux_arm64::CalculateFprOffset( 968 const RegisterInfo *reg_info) const { 969 return reg_info->byte_offset - 970 GetRegisterInfoAtIndex(m_reg_info.first_fpr)->byte_offset; 971 } 972 973 #endif // defined (__arm64__) || defined (__aarch64__) 974