1 //===-- NativeRegisterContextLinux_arm64.cpp --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #if defined(__arm64__) || defined(__aarch64__) 11 12 #include "NativeRegisterContextLinux_arm.h" 13 #include "NativeRegisterContextLinux_arm64.h" 14 15 // C Includes 16 // C++ Includes 17 18 // Other libraries and framework includes 19 #include "lldb/Core/RegisterValue.h" 20 #include "lldb/Host/common/NativeProcessProtocol.h" 21 #include "lldb/Utility/DataBufferHeap.h" 22 #include "lldb/Utility/Log.h" 23 #include "lldb/Utility/Status.h" 24 25 #include "Plugins/Process/Linux/NativeProcessLinux.h" 26 #include "Plugins/Process/Linux/Procfs.h" 27 #include "Plugins/Process/POSIX/ProcessPOSIXLog.h" 28 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" 29 30 // System includes - They have to be included after framework includes because 31 // they define some 32 // macros which collide with variable names in other modules 33 #include <sys/socket.h> 34 // NT_PRSTATUS and NT_FPREGSET definition 35 #include <elf.h> 36 // user_hwdebug_state definition 37 #include <asm/ptrace.h> 38 39 #define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize()) 40 41 using namespace lldb; 42 using namespace lldb_private; 43 using namespace lldb_private::process_linux; 44 45 // ARM64 general purpose registers. 46 static const uint32_t g_gpr_regnums_arm64[] = { 47 gpr_x0_arm64, gpr_x1_arm64, gpr_x2_arm64, gpr_x3_arm64, 48 gpr_x4_arm64, gpr_x5_arm64, gpr_x6_arm64, gpr_x7_arm64, 49 gpr_x8_arm64, gpr_x9_arm64, gpr_x10_arm64, gpr_x11_arm64, 50 gpr_x12_arm64, gpr_x13_arm64, gpr_x14_arm64, gpr_x15_arm64, 51 gpr_x16_arm64, gpr_x17_arm64, gpr_x18_arm64, gpr_x19_arm64, 52 gpr_x20_arm64, gpr_x21_arm64, gpr_x22_arm64, gpr_x23_arm64, 53 gpr_x24_arm64, gpr_x25_arm64, gpr_x26_arm64, gpr_x27_arm64, 54 gpr_x28_arm64, gpr_fp_arm64, gpr_lr_arm64, gpr_sp_arm64, 55 gpr_pc_arm64, gpr_cpsr_arm64, gpr_w0_arm64, gpr_w1_arm64, 56 gpr_w2_arm64, gpr_w3_arm64, gpr_w4_arm64, gpr_w5_arm64, 57 gpr_w6_arm64, gpr_w7_arm64, gpr_w8_arm64, gpr_w9_arm64, 58 gpr_w10_arm64, gpr_w11_arm64, gpr_w12_arm64, gpr_w13_arm64, 59 gpr_w14_arm64, gpr_w15_arm64, gpr_w16_arm64, gpr_w17_arm64, 60 gpr_w18_arm64, gpr_w19_arm64, gpr_w20_arm64, gpr_w21_arm64, 61 gpr_w22_arm64, gpr_w23_arm64, gpr_w24_arm64, gpr_w25_arm64, 62 gpr_w26_arm64, gpr_w27_arm64, gpr_w28_arm64, 63 LLDB_INVALID_REGNUM // register sets need to end with this flag 64 }; 65 static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) - 66 1) == k_num_gpr_registers_arm64, 67 "g_gpr_regnums_arm64 has wrong number of register infos"); 68 69 // ARM64 floating point registers. 70 static const uint32_t g_fpu_regnums_arm64[] = { 71 fpu_v0_arm64, fpu_v1_arm64, fpu_v2_arm64, fpu_v3_arm64, 72 fpu_v4_arm64, fpu_v5_arm64, fpu_v6_arm64, fpu_v7_arm64, 73 fpu_v8_arm64, fpu_v9_arm64, fpu_v10_arm64, fpu_v11_arm64, 74 fpu_v12_arm64, fpu_v13_arm64, fpu_v14_arm64, fpu_v15_arm64, 75 fpu_v16_arm64, fpu_v17_arm64, fpu_v18_arm64, fpu_v19_arm64, 76 fpu_v20_arm64, fpu_v21_arm64, fpu_v22_arm64, fpu_v23_arm64, 77 fpu_v24_arm64, fpu_v25_arm64, fpu_v26_arm64, fpu_v27_arm64, 78 fpu_v28_arm64, fpu_v29_arm64, fpu_v30_arm64, fpu_v31_arm64, 79 fpu_s0_arm64, fpu_s1_arm64, fpu_s2_arm64, fpu_s3_arm64, 80 fpu_s4_arm64, fpu_s5_arm64, fpu_s6_arm64, fpu_s7_arm64, 81 fpu_s8_arm64, fpu_s9_arm64, fpu_s10_arm64, fpu_s11_arm64, 82 fpu_s12_arm64, fpu_s13_arm64, fpu_s14_arm64, fpu_s15_arm64, 83 fpu_s16_arm64, fpu_s17_arm64, fpu_s18_arm64, fpu_s19_arm64, 84 fpu_s20_arm64, fpu_s21_arm64, fpu_s22_arm64, fpu_s23_arm64, 85 fpu_s24_arm64, fpu_s25_arm64, fpu_s26_arm64, fpu_s27_arm64, 86 fpu_s28_arm64, fpu_s29_arm64, fpu_s30_arm64, fpu_s31_arm64, 87 88 fpu_d0_arm64, fpu_d1_arm64, fpu_d2_arm64, fpu_d3_arm64, 89 fpu_d4_arm64, fpu_d5_arm64, fpu_d6_arm64, fpu_d7_arm64, 90 fpu_d8_arm64, fpu_d9_arm64, fpu_d10_arm64, fpu_d11_arm64, 91 fpu_d12_arm64, fpu_d13_arm64, fpu_d14_arm64, fpu_d15_arm64, 92 fpu_d16_arm64, fpu_d17_arm64, fpu_d18_arm64, fpu_d19_arm64, 93 fpu_d20_arm64, fpu_d21_arm64, fpu_d22_arm64, fpu_d23_arm64, 94 fpu_d24_arm64, fpu_d25_arm64, fpu_d26_arm64, fpu_d27_arm64, 95 fpu_d28_arm64, fpu_d29_arm64, fpu_d30_arm64, fpu_d31_arm64, 96 fpu_fpsr_arm64, fpu_fpcr_arm64, 97 LLDB_INVALID_REGNUM // register sets need to end with this flag 98 }; 99 static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) - 100 1) == k_num_fpr_registers_arm64, 101 "g_fpu_regnums_arm64 has wrong number of register infos"); 102 103 namespace { 104 // Number of register sets provided by this context. 105 enum { k_num_register_sets = 2 }; 106 } 107 108 // Register sets for ARM64. 109 static const RegisterSet g_reg_sets_arm64[k_num_register_sets] = { 110 {"General Purpose Registers", "gpr", k_num_gpr_registers_arm64, 111 g_gpr_regnums_arm64}, 112 {"Floating Point Registers", "fpu", k_num_fpr_registers_arm64, 113 g_fpu_regnums_arm64}}; 114 115 NativeRegisterContextLinux * 116 NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux( 117 const ArchSpec &target_arch, NativeThreadProtocol &native_thread, 118 uint32_t concrete_frame_idx) { 119 switch (target_arch.GetMachine()) { 120 case llvm::Triple::arm: 121 return new NativeRegisterContextLinux_arm(target_arch, native_thread, 122 concrete_frame_idx); 123 case llvm::Triple::aarch64: 124 return new NativeRegisterContextLinux_arm64(target_arch, native_thread, 125 concrete_frame_idx); 126 default: 127 llvm_unreachable("have no register context for architecture"); 128 } 129 } 130 131 NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64( 132 const ArchSpec &target_arch, NativeThreadProtocol &native_thread, 133 uint32_t concrete_frame_idx) 134 : NativeRegisterContextLinux(native_thread, concrete_frame_idx, 135 new RegisterInfoPOSIX_arm64(target_arch)) { 136 switch (target_arch.GetMachine()) { 137 case llvm::Triple::aarch64: 138 m_reg_info.num_registers = k_num_registers_arm64; 139 m_reg_info.num_gpr_registers = k_num_gpr_registers_arm64; 140 m_reg_info.num_fpr_registers = k_num_fpr_registers_arm64; 141 m_reg_info.last_gpr = k_last_gpr_arm64; 142 m_reg_info.first_fpr = k_first_fpr_arm64; 143 m_reg_info.last_fpr = k_last_fpr_arm64; 144 m_reg_info.first_fpr_v = fpu_v0_arm64; 145 m_reg_info.last_fpr_v = fpu_v31_arm64; 146 m_reg_info.gpr_flags = gpr_cpsr_arm64; 147 break; 148 default: 149 llvm_unreachable("Unhandled target architecture."); 150 break; 151 } 152 153 ::memset(&m_fpr, 0, sizeof(m_fpr)); 154 ::memset(&m_gpr_arm64, 0, sizeof(m_gpr_arm64)); 155 ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs)); 156 ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs)); 157 158 // 16 is just a maximum value, query hardware for actual watchpoint count 159 m_max_hwp_supported = 16; 160 m_max_hbp_supported = 16; 161 m_refresh_hwdebug_info = true; 162 } 163 164 uint32_t NativeRegisterContextLinux_arm64::GetRegisterSetCount() const { 165 return k_num_register_sets; 166 } 167 168 const RegisterSet * 169 NativeRegisterContextLinux_arm64::GetRegisterSet(uint32_t set_index) const { 170 if (set_index < k_num_register_sets) 171 return &g_reg_sets_arm64[set_index]; 172 173 return nullptr; 174 } 175 176 uint32_t NativeRegisterContextLinux_arm64::GetUserRegisterCount() const { 177 uint32_t count = 0; 178 for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index) 179 count += g_reg_sets_arm64[set_index].num_registers; 180 return count; 181 } 182 183 Status 184 NativeRegisterContextLinux_arm64::ReadRegister(const RegisterInfo *reg_info, 185 RegisterValue ®_value) { 186 Status error; 187 188 if (!reg_info) { 189 error.SetErrorString("reg_info NULL"); 190 return error; 191 } 192 193 const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; 194 195 if (IsFPR(reg)) { 196 error = ReadFPR(); 197 if (error.Fail()) 198 return error; 199 } else { 200 uint32_t full_reg = reg; 201 bool is_subreg = reg_info->invalidate_regs && 202 (reg_info->invalidate_regs[0] != LLDB_INVALID_REGNUM); 203 204 if (is_subreg) { 205 // Read the full aligned 64-bit register. 206 full_reg = reg_info->invalidate_regs[0]; 207 } 208 209 error = ReadRegisterRaw(full_reg, reg_value); 210 211 if (error.Success()) { 212 // If our read was not aligned (for ah,bh,ch,dh), shift our returned value 213 // one byte to the right. 214 if (is_subreg && (reg_info->byte_offset & 0x1)) 215 reg_value.SetUInt64(reg_value.GetAsUInt64() >> 8); 216 217 // If our return byte size was greater than the return value reg size, 218 // then 219 // use the type specified by reg_info rather than the uint64_t default 220 if (reg_value.GetByteSize() > reg_info->byte_size) 221 reg_value.SetType(reg_info); 222 } 223 return error; 224 } 225 226 // Get pointer to m_fpr variable and set the data from it. 227 uint32_t fpr_offset = CalculateFprOffset(reg_info); 228 assert(fpr_offset < sizeof m_fpr); 229 uint8_t *src = (uint8_t *)&m_fpr + fpr_offset; 230 reg_value.SetFromMemoryData(reg_info, src, reg_info->byte_size, 231 eByteOrderLittle, error); 232 233 return error; 234 } 235 236 Status NativeRegisterContextLinux_arm64::WriteRegister( 237 const RegisterInfo *reg_info, const RegisterValue ®_value) { 238 if (!reg_info) 239 return Status("reg_info NULL"); 240 241 const uint32_t reg_index = reg_info->kinds[lldb::eRegisterKindLLDB]; 242 if (reg_index == LLDB_INVALID_REGNUM) 243 return Status("no lldb regnum for %s", reg_info && reg_info->name 244 ? reg_info->name 245 : "<unknown register>"); 246 247 if (IsGPR(reg_index)) 248 return WriteRegisterRaw(reg_index, reg_value); 249 250 if (IsFPR(reg_index)) { 251 // Get pointer to m_fpr variable and set the data to it. 252 uint32_t fpr_offset = CalculateFprOffset(reg_info); 253 assert(fpr_offset < sizeof m_fpr); 254 uint8_t *dst = (uint8_t *)&m_fpr + fpr_offset; 255 switch (reg_info->byte_size) { 256 case 2: 257 *(uint16_t *)dst = reg_value.GetAsUInt16(); 258 break; 259 case 4: 260 *(uint32_t *)dst = reg_value.GetAsUInt32(); 261 break; 262 case 8: 263 *(uint64_t *)dst = reg_value.GetAsUInt64(); 264 break; 265 default: 266 assert(false && "Unhandled data size."); 267 return Status("unhandled register data size %" PRIu32, 268 reg_info->byte_size); 269 } 270 271 Status error = WriteFPR(); 272 if (error.Fail()) 273 return error; 274 275 return Status(); 276 } 277 278 return Status("failed - register wasn't recognized to be a GPR or an FPR, " 279 "write strategy unknown"); 280 } 281 282 Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues( 283 lldb::DataBufferSP &data_sp) { 284 Status error; 285 286 data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); 287 if (!data_sp) 288 return Status("failed to allocate DataBufferHeap instance of size %" PRIu64, 289 REG_CONTEXT_SIZE); 290 291 error = ReadGPR(); 292 if (error.Fail()) 293 return error; 294 295 error = ReadFPR(); 296 if (error.Fail()) 297 return error; 298 299 uint8_t *dst = data_sp->GetBytes(); 300 if (dst == nullptr) { 301 error.SetErrorStringWithFormat("DataBufferHeap instance of size %" PRIu64 302 " returned a null pointer", 303 REG_CONTEXT_SIZE); 304 return error; 305 } 306 307 ::memcpy(dst, &m_gpr_arm64, GetGPRSize()); 308 dst += GetGPRSize(); 309 ::memcpy(dst, &m_fpr, sizeof(m_fpr)); 310 311 return error; 312 } 313 314 Status NativeRegisterContextLinux_arm64::WriteAllRegisterValues( 315 const lldb::DataBufferSP &data_sp) { 316 Status error; 317 318 if (!data_sp) { 319 error.SetErrorStringWithFormat( 320 "NativeRegisterContextLinux_x86_64::%s invalid data_sp provided", 321 __FUNCTION__); 322 return error; 323 } 324 325 if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) { 326 error.SetErrorStringWithFormat( 327 "NativeRegisterContextLinux_x86_64::%s data_sp contained mismatched " 328 "data size, expected %" PRIu64 ", actual %" PRIu64, 329 __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize()); 330 return error; 331 } 332 333 uint8_t *src = data_sp->GetBytes(); 334 if (src == nullptr) { 335 error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s " 336 "DataBuffer::GetBytes() returned a null " 337 "pointer", 338 __FUNCTION__); 339 return error; 340 } 341 ::memcpy(&m_gpr_arm64, src, GetRegisterInfoInterface().GetGPRSize()); 342 343 error = WriteGPR(); 344 if (error.Fail()) 345 return error; 346 347 src += GetRegisterInfoInterface().GetGPRSize(); 348 ::memcpy(&m_fpr, src, sizeof(m_fpr)); 349 350 error = WriteFPR(); 351 if (error.Fail()) 352 return error; 353 354 return error; 355 } 356 357 bool NativeRegisterContextLinux_arm64::IsGPR(unsigned reg) const { 358 return reg <= m_reg_info.last_gpr; // GPR's come first. 359 } 360 361 bool NativeRegisterContextLinux_arm64::IsFPR(unsigned reg) const { 362 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr); 363 } 364 365 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareBreakpoints() { 366 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 367 368 if (log) 369 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 370 371 Status error; 372 373 // Read hardware breakpoint and watchpoint information. 374 error = ReadHardwareDebugInfo(); 375 376 if (error.Fail()) 377 return 0; 378 379 return m_max_hbp_supported; 380 } 381 382 uint32_t 383 NativeRegisterContextLinux_arm64::SetHardwareBreakpoint(lldb::addr_t addr, 384 size_t size) { 385 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 386 LLDB_LOG(log, "addr: {0:x}, size: {1:x}", addr, size); 387 388 // Read hardware breakpoint and watchpoint information. 389 Status error = ReadHardwareDebugInfo(); 390 391 if (error.Fail()) 392 return LLDB_INVALID_INDEX32; 393 394 uint32_t control_value = 0, bp_index = 0; 395 396 // Check if size has a valid hardware breakpoint length. 397 if (size != 4) 398 return LLDB_INVALID_INDEX32; // Invalid size for a AArch64 hardware 399 // breakpoint 400 401 // Check 4-byte alignment for hardware breakpoint target address. 402 if (addr & 0x03) 403 return LLDB_INVALID_INDEX32; // Invalid address, should be 4-byte aligned. 404 405 // Setup control value 406 control_value = 0; 407 control_value |= ((1 << size) - 1) << 5; 408 control_value |= (2 << 1) | 1; 409 410 // Iterate over stored breakpoints and find a free bp_index 411 bp_index = LLDB_INVALID_INDEX32; 412 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 413 if ((m_hbr_regs[i].control & 1) == 0) { 414 bp_index = i; // Mark last free slot 415 } else if (m_hbr_regs[i].address == addr) { 416 return LLDB_INVALID_INDEX32; // We do not support duplicate breakpoints. 417 } 418 } 419 420 if (bp_index == LLDB_INVALID_INDEX32) 421 return LLDB_INVALID_INDEX32; 422 423 // Update breakpoint in local cache 424 m_hbr_regs[bp_index].real_addr = addr; 425 m_hbr_regs[bp_index].address = addr; 426 m_hbr_regs[bp_index].control = control_value; 427 428 // PTRACE call to set corresponding hardware breakpoint register. 429 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 430 431 if (error.Fail()) { 432 m_hbr_regs[bp_index].address = 0; 433 m_hbr_regs[bp_index].control &= ~1; 434 435 return LLDB_INVALID_INDEX32; 436 } 437 438 return bp_index; 439 } 440 441 bool NativeRegisterContextLinux_arm64::ClearHardwareBreakpoint( 442 uint32_t hw_idx) { 443 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 444 LLDB_LOG(log, "hw_idx: {0}", hw_idx); 445 446 // Read hardware breakpoint and watchpoint information. 447 Status error = ReadHardwareDebugInfo(); 448 449 if (error.Fail()) 450 return false; 451 452 if (hw_idx >= m_max_hbp_supported) 453 return false; 454 455 // Create a backup we can revert to in case of failure. 456 lldb::addr_t tempAddr = m_hbr_regs[hw_idx].address; 457 uint32_t tempControl = m_hbr_regs[hw_idx].control; 458 459 m_hbr_regs[hw_idx].control &= ~1; 460 m_hbr_regs[hw_idx].address = 0; 461 462 // PTRACE call to clear corresponding hardware breakpoint register. 463 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 464 465 if (error.Fail()) { 466 m_hbr_regs[hw_idx].control = tempControl; 467 m_hbr_regs[hw_idx].address = tempAddr; 468 469 return false; 470 } 471 472 return true; 473 } 474 475 Status NativeRegisterContextLinux_arm64::GetHardwareBreakHitIndex( 476 uint32_t &bp_index, lldb::addr_t trap_addr) { 477 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 478 479 if (log) 480 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 481 482 lldb::addr_t break_addr; 483 484 for (bp_index = 0; bp_index < m_max_hbp_supported; ++bp_index) { 485 break_addr = m_hbr_regs[bp_index].address; 486 487 if ((m_hbr_regs[bp_index].control & 0x1) && (trap_addr == break_addr)) { 488 m_hbr_regs[bp_index].hit_addr = trap_addr; 489 return Status(); 490 } 491 } 492 493 bp_index = LLDB_INVALID_INDEX32; 494 return Status(); 495 } 496 497 Status NativeRegisterContextLinux_arm64::ClearAllHardwareBreakpoints() { 498 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_BREAKPOINTS)); 499 500 if (log) 501 log->Printf("NativeRegisterContextLinux_arm64::%s()", __FUNCTION__); 502 503 Status error; 504 505 // Read hardware breakpoint and watchpoint information. 506 error = ReadHardwareDebugInfo(); 507 508 if (error.Fail()) 509 return error; 510 511 lldb::addr_t tempAddr = 0; 512 uint32_t tempControl = 0; 513 514 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 515 if (m_hbr_regs[i].control & 0x01) { 516 // Create a backup we can revert to in case of failure. 517 tempAddr = m_hbr_regs[i].address; 518 tempControl = m_hbr_regs[i].control; 519 520 // Clear watchpoints in local cache 521 m_hbr_regs[i].control &= ~1; 522 m_hbr_regs[i].address = 0; 523 524 // Ptrace call to update hardware debug registers 525 error = WriteHardwareDebugRegs(eDREGTypeBREAK); 526 527 if (error.Fail()) { 528 m_hbr_regs[i].control = tempControl; 529 m_hbr_regs[i].address = tempAddr; 530 531 return error; 532 } 533 } 534 } 535 536 return Status(); 537 } 538 539 uint32_t NativeRegisterContextLinux_arm64::NumSupportedHardwareWatchpoints() { 540 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 541 542 // Read hardware breakpoint and watchpoint information. 543 Status error = ReadHardwareDebugInfo(); 544 545 if (error.Fail()) 546 return 0; 547 548 LLDB_LOG(log, "{0}", m_max_hwp_supported); 549 return m_max_hwp_supported; 550 } 551 552 uint32_t NativeRegisterContextLinux_arm64::SetHardwareWatchpoint( 553 lldb::addr_t addr, size_t size, uint32_t watch_flags) { 554 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 555 LLDB_LOG(log, "addr: {0:x}, size: {1:x} watch_flags: {2:x}", addr, size, 556 watch_flags); 557 558 // Read hardware breakpoint and watchpoint information. 559 Status error = ReadHardwareDebugInfo(); 560 561 if (error.Fail()) 562 return LLDB_INVALID_INDEX32; 563 564 uint32_t control_value = 0, wp_index = 0; 565 lldb::addr_t real_addr = addr; 566 567 // Check if we are setting watchpoint other than read/write/access 568 // Also update watchpoint flag to match AArch64 write-read bit configuration. 569 switch (watch_flags) { 570 case 1: 571 watch_flags = 2; 572 break; 573 case 2: 574 watch_flags = 1; 575 break; 576 case 3: 577 break; 578 default: 579 return LLDB_INVALID_INDEX32; 580 } 581 582 // Check if size has a valid hardware watchpoint length. 583 if (size != 1 && size != 2 && size != 4 && size != 8) 584 return LLDB_INVALID_INDEX32; 585 586 // Check 8-byte alignment for hardware watchpoint target address. 587 // Below is a hack to recalculate address and size in order to 588 // make sure we can watch non 8-byte alligned addresses as well. 589 if (addr & 0x07) { 590 uint8_t watch_mask = (addr & 0x07) + size; 591 592 if (watch_mask > 0x08) 593 return LLDB_INVALID_INDEX32; 594 else if (watch_mask <= 0x02) 595 size = 2; 596 else if (watch_mask <= 0x04) 597 size = 4; 598 else 599 size = 8; 600 601 addr = addr & (~0x07); 602 } 603 604 // Setup control value 605 control_value = watch_flags << 3; 606 control_value |= ((1 << size) - 1) << 5; 607 control_value |= (2 << 1) | 1; 608 609 // Iterate over stored watchpoints and find a free wp_index 610 wp_index = LLDB_INVALID_INDEX32; 611 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 612 if ((m_hwp_regs[i].control & 1) == 0) { 613 wp_index = i; // Mark last free slot 614 } else if (m_hwp_regs[i].address == addr) { 615 return LLDB_INVALID_INDEX32; // We do not support duplicate watchpoints. 616 } 617 } 618 619 if (wp_index == LLDB_INVALID_INDEX32) 620 return LLDB_INVALID_INDEX32; 621 622 // Update watchpoint in local cache 623 m_hwp_regs[wp_index].real_addr = real_addr; 624 m_hwp_regs[wp_index].address = addr; 625 m_hwp_regs[wp_index].control = control_value; 626 627 // PTRACE call to set corresponding watchpoint register. 628 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 629 630 if (error.Fail()) { 631 m_hwp_regs[wp_index].address = 0; 632 m_hwp_regs[wp_index].control &= ~1; 633 634 return LLDB_INVALID_INDEX32; 635 } 636 637 return wp_index; 638 } 639 640 bool NativeRegisterContextLinux_arm64::ClearHardwareWatchpoint( 641 uint32_t wp_index) { 642 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 643 LLDB_LOG(log, "wp_index: {0}", wp_index); 644 645 // Read hardware breakpoint and watchpoint information. 646 Status error = ReadHardwareDebugInfo(); 647 648 if (error.Fail()) 649 return false; 650 651 if (wp_index >= m_max_hwp_supported) 652 return false; 653 654 // Create a backup we can revert to in case of failure. 655 lldb::addr_t tempAddr = m_hwp_regs[wp_index].address; 656 uint32_t tempControl = m_hwp_regs[wp_index].control; 657 658 // Update watchpoint in local cache 659 m_hwp_regs[wp_index].control &= ~1; 660 m_hwp_regs[wp_index].address = 0; 661 662 // Ptrace call to update hardware debug registers 663 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 664 665 if (error.Fail()) { 666 m_hwp_regs[wp_index].control = tempControl; 667 m_hwp_regs[wp_index].address = tempAddr; 668 669 return false; 670 } 671 672 return true; 673 } 674 675 Status NativeRegisterContextLinux_arm64::ClearAllHardwareWatchpoints() { 676 // Read hardware breakpoint and watchpoint information. 677 Status error = ReadHardwareDebugInfo(); 678 679 if (error.Fail()) 680 return error; 681 682 lldb::addr_t tempAddr = 0; 683 uint32_t tempControl = 0; 684 685 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 686 if (m_hwp_regs[i].control & 0x01) { 687 // Create a backup we can revert to in case of failure. 688 tempAddr = m_hwp_regs[i].address; 689 tempControl = m_hwp_regs[i].control; 690 691 // Clear watchpoints in local cache 692 m_hwp_regs[i].control &= ~1; 693 m_hwp_regs[i].address = 0; 694 695 // Ptrace call to update hardware debug registers 696 error = WriteHardwareDebugRegs(eDREGTypeWATCH); 697 698 if (error.Fail()) { 699 m_hwp_regs[i].control = tempControl; 700 m_hwp_regs[i].address = tempAddr; 701 702 return error; 703 } 704 } 705 } 706 707 return Status(); 708 } 709 710 uint32_t 711 NativeRegisterContextLinux_arm64::GetWatchpointSize(uint32_t wp_index) { 712 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 713 LLDB_LOG(log, "wp_index: {0}", wp_index); 714 715 switch ((m_hwp_regs[wp_index].control >> 5) & 0xff) { 716 case 0x01: 717 return 1; 718 case 0x03: 719 return 2; 720 case 0x0f: 721 return 4; 722 case 0xff: 723 return 8; 724 default: 725 return 0; 726 } 727 } 728 bool NativeRegisterContextLinux_arm64::WatchpointIsEnabled(uint32_t wp_index) { 729 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 730 LLDB_LOG(log, "wp_index: {0}", wp_index); 731 732 if ((m_hwp_regs[wp_index].control & 0x1) == 0x1) 733 return true; 734 else 735 return false; 736 } 737 738 Status NativeRegisterContextLinux_arm64::GetWatchpointHitIndex( 739 uint32_t &wp_index, lldb::addr_t trap_addr) { 740 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 741 LLDB_LOG(log, "wp_index: {0}, trap_addr: {1:x}", wp_index, trap_addr); 742 743 uint32_t watch_size; 744 lldb::addr_t watch_addr; 745 746 for (wp_index = 0; wp_index < m_max_hwp_supported; ++wp_index) { 747 watch_size = GetWatchpointSize(wp_index); 748 watch_addr = m_hwp_regs[wp_index].address; 749 750 if (WatchpointIsEnabled(wp_index) && trap_addr >= watch_addr && 751 trap_addr < watch_addr + watch_size) { 752 m_hwp_regs[wp_index].hit_addr = trap_addr; 753 return Status(); 754 } 755 } 756 757 wp_index = LLDB_INVALID_INDEX32; 758 return Status(); 759 } 760 761 lldb::addr_t 762 NativeRegisterContextLinux_arm64::GetWatchpointAddress(uint32_t wp_index) { 763 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 764 LLDB_LOG(log, "wp_index: {0}", wp_index); 765 766 if (wp_index >= m_max_hwp_supported) 767 return LLDB_INVALID_ADDRESS; 768 769 if (WatchpointIsEnabled(wp_index)) 770 return m_hwp_regs[wp_index].real_addr; 771 else 772 return LLDB_INVALID_ADDRESS; 773 } 774 775 lldb::addr_t 776 NativeRegisterContextLinux_arm64::GetWatchpointHitAddress(uint32_t wp_index) { 777 Log *log(ProcessPOSIXLog::GetLogIfAllCategoriesSet(POSIX_LOG_WATCHPOINTS)); 778 LLDB_LOG(log, "wp_index: {0}", wp_index); 779 780 if (wp_index >= m_max_hwp_supported) 781 return LLDB_INVALID_ADDRESS; 782 783 if (WatchpointIsEnabled(wp_index)) 784 return m_hwp_regs[wp_index].hit_addr; 785 else 786 return LLDB_INVALID_ADDRESS; 787 } 788 789 Status NativeRegisterContextLinux_arm64::ReadHardwareDebugInfo() { 790 if (!m_refresh_hwdebug_info) { 791 return Status(); 792 } 793 794 ::pid_t tid = m_thread.GetID(); 795 796 int regset = NT_ARM_HW_WATCH; 797 struct iovec ioVec; 798 struct user_hwdebug_state dreg_state; 799 Status error; 800 801 ioVec.iov_base = &dreg_state; 802 ioVec.iov_len = sizeof(dreg_state); 803 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 804 &ioVec, ioVec.iov_len); 805 806 if (error.Fail()) 807 return error; 808 809 m_max_hwp_supported = dreg_state.dbg_info & 0xff; 810 811 regset = NT_ARM_HW_BREAK; 812 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 813 &ioVec, ioVec.iov_len); 814 815 if (error.Fail()) 816 return error; 817 818 m_max_hbp_supported = dreg_state.dbg_info & 0xff; 819 m_refresh_hwdebug_info = false; 820 821 return error; 822 } 823 824 Status NativeRegisterContextLinux_arm64::WriteHardwareDebugRegs(int hwbType) { 825 struct iovec ioVec; 826 struct user_hwdebug_state dreg_state; 827 Status error; 828 829 memset(&dreg_state, 0, sizeof(dreg_state)); 830 ioVec.iov_base = &dreg_state; 831 832 if (hwbType == eDREGTypeWATCH) { 833 hwbType = NT_ARM_HW_WATCH; 834 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 835 (sizeof(dreg_state.dbg_regs[0]) * m_max_hwp_supported); 836 837 for (uint32_t i = 0; i < m_max_hwp_supported; i++) { 838 dreg_state.dbg_regs[i].addr = m_hwp_regs[i].address; 839 dreg_state.dbg_regs[i].ctrl = m_hwp_regs[i].control; 840 } 841 } else { 842 hwbType = NT_ARM_HW_BREAK; 843 ioVec.iov_len = sizeof(dreg_state.dbg_info) + sizeof(dreg_state.pad) + 844 (sizeof(dreg_state.dbg_regs[0]) * m_max_hbp_supported); 845 846 for (uint32_t i = 0; i < m_max_hbp_supported; i++) { 847 dreg_state.dbg_regs[i].addr = m_hbr_regs[i].address; 848 dreg_state.dbg_regs[i].ctrl = m_hbr_regs[i].control; 849 } 850 } 851 852 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 853 &hwbType, &ioVec, ioVec.iov_len); 854 } 855 856 Status NativeRegisterContextLinux_arm64::DoReadRegisterValue( 857 uint32_t offset, const char *reg_name, uint32_t size, 858 RegisterValue &value) { 859 Status error; 860 if (offset > sizeof(struct user_pt_regs)) { 861 offset -= sizeof(struct user_pt_regs); 862 if (offset > sizeof(struct user_fpsimd_state)) { 863 error.SetErrorString("invalid offset value"); 864 return error; 865 } 866 elf_fpregset_t regs; 867 int regset = NT_FPREGSET; 868 struct iovec ioVec; 869 870 ioVec.iov_base = ®s; 871 ioVec.iov_len = sizeof regs; 872 error = NativeProcessLinux::PtraceWrapper( 873 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 874 if (error.Success()) { 875 ArchSpec arch; 876 if (m_thread.GetProcess().GetArchitecture(arch)) 877 value.SetBytes((void *)(((unsigned char *)(®s)) + offset), 16, 878 arch.GetByteOrder()); 879 else 880 error.SetErrorString("failed to get architecture"); 881 } 882 } else { 883 elf_gregset_t regs; 884 int regset = NT_PRSTATUS; 885 struct iovec ioVec; 886 887 ioVec.iov_base = ®s; 888 ioVec.iov_len = sizeof regs; 889 error = NativeProcessLinux::PtraceWrapper( 890 PTRACE_GETREGSET, m_thread.GetID(), ®set, &ioVec, sizeof regs); 891 if (error.Success()) { 892 ArchSpec arch; 893 if (m_thread.GetProcess().GetArchitecture(arch)) 894 value.SetBytes((void *)(((unsigned char *)(regs)) + offset), 8, 895 arch.GetByteOrder()); 896 else 897 error.SetErrorString("failed to get architecture"); 898 } 899 } 900 return error; 901 } 902 903 Status NativeRegisterContextLinux_arm64::DoWriteRegisterValue( 904 uint32_t offset, const char *reg_name, const RegisterValue &value) { 905 Status error; 906 ::pid_t tid = m_thread.GetID(); 907 if (offset > sizeof(struct user_pt_regs)) { 908 offset -= sizeof(struct user_pt_regs); 909 if (offset > sizeof(struct user_fpsimd_state)) { 910 error.SetErrorString("invalid offset value"); 911 return error; 912 } 913 elf_fpregset_t regs; 914 int regset = NT_FPREGSET; 915 struct iovec ioVec; 916 917 ioVec.iov_base = ®s; 918 ioVec.iov_len = sizeof regs; 919 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 920 &ioVec, sizeof regs); 921 922 if (error.Success()) { 923 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 924 16); 925 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 926 &ioVec, sizeof regs); 927 } 928 } else { 929 elf_gregset_t regs; 930 int regset = NT_PRSTATUS; 931 struct iovec ioVec; 932 933 ioVec.iov_base = ®s; 934 ioVec.iov_len = sizeof regs; 935 error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, ®set, 936 &ioVec, sizeof regs); 937 if (error.Success()) { 938 ::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 939 8); 940 error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, tid, ®set, 941 &ioVec, sizeof regs); 942 } 943 } 944 return error; 945 } 946 947 Status NativeRegisterContextLinux_arm64::DoReadGPR(void *buf, size_t buf_size) { 948 int regset = NT_PRSTATUS; 949 struct iovec ioVec; 950 Status error; 951 952 ioVec.iov_base = buf; 953 ioVec.iov_len = buf_size; 954 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 955 ®set, &ioVec, buf_size); 956 } 957 958 Status NativeRegisterContextLinux_arm64::DoWriteGPR(void *buf, 959 size_t buf_size) { 960 int regset = NT_PRSTATUS; 961 struct iovec ioVec; 962 Status error; 963 964 ioVec.iov_base = buf; 965 ioVec.iov_len = buf_size; 966 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 967 ®set, &ioVec, buf_size); 968 } 969 970 Status NativeRegisterContextLinux_arm64::DoReadFPR(void *buf, size_t buf_size) { 971 int regset = NT_FPREGSET; 972 struct iovec ioVec; 973 Status error; 974 975 ioVec.iov_base = buf; 976 ioVec.iov_len = buf_size; 977 return NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, m_thread.GetID(), 978 ®set, &ioVec, buf_size); 979 } 980 981 Status NativeRegisterContextLinux_arm64::DoWriteFPR(void *buf, 982 size_t buf_size) { 983 int regset = NT_FPREGSET; 984 struct iovec ioVec; 985 Status error; 986 987 ioVec.iov_base = buf; 988 ioVec.iov_len = buf_size; 989 return NativeProcessLinux::PtraceWrapper(PTRACE_SETREGSET, m_thread.GetID(), 990 ®set, &ioVec, buf_size); 991 } 992 993 uint32_t NativeRegisterContextLinux_arm64::CalculateFprOffset( 994 const RegisterInfo *reg_info) const { 995 return reg_info->byte_offset - 996 GetRegisterInfoAtIndex(m_reg_info.first_fpr)->byte_offset; 997 } 998 999 #endif // defined (__arm64__) || defined (__aarch64__) 1000