1 //===-- EmulateInstructionARM64.cpp ------------------------------*- C++-*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "EmulateInstructionARM64.h" 11 12 #include <stdlib.h> 13 14 #include "lldb/Core/Address.h" 15 #include "lldb/Core/ArchSpec.h" 16 #include "lldb/Core/PluginManager.h" 17 #include "lldb/Core/RegisterValue.h" 18 #include "lldb/Symbol/UnwindPlan.h" 19 #include "lldb/Utility/ConstString.h" 20 #include "lldb/Utility/Stream.h" 21 22 #include "Plugins/Process/Utility/ARMDefines.h" 23 #include "Plugins/Process/Utility/ARMUtils.h" 24 #include "Plugins/Process/Utility/lldb-arm64-register-enums.h" 25 26 #define GPR_OFFSET(idx) ((idx)*8) 27 #define GPR_OFFSET_NAME(reg) 0 28 #define FPU_OFFSET(idx) ((idx)*16) 29 #define FPU_OFFSET_NAME(reg) 0 30 #define EXC_OFFSET_NAME(reg) 0 31 #define DBG_OFFSET_NAME(reg) 0 32 #define DBG_OFFSET_NAME(reg) 0 33 #define DEFINE_DBG(re, y) \ 34 "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \ 35 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 36 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM}, \ 37 nullptr, nullptr, nullptr, 0 38 39 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 40 41 #include "Plugins/Process/Utility/RegisterInfos_arm64.h" 42 43 #include "llvm/ADT/STLExtras.h" 44 #include "llvm/Support/MathExtras.h" // for SignExtend32 template function 45 // and CountTrailingZeros_32 function 46 47 #include "Plugins/Process/Utility/InstructionUtils.h" 48 49 using namespace lldb; 50 using namespace lldb_private; 51 52 static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo ®_info) { 53 if (reg_num >= llvm::array_lengthof(g_register_infos_arm64_le)) 54 return false; 55 reg_info = g_register_infos_arm64_le[reg_num]; 56 return true; 57 } 58 59 #define No_VFP 0 60 #define VFPv1 (1u << 1) 61 #define VFPv2 (1u << 2) 62 #define VFPv3 (1u << 3) 63 #define AdvancedSIMD (1u << 4) 64 65 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD) 66 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD) 67 #define VFPv2v3 (VFPv2 | VFPv3) 68 69 #define UInt(x) ((uint64_t)x) 70 #define SInt(x) ((int64_t)x) 71 #define bit bool 72 #define boolean bool 73 #define integer int64_t 74 75 static inline bool IsZero(uint64_t x) { return x == 0; } 76 77 static inline uint64_t NOT(uint64_t x) { return ~x; } 78 79 #if 0 80 // LSL_C() 81 // ======= 82 static inline uint64_t 83 LSL_C (uint64_t x, integer shift, bool &carry_out) 84 { 85 assert (shift >= 0); 86 uint64_t result = x << shift; 87 carry_out = ((1ull << (64-1)) >> (shift - 1)) != 0; 88 return result; 89 } 90 #endif 91 92 // LSL() 93 // ===== 94 95 static inline uint64_t LSL(uint64_t x, integer shift) { 96 if (shift == 0) 97 return x; 98 return x << shift; 99 } 100 101 // AddWithCarry() 102 // =============== 103 static inline uint64_t 104 AddWithCarry(uint32_t N, uint64_t x, uint64_t y, bit carry_in, 105 EmulateInstructionARM64::ProcState &proc_state) { 106 uint64_t unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in); 107 int64_t signed_sum = SInt(x) + SInt(y) + UInt(carry_in); 108 uint64_t result = unsigned_sum; 109 if (N < 64) 110 result = Bits64(result, N - 1, 0); 111 proc_state.N = Bit64(result, N - 1); 112 proc_state.Z = IsZero(result); 113 proc_state.C = UInt(result) == unsigned_sum; 114 proc_state.V = SInt(result) == signed_sum; 115 return result; 116 } 117 118 // ConstrainUnpredictable() 119 // ======================== 120 121 EmulateInstructionARM64::ConstraintType 122 ConstrainUnpredictable(EmulateInstructionARM64::Unpredictable which) { 123 EmulateInstructionARM64::ConstraintType result = 124 EmulateInstructionARM64::Constraint_UNKNOWN; 125 switch (which) { 126 case EmulateInstructionARM64::Unpredictable_WBOVERLAP: 127 case EmulateInstructionARM64::Unpredictable_LDPOVERLAP: 128 // TODO: don't know what to really do here? Pseudo code says: 129 // set result to one of above Constraint behaviours or UNDEFINED 130 break; 131 } 132 return result; 133 } 134 135 //---------------------------------------------------------------------- 136 // 137 // EmulateInstructionARM implementation 138 // 139 //---------------------------------------------------------------------- 140 141 void EmulateInstructionARM64::Initialize() { 142 PluginManager::RegisterPlugin(GetPluginNameStatic(), 143 GetPluginDescriptionStatic(), CreateInstance); 144 } 145 146 void EmulateInstructionARM64::Terminate() { 147 PluginManager::UnregisterPlugin(CreateInstance); 148 } 149 150 ConstString EmulateInstructionARM64::GetPluginNameStatic() { 151 ConstString g_plugin_name("lldb.emulate-instruction.arm64"); 152 return g_plugin_name; 153 } 154 155 lldb_private::ConstString EmulateInstructionARM64::GetPluginName() { 156 static ConstString g_plugin_name("EmulateInstructionARM64"); 157 return g_plugin_name; 158 } 159 160 const char *EmulateInstructionARM64::GetPluginDescriptionStatic() { 161 return "Emulate instructions for the ARM64 architecture."; 162 } 163 164 EmulateInstruction * 165 EmulateInstructionARM64::CreateInstance(const ArchSpec &arch, 166 InstructionType inst_type) { 167 if (EmulateInstructionARM64::SupportsEmulatingInstructionsOfTypeStatic( 168 inst_type)) { 169 if (arch.GetTriple().getArch() == llvm::Triple::aarch64) { 170 std::auto_ptr<EmulateInstructionARM64> emulate_insn_ap( 171 new EmulateInstructionARM64(arch)); 172 if (emulate_insn_ap.get()) 173 return emulate_insn_ap.release(); 174 } 175 } 176 177 return NULL; 178 } 179 180 bool EmulateInstructionARM64::SetTargetTriple(const ArchSpec &arch) { 181 if (arch.GetTriple().getArch() == llvm::Triple::arm) 182 return true; 183 else if (arch.GetTriple().getArch() == llvm::Triple::thumb) 184 return true; 185 186 return false; 187 } 188 189 bool EmulateInstructionARM64::GetRegisterInfo(RegisterKind reg_kind, 190 uint32_t reg_num, 191 RegisterInfo ®_info) { 192 if (reg_kind == eRegisterKindGeneric) { 193 switch (reg_num) { 194 case LLDB_REGNUM_GENERIC_PC: 195 reg_kind = eRegisterKindLLDB; 196 reg_num = gpr_pc_arm64; 197 break; 198 case LLDB_REGNUM_GENERIC_SP: 199 reg_kind = eRegisterKindLLDB; 200 reg_num = gpr_sp_arm64; 201 break; 202 case LLDB_REGNUM_GENERIC_FP: 203 reg_kind = eRegisterKindLLDB; 204 reg_num = gpr_fp_arm64; 205 break; 206 case LLDB_REGNUM_GENERIC_RA: 207 reg_kind = eRegisterKindLLDB; 208 reg_num = gpr_lr_arm64; 209 break; 210 case LLDB_REGNUM_GENERIC_FLAGS: 211 reg_kind = eRegisterKindLLDB; 212 reg_num = gpr_cpsr_arm64; 213 break; 214 215 default: 216 return false; 217 } 218 } 219 220 if (reg_kind == eRegisterKindLLDB) 221 return LLDBTableGetRegisterInfo(reg_num, reg_info); 222 return false; 223 } 224 225 EmulateInstructionARM64::Opcode * 226 EmulateInstructionARM64::GetOpcodeForInstruction(const uint32_t opcode) { 227 static EmulateInstructionARM64::Opcode g_opcodes[] = { 228 //---------------------------------------------------------------------- 229 // Prologue instructions 230 //---------------------------------------------------------------------- 231 232 // push register(s) 233 {0xff000000, 0xd1000000, No_VFP, 234 &EmulateInstructionARM64::EmulateADDSUBImm, 235 "SUB <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"}, 236 {0xff000000, 0xf1000000, No_VFP, 237 &EmulateInstructionARM64::EmulateADDSUBImm, 238 "SUBS <Xd>, <Xn|SP>, #<imm> {, <shift>}"}, 239 {0xff000000, 0x91000000, No_VFP, 240 &EmulateInstructionARM64::EmulateADDSUBImm, 241 "ADD <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"}, 242 {0xff000000, 0xb1000000, No_VFP, 243 &EmulateInstructionARM64::EmulateADDSUBImm, 244 "ADDS <Xd>, <Xn|SP>, #<imm> {, <shift>}"}, 245 246 {0xff000000, 0x51000000, No_VFP, 247 &EmulateInstructionARM64::EmulateADDSUBImm, 248 "SUB <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"}, 249 {0xff000000, 0x71000000, No_VFP, 250 &EmulateInstructionARM64::EmulateADDSUBImm, 251 "SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"}, 252 {0xff000000, 0x11000000, No_VFP, 253 &EmulateInstructionARM64::EmulateADDSUBImm, 254 "ADD <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"}, 255 {0xff000000, 0x31000000, No_VFP, 256 &EmulateInstructionARM64::EmulateADDSUBImm, 257 "ADDS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"}, 258 259 {0xffc00000, 0x29000000, No_VFP, 260 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 261 "STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"}, 262 {0xffc00000, 0xa9000000, No_VFP, 263 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 264 "STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"}, 265 {0xffc00000, 0x2d000000, No_VFP, 266 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 267 "STP <St>, <St2>, [<Xn|SP>{, #<imm>}]"}, 268 {0xffc00000, 0x6d000000, No_VFP, 269 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 270 "STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"}, 271 {0xffc00000, 0xad000000, No_VFP, 272 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 273 "STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"}, 274 275 {0xffc00000, 0x29800000, No_VFP, 276 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 277 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 278 {0xffc00000, 0xa9800000, No_VFP, 279 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 280 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 281 {0xffc00000, 0x2d800000, No_VFP, 282 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 283 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 284 {0xffc00000, 0x6d800000, No_VFP, 285 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 286 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 287 {0xffc00000, 0xad800000, No_VFP, 288 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 289 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 290 291 {0xffc00000, 0x28800000, No_VFP, 292 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 293 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 294 {0xffc00000, 0xa8800000, No_VFP, 295 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 296 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 297 {0xffc00000, 0x2c800000, No_VFP, 298 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 299 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 300 {0xffc00000, 0x6c800000, No_VFP, 301 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 302 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 303 {0xffc00000, 0xac800000, No_VFP, 304 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 305 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 306 307 {0xffc00000, 0x29400000, No_VFP, 308 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 309 "LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"}, 310 {0xffc00000, 0xa9400000, No_VFP, 311 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 312 "LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"}, 313 {0xffc00000, 0x2d400000, No_VFP, 314 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 315 "LDP <St>, <St2>, [<Xn|SP>{, #<imm>}]"}, 316 {0xffc00000, 0x6d400000, No_VFP, 317 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 318 "LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"}, 319 {0xffc00000, 0xad400000, No_VFP, 320 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 321 "LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"}, 322 323 {0xffc00000, 0x29c00000, No_VFP, 324 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 325 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 326 {0xffc00000, 0xa9c00000, No_VFP, 327 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 328 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 329 {0xffc00000, 0x2dc00000, No_VFP, 330 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 331 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 332 {0xffc00000, 0x6dc00000, No_VFP, 333 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 334 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 335 {0xffc00000, 0xadc00000, No_VFP, 336 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 337 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 338 339 {0xffc00000, 0x28c00000, No_VFP, 340 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 341 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 342 {0xffc00000, 0xa8c00000, No_VFP, 343 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 344 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 345 {0xffc00000, 0x2cc00000, No_VFP, 346 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 347 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 348 {0xffc00000, 0x6cc00000, No_VFP, 349 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 350 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 351 {0xffc00000, 0xacc00000, No_VFP, 352 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 353 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 354 355 {0xffe00c00, 0xb8000400, No_VFP, 356 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 357 "STR <Wt>, [<Xn|SP>], #<simm>"}, 358 {0xffe00c00, 0xf8000400, No_VFP, 359 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 360 "STR <Xt>, [<Xn|SP>], #<simm>"}, 361 {0xffe00c00, 0xb8000c00, No_VFP, 362 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 363 "STR <Wt>, [<Xn|SP>, #<simm>]!"}, 364 {0xffe00c00, 0xf8000c00, No_VFP, 365 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 366 "STR <Xt>, [<Xn|SP>, #<simm>]!"}, 367 {0xffc00000, 0xb9000000, No_VFP, 368 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 369 "STR <Wt>, [<Xn|SP>{, #<pimm>}]"}, 370 {0xffc00000, 0xf9000000, No_VFP, 371 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 372 "STR <Xt>, [<Xn|SP>{, #<pimm>}]"}, 373 374 {0xffe00c00, 0xb8400400, No_VFP, 375 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 376 "LDR <Wt>, [<Xn|SP>], #<simm>"}, 377 {0xffe00c00, 0xf8400400, No_VFP, 378 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 379 "LDR <Xt>, [<Xn|SP>], #<simm>"}, 380 {0xffe00c00, 0xb8400c00, No_VFP, 381 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 382 "LDR <Wt>, [<Xn|SP>, #<simm>]!"}, 383 {0xffe00c00, 0xf8400c00, No_VFP, 384 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 385 "LDR <Xt>, [<Xn|SP>, #<simm>]!"}, 386 {0xffc00000, 0xb9400000, No_VFP, 387 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 388 "LDR <Wt>, [<Xn|SP>{, #<pimm>}]"}, 389 {0xffc00000, 0xf9400000, No_VFP, 390 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 391 "LDR <Xt>, [<Xn|SP>{, #<pimm>}]"}, 392 393 {0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB, 394 "B <label>"}, 395 {0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond, 396 "B.<cond> <label>"}, 397 {0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, 398 "CBZ <Wt>, <label>"}, 399 {0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, 400 "CBNZ <Wt>, <label>"}, 401 {0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, 402 "TBZ <R><t>, #<imm>, <label>"}, 403 {0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, 404 "TBNZ <R><t>, #<imm>, <label>"}, 405 406 }; 407 static const size_t k_num_arm_opcodes = llvm::array_lengthof(g_opcodes); 408 409 for (size_t i = 0; i < k_num_arm_opcodes; ++i) { 410 if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value) 411 return &g_opcodes[i]; 412 } 413 return nullptr; 414 } 415 416 bool EmulateInstructionARM64::ReadInstruction() { 417 bool success = false; 418 m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 419 LLDB_INVALID_ADDRESS, &success); 420 if (success) { 421 Context read_inst_context; 422 read_inst_context.type = eContextReadOpcode; 423 read_inst_context.SetNoArgs(); 424 m_opcode.SetOpcode32( 425 ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success), 426 GetByteOrder()); 427 } 428 if (!success) 429 m_addr = LLDB_INVALID_ADDRESS; 430 return success; 431 } 432 433 bool EmulateInstructionARM64::EvaluateInstruction(uint32_t evaluate_options) { 434 const uint32_t opcode = m_opcode.GetOpcode32(); 435 Opcode *opcode_data = GetOpcodeForInstruction(opcode); 436 if (opcode_data == NULL) 437 return false; 438 439 // printf ("opcode template for 0x%8.8x: %s\n", opcode, opcode_data->name); 440 const bool auto_advance_pc = 441 evaluate_options & eEmulateInstructionOptionAutoAdvancePC; 442 m_ignore_conditions = 443 evaluate_options & eEmulateInstructionOptionIgnoreConditions; 444 445 bool success = false; 446 // if (m_opcode_cpsr == 0 || m_ignore_conditions == false) 447 // { 448 // m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindLLDB, 449 // gpr_cpsr_arm64, 450 // 0, 451 // &success); 452 // } 453 454 // Only return false if we are unable to read the CPSR if we care about 455 // conditions 456 if (success == false && m_ignore_conditions == false) 457 return false; 458 459 uint32_t orig_pc_value = 0; 460 if (auto_advance_pc) { 461 orig_pc_value = 462 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success); 463 if (!success) 464 return false; 465 } 466 467 // Call the Emulate... function. 468 success = (this->*opcode_data->callback)(opcode); 469 if (!success) 470 return false; 471 472 if (auto_advance_pc) { 473 uint32_t new_pc_value = 474 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success); 475 if (!success) 476 return false; 477 478 if (auto_advance_pc && (new_pc_value == orig_pc_value)) { 479 EmulateInstruction::Context context; 480 context.type = eContextAdvancePC; 481 context.SetNoArgs(); 482 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_pc_arm64, 483 orig_pc_value + 4)) 484 return false; 485 } 486 } 487 return true; 488 } 489 490 bool EmulateInstructionARM64::CreateFunctionEntryUnwind( 491 UnwindPlan &unwind_plan) { 492 unwind_plan.Clear(); 493 unwind_plan.SetRegisterKind(eRegisterKindLLDB); 494 495 UnwindPlan::RowSP row(new UnwindPlan::Row); 496 497 // Our previous Call Frame Address is the stack pointer 498 row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0); 499 500 unwind_plan.AppendRow(row); 501 unwind_plan.SetSourceName("EmulateInstructionARM64"); 502 unwind_plan.SetSourcedFromCompiler(eLazyBoolNo); 503 unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes); 504 unwind_plan.SetReturnAddressRegister(gpr_lr_arm64); 505 return true; 506 } 507 508 uint32_t EmulateInstructionARM64::GetFramePointerRegisterNumber() const { 509 if (m_arch.GetTriple().isAndroid()) 510 return LLDB_INVALID_REGNUM; // Don't use frame pointer on android 511 512 return gpr_fp_arm64; 513 } 514 515 bool EmulateInstructionARM64::UsingAArch32() { 516 bool aarch32 = m_opcode_pstate.RW == 1; 517 // if !HaveAnyAArch32() then assert !aarch32; 518 // if HighestELUsingAArch32() then assert aarch32; 519 return aarch32; 520 } 521 522 bool EmulateInstructionARM64::BranchTo(const Context &context, uint32_t N, 523 addr_t target) { 524 #if 0 525 // Set program counter to a new address, with a branch reason hint 526 // for possible use by hardware fetching the next instruction. 527 BranchTo(bits(N) target, BranchType branch_type) 528 Hint_Branch(branch_type); 529 if N == 32 then 530 assert UsingAArch32(); 531 _PC = ZeroExtend(target); 532 else 533 assert N == 64 && !UsingAArch32(); 534 // Remove the tag bits from a tagged target 535 case PSTATE.EL of 536 when EL0, EL1 537 if target<55> == '1' && TCR_EL1.TBI1 == '1' then 538 target<63:56> = '11111111'; 539 if target<55> == '0' && TCR_EL1.TBI0 == '1' then 540 target<63:56> = '00000000'; 541 when EL2 542 if TCR_EL2.TBI == '1' then 543 target<63:56> = '00000000'; 544 when EL3 545 if TCR_EL3.TBI == '1' then 546 target<63:56> = '00000000'; 547 _PC = target<63:0>; 548 return; 549 #endif 550 551 addr_t addr; 552 553 // Hint_Branch(branch_type); 554 if (N == 32) { 555 if (!UsingAArch32()) 556 return false; 557 addr = target; 558 } else if (N == 64) { 559 if (UsingAArch32()) 560 return false; 561 // TODO: Remove the tag bits from a tagged target 562 addr = target; 563 } else 564 return false; 565 566 if (!WriteRegisterUnsigned(context, eRegisterKindGeneric, 567 LLDB_REGNUM_GENERIC_PC, addr)) 568 return false; 569 570 return true; 571 } 572 573 bool EmulateInstructionARM64::ConditionHolds(const uint32_t cond) { 574 // If we are ignoring conditions, then always return true. 575 // this allows us to iterate over disassembly code and still 576 // emulate an instruction even if we don't have all the right 577 // bits set in the CPSR register... 578 if (m_ignore_conditions) 579 return true; 580 581 bool result = false; 582 switch (UnsignedBits(cond, 3, 1)) { 583 case 0: 584 result = (m_opcode_pstate.Z == 1); 585 break; 586 case 1: 587 result = (m_opcode_pstate.C == 1); 588 break; 589 case 2: 590 result = (m_opcode_pstate.N == 1); 591 break; 592 case 3: 593 result = (m_opcode_pstate.V == 1); 594 break; 595 case 4: 596 result = (m_opcode_pstate.C == 1 && m_opcode_pstate.Z == 0); 597 break; 598 case 5: 599 result = (m_opcode_pstate.N == m_opcode_pstate.V); 600 break; 601 case 6: 602 result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0); 603 break; 604 case 7: 605 // Always execute (cond == 0b1110, or the special 0b1111 which gives 606 // opcodes different meanings, but always means execution happens. 607 return true; 608 } 609 610 if (cond & 1) 611 result = !result; 612 return result; 613 } 614 615 bool EmulateInstructionARM64::EmulateADDSUBImm(const uint32_t opcode) { 616 // integer d = UInt(Rd); 617 // integer n = UInt(Rn); 618 // integer datasize = if sf == 1 then 64 else 32; 619 // boolean sub_op = (op == 1); 620 // boolean setflags = (S == 1); 621 // bits(datasize) imm; 622 // 623 // case shift of 624 // when '00' imm = ZeroExtend(imm12, datasize); 625 // when '01' imm = ZeroExtend(imm12 : Zeros(12), datasize); 626 // when '1x' UNDEFINED; 627 // 628 // 629 // bits(datasize) result; 630 // bits(datasize) operand1 = if n == 31 then SP[] else X[n]; 631 // bits(datasize) operand2 = imm; 632 // bits(4) nzcv; 633 // bit carry_in; 634 // 635 // if sub_op then 636 // operand2 = NOT(operand2); 637 // carry_in = 1; 638 // else 639 // carry_in = 0; 640 // 641 // (result, nzcv) = AddWithCarry(operand1, operand2, carry_in); 642 // 643 // if setflags then 644 // PSTATE.NZCV = nzcv; 645 // 646 // if d == 31 && !setflags then 647 // SP[] = result; 648 // else 649 // X[d] = result; 650 651 const uint32_t sf = Bit32(opcode, 31); 652 const uint32_t op = Bit32(opcode, 30); 653 const uint32_t S = Bit32(opcode, 29); 654 const uint32_t shift = Bits32(opcode, 23, 22); 655 const uint32_t imm12 = Bits32(opcode, 21, 10); 656 const uint32_t Rn = Bits32(opcode, 9, 5); 657 const uint32_t Rd = Bits32(opcode, 4, 0); 658 659 bool success = false; 660 661 const uint32_t d = UInt(Rd); 662 const uint32_t n = UInt(Rn); 663 const uint32_t datasize = (sf == 1) ? 64 : 32; 664 boolean sub_op = op == 1; 665 boolean setflags = S == 1; 666 uint64_t imm; 667 668 switch (shift) { 669 case 0: 670 imm = imm12; 671 break; 672 case 1: 673 imm = imm12 << 12; 674 break; 675 default: 676 return false; // UNDEFINED; 677 } 678 uint64_t result; 679 uint64_t operand1 = 680 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 681 uint64_t operand2 = imm; 682 bit carry_in; 683 684 if (sub_op) { 685 operand2 = NOT(operand2); 686 carry_in = 1; 687 imm = -imm; // For the Register plug offset context below 688 } else { 689 carry_in = 0; 690 } 691 692 ProcState proc_state; 693 694 result = AddWithCarry(datasize, operand1, operand2, carry_in, proc_state); 695 696 if (setflags) { 697 m_emulated_pstate.N = proc_state.N; 698 m_emulated_pstate.Z = proc_state.Z; 699 m_emulated_pstate.C = proc_state.C; 700 m_emulated_pstate.V = proc_state.V; 701 } 702 703 Context context; 704 RegisterInfo reg_info_Rn; 705 if (GetRegisterInfo(eRegisterKindLLDB, n, reg_info_Rn)) 706 context.SetRegisterPlusOffset(reg_info_Rn, imm); 707 708 if (n == GetFramePointerRegisterNumber() && d == gpr_sp_arm64 && !setflags) { 709 // 'mov sp, fp' - common epilogue instruction, CFA is now in terms 710 // of the stack pointer, instead of frame pointer. 711 context.type = EmulateInstruction::eContextRestoreStackPointer; 712 } else if ((n == gpr_sp_arm64 || n == GetFramePointerRegisterNumber()) && 713 d == gpr_sp_arm64 && !setflags) { 714 context.type = EmulateInstruction::eContextAdjustStackPointer; 715 } else if (d == GetFramePointerRegisterNumber() && n == gpr_sp_arm64 && 716 !setflags) { 717 context.type = EmulateInstruction::eContextSetFramePointer; 718 } else { 719 context.type = EmulateInstruction::eContextImmediate; 720 } 721 722 // If setflags && d == gpr_sp_arm64 then d = WZR/XZR. See CMN, CMP 723 if (!setflags || d != gpr_sp_arm64) 724 WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_x0_arm64 + d, result); 725 726 return false; 727 } 728 729 template <EmulateInstructionARM64::AddrMode a_mode> 730 bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) { 731 uint32_t opc = Bits32(opcode, 31, 30); 732 uint32_t V = Bit32(opcode, 26); 733 uint32_t L = Bit32(opcode, 22); 734 uint32_t imm7 = Bits32(opcode, 21, 15); 735 uint32_t Rt2 = Bits32(opcode, 14, 10); 736 uint32_t Rn = Bits32(opcode, 9, 5); 737 uint32_t Rt = Bits32(opcode, 4, 0); 738 739 integer n = UInt(Rn); 740 integer t = UInt(Rt); 741 integer t2 = UInt(Rt2); 742 uint64_t idx; 743 744 MemOp memop = L == 1 ? MemOp_LOAD : MemOp_STORE; 745 boolean vector = (V == 1); 746 // AccType acctype = AccType_NORMAL; 747 boolean is_signed = false; 748 boolean wback = a_mode != AddrMode_OFF; 749 boolean wb_unknown = false; 750 boolean rt_unknown = false; 751 integer scale; 752 integer size; 753 754 if (opc == 3) 755 return false; // UNDEFINED 756 757 if (vector) { 758 scale = 2 + UInt(opc); 759 } else { 760 scale = (opc & 2) ? 3 : 2; 761 is_signed = (opc & 1) != 0; 762 if (is_signed && memop == MemOp_STORE) 763 return false; // UNDEFINED 764 } 765 766 if (!vector && wback && ((t == n) || (t2 == n))) { 767 switch (ConstrainUnpredictable(Unpredictable_WBOVERLAP)) { 768 case Constraint_UNKNOWN: 769 wb_unknown = true; // writeback is UNKNOWN 770 break; 771 772 case Constraint_SUPPRESSWB: 773 wback = false; // writeback is suppressed 774 break; 775 776 case Constraint_NOP: 777 memop = MemOp_NOP; // do nothing 778 wback = false; 779 break; 780 781 case Constraint_NONE: 782 break; 783 } 784 } 785 786 if (memop == MemOp_LOAD && t == t2) { 787 switch (ConstrainUnpredictable(Unpredictable_LDPOVERLAP)) { 788 case Constraint_UNKNOWN: 789 rt_unknown = true; // result is UNKNOWN 790 break; 791 792 case Constraint_NOP: 793 memop = MemOp_NOP; // do nothing 794 wback = false; 795 break; 796 797 default: 798 break; 799 } 800 } 801 802 idx = LSL(llvm::SignExtend64<7>(imm7), scale); 803 size = (integer)1 << scale; 804 uint64_t datasize = size * 8; 805 uint64_t address; 806 uint64_t wb_address; 807 808 RegisterValue data_Rt; 809 RegisterValue data_Rt2; 810 811 // if (vector) 812 // CheckFPEnabled(false); 813 814 RegisterInfo reg_info_base; 815 RegisterInfo reg_info_Rt; 816 RegisterInfo reg_info_Rt2; 817 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base)) 818 return false; 819 820 if (vector) { 821 if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t, reg_info_Rt)) 822 return false; 823 if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2, reg_info_Rt2)) 824 return false; 825 } else { 826 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt)) 827 return false; 828 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2, reg_info_Rt2)) 829 return false; 830 } 831 832 bool success = false; 833 if (n == 31) { 834 // CheckSPAlignment(); 835 address = 836 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success); 837 } else 838 address = 839 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 840 841 wb_address = address + idx; 842 if (a_mode != AddrMode_POST) 843 address = wb_address; 844 845 Context context_t; 846 Context context_t2; 847 848 uint8_t buffer[RegisterValue::kMaxRegisterByteSize]; 849 Status error; 850 851 switch (memop) { 852 case MemOp_STORE: { 853 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 854 // based off of the sp 855 // or fp register 856 { 857 context_t.type = eContextPushRegisterOnStack; 858 context_t2.type = eContextPushRegisterOnStack; 859 } else { 860 context_t.type = eContextRegisterStore; 861 context_t2.type = eContextRegisterStore; 862 } 863 context_t.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 0); 864 context_t2.SetRegisterToRegisterPlusOffset(reg_info_Rt2, reg_info_base, 865 size); 866 867 if (!ReadRegister(®_info_Rt, data_Rt)) 868 return false; 869 870 if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 871 eByteOrderLittle, error) == 0) 872 return false; 873 874 if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt.byte_size)) 875 return false; 876 877 if (!ReadRegister(®_info_Rt2, data_Rt2)) 878 return false; 879 880 if (data_Rt2.GetAsMemoryData(®_info_Rt2, buffer, reg_info_Rt2.byte_size, 881 eByteOrderLittle, error) == 0) 882 return false; 883 884 if (!WriteMemory(context_t2, address + size, buffer, 885 reg_info_Rt2.byte_size)) 886 return false; 887 } break; 888 889 case MemOp_LOAD: { 890 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this load is 891 // based off of the sp 892 // or fp register 893 { 894 context_t.type = eContextPopRegisterOffStack; 895 context_t2.type = eContextPopRegisterOffStack; 896 } else { 897 context_t.type = eContextRegisterLoad; 898 context_t2.type = eContextRegisterLoad; 899 } 900 context_t.SetAddress(address); 901 context_t2.SetAddress(address + size); 902 903 if (rt_unknown) 904 memset(buffer, 'U', reg_info_Rt.byte_size); 905 else { 906 if (!ReadMemory(context_t, address, buffer, reg_info_Rt.byte_size)) 907 return false; 908 } 909 910 if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 911 eByteOrderLittle, error) == 0) 912 return false; 913 914 if (!vector && is_signed && !data_Rt.SignExtend(datasize)) 915 return false; 916 917 if (!WriteRegister(context_t, ®_info_Rt, data_Rt)) 918 return false; 919 920 if (!rt_unknown) { 921 if (!ReadMemory(context_t2, address + size, buffer, 922 reg_info_Rt2.byte_size)) 923 return false; 924 } 925 926 if (data_Rt2.SetFromMemoryData(®_info_Rt2, buffer, 927 reg_info_Rt2.byte_size, eByteOrderLittle, 928 error) == 0) 929 return false; 930 931 if (!vector && is_signed && !data_Rt2.SignExtend(datasize)) 932 return false; 933 934 if (!WriteRegister(context_t2, ®_info_Rt2, data_Rt2)) 935 return false; 936 } break; 937 938 default: 939 break; 940 } 941 942 if (wback) { 943 if (wb_unknown) 944 wb_address = LLDB_INVALID_ADDRESS; 945 Context context; 946 context.SetImmediateSigned(idx); 947 if (n == 31) 948 context.type = eContextAdjustStackPointer; 949 else 950 context.type = eContextAdjustBaseRegister; 951 WriteRegisterUnsigned(context, ®_info_base, wb_address); 952 } 953 return true; 954 } 955 956 template <EmulateInstructionARM64::AddrMode a_mode> 957 bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) { 958 uint32_t size = Bits32(opcode, 31, 30); 959 uint32_t opc = Bits32(opcode, 23, 22); 960 uint32_t n = Bits32(opcode, 9, 5); 961 uint32_t t = Bits32(opcode, 4, 0); 962 963 bool wback; 964 bool postindex; 965 uint64_t offset; 966 967 switch (a_mode) { 968 case AddrMode_POST: 969 wback = true; 970 postindex = true; 971 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); 972 break; 973 case AddrMode_PRE: 974 wback = true; 975 postindex = false; 976 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); 977 break; 978 case AddrMode_OFF: 979 wback = false; 980 postindex = false; 981 offset = LSL(Bits32(opcode, 21, 10), size); 982 break; 983 } 984 985 MemOp memop; 986 987 if (Bit32(opc, 1) == 0) { 988 memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE; 989 } else { 990 memop = MemOp_LOAD; 991 if (size == 2 && Bit32(opc, 0) == 1) 992 return false; 993 } 994 995 Status error; 996 bool success = false; 997 uint64_t address; 998 uint8_t buffer[RegisterValue::kMaxRegisterByteSize]; 999 RegisterValue data_Rt; 1000 1001 if (n == 31) 1002 address = 1003 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success); 1004 else 1005 address = 1006 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 1007 1008 if (!success) 1009 return false; 1010 1011 if (!postindex) 1012 address += offset; 1013 1014 RegisterInfo reg_info_base; 1015 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base)) 1016 return false; 1017 1018 RegisterInfo reg_info_Rt; 1019 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt)) 1020 return false; 1021 1022 Context context; 1023 switch (memop) { 1024 case MemOp_STORE: 1025 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 1026 // based off of the sp 1027 // or fp register 1028 context.type = eContextPushRegisterOnStack; 1029 else 1030 context.type = eContextRegisterStore; 1031 context.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 1032 postindex ? 0 : offset); 1033 1034 if (!ReadRegister(®_info_Rt, data_Rt)) 1035 return false; 1036 1037 if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 1038 eByteOrderLittle, error) == 0) 1039 return false; 1040 1041 if (!WriteMemory(context, address, buffer, reg_info_Rt.byte_size)) 1042 return false; 1043 break; 1044 1045 case MemOp_LOAD: 1046 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 1047 // based off of the sp 1048 // or fp register 1049 context.type = eContextPopRegisterOffStack; 1050 else 1051 context.type = eContextRegisterLoad; 1052 context.SetAddress(address); 1053 1054 if (!ReadMemory(context, address, buffer, reg_info_Rt.byte_size)) 1055 return false; 1056 1057 if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 1058 eByteOrderLittle, error) == 0) 1059 return false; 1060 1061 if (!WriteRegister(context, ®_info_Rt, data_Rt)) 1062 return false; 1063 break; 1064 default: 1065 return false; 1066 } 1067 1068 if (wback) { 1069 if (postindex) 1070 address += offset; 1071 1072 if (n == 31) 1073 context.type = eContextAdjustStackPointer; 1074 else 1075 context.type = eContextAdjustBaseRegister; 1076 context.SetImmediateSigned(offset); 1077 1078 if (!WriteRegisterUnsigned(context, ®_info_base, address)) 1079 return false; 1080 } 1081 return true; 1082 } 1083 1084 bool EmulateInstructionARM64::EmulateB(const uint32_t opcode) { 1085 #if 0 1086 // ARM64 pseudo code... 1087 if branch_type == BranchType_CALL then X[30] = PC[] + 4; 1088 BranchTo(PC[] + offset, branch_type); 1089 #endif 1090 1091 bool success = false; 1092 1093 EmulateInstruction::Context context; 1094 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1095 const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, 1096 LLDB_REGNUM_GENERIC_PC, 0, &success); 1097 if (!success) 1098 return false; 1099 1100 int64_t offset = llvm::SignExtend64<28>(Bits32(opcode, 25, 0) << 2); 1101 BranchType branch_type = Bit32(opcode, 31) ? BranchType_CALL : BranchType_JMP; 1102 addr_t target = pc + offset; 1103 context.SetImmediateSigned(offset); 1104 1105 switch (branch_type) { 1106 case BranchType_CALL: { 1107 addr_t x30 = pc + 4; 1108 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_lr_arm64, x30)) 1109 return false; 1110 } break; 1111 case BranchType_JMP: 1112 break; 1113 default: 1114 return false; 1115 } 1116 1117 if (!BranchTo(context, 64, target)) 1118 return false; 1119 return true; 1120 } 1121 1122 bool EmulateInstructionARM64::EmulateBcond(const uint32_t opcode) { 1123 #if 0 1124 // ARM64 pseudo code... 1125 bits(64) offset = SignExtend(imm19:'00', 64); 1126 bits(4) condition = cond; 1127 if ConditionHolds(condition) then 1128 BranchTo(PC[] + offset, BranchType_JMP); 1129 #endif 1130 1131 if (ConditionHolds(Bits32(opcode, 3, 0))) { 1132 bool success = false; 1133 1134 const uint64_t pc = ReadRegisterUnsigned( 1135 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1136 if (!success) 1137 return false; 1138 1139 int64_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 1140 addr_t target = pc + offset; 1141 1142 EmulateInstruction::Context context; 1143 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1144 context.SetImmediateSigned(offset); 1145 if (!BranchTo(context, 64, target)) 1146 return false; 1147 } 1148 return true; 1149 } 1150 1151 bool EmulateInstructionARM64::EmulateCBZ(const uint32_t opcode) { 1152 #if 0 1153 integer t = UInt(Rt); 1154 integer datasize = if sf == '1' then 64 else 32; 1155 boolean iszero = (op == '0'); 1156 bits(64) offset = SignExtend(imm19:'00', 64); 1157 1158 bits(datasize) operand1 = X[t]; 1159 if IsZero(operand1) == iszero then 1160 BranchTo(PC[] + offset, BranchType_JMP); 1161 #endif 1162 1163 bool success = false; 1164 1165 uint32_t t = Bits32(opcode, 4, 0); 1166 bool is_zero = Bit32(opcode, 24) == 0; 1167 int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 1168 1169 const uint64_t operand = 1170 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success); 1171 if (!success) 1172 return false; 1173 1174 if (m_ignore_conditions || ((operand == 0) == is_zero)) { 1175 const uint64_t pc = ReadRegisterUnsigned( 1176 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1177 if (!success) 1178 return false; 1179 1180 EmulateInstruction::Context context; 1181 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1182 context.SetImmediateSigned(offset); 1183 if (!BranchTo(context, 64, pc + offset)) 1184 return false; 1185 } 1186 return true; 1187 } 1188 1189 bool EmulateInstructionARM64::EmulateTBZ(const uint32_t opcode) { 1190 #if 0 1191 integer t = UInt(Rt); 1192 integer datasize = if b5 == '1' then 64 else 32; 1193 integer bit_pos = UInt(b5:b40); 1194 bit bit_val = op; 1195 bits(64) offset = SignExtend(imm14:'00', 64); 1196 #endif 1197 1198 bool success = false; 1199 1200 uint32_t t = Bits32(opcode, 4, 0); 1201 uint32_t bit_pos = (Bit32(opcode, 31) << 6) | (Bits32(opcode, 23, 19)); 1202 uint32_t bit_val = Bit32(opcode, 24); 1203 int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2); 1204 1205 const uint64_t operand = 1206 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success); 1207 if (!success) 1208 return false; 1209 1210 if (m_ignore_conditions || Bit32(operand, bit_pos) == bit_val) { 1211 const uint64_t pc = ReadRegisterUnsigned( 1212 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1213 if (!success) 1214 return false; 1215 1216 EmulateInstruction::Context context; 1217 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1218 context.SetImmediateSigned(offset); 1219 if (!BranchTo(context, 64, pc + offset)) 1220 return false; 1221 } 1222 return true; 1223 } 1224