1 //===-- EmulateInstructionARM64.cpp -------------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "EmulateInstructionARM64.h" 11 12 #include <stdlib.h> 13 14 #include "lldb/Core/ArchSpec.h" 15 #include "lldb/Core/Address.h" 16 #include "lldb/Core/ConstString.h" 17 #include "lldb/Core/PluginManager.h" 18 #include "lldb/Core/Stream.h" 19 #include "lldb/Symbol/UnwindPlan.h" 20 21 #include "Plugins/Process/Utility/ARMDefines.h" 22 #include "Plugins/Process/Utility/ARMUtils.h" 23 #include "Utility/ARM64_DWARF_Registers.h" 24 25 #include "llvm/ADT/STLExtras.h" 26 #include "llvm/Support/MathExtras.h" // for SignExtend32 template function 27 // and CountTrailingZeros_32 function 28 29 #include "Plugins/Process/Utility/InstructionUtils.h" 30 31 using namespace lldb; 32 using namespace lldb_private; 33 34 #define No_VFP 0 35 #define VFPv1 (1u << 1) 36 #define VFPv2 (1u << 2) 37 #define VFPv3 (1u << 3) 38 #define AdvancedSIMD (1u << 4) 39 40 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD) 41 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD) 42 #define VFPv2v3 (VFPv2 | VFPv3) 43 44 #define UInt(x) ((uint64_t)x) 45 #define SInt(x) ((int64_t)x) 46 #define bit bool 47 #define boolean bool 48 #define integer int64_t 49 50 static inline bool 51 IsZero(uint64_t x) 52 { 53 return x == 0; 54 } 55 56 static inline uint64_t 57 NOT(uint64_t x) 58 { 59 return ~x; 60 } 61 62 #if 0 63 // LSL_C() 64 // ======= 65 static inline uint64_t 66 LSL_C (uint64_t x, integer shift, bool &carry_out) 67 { 68 assert (shift >= 0); 69 uint64_t result = x << shift; 70 carry_out = ((1ull << (64-1)) >> (shift - 1)) != 0; 71 return result; 72 } 73 #endif 74 75 // LSL() 76 // ===== 77 78 static inline uint64_t 79 LSL(uint64_t x, integer shift) 80 { 81 if (shift == 0) 82 return x; 83 return x << shift; 84 } 85 86 // AddWithCarry() 87 // =============== 88 static inline uint64_t 89 AddWithCarry (uint32_t N, uint64_t x, uint64_t y, bit carry_in, EmulateInstructionARM64::ProcState &proc_state) 90 { 91 uint64_t unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in); 92 int64_t signed_sum = SInt(x) + SInt(y) + UInt(carry_in); 93 uint64_t result = unsigned_sum; 94 if (N < 64) 95 result = Bits64 (result, N-1, 0); 96 proc_state.N = Bit64(result, N-1); 97 proc_state.Z = IsZero(result); 98 proc_state.C = UInt(result) == unsigned_sum; 99 proc_state.V = SInt(result) == signed_sum; 100 return result; 101 } 102 103 // ConstrainUnpredictable() 104 // ======================== 105 106 EmulateInstructionARM64::ConstraintType 107 ConstrainUnpredictable (EmulateInstructionARM64::Unpredictable which) 108 { 109 EmulateInstructionARM64::ConstraintType result = EmulateInstructionARM64::Constraint_UNKNOWN; 110 switch (which) 111 { 112 case EmulateInstructionARM64::Unpredictable_WBOVERLAP: 113 case EmulateInstructionARM64::Unpredictable_LDPOVERLAP: 114 // TODO: don't know what to really do here? Pseudo code says: 115 // set result to one of above Constraint behaviours or UNDEFINED 116 break; 117 } 118 return result; 119 } 120 121 122 123 //---------------------------------------------------------------------- 124 // 125 // EmulateInstructionARM implementation 126 // 127 //---------------------------------------------------------------------- 128 129 void 130 EmulateInstructionARM64::Initialize () 131 { 132 PluginManager::RegisterPlugin (GetPluginNameStatic (), 133 GetPluginDescriptionStatic (), 134 CreateInstance); 135 } 136 137 void 138 EmulateInstructionARM64::Terminate () 139 { 140 PluginManager::UnregisterPlugin (CreateInstance); 141 } 142 143 ConstString 144 EmulateInstructionARM64::GetPluginNameStatic () 145 { 146 ConstString g_plugin_name ("lldb.emulate-instruction.arm64"); 147 return g_plugin_name; 148 } 149 150 lldb_private::ConstString 151 EmulateInstructionARM64::GetPluginName() 152 { 153 static ConstString g_plugin_name ("EmulateInstructionARM64"); 154 return g_plugin_name; 155 } 156 157 const char * 158 EmulateInstructionARM64::GetPluginDescriptionStatic () 159 { 160 return "Emulate instructions for the ARM64 architecture."; 161 } 162 163 EmulateInstruction * 164 EmulateInstructionARM64::CreateInstance (const ArchSpec &arch, InstructionType inst_type) 165 { 166 if (EmulateInstructionARM64::SupportsEmulatingInstructionsOfTypeStatic(inst_type)) 167 { 168 if (arch.GetTriple().getArch() == llvm::Triple::aarch64) 169 { 170 std::auto_ptr<EmulateInstructionARM64> emulate_insn_ap (new EmulateInstructionARM64 (arch)); 171 if (emulate_insn_ap.get()) 172 return emulate_insn_ap.release(); 173 } 174 } 175 176 return NULL; 177 } 178 179 bool 180 EmulateInstructionARM64::SetTargetTriple (const ArchSpec &arch) 181 { 182 if (arch.GetTriple().getArch () == llvm::Triple::arm) 183 return true; 184 else if (arch.GetTriple().getArch () == llvm::Triple::thumb) 185 return true; 186 187 return false; 188 } 189 190 bool 191 EmulateInstructionARM64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num, RegisterInfo ®_info) 192 { 193 if (reg_kind == eRegisterKindGeneric) 194 { 195 switch (reg_num) 196 { 197 case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = arm64_dwarf::pc; break; 198 case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = arm64_dwarf::sp; break; 199 case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = arm64_dwarf::fp; break; 200 case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = arm64_dwarf::lr; break; 201 case LLDB_REGNUM_GENERIC_FLAGS: 202 // There is no DWARF register number for the CPSR right now... 203 reg_info.name = "cpsr"; 204 reg_info.alt_name = NULL; 205 reg_info.byte_size = 4; 206 reg_info.byte_offset = 0; 207 reg_info.encoding = eEncodingUint; 208 reg_info.format = eFormatHex; 209 for (uint32_t i=0; i<lldb::kNumRegisterKinds; ++i) 210 reg_info.kinds[reg_kind] = LLDB_INVALID_REGNUM; 211 reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; 212 return true; 213 214 default: return false; 215 } 216 } 217 218 if (reg_kind == eRegisterKindDWARF) 219 return arm64_dwarf::GetRegisterInfo(reg_num, reg_info); 220 return false; 221 } 222 223 EmulateInstructionARM64::Opcode* 224 EmulateInstructionARM64::GetOpcodeForInstruction (const uint32_t opcode) 225 { 226 static EmulateInstructionARM64::Opcode 227 g_opcodes[] = 228 { 229 //---------------------------------------------------------------------- 230 // Prologue instructions 231 //---------------------------------------------------------------------- 232 233 // push register(s) 234 { 0xff000000, 0xd1000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "SUB <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}" }, 235 { 0xff000000, 0xf1000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "SUBS <Xd>, <Xn|SP>, #<imm> {, <shift>}" }, 236 { 0xff000000, 0x91000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "ADD <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}" }, 237 { 0xff000000, 0xb1000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "ADDS <Xd>, <Xn|SP>, #<imm> {, <shift>}" }, 238 239 { 0xff000000, 0x51000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "SUB <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}" }, 240 { 0xff000000, 0x71000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}" }, 241 { 0xff000000, 0x11000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "ADD <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}" }, 242 { 0xff000000, 0x31000000, No_VFP, &EmulateInstructionARM64::Emulate_addsub_imm, "ADDS <Wd>, <Wn|WSP>, #<imm> {, <shift>}" }, 243 244 { 0xffc00000, 0x29000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]" }, 245 { 0xffc00000, 0xa9000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]" }, 246 { 0xffc00000, 0x2d000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <St>, <St2>, [<Xn|SP>{, #<imm>}]" }, 247 { 0xffc00000, 0x6d000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]" }, 248 { 0xffc00000, 0xad000000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]" }, 249 250 { 0xffc00000, 0x29800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, 251 { 0xffc00000, 0xa9800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, 252 { 0xffc00000, 0x2d800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, 253 { 0xffc00000, 0x6d800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, 254 { 0xffc00000, 0xad800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, 255 256 { 0xffc00000, 0x28800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, 257 { 0xffc00000, 0xa8800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, 258 { 0xffc00000, 0x2c800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, 259 { 0xffc00000, 0x6c800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, 260 { 0xffc00000, 0xac800000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, 261 262 { 0xffc00000, 0x29400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]" }, 263 { 0xffc00000, 0xa9400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]" }, 264 { 0xffc00000, 0x2d400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <St>, <St2>, [<Xn|SP>{, #<imm>}]" }, 265 { 0xffc00000, 0x6d400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]" }, 266 { 0xffc00000, 0xad400000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_off, "LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]" }, 267 268 { 0xffc00000, 0x29c00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, 269 { 0xffc00000, 0xa9c00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, 270 { 0xffc00000, 0x2dc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, 271 { 0xffc00000, 0x6dc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, 272 { 0xffc00000, 0xadc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_pre, "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, 273 274 { 0xffc00000, 0x28c00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!" }, 275 { 0xffc00000, 0xa8c00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!" }, 276 { 0xffc00000, 0x2cc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!" }, 277 { 0xffc00000, 0x6cc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!" }, 278 { 0xffc00000, 0xacc00000, No_VFP, &EmulateInstructionARM64::Emulate_ldstpair_post, "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!" }, 279 280 { 0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB, "B <label>" }, 281 { 0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond, "B.<cond> <label>" }, 282 { 0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, "CBZ <Wt>, <label>" }, 283 { 0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, "CBNZ <Wt>, <label>" }, 284 { 0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, "TBZ <R><t>, #<imm>, <label>" }, 285 { 0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, "TBNZ <R><t>, #<imm>, <label>" }, 286 287 }; 288 static const size_t k_num_arm_opcodes = llvm::array_lengthof(g_opcodes); 289 290 for (size_t i=0; i<k_num_arm_opcodes; ++i) 291 { 292 if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value) 293 return &g_opcodes[i]; 294 } 295 return nullptr; 296 } 297 298 bool 299 EmulateInstructionARM64::ReadInstruction () 300 { 301 bool success = false; 302 m_addr = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_ADDRESS, &success); 303 if (success) 304 { 305 Context read_inst_context; 306 read_inst_context.type = eContextReadOpcode; 307 read_inst_context.SetNoArgs (); 308 m_opcode.SetOpcode32 (ReadMemoryUnsigned (read_inst_context, m_addr, 4, 0, &success), GetByteOrder()); 309 } 310 if (!success) 311 m_addr = LLDB_INVALID_ADDRESS; 312 return success; 313 } 314 315 316 bool 317 EmulateInstructionARM64::EvaluateInstruction (uint32_t evaluate_options) 318 { 319 const uint32_t opcode = m_opcode.GetOpcode32(); 320 Opcode *opcode_data = GetOpcodeForInstruction(opcode); 321 if (opcode_data == NULL) 322 return false; 323 324 //printf ("opcode template for 0x%8.8x: %s\n", opcode, opcode_data->name); 325 const bool auto_advance_pc = evaluate_options & eEmulateInstructionOptionAutoAdvancePC; 326 m_ignore_conditions = evaluate_options & eEmulateInstructionOptionIgnoreConditions; 327 328 bool success = false; 329 // if (m_opcode_cpsr == 0 || m_ignore_conditions == false) 330 // { 331 // m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, // use eRegisterKindDWARF is we ever get a cpsr DWARF register number 332 // LLDB_REGNUM_GENERIC_FLAGS, // use arm64_dwarf::cpsr if we ever get one 333 // 0, 334 // &success); 335 // } 336 337 // Only return false if we are unable to read the CPSR if we care about conditions 338 if (success == false && m_ignore_conditions == false) 339 return false; 340 341 uint32_t orig_pc_value = 0; 342 if (auto_advance_pc) 343 { 344 orig_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, arm64_dwarf::pc, 0, &success); 345 if (!success) 346 return false; 347 } 348 349 // Call the Emulate... function. 350 success = (this->*opcode_data->callback) (opcode); 351 if (!success) 352 return false; 353 354 if (auto_advance_pc) 355 { 356 uint32_t new_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, arm64_dwarf::pc, 0, &success); 357 if (!success) 358 return false; 359 360 if (auto_advance_pc && (new_pc_value == orig_pc_value)) 361 { 362 EmulateInstruction::Context context; 363 context.type = eContextAdvancePC; 364 context.SetNoArgs(); 365 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, arm64_dwarf::pc, orig_pc_value + 4)) 366 return false; 367 } 368 } 369 return true; 370 } 371 372 bool 373 EmulateInstructionARM64::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) 374 { 375 unwind_plan.Clear(); 376 unwind_plan.SetRegisterKind (eRegisterKindDWARF); 377 378 UnwindPlan::RowSP row(new UnwindPlan::Row); 379 380 // Our previous Call Frame Address is the stack pointer 381 row->GetCFAValue().SetIsRegisterPlusOffset(arm64_dwarf::sp, 0); 382 383 unwind_plan.AppendRow (row); 384 unwind_plan.SetSourceName ("EmulateInstructionARM64"); 385 unwind_plan.SetSourcedFromCompiler (eLazyBoolNo); 386 unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolYes); 387 unwind_plan.SetReturnAddressRegister (arm64_dwarf::lr); 388 return true; 389 } 390 391 uint32_t 392 EmulateInstructionARM64::GetFramePointerRegisterNumber () const 393 { 394 if (m_arch.GetTriple().getEnvironment() == llvm::Triple::Android) 395 return LLDB_INVALID_REGNUM; // Don't use frame pointer on android 396 397 return arm64_dwarf::sp; 398 } 399 400 bool 401 EmulateInstructionARM64::UsingAArch32() 402 { 403 bool aarch32 = m_opcode_pstate.RW == 1; 404 // if !HaveAnyAArch32() then assert !aarch32; 405 // if HighestELUsingAArch32() then assert aarch32; 406 return aarch32; 407 } 408 409 bool 410 EmulateInstructionARM64::BranchTo (const Context &context, uint32_t N, addr_t target) 411 { 412 #if 0 413 // Set program counter to a new address, with a branch reason hint 414 // for possible use by hardware fetching the next instruction. 415 BranchTo(bits(N) target, BranchType branch_type) 416 Hint_Branch(branch_type); 417 if N == 32 then 418 assert UsingAArch32(); 419 _PC = ZeroExtend(target); 420 else 421 assert N == 64 && !UsingAArch32(); 422 // Remove the tag bits from a tagged target 423 case PSTATE.EL of 424 when EL0, EL1 425 if target<55> == '1' && TCR_EL1.TBI1 == '1' then 426 target<63:56> = '11111111'; 427 if target<55> == '0' && TCR_EL1.TBI0 == '1' then 428 target<63:56> = '00000000'; 429 when EL2 430 if TCR_EL2.TBI == '1' then 431 target<63:56> = '00000000'; 432 when EL3 433 if TCR_EL3.TBI == '1' then 434 target<63:56> = '00000000'; 435 _PC = target<63:0>; 436 return; 437 #endif 438 439 addr_t addr; 440 441 //Hint_Branch(branch_type); 442 if (N == 32) 443 { 444 if (!UsingAArch32()) 445 return false; 446 addr = target; 447 } 448 else if (N == 64) 449 { 450 if (UsingAArch32()) 451 return false; 452 // TODO: Remove the tag bits from a tagged target 453 addr = target; 454 } 455 else 456 return false; 457 458 if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, addr)) 459 return false; 460 461 return true; 462 } 463 464 bool 465 EmulateInstructionARM64::ConditionHolds (const uint32_t cond, bool *is_conditional) 466 { 467 // If we are ignoring conditions, then always return true. 468 // this allows us to iterate over disassembly code and still 469 // emulate an instruction even if we don't have all the right 470 // bits set in the CPSR register... 471 if (m_ignore_conditions) 472 return true; 473 474 if (is_conditional) 475 *is_conditional = true; 476 477 bool result = false; 478 switch (UnsignedBits(cond, 3, 1)) 479 { 480 case 0: 481 result = (m_opcode_pstate.Z == 1); 482 break; 483 case 1: 484 result = (m_opcode_pstate.C == 1); 485 break; 486 case 2: 487 result = (m_opcode_pstate.N == 1); 488 break; 489 case 3: 490 result = (m_opcode_pstate.V == 1); 491 break; 492 case 4: 493 result = (m_opcode_pstate.C == 1 && m_opcode_pstate.Z == 0); 494 break; 495 case 5: 496 result = (m_opcode_pstate.N == m_opcode_pstate.V); 497 break; 498 case 6: 499 result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0); 500 break; 501 case 7: 502 result = true; 503 if (is_conditional) 504 *is_conditional = false; 505 break; 506 } 507 508 if (cond & 1 && cond != 15) 509 result = !result; 510 return result; 511 } 512 513 bool 514 EmulateInstructionARM64::Emulate_addsub_imm (const uint32_t opcode) 515 { 516 // integer d = UInt(Rd); 517 // integer n = UInt(Rn); 518 // integer datasize = if sf == 1 then 64 else 32; 519 // boolean sub_op = (op == 1); 520 // boolean setflags = (S == 1); 521 // bits(datasize) imm; 522 // 523 // case shift of 524 // when '00' imm = ZeroExtend(imm12, datasize); 525 // when '01' imm = ZeroExtend(imm12 : Zeros(12), datasize); 526 // when '1x' UNDEFINED; 527 // 528 // 529 // bits(datasize) result; 530 // bits(datasize) operand1 = if n == 31 then SP[] else X[n]; 531 // bits(datasize) operand2 = imm; 532 // bits(4) nzcv; 533 // bit carry_in; 534 // 535 // if sub_op then 536 // operand2 = NOT(operand2); 537 // carry_in = 1; 538 // else 539 // carry_in = 0; 540 // 541 // (result, nzcv) = AddWithCarry(operand1, operand2, carry_in); 542 // 543 // if setflags then 544 // PSTATE.NZCV = nzcv; 545 // 546 // if d == 31 && !setflags then 547 // SP[] = result; 548 // else 549 // X[d] = result; 550 551 const uint32_t sf = Bit32(opcode, 31); 552 const uint32_t op = Bit32(opcode, 30); 553 const uint32_t S = Bit32(opcode, 29); 554 const uint32_t shift = Bits32(opcode, 23, 22); 555 const uint32_t imm12 = Bits32(opcode, 21, 10); 556 const uint32_t Rn = Bits32(opcode, 9, 5); 557 const uint32_t Rd = Bits32(opcode, 4, 0); 558 559 bool success = false; 560 561 const uint32_t d = UInt(Rd); 562 const uint32_t n = UInt(Rn); 563 const uint32_t datasize = (sf == 1) ? 64 : 32; 564 boolean sub_op = op == 1; 565 boolean setflags = S == 1; 566 uint64_t imm; 567 568 switch (shift) 569 { 570 case 0: imm = imm12; break; 571 case 1: imm = imm12 << 12; break; 572 default: return false; // UNDEFINED; 573 } 574 uint64_t result; 575 uint64_t operand1 = ReadRegisterUnsigned (eRegisterKindDWARF, arm64_dwarf::x0 + n, 0, &success); 576 uint64_t operand2 = imm; 577 bit carry_in; 578 579 if (sub_op) 580 { 581 operand2 = NOT(operand2); 582 carry_in = 1; 583 imm = -imm; // For the Register plug offset context below 584 } 585 else 586 { 587 carry_in = 0; 588 } 589 590 ProcState proc_state; 591 592 result = AddWithCarry (datasize, operand1, operand2, carry_in, proc_state); 593 594 if (setflags) 595 { 596 m_emulated_pstate.N = proc_state.N; 597 m_emulated_pstate.Z = proc_state.Z; 598 m_emulated_pstate.C = proc_state.C; 599 m_emulated_pstate.V = proc_state.V; 600 } 601 602 Context context; 603 RegisterInfo reg_info_Rn; 604 if (arm64_dwarf::GetRegisterInfo (n, reg_info_Rn)) 605 context.SetRegisterPlusOffset (reg_info_Rn, imm); 606 607 if ((n == arm64_dwarf::sp || n == GetFramePointerRegisterNumber()) && 608 d == arm64_dwarf::sp && 609 !setflags) 610 { 611 context.type = EmulateInstruction::eContextAdjustStackPointer; 612 } 613 else if (d == GetFramePointerRegisterNumber() && 614 n == arm64_dwarf::sp && 615 !setflags) 616 { 617 context.type = EmulateInstruction::eContextSetFramePointer; 618 } 619 else 620 { 621 context.type = EmulateInstruction::eContextImmediate; 622 } 623 624 // If setflags && d == arm64_dwarf::sp then d = WZR/XZR. See CMN, CMP 625 if (!setflags || d != arm64_dwarf::sp) 626 WriteRegisterUnsigned (context, eRegisterKindDWARF, arm64_dwarf::x0 + d, result); 627 628 return false; 629 } 630 631 bool 632 EmulateInstructionARM64::Emulate_ldstpair_off (const uint32_t opcode) 633 { 634 return Emulate_ldstpair (opcode, AddrMode_OFF); 635 } 636 637 bool 638 EmulateInstructionARM64::Emulate_ldstpair_pre (const uint32_t opcode) 639 { 640 return Emulate_ldstpair (opcode, AddrMode_PRE); 641 } 642 643 bool 644 EmulateInstructionARM64::Emulate_ldstpair_post (const uint32_t opcode) 645 { 646 return Emulate_ldstpair (opcode, AddrMode_POST); 647 } 648 649 bool 650 EmulateInstructionARM64::Emulate_ldstpair (const uint32_t opcode, AddrMode a_mode) 651 { 652 uint32_t opc = Bits32(opcode, 31, 30); 653 uint32_t V = Bit32(opcode, 26); 654 uint32_t L = Bit32(opcode, 22); 655 uint32_t imm7 = Bits32(opcode, 21, 15); 656 uint32_t Rt2 = Bits32(opcode, 14, 10); 657 uint32_t Rn = Bits32(opcode, 9, 5); 658 uint32_t Rt = Bits32(opcode, 4, 0); 659 660 integer n = UInt(Rn); 661 integer t = UInt(Rt); 662 integer t2 = UInt(Rt2); 663 uint64_t idx; 664 665 MemOp memop = L == 1 ? MemOp_LOAD : MemOp_STORE; 666 boolean vector = (V == 1); 667 //AccType acctype = AccType_NORMAL; 668 boolean is_signed = false; 669 boolean wback = a_mode != AddrMode_OFF; 670 boolean wb_unknown = false; 671 boolean rt_unknown = false; 672 integer scale; 673 integer size; 674 675 if (opc == 3) 676 return false; // UNDEFINED 677 678 if (vector) 679 { 680 scale = 2 + UInt(opc); 681 } 682 else 683 { 684 scale = (opc & 2) ? 3 : 2; 685 is_signed = (opc & 1) != 0; 686 if (is_signed && memop == MemOp_STORE) 687 return false; // UNDEFINED 688 } 689 690 if (!vector && wback && ((t == n) || (t2 == n))) 691 { 692 switch (ConstrainUnpredictable(Unpredictable_WBOVERLAP)) 693 { 694 case Constraint_UNKNOWN: 695 wb_unknown = true; // writeback is UNKNOWN 696 break; 697 698 case Constraint_SUPPRESSWB: 699 wback = false; // writeback is suppressed 700 break; 701 702 case Constraint_NOP: 703 memop = MemOp_NOP; // do nothing 704 wback = false; 705 break; 706 707 case Constraint_NONE: 708 break; 709 } 710 } 711 712 if (memop == MemOp_LOAD && t == t2) 713 { 714 switch (ConstrainUnpredictable(Unpredictable_LDPOVERLAP)) 715 { 716 case Constraint_UNKNOWN: 717 rt_unknown = true; // result is UNKNOWN 718 break; 719 720 case Constraint_NOP: 721 memop = MemOp_NOP; // do nothing 722 wback = false; 723 break; 724 725 default: 726 break; 727 } 728 } 729 730 idx = LSL(llvm::SignExtend64<7>(imm7), scale); 731 size = (integer)1 << scale; 732 uint64_t datasize = size * 8; 733 uint64_t address; 734 uint64_t wb_address; 735 736 RegisterValue data_Rt; 737 RegisterValue data_Rt2; 738 739 // if (vector) 740 // CheckFPEnabled(false); 741 742 RegisterInfo reg_info_base; 743 RegisterInfo reg_info_Rt; 744 RegisterInfo reg_info_Rt2; 745 if (!GetRegisterInfo (eRegisterKindDWARF, arm64_dwarf::x0 + n, reg_info_base)) 746 return false; 747 748 if (vector) 749 { 750 if (!GetRegisterInfo (eRegisterKindDWARF, arm64_dwarf::v0 + n, reg_info_Rt)) 751 return false; 752 if (!GetRegisterInfo (eRegisterKindDWARF, arm64_dwarf::v0 + n, reg_info_Rt2)) 753 return false; 754 } 755 else 756 { 757 if (!GetRegisterInfo (eRegisterKindDWARF, arm64_dwarf::x0 + t, reg_info_Rt)) 758 return false; 759 if (!GetRegisterInfo (eRegisterKindDWARF, arm64_dwarf::x0 + t2, reg_info_Rt2)) 760 return false; 761 } 762 763 bool success = false; 764 if (n == 31) 765 { 766 //CheckSPAlignment(); 767 address = ReadRegisterUnsigned (eRegisterKindDWARF, arm64_dwarf::sp, 0, &success); 768 } 769 else 770 address = ReadRegisterUnsigned (eRegisterKindDWARF, arm64_dwarf::x0 + n, 0, &success); 771 772 wb_address = address + idx; 773 if (a_mode != AddrMode_POST) 774 address = wb_address; 775 776 Context context_t; 777 Context context_t2; 778 779 context_t.type = eContextRegisterPlusOffset; 780 context_t2.type = eContextRegisterPlusOffset; 781 context_t.SetRegisterToRegisterPlusOffset (reg_info_Rt, reg_info_base, 0); 782 context_t2.SetRegisterToRegisterPlusOffset (reg_info_Rt2, reg_info_base, size); 783 uint8_t buffer [RegisterValue::kMaxRegisterByteSize]; 784 Error error; 785 786 switch (memop) 787 { 788 case MemOp_STORE: 789 { 790 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is based off of the sp or fp register 791 { 792 context_t.type = eContextPushRegisterOnStack; 793 context_t2.type = eContextPushRegisterOnStack; 794 } 795 796 if (!ReadRegister (®_info_Rt, data_Rt)) 797 return false; 798 799 if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, eByteOrderLittle, error) == 0) 800 return false; 801 802 if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt.byte_size)) 803 return false; 804 805 if (!ReadRegister (®_info_Rt2, data_Rt2)) 806 return false; 807 808 if (data_Rt2.GetAsMemoryData(®_info_Rt2, buffer, reg_info_Rt2.byte_size, eByteOrderLittle, error) == 0) 809 return false; 810 811 if (!WriteMemory(context_t2, address + size, buffer, reg_info_Rt2.byte_size)) 812 return false; 813 } 814 break; 815 816 case MemOp_LOAD: 817 { 818 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this load is based off of the sp or fp register 819 { 820 context_t.type = eContextPopRegisterOffStack; 821 context_t2.type = eContextPopRegisterOffStack; 822 } 823 824 if (rt_unknown) 825 memset (buffer, 'U', reg_info_Rt.byte_size); 826 else 827 { 828 if (!ReadMemory (context_t, address, buffer, reg_info_Rt.byte_size)) 829 return false; 830 } 831 832 if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, eByteOrderLittle, error) == 0) 833 return false; 834 835 if (!vector && is_signed && !data_Rt.SignExtend (datasize)) 836 return false; 837 838 if (!WriteRegister (context_t, ®_info_Rt, data_Rt)) 839 return false; 840 841 if (!rt_unknown) 842 { 843 if (!ReadMemory (context_t2, address + size, buffer, reg_info_Rt2.byte_size)) 844 return false; 845 } 846 847 if (data_Rt2.SetFromMemoryData(®_info_Rt2, buffer, reg_info_Rt2.byte_size, eByteOrderLittle, error) == 0) 848 return false; 849 850 if (!vector && is_signed && !data_Rt2.SignExtend (datasize)) 851 return false; 852 853 if (!WriteRegister (context_t2, ®_info_Rt2, data_Rt2)) 854 return false; 855 } 856 break; 857 858 default: 859 break; 860 } 861 862 if (wback) 863 { 864 if (wb_unknown) 865 wb_address = LLDB_INVALID_ADDRESS; 866 Context context; 867 context.SetImmediateSigned (idx); 868 if (n == 31) 869 context.type = eContextAdjustStackPointer; 870 else 871 context.type = eContextAdjustBaseRegister; 872 WriteRegisterUnsigned (context, ®_info_base, wb_address); 873 } 874 return true; 875 } 876 877 bool 878 EmulateInstructionARM64::EmulateB (const uint32_t opcode) 879 { 880 #if 0 881 // ARM64 pseudo code... 882 if branch_type == BranchType_CALL then X[30] = PC[] + 4; 883 BranchTo(PC[] + offset, branch_type); 884 #endif 885 886 bool success = false; 887 888 EmulateInstruction::Context context; 889 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 890 const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 891 if (!success) 892 return false; 893 894 int64_t offset = llvm::SignExtend64<28>(Bits32(opcode, 25, 0) << 2); 895 BranchType branch_type = Bit32(opcode, 31) ? BranchType_CALL : BranchType_JMP; 896 addr_t target = pc + offset; 897 context.SetImmediateSigned(offset); 898 899 switch (branch_type) 900 { 901 case BranchType_CALL: 902 { 903 addr_t x30 = pc + 4; 904 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, arm64_dwarf::x30, x30)) 905 return false; 906 } 907 break; 908 case BranchType_JMP: 909 break; 910 default: 911 return false; 912 } 913 914 if (!BranchTo(context, 64, target)) 915 return false; 916 return true; 917 } 918 919 bool 920 EmulateInstructionARM64::EmulateBcond (const uint32_t opcode) 921 { 922 #if 0 923 // ARM64 pseudo code... 924 bits(64) offset = SignExtend(imm19:'00', 64); 925 bits(4) condition = cond; 926 if ConditionHolds(condition) then 927 BranchTo(PC[] + offset, BranchType_JMP); 928 #endif 929 930 if (ConditionHolds(Bits32(opcode, 3, 0))) 931 { 932 bool success = false; 933 934 const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 935 if (!success) 936 return false; 937 938 int64_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 939 addr_t target = pc + offset; 940 941 EmulateInstruction::Context context; 942 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 943 context.SetImmediateSigned(offset); 944 if (!BranchTo(context, 64, target)) 945 return false; 946 } 947 return true; 948 } 949 950 bool 951 EmulateInstructionARM64::EmulateCBZ (const uint32_t opcode) 952 { 953 #if 0 954 integer t = UInt(Rt); 955 integer datasize = if sf == '1' then 64 else 32; 956 boolean iszero = (op == '0'); 957 bits(64) offset = SignExtend(imm19:'00', 64); 958 959 bits(datasize) operand1 = X[t]; 960 if IsZero(operand1) == iszero then 961 BranchTo(PC[] + offset, BranchType_JMP); 962 #endif 963 964 bool success = false; 965 966 uint32_t t = Bits32(opcode, 4, 0); 967 bool is_zero = Bit32(opcode, 24) == 0; 968 int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 969 970 const uint64_t operand = ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::x0 + t, 0, &success); 971 if (!success) 972 return false; 973 974 if (m_ignore_conditions || ((operand == 0) == is_zero)) 975 { 976 const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 977 if (!success) 978 return false; 979 980 EmulateInstruction::Context context; 981 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 982 context.SetImmediateSigned(offset); 983 if (!BranchTo(context, 64, pc + offset)) 984 return false; 985 } 986 return true; 987 } 988 989 bool 990 EmulateInstructionARM64::EmulateTBZ (const uint32_t opcode) 991 { 992 #if 0 993 integer t = UInt(Rt); 994 integer datasize = if b5 == '1' then 64 else 32; 995 integer bit_pos = UInt(b5:b40); 996 bit bit_val = op; 997 bits(64) offset = SignExtend(imm14:'00', 64); 998 #endif 999 1000 bool success = false; 1001 1002 uint32_t t = Bits32(opcode, 4, 0); 1003 uint32_t bit_pos = (Bit32(opcode, 31) << 6) | (Bits32(opcode, 23, 19)); 1004 uint32_t bit_val = Bit32(opcode, 24); 1005 int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2); 1006 1007 const uint64_t operand = ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::x0 + t, 0, &success); 1008 if (!success) 1009 return false; 1010 1011 if (m_ignore_conditions || Bit32(operand, bit_pos) == bit_val) 1012 { 1013 const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1014 if (!success) 1015 return false; 1016 1017 EmulateInstruction::Context context; 1018 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1019 context.SetImmediateSigned(offset); 1020 if (!BranchTo(context, 64, pc + offset)) 1021 return false; 1022 } 1023 return true; 1024 } 1025