1 //===-- EmulateInstructionARM64.cpp ------------------------------*- C++-*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "EmulateInstructionARM64.h" 11 12 #include <stdlib.h> 13 14 #include "lldb/Core/Address.h" 15 #include "lldb/Core/ArchSpec.h" 16 #include "lldb/Core/PluginManager.h" 17 #include "lldb/Core/RegisterValue.h" 18 #include "lldb/Symbol/UnwindPlan.h" 19 #include "lldb/Utility/ConstString.h" 20 #include "lldb/Utility/Stream.h" 21 22 #include "Plugins/Process/Utility/ARMDefines.h" 23 #include "Plugins/Process/Utility/ARMUtils.h" 24 #include "Plugins/Process/Utility/lldb-arm64-register-enums.h" 25 26 #define GPR_OFFSET(idx) ((idx)*8) 27 #define GPR_OFFSET_NAME(reg) 0 28 #define FPU_OFFSET(idx) ((idx)*16) 29 #define FPU_OFFSET_NAME(reg) 0 30 #define EXC_OFFSET_NAME(reg) 0 31 #define DBG_OFFSET_NAME(reg) 0 32 #define DBG_OFFSET_NAME(reg) 0 33 #define DEFINE_DBG(re, y) \ 34 "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \ 35 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 36 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM}, \ 37 nullptr, nullptr, nullptr, 0 38 39 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 40 41 #include "Plugins/Process/Utility/RegisterInfos_arm64.h" 42 43 #include "llvm/ADT/STLExtras.h" 44 #include "llvm/Support/MathExtras.h" // for SignExtend32 template function 45 // and CountTrailingZeros_32 function 46 47 #include "Plugins/Process/Utility/InstructionUtils.h" 48 49 using namespace lldb; 50 using namespace lldb_private; 51 52 static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo ®_info) { 53 if (reg_num >= llvm::array_lengthof(g_register_infos_arm64_le)) 54 return false; 55 reg_info = g_register_infos_arm64_le[reg_num]; 56 return true; 57 } 58 59 #define No_VFP 0 60 #define VFPv1 (1u << 1) 61 #define VFPv2 (1u << 2) 62 #define VFPv3 (1u << 3) 63 #define AdvancedSIMD (1u << 4) 64 65 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD) 66 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD) 67 #define VFPv2v3 (VFPv2 | VFPv3) 68 69 #define UInt(x) ((uint64_t)x) 70 #define SInt(x) ((int64_t)x) 71 #define bit bool 72 #define boolean bool 73 #define integer int64_t 74 75 static inline bool IsZero(uint64_t x) { return x == 0; } 76 77 static inline uint64_t NOT(uint64_t x) { return ~x; } 78 79 #if 0 80 // LSL_C() 81 // ======= 82 static inline uint64_t 83 LSL_C (uint64_t x, integer shift, bool &carry_out) 84 { 85 assert (shift >= 0); 86 uint64_t result = x << shift; 87 carry_out = ((1ull << (64-1)) >> (shift - 1)) != 0; 88 return result; 89 } 90 #endif 91 92 // LSL() 93 // ===== 94 95 static inline uint64_t LSL(uint64_t x, integer shift) { 96 if (shift == 0) 97 return x; 98 return x << shift; 99 } 100 101 // AddWithCarry() 102 // =============== 103 static inline uint64_t 104 AddWithCarry(uint32_t N, uint64_t x, uint64_t y, bit carry_in, 105 EmulateInstructionARM64::ProcState &proc_state) { 106 uint64_t unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in); 107 int64_t signed_sum = SInt(x) + SInt(y) + UInt(carry_in); 108 uint64_t result = unsigned_sum; 109 if (N < 64) 110 result = Bits64(result, N - 1, 0); 111 proc_state.N = Bit64(result, N - 1); 112 proc_state.Z = IsZero(result); 113 proc_state.C = UInt(result) == unsigned_sum; 114 proc_state.V = SInt(result) == signed_sum; 115 return result; 116 } 117 118 // ConstrainUnpredictable() 119 // ======================== 120 121 EmulateInstructionARM64::ConstraintType 122 ConstrainUnpredictable(EmulateInstructionARM64::Unpredictable which) { 123 EmulateInstructionARM64::ConstraintType result = 124 EmulateInstructionARM64::Constraint_UNKNOWN; 125 switch (which) { 126 case EmulateInstructionARM64::Unpredictable_WBOVERLAP: 127 case EmulateInstructionARM64::Unpredictable_LDPOVERLAP: 128 // TODO: don't know what to really do here? Pseudo code says: 129 // set result to one of above Constraint behaviours or UNDEFINED 130 break; 131 } 132 return result; 133 } 134 135 //---------------------------------------------------------------------- 136 // 137 // EmulateInstructionARM implementation 138 // 139 //---------------------------------------------------------------------- 140 141 void EmulateInstructionARM64::Initialize() { 142 PluginManager::RegisterPlugin(GetPluginNameStatic(), 143 GetPluginDescriptionStatic(), CreateInstance); 144 } 145 146 void EmulateInstructionARM64::Terminate() { 147 PluginManager::UnregisterPlugin(CreateInstance); 148 } 149 150 ConstString EmulateInstructionARM64::GetPluginNameStatic() { 151 ConstString g_plugin_name("lldb.emulate-instruction.arm64"); 152 return g_plugin_name; 153 } 154 155 lldb_private::ConstString EmulateInstructionARM64::GetPluginName() { 156 static ConstString g_plugin_name("EmulateInstructionARM64"); 157 return g_plugin_name; 158 } 159 160 const char *EmulateInstructionARM64::GetPluginDescriptionStatic() { 161 return "Emulate instructions for the ARM64 architecture."; 162 } 163 164 EmulateInstruction * 165 EmulateInstructionARM64::CreateInstance(const ArchSpec &arch, 166 InstructionType inst_type) { 167 if (EmulateInstructionARM64::SupportsEmulatingInstructionsOfTypeStatic( 168 inst_type)) { 169 if (arch.GetTriple().getArch() == llvm::Triple::aarch64) { 170 return new EmulateInstructionARM64(arch); 171 } 172 } 173 174 return NULL; 175 } 176 177 bool EmulateInstructionARM64::SetTargetTriple(const ArchSpec &arch) { 178 if (arch.GetTriple().getArch() == llvm::Triple::arm) 179 return true; 180 else if (arch.GetTriple().getArch() == llvm::Triple::thumb) 181 return true; 182 183 return false; 184 } 185 186 bool EmulateInstructionARM64::GetRegisterInfo(RegisterKind reg_kind, 187 uint32_t reg_num, 188 RegisterInfo ®_info) { 189 if (reg_kind == eRegisterKindGeneric) { 190 switch (reg_num) { 191 case LLDB_REGNUM_GENERIC_PC: 192 reg_kind = eRegisterKindLLDB; 193 reg_num = gpr_pc_arm64; 194 break; 195 case LLDB_REGNUM_GENERIC_SP: 196 reg_kind = eRegisterKindLLDB; 197 reg_num = gpr_sp_arm64; 198 break; 199 case LLDB_REGNUM_GENERIC_FP: 200 reg_kind = eRegisterKindLLDB; 201 reg_num = gpr_fp_arm64; 202 break; 203 case LLDB_REGNUM_GENERIC_RA: 204 reg_kind = eRegisterKindLLDB; 205 reg_num = gpr_lr_arm64; 206 break; 207 case LLDB_REGNUM_GENERIC_FLAGS: 208 reg_kind = eRegisterKindLLDB; 209 reg_num = gpr_cpsr_arm64; 210 break; 211 212 default: 213 return false; 214 } 215 } 216 217 if (reg_kind == eRegisterKindLLDB) 218 return LLDBTableGetRegisterInfo(reg_num, reg_info); 219 return false; 220 } 221 222 EmulateInstructionARM64::Opcode * 223 EmulateInstructionARM64::GetOpcodeForInstruction(const uint32_t opcode) { 224 static EmulateInstructionARM64::Opcode g_opcodes[] = { 225 //---------------------------------------------------------------------- 226 // Prologue instructions 227 //---------------------------------------------------------------------- 228 229 // push register(s) 230 {0xff000000, 0xd1000000, No_VFP, 231 &EmulateInstructionARM64::EmulateADDSUBImm, 232 "SUB <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"}, 233 {0xff000000, 0xf1000000, No_VFP, 234 &EmulateInstructionARM64::EmulateADDSUBImm, 235 "SUBS <Xd>, <Xn|SP>, #<imm> {, <shift>}"}, 236 {0xff000000, 0x91000000, No_VFP, 237 &EmulateInstructionARM64::EmulateADDSUBImm, 238 "ADD <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"}, 239 {0xff000000, 0xb1000000, No_VFP, 240 &EmulateInstructionARM64::EmulateADDSUBImm, 241 "ADDS <Xd>, <Xn|SP>, #<imm> {, <shift>}"}, 242 243 {0xff000000, 0x51000000, No_VFP, 244 &EmulateInstructionARM64::EmulateADDSUBImm, 245 "SUB <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"}, 246 {0xff000000, 0x71000000, No_VFP, 247 &EmulateInstructionARM64::EmulateADDSUBImm, 248 "SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"}, 249 {0xff000000, 0x11000000, No_VFP, 250 &EmulateInstructionARM64::EmulateADDSUBImm, 251 "ADD <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"}, 252 {0xff000000, 0x31000000, No_VFP, 253 &EmulateInstructionARM64::EmulateADDSUBImm, 254 "ADDS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"}, 255 256 {0xffc00000, 0x29000000, No_VFP, 257 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 258 "STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"}, 259 {0xffc00000, 0xa9000000, No_VFP, 260 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 261 "STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"}, 262 {0xffc00000, 0x2d000000, No_VFP, 263 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 264 "STP <St>, <St2>, [<Xn|SP>{, #<imm>}]"}, 265 {0xffc00000, 0x6d000000, No_VFP, 266 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 267 "STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"}, 268 {0xffc00000, 0xad000000, No_VFP, 269 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 270 "STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"}, 271 272 {0xffc00000, 0x29800000, No_VFP, 273 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 274 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 275 {0xffc00000, 0xa9800000, No_VFP, 276 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 277 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 278 {0xffc00000, 0x2d800000, No_VFP, 279 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 280 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 281 {0xffc00000, 0x6d800000, No_VFP, 282 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 283 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 284 {0xffc00000, 0xad800000, No_VFP, 285 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 286 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 287 288 {0xffc00000, 0x28800000, No_VFP, 289 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 290 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 291 {0xffc00000, 0xa8800000, No_VFP, 292 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 293 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 294 {0xffc00000, 0x2c800000, No_VFP, 295 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 296 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 297 {0xffc00000, 0x6c800000, No_VFP, 298 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 299 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 300 {0xffc00000, 0xac800000, No_VFP, 301 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 302 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 303 304 {0xffc00000, 0x29400000, No_VFP, 305 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 306 "LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"}, 307 {0xffc00000, 0xa9400000, No_VFP, 308 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 309 "LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"}, 310 {0xffc00000, 0x2d400000, No_VFP, 311 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 312 "LDP <St>, <St2>, [<Xn|SP>{, #<imm>}]"}, 313 {0xffc00000, 0x6d400000, No_VFP, 314 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 315 "LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"}, 316 {0xffc00000, 0xad400000, No_VFP, 317 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 318 "LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"}, 319 320 {0xffc00000, 0x29c00000, No_VFP, 321 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 322 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 323 {0xffc00000, 0xa9c00000, No_VFP, 324 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 325 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 326 {0xffc00000, 0x2dc00000, No_VFP, 327 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 328 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 329 {0xffc00000, 0x6dc00000, No_VFP, 330 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 331 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 332 {0xffc00000, 0xadc00000, No_VFP, 333 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 334 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 335 336 {0xffc00000, 0x28c00000, No_VFP, 337 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 338 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 339 {0xffc00000, 0xa8c00000, No_VFP, 340 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 341 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 342 {0xffc00000, 0x2cc00000, No_VFP, 343 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 344 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 345 {0xffc00000, 0x6cc00000, No_VFP, 346 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 347 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 348 {0xffc00000, 0xacc00000, No_VFP, 349 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 350 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 351 352 {0xffe00c00, 0xb8000400, No_VFP, 353 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 354 "STR <Wt>, [<Xn|SP>], #<simm>"}, 355 {0xffe00c00, 0xf8000400, No_VFP, 356 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 357 "STR <Xt>, [<Xn|SP>], #<simm>"}, 358 {0xffe00c00, 0xb8000c00, No_VFP, 359 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 360 "STR <Wt>, [<Xn|SP>, #<simm>]!"}, 361 {0xffe00c00, 0xf8000c00, No_VFP, 362 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 363 "STR <Xt>, [<Xn|SP>, #<simm>]!"}, 364 {0xffc00000, 0xb9000000, No_VFP, 365 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 366 "STR <Wt>, [<Xn|SP>{, #<pimm>}]"}, 367 {0xffc00000, 0xf9000000, No_VFP, 368 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 369 "STR <Xt>, [<Xn|SP>{, #<pimm>}]"}, 370 371 {0xffe00c00, 0xb8400400, No_VFP, 372 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 373 "LDR <Wt>, [<Xn|SP>], #<simm>"}, 374 {0xffe00c00, 0xf8400400, No_VFP, 375 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 376 "LDR <Xt>, [<Xn|SP>], #<simm>"}, 377 {0xffe00c00, 0xb8400c00, No_VFP, 378 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 379 "LDR <Wt>, [<Xn|SP>, #<simm>]!"}, 380 {0xffe00c00, 0xf8400c00, No_VFP, 381 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 382 "LDR <Xt>, [<Xn|SP>, #<simm>]!"}, 383 {0xffc00000, 0xb9400000, No_VFP, 384 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 385 "LDR <Wt>, [<Xn|SP>{, #<pimm>}]"}, 386 {0xffc00000, 0xf9400000, No_VFP, 387 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 388 "LDR <Xt>, [<Xn|SP>{, #<pimm>}]"}, 389 390 {0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB, 391 "B <label>"}, 392 {0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond, 393 "B.<cond> <label>"}, 394 {0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, 395 "CBZ <Wt>, <label>"}, 396 {0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, 397 "CBNZ <Wt>, <label>"}, 398 {0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, 399 "TBZ <R><t>, #<imm>, <label>"}, 400 {0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, 401 "TBNZ <R><t>, #<imm>, <label>"}, 402 403 }; 404 static const size_t k_num_arm_opcodes = llvm::array_lengthof(g_opcodes); 405 406 for (size_t i = 0; i < k_num_arm_opcodes; ++i) { 407 if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value) 408 return &g_opcodes[i]; 409 } 410 return nullptr; 411 } 412 413 bool EmulateInstructionARM64::ReadInstruction() { 414 bool success = false; 415 m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 416 LLDB_INVALID_ADDRESS, &success); 417 if (success) { 418 Context read_inst_context; 419 read_inst_context.type = eContextReadOpcode; 420 read_inst_context.SetNoArgs(); 421 m_opcode.SetOpcode32( 422 ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success), 423 GetByteOrder()); 424 } 425 if (!success) 426 m_addr = LLDB_INVALID_ADDRESS; 427 return success; 428 } 429 430 bool EmulateInstructionARM64::EvaluateInstruction(uint32_t evaluate_options) { 431 const uint32_t opcode = m_opcode.GetOpcode32(); 432 Opcode *opcode_data = GetOpcodeForInstruction(opcode); 433 if (opcode_data == NULL) 434 return false; 435 436 // printf ("opcode template for 0x%8.8x: %s\n", opcode, opcode_data->name); 437 const bool auto_advance_pc = 438 evaluate_options & eEmulateInstructionOptionAutoAdvancePC; 439 m_ignore_conditions = 440 evaluate_options & eEmulateInstructionOptionIgnoreConditions; 441 442 bool success = false; 443 // if (m_opcode_cpsr == 0 || m_ignore_conditions == false) 444 // { 445 // m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindLLDB, 446 // gpr_cpsr_arm64, 447 // 0, 448 // &success); 449 // } 450 451 // Only return false if we are unable to read the CPSR if we care about 452 // conditions 453 if (success == false && m_ignore_conditions == false) 454 return false; 455 456 uint32_t orig_pc_value = 0; 457 if (auto_advance_pc) { 458 orig_pc_value = 459 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success); 460 if (!success) 461 return false; 462 } 463 464 // Call the Emulate... function. 465 success = (this->*opcode_data->callback)(opcode); 466 if (!success) 467 return false; 468 469 if (auto_advance_pc) { 470 uint32_t new_pc_value = 471 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success); 472 if (!success) 473 return false; 474 475 if (auto_advance_pc && (new_pc_value == orig_pc_value)) { 476 EmulateInstruction::Context context; 477 context.type = eContextAdvancePC; 478 context.SetNoArgs(); 479 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_pc_arm64, 480 orig_pc_value + 4)) 481 return false; 482 } 483 } 484 return true; 485 } 486 487 bool EmulateInstructionARM64::CreateFunctionEntryUnwind( 488 UnwindPlan &unwind_plan) { 489 unwind_plan.Clear(); 490 unwind_plan.SetRegisterKind(eRegisterKindLLDB); 491 492 UnwindPlan::RowSP row(new UnwindPlan::Row); 493 494 // Our previous Call Frame Address is the stack pointer 495 row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0); 496 497 unwind_plan.AppendRow(row); 498 unwind_plan.SetSourceName("EmulateInstructionARM64"); 499 unwind_plan.SetSourcedFromCompiler(eLazyBoolNo); 500 unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes); 501 unwind_plan.SetReturnAddressRegister(gpr_lr_arm64); 502 return true; 503 } 504 505 uint32_t EmulateInstructionARM64::GetFramePointerRegisterNumber() const { 506 if (m_arch.GetTriple().isAndroid()) 507 return LLDB_INVALID_REGNUM; // Don't use frame pointer on android 508 509 return gpr_fp_arm64; 510 } 511 512 bool EmulateInstructionARM64::UsingAArch32() { 513 bool aarch32 = m_opcode_pstate.RW == 1; 514 // if !HaveAnyAArch32() then assert !aarch32; 515 // if HighestELUsingAArch32() then assert aarch32; 516 return aarch32; 517 } 518 519 bool EmulateInstructionARM64::BranchTo(const Context &context, uint32_t N, 520 addr_t target) { 521 #if 0 522 // Set program counter to a new address, with a branch reason hint 523 // for possible use by hardware fetching the next instruction. 524 BranchTo(bits(N) target, BranchType branch_type) 525 Hint_Branch(branch_type); 526 if N == 32 then 527 assert UsingAArch32(); 528 _PC = ZeroExtend(target); 529 else 530 assert N == 64 && !UsingAArch32(); 531 // Remove the tag bits from a tagged target 532 case PSTATE.EL of 533 when EL0, EL1 534 if target<55> == '1' && TCR_EL1.TBI1 == '1' then 535 target<63:56> = '11111111'; 536 if target<55> == '0' && TCR_EL1.TBI0 == '1' then 537 target<63:56> = '00000000'; 538 when EL2 539 if TCR_EL2.TBI == '1' then 540 target<63:56> = '00000000'; 541 when EL3 542 if TCR_EL3.TBI == '1' then 543 target<63:56> = '00000000'; 544 _PC = target<63:0>; 545 return; 546 #endif 547 548 addr_t addr; 549 550 // Hint_Branch(branch_type); 551 if (N == 32) { 552 if (!UsingAArch32()) 553 return false; 554 addr = target; 555 } else if (N == 64) { 556 if (UsingAArch32()) 557 return false; 558 // TODO: Remove the tag bits from a tagged target 559 addr = target; 560 } else 561 return false; 562 563 if (!WriteRegisterUnsigned(context, eRegisterKindGeneric, 564 LLDB_REGNUM_GENERIC_PC, addr)) 565 return false; 566 567 return true; 568 } 569 570 bool EmulateInstructionARM64::ConditionHolds(const uint32_t cond) { 571 // If we are ignoring conditions, then always return true. 572 // this allows us to iterate over disassembly code and still 573 // emulate an instruction even if we don't have all the right 574 // bits set in the CPSR register... 575 if (m_ignore_conditions) 576 return true; 577 578 bool result = false; 579 switch (UnsignedBits(cond, 3, 1)) { 580 case 0: 581 result = (m_opcode_pstate.Z == 1); 582 break; 583 case 1: 584 result = (m_opcode_pstate.C == 1); 585 break; 586 case 2: 587 result = (m_opcode_pstate.N == 1); 588 break; 589 case 3: 590 result = (m_opcode_pstate.V == 1); 591 break; 592 case 4: 593 result = (m_opcode_pstate.C == 1 && m_opcode_pstate.Z == 0); 594 break; 595 case 5: 596 result = (m_opcode_pstate.N == m_opcode_pstate.V); 597 break; 598 case 6: 599 result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0); 600 break; 601 case 7: 602 // Always execute (cond == 0b1110, or the special 0b1111 which gives 603 // opcodes different meanings, but always means execution happens. 604 return true; 605 } 606 607 if (cond & 1) 608 result = !result; 609 return result; 610 } 611 612 bool EmulateInstructionARM64::EmulateADDSUBImm(const uint32_t opcode) { 613 // integer d = UInt(Rd); 614 // integer n = UInt(Rn); 615 // integer datasize = if sf == 1 then 64 else 32; 616 // boolean sub_op = (op == 1); 617 // boolean setflags = (S == 1); 618 // bits(datasize) imm; 619 // 620 // case shift of 621 // when '00' imm = ZeroExtend(imm12, datasize); 622 // when '01' imm = ZeroExtend(imm12 : Zeros(12), datasize); 623 // when '1x' UNDEFINED; 624 // 625 // 626 // bits(datasize) result; 627 // bits(datasize) operand1 = if n == 31 then SP[] else X[n]; 628 // bits(datasize) operand2 = imm; 629 // bits(4) nzcv; 630 // bit carry_in; 631 // 632 // if sub_op then 633 // operand2 = NOT(operand2); 634 // carry_in = 1; 635 // else 636 // carry_in = 0; 637 // 638 // (result, nzcv) = AddWithCarry(operand1, operand2, carry_in); 639 // 640 // if setflags then 641 // PSTATE.NZCV = nzcv; 642 // 643 // if d == 31 && !setflags then 644 // SP[] = result; 645 // else 646 // X[d] = result; 647 648 const uint32_t sf = Bit32(opcode, 31); 649 const uint32_t op = Bit32(opcode, 30); 650 const uint32_t S = Bit32(opcode, 29); 651 const uint32_t shift = Bits32(opcode, 23, 22); 652 const uint32_t imm12 = Bits32(opcode, 21, 10); 653 const uint32_t Rn = Bits32(opcode, 9, 5); 654 const uint32_t Rd = Bits32(opcode, 4, 0); 655 656 bool success = false; 657 658 const uint32_t d = UInt(Rd); 659 const uint32_t n = UInt(Rn); 660 const uint32_t datasize = (sf == 1) ? 64 : 32; 661 boolean sub_op = op == 1; 662 boolean setflags = S == 1; 663 uint64_t imm; 664 665 switch (shift) { 666 case 0: 667 imm = imm12; 668 break; 669 case 1: 670 imm = imm12 << 12; 671 break; 672 default: 673 return false; // UNDEFINED; 674 } 675 uint64_t result; 676 uint64_t operand1 = 677 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 678 uint64_t operand2 = imm; 679 bit carry_in; 680 681 if (sub_op) { 682 operand2 = NOT(operand2); 683 carry_in = 1; 684 imm = -imm; // For the Register plug offset context below 685 } else { 686 carry_in = 0; 687 } 688 689 ProcState proc_state; 690 691 result = AddWithCarry(datasize, operand1, operand2, carry_in, proc_state); 692 693 if (setflags) { 694 m_emulated_pstate.N = proc_state.N; 695 m_emulated_pstate.Z = proc_state.Z; 696 m_emulated_pstate.C = proc_state.C; 697 m_emulated_pstate.V = proc_state.V; 698 } 699 700 Context context; 701 RegisterInfo reg_info_Rn; 702 if (GetRegisterInfo(eRegisterKindLLDB, n, reg_info_Rn)) 703 context.SetRegisterPlusOffset(reg_info_Rn, imm); 704 705 if (n == GetFramePointerRegisterNumber() && d == gpr_sp_arm64 && !setflags) { 706 // 'mov sp, fp' - common epilogue instruction, CFA is now in terms 707 // of the stack pointer, instead of frame pointer. 708 context.type = EmulateInstruction::eContextRestoreStackPointer; 709 } else if ((n == gpr_sp_arm64 || n == GetFramePointerRegisterNumber()) && 710 d == gpr_sp_arm64 && !setflags) { 711 context.type = EmulateInstruction::eContextAdjustStackPointer; 712 } else if (d == GetFramePointerRegisterNumber() && n == gpr_sp_arm64 && 713 !setflags) { 714 context.type = EmulateInstruction::eContextSetFramePointer; 715 } else { 716 context.type = EmulateInstruction::eContextImmediate; 717 } 718 719 // If setflags && d == gpr_sp_arm64 then d = WZR/XZR. See CMN, CMP 720 if (!setflags || d != gpr_sp_arm64) 721 WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_x0_arm64 + d, result); 722 723 return false; 724 } 725 726 template <EmulateInstructionARM64::AddrMode a_mode> 727 bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) { 728 uint32_t opc = Bits32(opcode, 31, 30); 729 uint32_t V = Bit32(opcode, 26); 730 uint32_t L = Bit32(opcode, 22); 731 uint32_t imm7 = Bits32(opcode, 21, 15); 732 uint32_t Rt2 = Bits32(opcode, 14, 10); 733 uint32_t Rn = Bits32(opcode, 9, 5); 734 uint32_t Rt = Bits32(opcode, 4, 0); 735 736 integer n = UInt(Rn); 737 integer t = UInt(Rt); 738 integer t2 = UInt(Rt2); 739 uint64_t idx; 740 741 MemOp memop = L == 1 ? MemOp_LOAD : MemOp_STORE; 742 boolean vector = (V == 1); 743 // AccType acctype = AccType_NORMAL; 744 boolean is_signed = false; 745 boolean wback = a_mode != AddrMode_OFF; 746 boolean wb_unknown = false; 747 boolean rt_unknown = false; 748 integer scale; 749 integer size; 750 751 if (opc == 3) 752 return false; // UNDEFINED 753 754 if (vector) { 755 scale = 2 + UInt(opc); 756 } else { 757 scale = (opc & 2) ? 3 : 2; 758 is_signed = (opc & 1) != 0; 759 if (is_signed && memop == MemOp_STORE) 760 return false; // UNDEFINED 761 } 762 763 if (!vector && wback && ((t == n) || (t2 == n))) { 764 switch (ConstrainUnpredictable(Unpredictable_WBOVERLAP)) { 765 case Constraint_UNKNOWN: 766 wb_unknown = true; // writeback is UNKNOWN 767 break; 768 769 case Constraint_SUPPRESSWB: 770 wback = false; // writeback is suppressed 771 break; 772 773 case Constraint_NOP: 774 memop = MemOp_NOP; // do nothing 775 wback = false; 776 break; 777 778 case Constraint_NONE: 779 break; 780 } 781 } 782 783 if (memop == MemOp_LOAD && t == t2) { 784 switch (ConstrainUnpredictable(Unpredictable_LDPOVERLAP)) { 785 case Constraint_UNKNOWN: 786 rt_unknown = true; // result is UNKNOWN 787 break; 788 789 case Constraint_NOP: 790 memop = MemOp_NOP; // do nothing 791 wback = false; 792 break; 793 794 default: 795 break; 796 } 797 } 798 799 idx = LSL(llvm::SignExtend64<7>(imm7), scale); 800 size = (integer)1 << scale; 801 uint64_t datasize = size * 8; 802 uint64_t address; 803 uint64_t wb_address; 804 805 RegisterValue data_Rt; 806 RegisterValue data_Rt2; 807 808 // if (vector) 809 // CheckFPEnabled(false); 810 811 RegisterInfo reg_info_base; 812 RegisterInfo reg_info_Rt; 813 RegisterInfo reg_info_Rt2; 814 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base)) 815 return false; 816 817 if (vector) { 818 if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t, reg_info_Rt)) 819 return false; 820 if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2, reg_info_Rt2)) 821 return false; 822 } else { 823 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt)) 824 return false; 825 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2, reg_info_Rt2)) 826 return false; 827 } 828 829 bool success = false; 830 if (n == 31) { 831 // CheckSPAlignment(); 832 address = 833 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success); 834 } else 835 address = 836 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 837 838 wb_address = address + idx; 839 if (a_mode != AddrMode_POST) 840 address = wb_address; 841 842 Context context_t; 843 Context context_t2; 844 845 uint8_t buffer[RegisterValue::kMaxRegisterByteSize]; 846 Status error; 847 848 switch (memop) { 849 case MemOp_STORE: { 850 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 851 // based off of the sp 852 // or fp register 853 { 854 context_t.type = eContextPushRegisterOnStack; 855 context_t2.type = eContextPushRegisterOnStack; 856 } else { 857 context_t.type = eContextRegisterStore; 858 context_t2.type = eContextRegisterStore; 859 } 860 context_t.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 0); 861 context_t2.SetRegisterToRegisterPlusOffset(reg_info_Rt2, reg_info_base, 862 size); 863 864 if (!ReadRegister(®_info_Rt, data_Rt)) 865 return false; 866 867 if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 868 eByteOrderLittle, error) == 0) 869 return false; 870 871 if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt.byte_size)) 872 return false; 873 874 if (!ReadRegister(®_info_Rt2, data_Rt2)) 875 return false; 876 877 if (data_Rt2.GetAsMemoryData(®_info_Rt2, buffer, reg_info_Rt2.byte_size, 878 eByteOrderLittle, error) == 0) 879 return false; 880 881 if (!WriteMemory(context_t2, address + size, buffer, 882 reg_info_Rt2.byte_size)) 883 return false; 884 } break; 885 886 case MemOp_LOAD: { 887 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this load is 888 // based off of the sp 889 // or fp register 890 { 891 context_t.type = eContextPopRegisterOffStack; 892 context_t2.type = eContextPopRegisterOffStack; 893 } else { 894 context_t.type = eContextRegisterLoad; 895 context_t2.type = eContextRegisterLoad; 896 } 897 context_t.SetAddress(address); 898 context_t2.SetAddress(address + size); 899 900 if (rt_unknown) 901 memset(buffer, 'U', reg_info_Rt.byte_size); 902 else { 903 if (!ReadMemory(context_t, address, buffer, reg_info_Rt.byte_size)) 904 return false; 905 } 906 907 if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 908 eByteOrderLittle, error) == 0) 909 return false; 910 911 if (!vector && is_signed && !data_Rt.SignExtend(datasize)) 912 return false; 913 914 if (!WriteRegister(context_t, ®_info_Rt, data_Rt)) 915 return false; 916 917 if (!rt_unknown) { 918 if (!ReadMemory(context_t2, address + size, buffer, 919 reg_info_Rt2.byte_size)) 920 return false; 921 } 922 923 if (data_Rt2.SetFromMemoryData(®_info_Rt2, buffer, 924 reg_info_Rt2.byte_size, eByteOrderLittle, 925 error) == 0) 926 return false; 927 928 if (!vector && is_signed && !data_Rt2.SignExtend(datasize)) 929 return false; 930 931 if (!WriteRegister(context_t2, ®_info_Rt2, data_Rt2)) 932 return false; 933 } break; 934 935 default: 936 break; 937 } 938 939 if (wback) { 940 if (wb_unknown) 941 wb_address = LLDB_INVALID_ADDRESS; 942 Context context; 943 context.SetImmediateSigned(idx); 944 if (n == 31) 945 context.type = eContextAdjustStackPointer; 946 else 947 context.type = eContextAdjustBaseRegister; 948 WriteRegisterUnsigned(context, ®_info_base, wb_address); 949 } 950 return true; 951 } 952 953 template <EmulateInstructionARM64::AddrMode a_mode> 954 bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) { 955 uint32_t size = Bits32(opcode, 31, 30); 956 uint32_t opc = Bits32(opcode, 23, 22); 957 uint32_t n = Bits32(opcode, 9, 5); 958 uint32_t t = Bits32(opcode, 4, 0); 959 960 bool wback; 961 bool postindex; 962 uint64_t offset; 963 964 switch (a_mode) { 965 case AddrMode_POST: 966 wback = true; 967 postindex = true; 968 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); 969 break; 970 case AddrMode_PRE: 971 wback = true; 972 postindex = false; 973 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); 974 break; 975 case AddrMode_OFF: 976 wback = false; 977 postindex = false; 978 offset = LSL(Bits32(opcode, 21, 10), size); 979 break; 980 } 981 982 MemOp memop; 983 984 if (Bit32(opc, 1) == 0) { 985 memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE; 986 } else { 987 memop = MemOp_LOAD; 988 if (size == 2 && Bit32(opc, 0) == 1) 989 return false; 990 } 991 992 Status error; 993 bool success = false; 994 uint64_t address; 995 uint8_t buffer[RegisterValue::kMaxRegisterByteSize]; 996 RegisterValue data_Rt; 997 998 if (n == 31) 999 address = 1000 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success); 1001 else 1002 address = 1003 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 1004 1005 if (!success) 1006 return false; 1007 1008 if (!postindex) 1009 address += offset; 1010 1011 RegisterInfo reg_info_base; 1012 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base)) 1013 return false; 1014 1015 RegisterInfo reg_info_Rt; 1016 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt)) 1017 return false; 1018 1019 Context context; 1020 switch (memop) { 1021 case MemOp_STORE: 1022 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 1023 // based off of the sp 1024 // or fp register 1025 context.type = eContextPushRegisterOnStack; 1026 else 1027 context.type = eContextRegisterStore; 1028 context.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 1029 postindex ? 0 : offset); 1030 1031 if (!ReadRegister(®_info_Rt, data_Rt)) 1032 return false; 1033 1034 if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 1035 eByteOrderLittle, error) == 0) 1036 return false; 1037 1038 if (!WriteMemory(context, address, buffer, reg_info_Rt.byte_size)) 1039 return false; 1040 break; 1041 1042 case MemOp_LOAD: 1043 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 1044 // based off of the sp 1045 // or fp register 1046 context.type = eContextPopRegisterOffStack; 1047 else 1048 context.type = eContextRegisterLoad; 1049 context.SetAddress(address); 1050 1051 if (!ReadMemory(context, address, buffer, reg_info_Rt.byte_size)) 1052 return false; 1053 1054 if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 1055 eByteOrderLittle, error) == 0) 1056 return false; 1057 1058 if (!WriteRegister(context, ®_info_Rt, data_Rt)) 1059 return false; 1060 break; 1061 default: 1062 return false; 1063 } 1064 1065 if (wback) { 1066 if (postindex) 1067 address += offset; 1068 1069 if (n == 31) 1070 context.type = eContextAdjustStackPointer; 1071 else 1072 context.type = eContextAdjustBaseRegister; 1073 context.SetImmediateSigned(offset); 1074 1075 if (!WriteRegisterUnsigned(context, ®_info_base, address)) 1076 return false; 1077 } 1078 return true; 1079 } 1080 1081 bool EmulateInstructionARM64::EmulateB(const uint32_t opcode) { 1082 #if 0 1083 // ARM64 pseudo code... 1084 if branch_type == BranchType_CALL then X[30] = PC[] + 4; 1085 BranchTo(PC[] + offset, branch_type); 1086 #endif 1087 1088 bool success = false; 1089 1090 EmulateInstruction::Context context; 1091 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1092 const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, 1093 LLDB_REGNUM_GENERIC_PC, 0, &success); 1094 if (!success) 1095 return false; 1096 1097 int64_t offset = llvm::SignExtend64<28>(Bits32(opcode, 25, 0) << 2); 1098 BranchType branch_type = Bit32(opcode, 31) ? BranchType_CALL : BranchType_JMP; 1099 addr_t target = pc + offset; 1100 context.SetImmediateSigned(offset); 1101 1102 switch (branch_type) { 1103 case BranchType_CALL: { 1104 addr_t x30 = pc + 4; 1105 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_lr_arm64, x30)) 1106 return false; 1107 } break; 1108 case BranchType_JMP: 1109 break; 1110 default: 1111 return false; 1112 } 1113 1114 if (!BranchTo(context, 64, target)) 1115 return false; 1116 return true; 1117 } 1118 1119 bool EmulateInstructionARM64::EmulateBcond(const uint32_t opcode) { 1120 #if 0 1121 // ARM64 pseudo code... 1122 bits(64) offset = SignExtend(imm19:'00', 64); 1123 bits(4) condition = cond; 1124 if ConditionHolds(condition) then 1125 BranchTo(PC[] + offset, BranchType_JMP); 1126 #endif 1127 1128 if (ConditionHolds(Bits32(opcode, 3, 0))) { 1129 bool success = false; 1130 1131 const uint64_t pc = ReadRegisterUnsigned( 1132 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1133 if (!success) 1134 return false; 1135 1136 int64_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 1137 addr_t target = pc + offset; 1138 1139 EmulateInstruction::Context context; 1140 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1141 context.SetImmediateSigned(offset); 1142 if (!BranchTo(context, 64, target)) 1143 return false; 1144 } 1145 return true; 1146 } 1147 1148 bool EmulateInstructionARM64::EmulateCBZ(const uint32_t opcode) { 1149 #if 0 1150 integer t = UInt(Rt); 1151 integer datasize = if sf == '1' then 64 else 32; 1152 boolean iszero = (op == '0'); 1153 bits(64) offset = SignExtend(imm19:'00', 64); 1154 1155 bits(datasize) operand1 = X[t]; 1156 if IsZero(operand1) == iszero then 1157 BranchTo(PC[] + offset, BranchType_JMP); 1158 #endif 1159 1160 bool success = false; 1161 1162 uint32_t t = Bits32(opcode, 4, 0); 1163 bool is_zero = Bit32(opcode, 24) == 0; 1164 int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 1165 1166 const uint64_t operand = 1167 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success); 1168 if (!success) 1169 return false; 1170 1171 if (m_ignore_conditions || ((operand == 0) == is_zero)) { 1172 const uint64_t pc = ReadRegisterUnsigned( 1173 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1174 if (!success) 1175 return false; 1176 1177 EmulateInstruction::Context context; 1178 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1179 context.SetImmediateSigned(offset); 1180 if (!BranchTo(context, 64, pc + offset)) 1181 return false; 1182 } 1183 return true; 1184 } 1185 1186 bool EmulateInstructionARM64::EmulateTBZ(const uint32_t opcode) { 1187 #if 0 1188 integer t = UInt(Rt); 1189 integer datasize = if b5 == '1' then 64 else 32; 1190 integer bit_pos = UInt(b5:b40); 1191 bit bit_val = op; 1192 bits(64) offset = SignExtend(imm14:'00', 64); 1193 #endif 1194 1195 bool success = false; 1196 1197 uint32_t t = Bits32(opcode, 4, 0); 1198 uint32_t bit_pos = (Bit32(opcode, 31) << 6) | (Bits32(opcode, 23, 19)); 1199 uint32_t bit_val = Bit32(opcode, 24); 1200 int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2); 1201 1202 const uint64_t operand = 1203 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success); 1204 if (!success) 1205 return false; 1206 1207 if (m_ignore_conditions || Bit32(operand, bit_pos) == bit_val) { 1208 const uint64_t pc = ReadRegisterUnsigned( 1209 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1210 if (!success) 1211 return false; 1212 1213 EmulateInstruction::Context context; 1214 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1215 context.SetImmediateSigned(offset); 1216 if (!BranchTo(context, 64, pc + offset)) 1217 return false; 1218 } 1219 return true; 1220 } 1221