1 //===-- EmulateInstructionARM64.cpp ------------------------------*- C++-*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "EmulateInstructionARM64.h"
11 
12 #include <stdlib.h>
13 
14 #include "lldb/Core/Address.h"
15 #include "lldb/Core/PluginManager.h"
16 #include "lldb/Symbol/UnwindPlan.h"
17 #include "lldb/Utility/ArchSpec.h"
18 #include "lldb/Utility/ConstString.h"
19 #include "lldb/Utility/RegisterValue.h"
20 #include "lldb/Utility/Stream.h"
21 
22 #include "Plugins/Process/Utility/ARMDefines.h"
23 #include "Plugins/Process/Utility/ARMUtils.h"
24 #include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
25 
26 #define GPR_OFFSET(idx) ((idx)*8)
27 #define GPR_OFFSET_NAME(reg) 0
28 #define FPU_OFFSET(idx) ((idx)*16)
29 #define FPU_OFFSET_NAME(reg) 0
30 #define EXC_OFFSET_NAME(reg) 0
31 #define DBG_OFFSET_NAME(reg) 0
32 #define DBG_OFFSET_NAME(reg) 0
33 #define DEFINE_DBG(re, y)                                                      \
34   "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex,                  \
35       {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,          \
36        LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},                              \
37       nullptr, nullptr, nullptr, 0
38 
39 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
40 
41 #include "Plugins/Process/Utility/RegisterInfos_arm64.h"
42 
43 #include "llvm/ADT/STLExtras.h"
44 #include "llvm/Support/MathExtras.h"
45 
46 #include "Plugins/Process/Utility/InstructionUtils.h"
47 
48 using namespace lldb;
49 using namespace lldb_private;
50 
51 static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo &reg_info) {
52   if (reg_num >= llvm::array_lengthof(g_register_infos_arm64_le))
53     return false;
54   reg_info = g_register_infos_arm64_le[reg_num];
55   return true;
56 }
57 
58 #define No_VFP 0
59 #define VFPv1 (1u << 1)
60 #define VFPv2 (1u << 2)
61 #define VFPv3 (1u << 3)
62 #define AdvancedSIMD (1u << 4)
63 
64 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
65 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
66 #define VFPv2v3 (VFPv2 | VFPv3)
67 
68 #define UInt(x) ((uint64_t)x)
69 #define SInt(x) ((int64_t)x)
70 #define bit bool
71 #define boolean bool
72 #define integer int64_t
73 
74 static inline bool IsZero(uint64_t x) { return x == 0; }
75 
76 static inline uint64_t NOT(uint64_t x) { return ~x; }
77 
78 // LSL()
79 // =====
80 
81 static inline uint64_t LSL(uint64_t x, integer shift) {
82   if (shift == 0)
83     return x;
84   return x << shift;
85 }
86 
87 // AddWithCarry()
88 // ===============
89 static inline uint64_t
90 AddWithCarry(uint32_t N, uint64_t x, uint64_t y, bit carry_in,
91              EmulateInstructionARM64::ProcState &proc_state) {
92   uint64_t unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in);
93   int64_t signed_sum = SInt(x) + SInt(y) + UInt(carry_in);
94   uint64_t result = unsigned_sum;
95   if (N < 64)
96     result = Bits64(result, N - 1, 0);
97   proc_state.N = Bit64(result, N - 1);
98   proc_state.Z = IsZero(result);
99   proc_state.C = UInt(result) == unsigned_sum;
100   proc_state.V = SInt(result) == signed_sum;
101   return result;
102 }
103 
104 // ConstrainUnpredictable()
105 // ========================
106 
107 EmulateInstructionARM64::ConstraintType
108 ConstrainUnpredictable(EmulateInstructionARM64::Unpredictable which) {
109   EmulateInstructionARM64::ConstraintType result =
110       EmulateInstructionARM64::Constraint_UNKNOWN;
111   switch (which) {
112   case EmulateInstructionARM64::Unpredictable_WBOVERLAP:
113   case EmulateInstructionARM64::Unpredictable_LDPOVERLAP:
114     // TODO: don't know what to really do here? Pseudo code says:
115     // set result to one of above Constraint behaviours or UNDEFINED
116     break;
117   }
118   return result;
119 }
120 
121 //----------------------------------------------------------------------
122 //
123 // EmulateInstructionARM implementation
124 //
125 //----------------------------------------------------------------------
126 
127 void EmulateInstructionARM64::Initialize() {
128   PluginManager::RegisterPlugin(GetPluginNameStatic(),
129                                 GetPluginDescriptionStatic(), CreateInstance);
130 }
131 
132 void EmulateInstructionARM64::Terminate() {
133   PluginManager::UnregisterPlugin(CreateInstance);
134 }
135 
136 ConstString EmulateInstructionARM64::GetPluginNameStatic() {
137   ConstString g_plugin_name("lldb.emulate-instruction.arm64");
138   return g_plugin_name;
139 }
140 
141 lldb_private::ConstString EmulateInstructionARM64::GetPluginName() {
142   static ConstString g_plugin_name("EmulateInstructionARM64");
143   return g_plugin_name;
144 }
145 
146 const char *EmulateInstructionARM64::GetPluginDescriptionStatic() {
147   return "Emulate instructions for the ARM64 architecture.";
148 }
149 
150 EmulateInstruction *
151 EmulateInstructionARM64::CreateInstance(const ArchSpec &arch,
152                                         InstructionType inst_type) {
153   if (EmulateInstructionARM64::SupportsEmulatingInstructionsOfTypeStatic(
154           inst_type)) {
155     if (arch.GetTriple().getArch() == llvm::Triple::aarch64) {
156       return new EmulateInstructionARM64(arch);
157     }
158   }
159 
160   return NULL;
161 }
162 
163 bool EmulateInstructionARM64::SetTargetTriple(const ArchSpec &arch) {
164   if (arch.GetTriple().getArch() == llvm::Triple::arm)
165     return true;
166   else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
167     return true;
168 
169   return false;
170 }
171 
172 bool EmulateInstructionARM64::GetRegisterInfo(RegisterKind reg_kind,
173                                               uint32_t reg_num,
174                                               RegisterInfo &reg_info) {
175   if (reg_kind == eRegisterKindGeneric) {
176     switch (reg_num) {
177     case LLDB_REGNUM_GENERIC_PC:
178       reg_kind = eRegisterKindLLDB;
179       reg_num = gpr_pc_arm64;
180       break;
181     case LLDB_REGNUM_GENERIC_SP:
182       reg_kind = eRegisterKindLLDB;
183       reg_num = gpr_sp_arm64;
184       break;
185     case LLDB_REGNUM_GENERIC_FP:
186       reg_kind = eRegisterKindLLDB;
187       reg_num = gpr_fp_arm64;
188       break;
189     case LLDB_REGNUM_GENERIC_RA:
190       reg_kind = eRegisterKindLLDB;
191       reg_num = gpr_lr_arm64;
192       break;
193     case LLDB_REGNUM_GENERIC_FLAGS:
194       reg_kind = eRegisterKindLLDB;
195       reg_num = gpr_cpsr_arm64;
196       break;
197 
198     default:
199       return false;
200     }
201   }
202 
203   if (reg_kind == eRegisterKindLLDB)
204     return LLDBTableGetRegisterInfo(reg_num, reg_info);
205   return false;
206 }
207 
208 EmulateInstructionARM64::Opcode *
209 EmulateInstructionARM64::GetOpcodeForInstruction(const uint32_t opcode) {
210   static EmulateInstructionARM64::Opcode g_opcodes[] = {
211       //----------------------------------------------------------------------
212       // Prologue instructions
213       //----------------------------------------------------------------------
214 
215       // push register(s)
216       {0xff000000, 0xd1000000, No_VFP,
217        &EmulateInstructionARM64::EmulateADDSUBImm,
218        "SUB  <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"},
219       {0xff000000, 0xf1000000, No_VFP,
220        &EmulateInstructionARM64::EmulateADDSUBImm,
221        "SUBS  <Xd>, <Xn|SP>, #<imm> {, <shift>}"},
222       {0xff000000, 0x91000000, No_VFP,
223        &EmulateInstructionARM64::EmulateADDSUBImm,
224        "ADD  <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"},
225       {0xff000000, 0xb1000000, No_VFP,
226        &EmulateInstructionARM64::EmulateADDSUBImm,
227        "ADDS  <Xd>, <Xn|SP>, #<imm> {, <shift>}"},
228 
229       {0xff000000, 0x51000000, No_VFP,
230        &EmulateInstructionARM64::EmulateADDSUBImm,
231        "SUB  <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"},
232       {0xff000000, 0x71000000, No_VFP,
233        &EmulateInstructionARM64::EmulateADDSUBImm,
234        "SUBS  <Wd>, <Wn|WSP>, #<imm> {, <shift>}"},
235       {0xff000000, 0x11000000, No_VFP,
236        &EmulateInstructionARM64::EmulateADDSUBImm,
237        "ADD  <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"},
238       {0xff000000, 0x31000000, No_VFP,
239        &EmulateInstructionARM64::EmulateADDSUBImm,
240        "ADDS  <Wd>, <Wn|WSP>, #<imm> {, <shift>}"},
241 
242       {0xffc00000, 0x29000000, No_VFP,
243        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
244        "STP  <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"},
245       {0xffc00000, 0xa9000000, No_VFP,
246        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
247        "STP  <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"},
248       {0xffc00000, 0x2d000000, No_VFP,
249        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
250        "STP  <St>, <St2>, [<Xn|SP>{, #<imm>}]"},
251       {0xffc00000, 0x6d000000, No_VFP,
252        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
253        "STP  <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"},
254       {0xffc00000, 0xad000000, No_VFP,
255        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
256        "STP  <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"},
257 
258       {0xffc00000, 0x29800000, No_VFP,
259        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
260        "STP  <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
261       {0xffc00000, 0xa9800000, No_VFP,
262        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
263        "STP  <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
264       {0xffc00000, 0x2d800000, No_VFP,
265        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
266        "STP  <St>, <St2>, [<Xn|SP>, #<imm>]!"},
267       {0xffc00000, 0x6d800000, No_VFP,
268        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
269        "STP  <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
270       {0xffc00000, 0xad800000, No_VFP,
271        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
272        "STP  <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
273 
274       {0xffc00000, 0x28800000, No_VFP,
275        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
276        "STP  <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
277       {0xffc00000, 0xa8800000, No_VFP,
278        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
279        "STP  <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
280       {0xffc00000, 0x2c800000, No_VFP,
281        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
282        "STP  <St>, <St2>, [<Xn|SP>, #<imm>]!"},
283       {0xffc00000, 0x6c800000, No_VFP,
284        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
285        "STP  <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
286       {0xffc00000, 0xac800000, No_VFP,
287        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
288        "STP  <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
289 
290       {0xffc00000, 0x29400000, No_VFP,
291        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
292        "LDP  <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"},
293       {0xffc00000, 0xa9400000, No_VFP,
294        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
295        "LDP  <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"},
296       {0xffc00000, 0x2d400000, No_VFP,
297        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
298        "LDP  <St>, <St2>, [<Xn|SP>{, #<imm>}]"},
299       {0xffc00000, 0x6d400000, No_VFP,
300        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
301        "LDP  <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"},
302       {0xffc00000, 0xad400000, No_VFP,
303        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>,
304        "LDP  <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"},
305 
306       {0xffc00000, 0x29c00000, No_VFP,
307        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
308        "LDP  <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
309       {0xffc00000, 0xa9c00000, No_VFP,
310        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
311        "LDP  <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
312       {0xffc00000, 0x2dc00000, No_VFP,
313        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
314        "LDP  <St>, <St2>, [<Xn|SP>, #<imm>]!"},
315       {0xffc00000, 0x6dc00000, No_VFP,
316        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
317        "LDP  <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
318       {0xffc00000, 0xadc00000, No_VFP,
319        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>,
320        "LDP  <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
321 
322       {0xffc00000, 0x28c00000, No_VFP,
323        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
324        "LDP  <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"},
325       {0xffc00000, 0xa8c00000, No_VFP,
326        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
327        "LDP  <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"},
328       {0xffc00000, 0x2cc00000, No_VFP,
329        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
330        "LDP  <St>, <St2>, [<Xn|SP>, #<imm>]!"},
331       {0xffc00000, 0x6cc00000, No_VFP,
332        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
333        "LDP  <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"},
334       {0xffc00000, 0xacc00000, No_VFP,
335        &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>,
336        "LDP  <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"},
337 
338       {0xffe00c00, 0xb8000400, No_VFP,
339        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
340        "STR <Wt>, [<Xn|SP>], #<simm>"},
341       {0xffe00c00, 0xf8000400, No_VFP,
342        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
343        "STR <Xt>, [<Xn|SP>], #<simm>"},
344       {0xffe00c00, 0xb8000c00, No_VFP,
345        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
346        "STR <Wt>, [<Xn|SP>, #<simm>]!"},
347       {0xffe00c00, 0xf8000c00, No_VFP,
348        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
349        "STR <Xt>, [<Xn|SP>, #<simm>]!"},
350       {0xffc00000, 0xb9000000, No_VFP,
351        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
352        "STR <Wt>, [<Xn|SP>{, #<pimm>}]"},
353       {0xffc00000, 0xf9000000, No_VFP,
354        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
355        "STR <Xt>, [<Xn|SP>{, #<pimm>}]"},
356 
357       {0xffe00c00, 0xb8400400, No_VFP,
358        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
359        "LDR <Wt>, [<Xn|SP>], #<simm>"},
360       {0xffe00c00, 0xf8400400, No_VFP,
361        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>,
362        "LDR <Xt>, [<Xn|SP>], #<simm>"},
363       {0xffe00c00, 0xb8400c00, No_VFP,
364        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
365        "LDR <Wt>, [<Xn|SP>, #<simm>]!"},
366       {0xffe00c00, 0xf8400c00, No_VFP,
367        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>,
368        "LDR <Xt>, [<Xn|SP>, #<simm>]!"},
369       {0xffc00000, 0xb9400000, No_VFP,
370        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
371        "LDR <Wt>, [<Xn|SP>{, #<pimm>}]"},
372       {0xffc00000, 0xf9400000, No_VFP,
373        &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>,
374        "LDR <Xt>, [<Xn|SP>{, #<pimm>}]"},
375 
376       {0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB,
377        "B <label>"},
378       {0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond,
379        "B.<cond> <label>"},
380       {0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ,
381        "CBZ <Wt>, <label>"},
382       {0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ,
383        "CBNZ <Wt>, <label>"},
384       {0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ,
385        "TBZ <R><t>, #<imm>, <label>"},
386       {0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ,
387        "TBNZ <R><t>, #<imm>, <label>"},
388 
389   };
390   static const size_t k_num_arm_opcodes = llvm::array_lengthof(g_opcodes);
391 
392   for (size_t i = 0; i < k_num_arm_opcodes; ++i) {
393     if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value)
394       return &g_opcodes[i];
395   }
396   return nullptr;
397 }
398 
399 bool EmulateInstructionARM64::ReadInstruction() {
400   bool success = false;
401   m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
402                                 LLDB_INVALID_ADDRESS, &success);
403   if (success) {
404     Context read_inst_context;
405     read_inst_context.type = eContextReadOpcode;
406     read_inst_context.SetNoArgs();
407     m_opcode.SetOpcode32(
408         ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success),
409         GetByteOrder());
410   }
411   if (!success)
412     m_addr = LLDB_INVALID_ADDRESS;
413   return success;
414 }
415 
416 bool EmulateInstructionARM64::EvaluateInstruction(uint32_t evaluate_options) {
417   const uint32_t opcode = m_opcode.GetOpcode32();
418   Opcode *opcode_data = GetOpcodeForInstruction(opcode);
419   if (opcode_data == NULL)
420     return false;
421 
422   // printf ("opcode template for 0x%8.8x: %s\n", opcode, opcode_data->name);
423   const bool auto_advance_pc =
424       evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
425   m_ignore_conditions =
426       evaluate_options & eEmulateInstructionOptionIgnoreConditions;
427 
428   bool success = false;
429   //    if (m_opcode_cpsr == 0 || m_ignore_conditions == false)
430   //    {
431   //        m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindLLDB,
432   //                                              gpr_cpsr_arm64,
433   //                                              0,
434   //                                              &success);
435   //    }
436 
437   // Only return false if we are unable to read the CPSR if we care about
438   // conditions
439   if (!success && !m_ignore_conditions)
440     return false;
441 
442   uint32_t orig_pc_value = 0;
443   if (auto_advance_pc) {
444     orig_pc_value =
445         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
446     if (!success)
447       return false;
448   }
449 
450   // Call the Emulate... function.
451   success = (this->*opcode_data->callback)(opcode);
452   if (!success)
453     return false;
454 
455   if (auto_advance_pc) {
456     uint32_t new_pc_value =
457         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
458     if (!success)
459       return false;
460 
461     if (auto_advance_pc && (new_pc_value == orig_pc_value)) {
462       EmulateInstruction::Context context;
463       context.type = eContextAdvancePC;
464       context.SetNoArgs();
465       if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_pc_arm64,
466                                  orig_pc_value + 4))
467         return false;
468     }
469   }
470   return true;
471 }
472 
473 bool EmulateInstructionARM64::CreateFunctionEntryUnwind(
474     UnwindPlan &unwind_plan) {
475   unwind_plan.Clear();
476   unwind_plan.SetRegisterKind(eRegisterKindLLDB);
477 
478   UnwindPlan::RowSP row(new UnwindPlan::Row);
479 
480   // Our previous Call Frame Address is the stack pointer
481   row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0);
482 
483   unwind_plan.AppendRow(row);
484   unwind_plan.SetSourceName("EmulateInstructionARM64");
485   unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
486   unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes);
487   unwind_plan.SetReturnAddressRegister(gpr_lr_arm64);
488   return true;
489 }
490 
491 uint32_t EmulateInstructionARM64::GetFramePointerRegisterNumber() const {
492   if (m_arch.GetTriple().isAndroid())
493     return LLDB_INVALID_REGNUM; // Don't use frame pointer on android
494 
495   return gpr_fp_arm64;
496 }
497 
498 bool EmulateInstructionARM64::UsingAArch32() {
499   bool aarch32 = m_opcode_pstate.RW == 1;
500   // if !HaveAnyAArch32() then assert !aarch32;
501   // if HighestELUsingAArch32() then assert aarch32;
502   return aarch32;
503 }
504 
505 bool EmulateInstructionARM64::BranchTo(const Context &context, uint32_t N,
506                                        addr_t target) {
507 #if 0
508     // Set program counter to a new address, with a branch reason hint for
509     // possible use by hardware fetching the next instruction.
510     BranchTo(bits(N) target, BranchType branch_type)
511         Hint_Branch(branch_type);
512         if N == 32 then
513             assert UsingAArch32();
514             _PC = ZeroExtend(target);
515         else
516             assert N == 64 && !UsingAArch32();
517             // Remove the tag bits from a tagged target
518             case PSTATE.EL of
519                 when EL0, EL1
520                     if target<55> == '1' && TCR_EL1.TBI1 == '1' then
521                         target<63:56> = '11111111';
522                     if target<55> == '0' && TCR_EL1.TBI0 == '1' then
523                         target<63:56> = '00000000';
524                 when EL2
525                     if TCR_EL2.TBI == '1' then
526                         target<63:56> = '00000000';
527                 when EL3
528                     if TCR_EL3.TBI == '1' then
529                         target<63:56> = '00000000';
530         _PC = target<63:0>;
531         return;
532 #endif
533 
534   addr_t addr;
535 
536   // Hint_Branch(branch_type);
537   if (N == 32) {
538     if (!UsingAArch32())
539       return false;
540     addr = target;
541   } else if (N == 64) {
542     if (UsingAArch32())
543       return false;
544     // TODO: Remove the tag bits from a tagged target
545     addr = target;
546   } else
547     return false;
548 
549   return WriteRegisterUnsigned(context, eRegisterKindGeneric,
550                                LLDB_REGNUM_GENERIC_PC, addr);
551 }
552 
553 bool EmulateInstructionARM64::ConditionHolds(const uint32_t cond) {
554   // If we are ignoring conditions, then always return true. this allows us to
555   // iterate over disassembly code and still emulate an instruction even if we
556   // don't have all the right bits set in the CPSR register...
557   if (m_ignore_conditions)
558     return true;
559 
560   bool result = false;
561   switch (UnsignedBits(cond, 3, 1)) {
562   case 0:
563     result = (m_opcode_pstate.Z == 1);
564     break;
565   case 1:
566     result = (m_opcode_pstate.C == 1);
567     break;
568   case 2:
569     result = (m_opcode_pstate.N == 1);
570     break;
571   case 3:
572     result = (m_opcode_pstate.V == 1);
573     break;
574   case 4:
575     result = (m_opcode_pstate.C == 1 && m_opcode_pstate.Z == 0);
576     break;
577   case 5:
578     result = (m_opcode_pstate.N == m_opcode_pstate.V);
579     break;
580   case 6:
581     result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0);
582     break;
583   case 7:
584     // Always execute (cond == 0b1110, or the special 0b1111 which gives
585     // opcodes different meanings, but always means execution happens.
586     return true;
587   }
588 
589   if (cond & 1)
590     result = !result;
591   return result;
592 }
593 
594 bool EmulateInstructionARM64::EmulateADDSUBImm(const uint32_t opcode) {
595   // integer d = UInt(Rd);
596   // integer n = UInt(Rn);
597   // integer datasize = if sf == 1 then 64 else 32;
598   // boolean sub_op = (op == 1);
599   // boolean setflags = (S == 1);
600   // bits(datasize) imm;
601   //
602   // case shift of
603   //     when '00' imm = ZeroExtend(imm12, datasize);
604   //     when '01' imm = ZeroExtend(imm12 : Zeros(12), datasize);
605   //    when '1x' UNDEFINED;
606   //
607   //
608   // bits(datasize) result;
609   // bits(datasize) operand1 = if n == 31 then SP[] else X[n];
610   // bits(datasize) operand2 = imm;
611   // bits(4) nzcv;
612   // bit carry_in;
613   //
614   // if sub_op then
615   //     operand2 = NOT(operand2);
616   //     carry_in = 1;
617   // else
618   //     carry_in = 0;
619   //
620   // (result, nzcv) = AddWithCarry(operand1, operand2, carry_in);
621   //
622   // if setflags then
623   //     PSTATE.NZCV = nzcv;
624   //
625   // if d == 31 && !setflags then
626   //     SP[] = result;
627   // else
628   //     X[d] = result;
629 
630   const uint32_t sf = Bit32(opcode, 31);
631   const uint32_t op = Bit32(opcode, 30);
632   const uint32_t S = Bit32(opcode, 29);
633   const uint32_t shift = Bits32(opcode, 23, 22);
634   const uint32_t imm12 = Bits32(opcode, 21, 10);
635   const uint32_t Rn = Bits32(opcode, 9, 5);
636   const uint32_t Rd = Bits32(opcode, 4, 0);
637 
638   bool success = false;
639 
640   const uint32_t d = UInt(Rd);
641   const uint32_t n = UInt(Rn);
642   const uint32_t datasize = (sf == 1) ? 64 : 32;
643   boolean sub_op = op == 1;
644   boolean setflags = S == 1;
645   uint64_t imm;
646 
647   switch (shift) {
648   case 0:
649     imm = imm12;
650     break;
651   case 1:
652     imm = imm12 << 12;
653     break;
654   default:
655     return false; // UNDEFINED;
656   }
657   uint64_t result;
658   uint64_t operand1 =
659       ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
660   uint64_t operand2 = imm;
661   bit carry_in;
662 
663   if (sub_op) {
664     operand2 = NOT(operand2);
665     carry_in = 1;
666     imm = -imm; // For the Register plug offset context below
667   } else {
668     carry_in = 0;
669   }
670 
671   ProcState proc_state;
672 
673   result = AddWithCarry(datasize, operand1, operand2, carry_in, proc_state);
674 
675   if (setflags) {
676     m_emulated_pstate.N = proc_state.N;
677     m_emulated_pstate.Z = proc_state.Z;
678     m_emulated_pstate.C = proc_state.C;
679     m_emulated_pstate.V = proc_state.V;
680   }
681 
682   Context context;
683   RegisterInfo reg_info_Rn;
684   if (GetRegisterInfo(eRegisterKindLLDB, n, reg_info_Rn))
685     context.SetRegisterPlusOffset(reg_info_Rn, imm);
686 
687   if (n == GetFramePointerRegisterNumber() && d == gpr_sp_arm64 && !setflags) {
688     // 'mov sp, fp' - common epilogue instruction, CFA is now in terms of the
689     // stack pointer, instead of frame pointer.
690     context.type = EmulateInstruction::eContextRestoreStackPointer;
691   } else if ((n == gpr_sp_arm64 || n == GetFramePointerRegisterNumber()) &&
692              d == gpr_sp_arm64 && !setflags) {
693     context.type = EmulateInstruction::eContextAdjustStackPointer;
694   } else if (d == GetFramePointerRegisterNumber() && n == gpr_sp_arm64 &&
695              !setflags) {
696     context.type = EmulateInstruction::eContextSetFramePointer;
697   } else {
698     context.type = EmulateInstruction::eContextImmediate;
699   }
700 
701   // If setflags && d == gpr_sp_arm64 then d = WZR/XZR. See CMN, CMP
702   if (!setflags || d != gpr_sp_arm64)
703     WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_x0_arm64 + d, result);
704 
705   return false;
706 }
707 
708 template <EmulateInstructionARM64::AddrMode a_mode>
709 bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) {
710   uint32_t opc = Bits32(opcode, 31, 30);
711   uint32_t V = Bit32(opcode, 26);
712   uint32_t L = Bit32(opcode, 22);
713   uint32_t imm7 = Bits32(opcode, 21, 15);
714   uint32_t Rt2 = Bits32(opcode, 14, 10);
715   uint32_t Rn = Bits32(opcode, 9, 5);
716   uint32_t Rt = Bits32(opcode, 4, 0);
717 
718   integer n = UInt(Rn);
719   integer t = UInt(Rt);
720   integer t2 = UInt(Rt2);
721   uint64_t idx;
722 
723   MemOp memop = L == 1 ? MemOp_LOAD : MemOp_STORE;
724   boolean vector = (V == 1);
725   // AccType acctype = AccType_NORMAL;
726   boolean is_signed = false;
727   boolean wback = a_mode != AddrMode_OFF;
728   boolean wb_unknown = false;
729   boolean rt_unknown = false;
730   integer scale;
731   integer size;
732 
733   if (opc == 3)
734     return false; // UNDEFINED
735 
736   if (vector) {
737     scale = 2 + UInt(opc);
738   } else {
739     scale = (opc & 2) ? 3 : 2;
740     is_signed = (opc & 1) != 0;
741     if (is_signed && memop == MemOp_STORE)
742       return false; // UNDEFINED
743   }
744 
745   if (!vector && wback && ((t == n) || (t2 == n))) {
746     switch (ConstrainUnpredictable(Unpredictable_WBOVERLAP)) {
747     case Constraint_UNKNOWN:
748       wb_unknown = true; // writeback is UNKNOWN
749       break;
750 
751     case Constraint_SUPPRESSWB:
752       wback = false; // writeback is suppressed
753       break;
754 
755     case Constraint_NOP:
756       memop = MemOp_NOP; // do nothing
757       wback = false;
758       break;
759 
760     case Constraint_NONE:
761       break;
762     }
763   }
764 
765   if (memop == MemOp_LOAD && t == t2) {
766     switch (ConstrainUnpredictable(Unpredictable_LDPOVERLAP)) {
767     case Constraint_UNKNOWN:
768       rt_unknown = true; // result is UNKNOWN
769       break;
770 
771     case Constraint_NOP:
772       memop = MemOp_NOP; // do nothing
773       wback = false;
774       break;
775 
776     default:
777       break;
778     }
779   }
780 
781   idx = LSL(llvm::SignExtend64<7>(imm7), scale);
782   size = (integer)1 << scale;
783   uint64_t datasize = size * 8;
784   uint64_t address;
785   uint64_t wb_address;
786 
787   RegisterValue data_Rt;
788   RegisterValue data_Rt2;
789 
790   //    if (vector)
791   //        CheckFPEnabled(false);
792 
793   RegisterInfo reg_info_base;
794   RegisterInfo reg_info_Rt;
795   RegisterInfo reg_info_Rt2;
796   if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base))
797     return false;
798 
799   if (vector) {
800     if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t, reg_info_Rt))
801       return false;
802     if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2, reg_info_Rt2))
803       return false;
804   } else {
805     if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt))
806       return false;
807     if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2, reg_info_Rt2))
808       return false;
809   }
810 
811   bool success = false;
812   if (n == 31) {
813     // CheckSPAlignment();
814     address =
815         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
816   } else
817     address =
818         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
819 
820   wb_address = address + idx;
821   if (a_mode != AddrMode_POST)
822     address = wb_address;
823 
824   Context context_t;
825   Context context_t2;
826 
827   uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
828   Status error;
829 
830   switch (memop) {
831   case MemOp_STORE: {
832     if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is
833                                                          // based off of the sp
834                                                          // or fp register
835     {
836       context_t.type = eContextPushRegisterOnStack;
837       context_t2.type = eContextPushRegisterOnStack;
838     } else {
839       context_t.type = eContextRegisterStore;
840       context_t2.type = eContextRegisterStore;
841     }
842     context_t.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 0);
843     context_t2.SetRegisterToRegisterPlusOffset(reg_info_Rt2, reg_info_base,
844                                                size);
845 
846     if (!ReadRegister(&reg_info_Rt, data_Rt))
847       return false;
848 
849     if (data_Rt.GetAsMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
850                                 eByteOrderLittle, error) == 0)
851       return false;
852 
853     if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt.byte_size))
854       return false;
855 
856     if (!ReadRegister(&reg_info_Rt2, data_Rt2))
857       return false;
858 
859     if (data_Rt2.GetAsMemoryData(&reg_info_Rt2, buffer, reg_info_Rt2.byte_size,
860                                  eByteOrderLittle, error) == 0)
861       return false;
862 
863     if (!WriteMemory(context_t2, address + size, buffer,
864                      reg_info_Rt2.byte_size))
865       return false;
866   } break;
867 
868   case MemOp_LOAD: {
869     if (n == 31 || n == GetFramePointerRegisterNumber()) // if this load is
870                                                          // based off of the sp
871                                                          // or fp register
872     {
873       context_t.type = eContextPopRegisterOffStack;
874       context_t2.type = eContextPopRegisterOffStack;
875     } else {
876       context_t.type = eContextRegisterLoad;
877       context_t2.type = eContextRegisterLoad;
878     }
879     context_t.SetAddress(address);
880     context_t2.SetAddress(address + size);
881 
882     if (rt_unknown)
883       memset(buffer, 'U', reg_info_Rt.byte_size);
884     else {
885       if (!ReadMemory(context_t, address, buffer, reg_info_Rt.byte_size))
886         return false;
887     }
888 
889     if (data_Rt.SetFromMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
890                                   eByteOrderLittle, error) == 0)
891       return false;
892 
893     if (!vector && is_signed && !data_Rt.SignExtend(datasize))
894       return false;
895 
896     if (!WriteRegister(context_t, &reg_info_Rt, data_Rt))
897       return false;
898 
899     if (!rt_unknown) {
900       if (!ReadMemory(context_t2, address + size, buffer,
901                       reg_info_Rt2.byte_size))
902         return false;
903     }
904 
905     if (data_Rt2.SetFromMemoryData(&reg_info_Rt2, buffer,
906                                    reg_info_Rt2.byte_size, eByteOrderLittle,
907                                    error) == 0)
908       return false;
909 
910     if (!vector && is_signed && !data_Rt2.SignExtend(datasize))
911       return false;
912 
913     if (!WriteRegister(context_t2, &reg_info_Rt2, data_Rt2))
914       return false;
915   } break;
916 
917   default:
918     break;
919   }
920 
921   if (wback) {
922     if (wb_unknown)
923       wb_address = LLDB_INVALID_ADDRESS;
924     Context context;
925     context.SetImmediateSigned(idx);
926     if (n == 31)
927       context.type = eContextAdjustStackPointer;
928     else
929       context.type = eContextAdjustBaseRegister;
930     WriteRegisterUnsigned(context, &reg_info_base, wb_address);
931   }
932   return true;
933 }
934 
935 template <EmulateInstructionARM64::AddrMode a_mode>
936 bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) {
937   uint32_t size = Bits32(opcode, 31, 30);
938   uint32_t opc = Bits32(opcode, 23, 22);
939   uint32_t n = Bits32(opcode, 9, 5);
940   uint32_t t = Bits32(opcode, 4, 0);
941 
942   bool wback;
943   bool postindex;
944   uint64_t offset;
945 
946   switch (a_mode) {
947   case AddrMode_POST:
948     wback = true;
949     postindex = true;
950     offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12));
951     break;
952   case AddrMode_PRE:
953     wback = true;
954     postindex = false;
955     offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12));
956     break;
957   case AddrMode_OFF:
958     wback = false;
959     postindex = false;
960     offset = LSL(Bits32(opcode, 21, 10), size);
961     break;
962   }
963 
964   MemOp memop;
965 
966   if (Bit32(opc, 1) == 0) {
967     memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE;
968   } else {
969     memop = MemOp_LOAD;
970     if (size == 2 && Bit32(opc, 0) == 1)
971       return false;
972   }
973 
974   Status error;
975   bool success = false;
976   uint64_t address;
977   uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
978   RegisterValue data_Rt;
979 
980   if (n == 31)
981     address =
982         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
983   else
984     address =
985         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
986 
987   if (!success)
988     return false;
989 
990   if (!postindex)
991     address += offset;
992 
993   RegisterInfo reg_info_base;
994   if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base))
995     return false;
996 
997   RegisterInfo reg_info_Rt;
998   if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt))
999     return false;
1000 
1001   Context context;
1002   switch (memop) {
1003   case MemOp_STORE:
1004     if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is
1005                                                          // based off of the sp
1006                                                          // or fp register
1007       context.type = eContextPushRegisterOnStack;
1008     else
1009       context.type = eContextRegisterStore;
1010     context.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base,
1011                                             postindex ? 0 : offset);
1012 
1013     if (!ReadRegister(&reg_info_Rt, data_Rt))
1014       return false;
1015 
1016     if (data_Rt.GetAsMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
1017                                 eByteOrderLittle, error) == 0)
1018       return false;
1019 
1020     if (!WriteMemory(context, address, buffer, reg_info_Rt.byte_size))
1021       return false;
1022     break;
1023 
1024   case MemOp_LOAD:
1025     if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is
1026                                                          // based off of the sp
1027                                                          // or fp register
1028       context.type = eContextPopRegisterOffStack;
1029     else
1030       context.type = eContextRegisterLoad;
1031     context.SetAddress(address);
1032 
1033     if (!ReadMemory(context, address, buffer, reg_info_Rt.byte_size))
1034       return false;
1035 
1036     if (data_Rt.SetFromMemoryData(&reg_info_Rt, buffer, reg_info_Rt.byte_size,
1037                                   eByteOrderLittle, error) == 0)
1038       return false;
1039 
1040     if (!WriteRegister(context, &reg_info_Rt, data_Rt))
1041       return false;
1042     break;
1043   default:
1044     return false;
1045   }
1046 
1047   if (wback) {
1048     if (postindex)
1049       address += offset;
1050 
1051     if (n == 31)
1052       context.type = eContextAdjustStackPointer;
1053     else
1054       context.type = eContextAdjustBaseRegister;
1055     context.SetImmediateSigned(offset);
1056 
1057     if (!WriteRegisterUnsigned(context, &reg_info_base, address))
1058       return false;
1059   }
1060   return true;
1061 }
1062 
1063 bool EmulateInstructionARM64::EmulateB(const uint32_t opcode) {
1064 #if 0
1065     // ARM64 pseudo code...
1066     if branch_type == BranchType_CALL then X[30] = PC[] + 4;
1067     BranchTo(PC[] + offset, branch_type);
1068 #endif
1069 
1070   bool success = false;
1071 
1072   EmulateInstruction::Context context;
1073   context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1074   const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric,
1075                                            LLDB_REGNUM_GENERIC_PC, 0, &success);
1076   if (!success)
1077     return false;
1078 
1079   int64_t offset = llvm::SignExtend64<28>(Bits32(opcode, 25, 0) << 2);
1080   BranchType branch_type = Bit32(opcode, 31) ? BranchType_CALL : BranchType_JMP;
1081   addr_t target = pc + offset;
1082   context.SetImmediateSigned(offset);
1083 
1084   switch (branch_type) {
1085   case BranchType_CALL: {
1086     addr_t x30 = pc + 4;
1087     if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_lr_arm64, x30))
1088       return false;
1089   } break;
1090   case BranchType_JMP:
1091     break;
1092   default:
1093     return false;
1094   }
1095 
1096   return BranchTo(context, 64, target);
1097 }
1098 
1099 bool EmulateInstructionARM64::EmulateBcond(const uint32_t opcode) {
1100 #if 0
1101     // ARM64 pseudo code...
1102     bits(64) offset = SignExtend(imm19:'00', 64);
1103     bits(4) condition = cond;
1104     if ConditionHolds(condition) then
1105         BranchTo(PC[] + offset, BranchType_JMP);
1106 #endif
1107 
1108   if (ConditionHolds(Bits32(opcode, 3, 0))) {
1109     bool success = false;
1110 
1111     const uint64_t pc = ReadRegisterUnsigned(
1112         eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1113     if (!success)
1114       return false;
1115 
1116     int64_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2);
1117     addr_t target = pc + offset;
1118 
1119     EmulateInstruction::Context context;
1120     context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1121     context.SetImmediateSigned(offset);
1122     if (!BranchTo(context, 64, target))
1123       return false;
1124   }
1125   return true;
1126 }
1127 
1128 bool EmulateInstructionARM64::EmulateCBZ(const uint32_t opcode) {
1129 #if 0
1130     integer t = UInt(Rt);
1131     integer datasize = if sf == '1' then 64 else 32;
1132     boolean iszero = (op == '0');
1133     bits(64) offset = SignExtend(imm19:'00', 64);
1134 
1135     bits(datasize) operand1 = X[t];
1136     if IsZero(operand1) == iszero then
1137         BranchTo(PC[] + offset, BranchType_JMP);
1138 #endif
1139 
1140   bool success = false;
1141 
1142   uint32_t t = Bits32(opcode, 4, 0);
1143   bool is_zero = Bit32(opcode, 24) == 0;
1144   int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2);
1145 
1146   const uint64_t operand =
1147       ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
1148   if (!success)
1149     return false;
1150 
1151   if (m_ignore_conditions || ((operand == 0) == is_zero)) {
1152     const uint64_t pc = ReadRegisterUnsigned(
1153         eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1154     if (!success)
1155       return false;
1156 
1157     EmulateInstruction::Context context;
1158     context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1159     context.SetImmediateSigned(offset);
1160     if (!BranchTo(context, 64, pc + offset))
1161       return false;
1162   }
1163   return true;
1164 }
1165 
1166 bool EmulateInstructionARM64::EmulateTBZ(const uint32_t opcode) {
1167 #if 0
1168     integer t = UInt(Rt);
1169     integer datasize = if b5 == '1' then 64 else 32;
1170     integer bit_pos = UInt(b5:b40);
1171     bit bit_val = op;
1172     bits(64) offset = SignExtend(imm14:'00', 64);
1173 #endif
1174 
1175   bool success = false;
1176 
1177   uint32_t t = Bits32(opcode, 4, 0);
1178   uint32_t bit_pos = (Bit32(opcode, 31) << 6) | (Bits32(opcode, 23, 19));
1179   uint32_t bit_val = Bit32(opcode, 24);
1180   int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2);
1181 
1182   const uint64_t operand =
1183       ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
1184   if (!success)
1185     return false;
1186 
1187   if (m_ignore_conditions || Bit32(operand, bit_pos) == bit_val) {
1188     const uint64_t pc = ReadRegisterUnsigned(
1189         eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1190     if (!success)
1191       return false;
1192 
1193     EmulateInstruction::Context context;
1194     context.type = EmulateInstruction::eContextRelativeBranchImmediate;
1195     context.SetImmediateSigned(offset);
1196     if (!BranchTo(context, 64, pc + offset))
1197       return false;
1198   }
1199   return true;
1200 }
1201