1 //===-- EmulateInstructionARM64.cpp ---------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "EmulateInstructionARM64.h" 10 11 #include <stdlib.h> 12 13 #include "lldb/Core/Address.h" 14 #include "lldb/Core/PluginManager.h" 15 #include "lldb/Symbol/UnwindPlan.h" 16 #include "lldb/Utility/ArchSpec.h" 17 #include "lldb/Utility/ConstString.h" 18 #include "lldb/Utility/RegisterValue.h" 19 #include "lldb/Utility/Stream.h" 20 21 #include "Plugins/Process/Utility/ARMDefines.h" 22 #include "Plugins/Process/Utility/ARMUtils.h" 23 #include "Plugins/Process/Utility/lldb-arm64-register-enums.h" 24 25 #define GPR_OFFSET(idx) ((idx)*8) 26 #define GPR_OFFSET_NAME(reg) 0 27 #define FPU_OFFSET(idx) ((idx)*16) 28 #define FPU_OFFSET_NAME(reg) 0 29 #define EXC_OFFSET_NAME(reg) 0 30 #define DBG_OFFSET_NAME(reg) 0 31 #define DBG_OFFSET_NAME(reg) 0 32 #define DEFINE_DBG(re, y) \ 33 "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \ 34 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 35 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM}, \ 36 nullptr, nullptr, nullptr, 0 37 38 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 39 40 #include "Plugins/Process/Utility/RegisterInfos_arm64.h" 41 42 #include "llvm/ADT/STLExtras.h" 43 #include "llvm/Support/MathExtras.h" 44 45 #include "Plugins/Process/Utility/InstructionUtils.h" 46 47 using namespace lldb; 48 using namespace lldb_private; 49 50 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionARM64, InstructionARM64) 51 52 static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo ®_info) { 53 if (reg_num >= llvm::array_lengthof(g_register_infos_arm64_le)) 54 return false; 55 reg_info = g_register_infos_arm64_le[reg_num]; 56 return true; 57 } 58 59 #define No_VFP 0 60 #define VFPv1 (1u << 1) 61 #define VFPv2 (1u << 2) 62 #define VFPv3 (1u << 3) 63 #define AdvancedSIMD (1u << 4) 64 65 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD) 66 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD) 67 #define VFPv2v3 (VFPv2 | VFPv3) 68 69 #define UInt(x) ((uint64_t)x) 70 #define SInt(x) ((int64_t)x) 71 #define bit bool 72 #define boolean bool 73 #define integer int64_t 74 75 static inline bool IsZero(uint64_t x) { return x == 0; } 76 77 static inline uint64_t NOT(uint64_t x) { return ~x; } 78 79 // LSL() 80 // ===== 81 82 static inline uint64_t LSL(uint64_t x, integer shift) { 83 if (shift == 0) 84 return x; 85 return x << shift; 86 } 87 88 // AddWithCarry() 89 // =============== 90 static inline uint64_t 91 AddWithCarry(uint32_t N, uint64_t x, uint64_t y, bit carry_in, 92 EmulateInstructionARM64::ProcState &proc_state) { 93 uint64_t unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in); 94 int64_t signed_sum = SInt(x) + SInt(y) + UInt(carry_in); 95 uint64_t result = unsigned_sum; 96 if (N < 64) 97 result = Bits64(result, N - 1, 0); 98 proc_state.N = Bit64(result, N - 1); 99 proc_state.Z = IsZero(result); 100 proc_state.C = UInt(result) == unsigned_sum; 101 proc_state.V = SInt(result) == signed_sum; 102 return result; 103 } 104 105 // ConstrainUnpredictable() 106 // ======================== 107 108 EmulateInstructionARM64::ConstraintType 109 ConstrainUnpredictable(EmulateInstructionARM64::Unpredictable which) { 110 EmulateInstructionARM64::ConstraintType result = 111 EmulateInstructionARM64::Constraint_UNKNOWN; 112 switch (which) { 113 case EmulateInstructionARM64::Unpredictable_WBOVERLAP: 114 case EmulateInstructionARM64::Unpredictable_LDPOVERLAP: 115 // TODO: don't know what to really do here? Pseudo code says: 116 // set result to one of above Constraint behaviours or UNDEFINED 117 break; 118 } 119 return result; 120 } 121 122 // 123 // EmulateInstructionARM implementation 124 // 125 126 void EmulateInstructionARM64::Initialize() { 127 PluginManager::RegisterPlugin(GetPluginNameStatic(), 128 GetPluginDescriptionStatic(), CreateInstance); 129 } 130 131 void EmulateInstructionARM64::Terminate() { 132 PluginManager::UnregisterPlugin(CreateInstance); 133 } 134 135 ConstString EmulateInstructionARM64::GetPluginNameStatic() { 136 ConstString g_plugin_name("lldb.emulate-instruction.arm64"); 137 return g_plugin_name; 138 } 139 140 lldb_private::ConstString EmulateInstructionARM64::GetPluginName() { 141 static ConstString g_plugin_name("EmulateInstructionARM64"); 142 return g_plugin_name; 143 } 144 145 const char *EmulateInstructionARM64::GetPluginDescriptionStatic() { 146 return "Emulate instructions for the ARM64 architecture."; 147 } 148 149 EmulateInstruction * 150 EmulateInstructionARM64::CreateInstance(const ArchSpec &arch, 151 InstructionType inst_type) { 152 if (EmulateInstructionARM64::SupportsEmulatingInstructionsOfTypeStatic( 153 inst_type)) { 154 if (arch.GetTriple().getArch() == llvm::Triple::aarch64 || 155 arch.GetTriple().getArch() == llvm::Triple::aarch64_32) { 156 return new EmulateInstructionARM64(arch); 157 } 158 } 159 160 return nullptr; 161 } 162 163 bool EmulateInstructionARM64::SetTargetTriple(const ArchSpec &arch) { 164 if (arch.GetTriple().getArch() == llvm::Triple::arm) 165 return true; 166 else if (arch.GetTriple().getArch() == llvm::Triple::thumb) 167 return true; 168 169 return false; 170 } 171 172 bool EmulateInstructionARM64::GetRegisterInfo(RegisterKind reg_kind, 173 uint32_t reg_num, 174 RegisterInfo ®_info) { 175 if (reg_kind == eRegisterKindGeneric) { 176 switch (reg_num) { 177 case LLDB_REGNUM_GENERIC_PC: 178 reg_kind = eRegisterKindLLDB; 179 reg_num = gpr_pc_arm64; 180 break; 181 case LLDB_REGNUM_GENERIC_SP: 182 reg_kind = eRegisterKindLLDB; 183 reg_num = gpr_sp_arm64; 184 break; 185 case LLDB_REGNUM_GENERIC_FP: 186 reg_kind = eRegisterKindLLDB; 187 reg_num = gpr_fp_arm64; 188 break; 189 case LLDB_REGNUM_GENERIC_RA: 190 reg_kind = eRegisterKindLLDB; 191 reg_num = gpr_lr_arm64; 192 break; 193 case LLDB_REGNUM_GENERIC_FLAGS: 194 reg_kind = eRegisterKindLLDB; 195 reg_num = gpr_cpsr_arm64; 196 break; 197 198 default: 199 return false; 200 } 201 } 202 203 if (reg_kind == eRegisterKindLLDB) 204 return LLDBTableGetRegisterInfo(reg_num, reg_info); 205 return false; 206 } 207 208 EmulateInstructionARM64::Opcode * 209 EmulateInstructionARM64::GetOpcodeForInstruction(const uint32_t opcode) { 210 static EmulateInstructionARM64::Opcode g_opcodes[] = { 211 // Prologue instructions 212 213 // push register(s) 214 {0xff000000, 0xd1000000, No_VFP, 215 &EmulateInstructionARM64::EmulateADDSUBImm, 216 "SUB <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"}, 217 {0xff000000, 0xf1000000, No_VFP, 218 &EmulateInstructionARM64::EmulateADDSUBImm, 219 "SUBS <Xd>, <Xn|SP>, #<imm> {, <shift>}"}, 220 {0xff000000, 0x91000000, No_VFP, 221 &EmulateInstructionARM64::EmulateADDSUBImm, 222 "ADD <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"}, 223 {0xff000000, 0xb1000000, No_VFP, 224 &EmulateInstructionARM64::EmulateADDSUBImm, 225 "ADDS <Xd>, <Xn|SP>, #<imm> {, <shift>}"}, 226 227 {0xff000000, 0x51000000, No_VFP, 228 &EmulateInstructionARM64::EmulateADDSUBImm, 229 "SUB <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"}, 230 {0xff000000, 0x71000000, No_VFP, 231 &EmulateInstructionARM64::EmulateADDSUBImm, 232 "SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"}, 233 {0xff000000, 0x11000000, No_VFP, 234 &EmulateInstructionARM64::EmulateADDSUBImm, 235 "ADD <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"}, 236 {0xff000000, 0x31000000, No_VFP, 237 &EmulateInstructionARM64::EmulateADDSUBImm, 238 "ADDS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"}, 239 240 {0xffc00000, 0x29000000, No_VFP, 241 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 242 "STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"}, 243 {0xffc00000, 0xa9000000, No_VFP, 244 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 245 "STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"}, 246 {0xffc00000, 0x2d000000, No_VFP, 247 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 248 "STP <St>, <St2>, [<Xn|SP>{, #<imm>}]"}, 249 {0xffc00000, 0x6d000000, No_VFP, 250 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 251 "STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"}, 252 {0xffc00000, 0xad000000, No_VFP, 253 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 254 "STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"}, 255 256 {0xffc00000, 0x29800000, No_VFP, 257 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 258 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 259 {0xffc00000, 0xa9800000, No_VFP, 260 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 261 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 262 {0xffc00000, 0x2d800000, No_VFP, 263 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 264 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 265 {0xffc00000, 0x6d800000, No_VFP, 266 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 267 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 268 {0xffc00000, 0xad800000, No_VFP, 269 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 270 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 271 272 {0xffc00000, 0x28800000, No_VFP, 273 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 274 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 275 {0xffc00000, 0xa8800000, No_VFP, 276 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 277 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 278 {0xffc00000, 0x2c800000, No_VFP, 279 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 280 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 281 {0xffc00000, 0x6c800000, No_VFP, 282 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 283 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 284 {0xffc00000, 0xac800000, No_VFP, 285 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 286 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 287 288 {0xffc00000, 0x29400000, No_VFP, 289 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 290 "LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"}, 291 {0xffc00000, 0xa9400000, No_VFP, 292 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 293 "LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"}, 294 {0xffc00000, 0x2d400000, No_VFP, 295 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 296 "LDP <St>, <St2>, [<Xn|SP>{, #<imm>}]"}, 297 {0xffc00000, 0x6d400000, No_VFP, 298 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 299 "LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"}, 300 {0xffc00000, 0xad400000, No_VFP, 301 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 302 "LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"}, 303 304 {0xffc00000, 0x29c00000, No_VFP, 305 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 306 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 307 {0xffc00000, 0xa9c00000, No_VFP, 308 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 309 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 310 {0xffc00000, 0x2dc00000, No_VFP, 311 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 312 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 313 {0xffc00000, 0x6dc00000, No_VFP, 314 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 315 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 316 {0xffc00000, 0xadc00000, No_VFP, 317 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 318 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 319 320 {0xffc00000, 0x28c00000, No_VFP, 321 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 322 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 323 {0xffc00000, 0xa8c00000, No_VFP, 324 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 325 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 326 {0xffc00000, 0x2cc00000, No_VFP, 327 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 328 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 329 {0xffc00000, 0x6cc00000, No_VFP, 330 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 331 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 332 {0xffc00000, 0xacc00000, No_VFP, 333 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 334 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 335 336 {0xffe00c00, 0xb8000400, No_VFP, 337 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 338 "STR <Wt>, [<Xn|SP>], #<simm>"}, 339 {0xffe00c00, 0xf8000400, No_VFP, 340 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 341 "STR <Xt>, [<Xn|SP>], #<simm>"}, 342 {0xffe00c00, 0xb8000c00, No_VFP, 343 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 344 "STR <Wt>, [<Xn|SP>, #<simm>]!"}, 345 {0xffe00c00, 0xf8000c00, No_VFP, 346 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 347 "STR <Xt>, [<Xn|SP>, #<simm>]!"}, 348 {0xffc00000, 0xb9000000, No_VFP, 349 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 350 "STR <Wt>, [<Xn|SP>{, #<pimm>}]"}, 351 {0xffc00000, 0xf9000000, No_VFP, 352 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 353 "STR <Xt>, [<Xn|SP>{, #<pimm>}]"}, 354 355 {0xffe00c00, 0xb8400400, No_VFP, 356 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 357 "LDR <Wt>, [<Xn|SP>], #<simm>"}, 358 {0xffe00c00, 0xf8400400, No_VFP, 359 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 360 "LDR <Xt>, [<Xn|SP>], #<simm>"}, 361 {0xffe00c00, 0xb8400c00, No_VFP, 362 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 363 "LDR <Wt>, [<Xn|SP>, #<simm>]!"}, 364 {0xffe00c00, 0xf8400c00, No_VFP, 365 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 366 "LDR <Xt>, [<Xn|SP>, #<simm>]!"}, 367 {0xffc00000, 0xb9400000, No_VFP, 368 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 369 "LDR <Wt>, [<Xn|SP>{, #<pimm>}]"}, 370 {0xffc00000, 0xf9400000, No_VFP, 371 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 372 "LDR <Xt>, [<Xn|SP>{, #<pimm>}]"}, 373 374 {0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB, 375 "B <label>"}, 376 {0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond, 377 "B.<cond> <label>"}, 378 {0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, 379 "CBZ <Wt>, <label>"}, 380 {0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, 381 "CBNZ <Wt>, <label>"}, 382 {0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, 383 "TBZ <R><t>, #<imm>, <label>"}, 384 {0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, 385 "TBNZ <R><t>, #<imm>, <label>"}, 386 387 }; 388 static const size_t k_num_arm_opcodes = llvm::array_lengthof(g_opcodes); 389 390 for (size_t i = 0; i < k_num_arm_opcodes; ++i) { 391 if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value) 392 return &g_opcodes[i]; 393 } 394 return nullptr; 395 } 396 397 bool EmulateInstructionARM64::ReadInstruction() { 398 bool success = false; 399 m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 400 LLDB_INVALID_ADDRESS, &success); 401 if (success) { 402 Context read_inst_context; 403 read_inst_context.type = eContextReadOpcode; 404 read_inst_context.SetNoArgs(); 405 m_opcode.SetOpcode32( 406 ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success), 407 GetByteOrder()); 408 } 409 if (!success) 410 m_addr = LLDB_INVALID_ADDRESS; 411 return success; 412 } 413 414 bool EmulateInstructionARM64::EvaluateInstruction(uint32_t evaluate_options) { 415 const uint32_t opcode = m_opcode.GetOpcode32(); 416 Opcode *opcode_data = GetOpcodeForInstruction(opcode); 417 if (opcode_data == nullptr) 418 return false; 419 420 // printf ("opcode template for 0x%8.8x: %s\n", opcode, opcode_data->name); 421 const bool auto_advance_pc = 422 evaluate_options & eEmulateInstructionOptionAutoAdvancePC; 423 m_ignore_conditions = 424 evaluate_options & eEmulateInstructionOptionIgnoreConditions; 425 426 bool success = false; 427 // if (m_opcode_cpsr == 0 || m_ignore_conditions == false) 428 // { 429 // m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindLLDB, 430 // gpr_cpsr_arm64, 431 // 0, 432 // &success); 433 // } 434 435 // Only return false if we are unable to read the CPSR if we care about 436 // conditions 437 if (!success && !m_ignore_conditions) 438 return false; 439 440 uint32_t orig_pc_value = 0; 441 if (auto_advance_pc) { 442 orig_pc_value = 443 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success); 444 if (!success) 445 return false; 446 } 447 448 // Call the Emulate... function. 449 success = (this->*opcode_data->callback)(opcode); 450 if (!success) 451 return false; 452 453 if (auto_advance_pc) { 454 uint32_t new_pc_value = 455 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success); 456 if (!success) 457 return false; 458 459 if (auto_advance_pc && (new_pc_value == orig_pc_value)) { 460 EmulateInstruction::Context context; 461 context.type = eContextAdvancePC; 462 context.SetNoArgs(); 463 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_pc_arm64, 464 orig_pc_value + 4)) 465 return false; 466 } 467 } 468 return true; 469 } 470 471 bool EmulateInstructionARM64::CreateFunctionEntryUnwind( 472 UnwindPlan &unwind_plan) { 473 unwind_plan.Clear(); 474 unwind_plan.SetRegisterKind(eRegisterKindLLDB); 475 476 UnwindPlan::RowSP row(new UnwindPlan::Row); 477 478 // Our previous Call Frame Address is the stack pointer 479 row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0); 480 481 unwind_plan.AppendRow(row); 482 unwind_plan.SetSourceName("EmulateInstructionARM64"); 483 unwind_plan.SetSourcedFromCompiler(eLazyBoolNo); 484 unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes); 485 unwind_plan.SetUnwindPlanForSignalTrap(eLazyBoolNo); 486 unwind_plan.SetReturnAddressRegister(gpr_lr_arm64); 487 return true; 488 } 489 490 uint32_t EmulateInstructionARM64::GetFramePointerRegisterNumber() const { 491 if (m_arch.GetTriple().isAndroid()) 492 return LLDB_INVALID_REGNUM; // Don't use frame pointer on android 493 494 return gpr_fp_arm64; 495 } 496 497 bool EmulateInstructionARM64::UsingAArch32() { 498 bool aarch32 = m_opcode_pstate.RW == 1; 499 // if !HaveAnyAArch32() then assert !aarch32; 500 // if HighestELUsingAArch32() then assert aarch32; 501 return aarch32; 502 } 503 504 bool EmulateInstructionARM64::BranchTo(const Context &context, uint32_t N, 505 addr_t target) { 506 #if 0 507 // Set program counter to a new address, with a branch reason hint for 508 // possible use by hardware fetching the next instruction. 509 BranchTo(bits(N) target, BranchType branch_type) 510 Hint_Branch(branch_type); 511 if N == 32 then 512 assert UsingAArch32(); 513 _PC = ZeroExtend(target); 514 else 515 assert N == 64 && !UsingAArch32(); 516 // Remove the tag bits from a tagged target 517 case PSTATE.EL of 518 when EL0, EL1 519 if target<55> == '1' && TCR_EL1.TBI1 == '1' then 520 target<63:56> = '11111111'; 521 if target<55> == '0' && TCR_EL1.TBI0 == '1' then 522 target<63:56> = '00000000'; 523 when EL2 524 if TCR_EL2.TBI == '1' then 525 target<63:56> = '00000000'; 526 when EL3 527 if TCR_EL3.TBI == '1' then 528 target<63:56> = '00000000'; 529 _PC = target<63:0>; 530 return; 531 #endif 532 533 addr_t addr; 534 535 // Hint_Branch(branch_type); 536 if (N == 32) { 537 if (!UsingAArch32()) 538 return false; 539 addr = target; 540 } else if (N == 64) { 541 if (UsingAArch32()) 542 return false; 543 // TODO: Remove the tag bits from a tagged target 544 addr = target; 545 } else 546 return false; 547 548 return WriteRegisterUnsigned(context, eRegisterKindGeneric, 549 LLDB_REGNUM_GENERIC_PC, addr); 550 } 551 552 bool EmulateInstructionARM64::ConditionHolds(const uint32_t cond) { 553 // If we are ignoring conditions, then always return true. this allows us to 554 // iterate over disassembly code and still emulate an instruction even if we 555 // don't have all the right bits set in the CPSR register... 556 if (m_ignore_conditions) 557 return true; 558 559 bool result = false; 560 switch (UnsignedBits(cond, 3, 1)) { 561 case 0: 562 result = (m_opcode_pstate.Z == 1); 563 break; 564 case 1: 565 result = (m_opcode_pstate.C == 1); 566 break; 567 case 2: 568 result = (m_opcode_pstate.N == 1); 569 break; 570 case 3: 571 result = (m_opcode_pstate.V == 1); 572 break; 573 case 4: 574 result = (m_opcode_pstate.C == 1 && m_opcode_pstate.Z == 0); 575 break; 576 case 5: 577 result = (m_opcode_pstate.N == m_opcode_pstate.V); 578 break; 579 case 6: 580 result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0); 581 break; 582 case 7: 583 // Always execute (cond == 0b1110, or the special 0b1111 which gives 584 // opcodes different meanings, but always means execution happens. 585 return true; 586 } 587 588 if (cond & 1) 589 result = !result; 590 return result; 591 } 592 593 bool EmulateInstructionARM64::EmulateADDSUBImm(const uint32_t opcode) { 594 // integer d = UInt(Rd); 595 // integer n = UInt(Rn); 596 // integer datasize = if sf == 1 then 64 else 32; 597 // boolean sub_op = (op == 1); 598 // boolean setflags = (S == 1); 599 // bits(datasize) imm; 600 // 601 // case shift of 602 // when '00' imm = ZeroExtend(imm12, datasize); 603 // when '01' imm = ZeroExtend(imm12 : Zeros(12), datasize); 604 // when '1x' UNDEFINED; 605 // 606 // 607 // bits(datasize) result; 608 // bits(datasize) operand1 = if n == 31 then SP[] else X[n]; 609 // bits(datasize) operand2 = imm; 610 // bits(4) nzcv; 611 // bit carry_in; 612 // 613 // if sub_op then 614 // operand2 = NOT(operand2); 615 // carry_in = 1; 616 // else 617 // carry_in = 0; 618 // 619 // (result, nzcv) = AddWithCarry(operand1, operand2, carry_in); 620 // 621 // if setflags then 622 // PSTATE.NZCV = nzcv; 623 // 624 // if d == 31 && !setflags then 625 // SP[] = result; 626 // else 627 // X[d] = result; 628 629 const uint32_t sf = Bit32(opcode, 31); 630 const uint32_t op = Bit32(opcode, 30); 631 const uint32_t S = Bit32(opcode, 29); 632 const uint32_t shift = Bits32(opcode, 23, 22); 633 const uint32_t imm12 = Bits32(opcode, 21, 10); 634 const uint32_t Rn = Bits32(opcode, 9, 5); 635 const uint32_t Rd = Bits32(opcode, 4, 0); 636 637 bool success = false; 638 639 const uint32_t d = UInt(Rd); 640 const uint32_t n = UInt(Rn); 641 const uint32_t datasize = (sf == 1) ? 64 : 32; 642 boolean sub_op = op == 1; 643 boolean setflags = S == 1; 644 uint64_t imm; 645 646 switch (shift) { 647 case 0: 648 imm = imm12; 649 break; 650 case 1: 651 imm = imm12 << 12; 652 break; 653 default: 654 return false; // UNDEFINED; 655 } 656 uint64_t result; 657 uint64_t operand1 = 658 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 659 uint64_t operand2 = imm; 660 bit carry_in; 661 662 if (sub_op) { 663 operand2 = NOT(operand2); 664 carry_in = true; 665 imm = -imm; // For the Register plug offset context below 666 } else { 667 carry_in = false; 668 } 669 670 ProcState proc_state; 671 672 result = AddWithCarry(datasize, operand1, operand2, carry_in, proc_state); 673 674 if (setflags) { 675 m_emulated_pstate.N = proc_state.N; 676 m_emulated_pstate.Z = proc_state.Z; 677 m_emulated_pstate.C = proc_state.C; 678 m_emulated_pstate.V = proc_state.V; 679 } 680 681 Context context; 682 RegisterInfo reg_info_Rn; 683 if (GetRegisterInfo(eRegisterKindLLDB, n, reg_info_Rn)) 684 context.SetRegisterPlusOffset(reg_info_Rn, imm); 685 686 if (n == GetFramePointerRegisterNumber() && d == gpr_sp_arm64 && !setflags) { 687 // 'mov sp, fp' - common epilogue instruction, CFA is now in terms of the 688 // stack pointer, instead of frame pointer. 689 context.type = EmulateInstruction::eContextRestoreStackPointer; 690 } else if ((n == gpr_sp_arm64 || n == GetFramePointerRegisterNumber()) && 691 d == gpr_sp_arm64 && !setflags) { 692 context.type = EmulateInstruction::eContextAdjustStackPointer; 693 } else if (d == GetFramePointerRegisterNumber() && n == gpr_sp_arm64 && 694 !setflags) { 695 context.type = EmulateInstruction::eContextSetFramePointer; 696 } else { 697 context.type = EmulateInstruction::eContextImmediate; 698 } 699 700 // If setflags && d == gpr_sp_arm64 then d = WZR/XZR. See CMN, CMP 701 if (!setflags || d != gpr_sp_arm64) 702 WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_x0_arm64 + d, result); 703 704 return false; 705 } 706 707 template <EmulateInstructionARM64::AddrMode a_mode> 708 bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) { 709 uint32_t opc = Bits32(opcode, 31, 30); 710 uint32_t V = Bit32(opcode, 26); 711 uint32_t L = Bit32(opcode, 22); 712 uint32_t imm7 = Bits32(opcode, 21, 15); 713 uint32_t Rt2 = Bits32(opcode, 14, 10); 714 uint32_t Rn = Bits32(opcode, 9, 5); 715 uint32_t Rt = Bits32(opcode, 4, 0); 716 717 integer n = UInt(Rn); 718 integer t = UInt(Rt); 719 integer t2 = UInt(Rt2); 720 uint64_t idx; 721 722 MemOp memop = L == 1 ? MemOp_LOAD : MemOp_STORE; 723 boolean vector = (V == 1); 724 // AccType acctype = AccType_NORMAL; 725 boolean is_signed = false; 726 boolean wback = a_mode != AddrMode_OFF; 727 boolean wb_unknown = false; 728 boolean rt_unknown = false; 729 integer scale; 730 integer size; 731 732 if (opc == 3) 733 return false; // UNDEFINED 734 735 if (vector) { 736 scale = 2 + UInt(opc); 737 } else { 738 scale = (opc & 2) ? 3 : 2; 739 is_signed = (opc & 1) != 0; 740 if (is_signed && memop == MemOp_STORE) 741 return false; // UNDEFINED 742 } 743 744 if (!vector && wback && ((t == n) || (t2 == n))) { 745 switch (ConstrainUnpredictable(Unpredictable_WBOVERLAP)) { 746 case Constraint_UNKNOWN: 747 wb_unknown = true; // writeback is UNKNOWN 748 break; 749 750 case Constraint_SUPPRESSWB: 751 wback = false; // writeback is suppressed 752 break; 753 754 case Constraint_NOP: 755 memop = MemOp_NOP; // do nothing 756 wback = false; 757 break; 758 759 case Constraint_NONE: 760 break; 761 } 762 } 763 764 if (memop == MemOp_LOAD && t == t2) { 765 switch (ConstrainUnpredictable(Unpredictable_LDPOVERLAP)) { 766 case Constraint_UNKNOWN: 767 rt_unknown = true; // result is UNKNOWN 768 break; 769 770 case Constraint_NOP: 771 memop = MemOp_NOP; // do nothing 772 wback = false; 773 break; 774 775 default: 776 break; 777 } 778 } 779 780 idx = LSL(llvm::SignExtend64<7>(imm7), scale); 781 size = (integer)1 << scale; 782 uint64_t datasize = size * 8; 783 uint64_t address; 784 uint64_t wb_address; 785 786 RegisterValue data_Rt; 787 RegisterValue data_Rt2; 788 789 // if (vector) 790 // CheckFPEnabled(false); 791 792 RegisterInfo reg_info_base; 793 RegisterInfo reg_info_Rt; 794 RegisterInfo reg_info_Rt2; 795 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base)) 796 return false; 797 798 if (vector) { 799 if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t, reg_info_Rt)) 800 return false; 801 if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2, reg_info_Rt2)) 802 return false; 803 } else { 804 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt)) 805 return false; 806 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2, reg_info_Rt2)) 807 return false; 808 } 809 810 bool success = false; 811 if (n == 31) { 812 // CheckSPAlignment(); 813 address = 814 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success); 815 } else 816 address = 817 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 818 819 wb_address = address + idx; 820 if (a_mode != AddrMode_POST) 821 address = wb_address; 822 823 Context context_t; 824 Context context_t2; 825 826 uint8_t buffer[RegisterValue::kMaxRegisterByteSize]; 827 Status error; 828 829 switch (memop) { 830 case MemOp_STORE: { 831 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 832 // based off of the sp 833 // or fp register 834 { 835 context_t.type = eContextPushRegisterOnStack; 836 context_t2.type = eContextPushRegisterOnStack; 837 } else { 838 context_t.type = eContextRegisterStore; 839 context_t2.type = eContextRegisterStore; 840 } 841 context_t.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 0); 842 context_t2.SetRegisterToRegisterPlusOffset(reg_info_Rt2, reg_info_base, 843 size); 844 845 if (!ReadRegister(®_info_Rt, data_Rt)) 846 return false; 847 848 if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 849 eByteOrderLittle, error) == 0) 850 return false; 851 852 if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt.byte_size)) 853 return false; 854 855 if (!ReadRegister(®_info_Rt2, data_Rt2)) 856 return false; 857 858 if (data_Rt2.GetAsMemoryData(®_info_Rt2, buffer, reg_info_Rt2.byte_size, 859 eByteOrderLittle, error) == 0) 860 return false; 861 862 if (!WriteMemory(context_t2, address + size, buffer, 863 reg_info_Rt2.byte_size)) 864 return false; 865 } break; 866 867 case MemOp_LOAD: { 868 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this load is 869 // based off of the sp 870 // or fp register 871 { 872 context_t.type = eContextPopRegisterOffStack; 873 context_t2.type = eContextPopRegisterOffStack; 874 } else { 875 context_t.type = eContextRegisterLoad; 876 context_t2.type = eContextRegisterLoad; 877 } 878 context_t.SetAddress(address); 879 context_t2.SetAddress(address + size); 880 881 if (rt_unknown) 882 memset(buffer, 'U', reg_info_Rt.byte_size); 883 else { 884 if (!ReadMemory(context_t, address, buffer, reg_info_Rt.byte_size)) 885 return false; 886 } 887 888 if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 889 eByteOrderLittle, error) == 0) 890 return false; 891 892 if (!vector && is_signed && !data_Rt.SignExtend(datasize)) 893 return false; 894 895 if (!WriteRegister(context_t, ®_info_Rt, data_Rt)) 896 return false; 897 898 if (!rt_unknown) { 899 if (!ReadMemory(context_t2, address + size, buffer, 900 reg_info_Rt2.byte_size)) 901 return false; 902 } 903 904 if (data_Rt2.SetFromMemoryData(®_info_Rt2, buffer, 905 reg_info_Rt2.byte_size, eByteOrderLittle, 906 error) == 0) 907 return false; 908 909 if (!vector && is_signed && !data_Rt2.SignExtend(datasize)) 910 return false; 911 912 if (!WriteRegister(context_t2, ®_info_Rt2, data_Rt2)) 913 return false; 914 } break; 915 916 default: 917 break; 918 } 919 920 if (wback) { 921 if (wb_unknown) 922 wb_address = LLDB_INVALID_ADDRESS; 923 Context context; 924 context.SetImmediateSigned(idx); 925 if (n == 31) 926 context.type = eContextAdjustStackPointer; 927 else 928 context.type = eContextAdjustBaseRegister; 929 WriteRegisterUnsigned(context, ®_info_base, wb_address); 930 } 931 return true; 932 } 933 934 template <EmulateInstructionARM64::AddrMode a_mode> 935 bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) { 936 uint32_t size = Bits32(opcode, 31, 30); 937 uint32_t opc = Bits32(opcode, 23, 22); 938 uint32_t n = Bits32(opcode, 9, 5); 939 uint32_t t = Bits32(opcode, 4, 0); 940 941 bool wback; 942 bool postindex; 943 uint64_t offset; 944 945 switch (a_mode) { 946 case AddrMode_POST: 947 wback = true; 948 postindex = true; 949 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); 950 break; 951 case AddrMode_PRE: 952 wback = true; 953 postindex = false; 954 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); 955 break; 956 case AddrMode_OFF: 957 wback = false; 958 postindex = false; 959 offset = LSL(Bits32(opcode, 21, 10), size); 960 break; 961 } 962 963 MemOp memop; 964 965 if (Bit32(opc, 1) == 0) { 966 memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE; 967 } else { 968 memop = MemOp_LOAD; 969 if (size == 2 && Bit32(opc, 0) == 1) 970 return false; 971 } 972 973 Status error; 974 bool success = false; 975 uint64_t address; 976 uint8_t buffer[RegisterValue::kMaxRegisterByteSize]; 977 RegisterValue data_Rt; 978 979 if (n == 31) 980 address = 981 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success); 982 else 983 address = 984 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 985 986 if (!success) 987 return false; 988 989 if (!postindex) 990 address += offset; 991 992 RegisterInfo reg_info_base; 993 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base)) 994 return false; 995 996 RegisterInfo reg_info_Rt; 997 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt)) 998 return false; 999 1000 Context context; 1001 switch (memop) { 1002 case MemOp_STORE: 1003 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 1004 // based off of the sp 1005 // or fp register 1006 context.type = eContextPushRegisterOnStack; 1007 else 1008 context.type = eContextRegisterStore; 1009 context.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 1010 postindex ? 0 : offset); 1011 1012 if (!ReadRegister(®_info_Rt, data_Rt)) 1013 return false; 1014 1015 if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 1016 eByteOrderLittle, error) == 0) 1017 return false; 1018 1019 if (!WriteMemory(context, address, buffer, reg_info_Rt.byte_size)) 1020 return false; 1021 break; 1022 1023 case MemOp_LOAD: 1024 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 1025 // based off of the sp 1026 // or fp register 1027 context.type = eContextPopRegisterOffStack; 1028 else 1029 context.type = eContextRegisterLoad; 1030 context.SetAddress(address); 1031 1032 if (!ReadMemory(context, address, buffer, reg_info_Rt.byte_size)) 1033 return false; 1034 1035 if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 1036 eByteOrderLittle, error) == 0) 1037 return false; 1038 1039 if (!WriteRegister(context, ®_info_Rt, data_Rt)) 1040 return false; 1041 break; 1042 default: 1043 return false; 1044 } 1045 1046 if (wback) { 1047 if (postindex) 1048 address += offset; 1049 1050 if (n == 31) 1051 context.type = eContextAdjustStackPointer; 1052 else 1053 context.type = eContextAdjustBaseRegister; 1054 context.SetImmediateSigned(offset); 1055 1056 if (!WriteRegisterUnsigned(context, ®_info_base, address)) 1057 return false; 1058 } 1059 return true; 1060 } 1061 1062 bool EmulateInstructionARM64::EmulateB(const uint32_t opcode) { 1063 #if 0 1064 // ARM64 pseudo code... 1065 if branch_type == BranchType_CALL then X[30] = PC[] + 4; 1066 BranchTo(PC[] + offset, branch_type); 1067 #endif 1068 1069 bool success = false; 1070 1071 EmulateInstruction::Context context; 1072 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1073 const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, 1074 LLDB_REGNUM_GENERIC_PC, 0, &success); 1075 if (!success) 1076 return false; 1077 1078 int64_t offset = llvm::SignExtend64<28>(Bits32(opcode, 25, 0) << 2); 1079 BranchType branch_type = Bit32(opcode, 31) ? BranchType_CALL : BranchType_JMP; 1080 addr_t target = pc + offset; 1081 context.SetImmediateSigned(offset); 1082 1083 switch (branch_type) { 1084 case BranchType_CALL: { 1085 addr_t x30 = pc + 4; 1086 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_lr_arm64, x30)) 1087 return false; 1088 } break; 1089 case BranchType_JMP: 1090 break; 1091 default: 1092 return false; 1093 } 1094 1095 return BranchTo(context, 64, target); 1096 } 1097 1098 bool EmulateInstructionARM64::EmulateBcond(const uint32_t opcode) { 1099 #if 0 1100 // ARM64 pseudo code... 1101 bits(64) offset = SignExtend(imm19:'00', 64); 1102 bits(4) condition = cond; 1103 if ConditionHolds(condition) then 1104 BranchTo(PC[] + offset, BranchType_JMP); 1105 #endif 1106 1107 if (ConditionHolds(Bits32(opcode, 3, 0))) { 1108 bool success = false; 1109 1110 const uint64_t pc = ReadRegisterUnsigned( 1111 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1112 if (!success) 1113 return false; 1114 1115 int64_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 1116 addr_t target = pc + offset; 1117 1118 EmulateInstruction::Context context; 1119 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1120 context.SetImmediateSigned(offset); 1121 if (!BranchTo(context, 64, target)) 1122 return false; 1123 } 1124 return true; 1125 } 1126 1127 bool EmulateInstructionARM64::EmulateCBZ(const uint32_t opcode) { 1128 #if 0 1129 integer t = UInt(Rt); 1130 integer datasize = if sf == '1' then 64 else 32; 1131 boolean iszero = (op == '0'); 1132 bits(64) offset = SignExtend(imm19:'00', 64); 1133 1134 bits(datasize) operand1 = X[t]; 1135 if IsZero(operand1) == iszero then 1136 BranchTo(PC[] + offset, BranchType_JMP); 1137 #endif 1138 1139 bool success = false; 1140 1141 uint32_t t = Bits32(opcode, 4, 0); 1142 bool is_zero = Bit32(opcode, 24) == 0; 1143 int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 1144 1145 const uint64_t operand = 1146 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success); 1147 if (!success) 1148 return false; 1149 1150 if (m_ignore_conditions || ((operand == 0) == is_zero)) { 1151 const uint64_t pc = ReadRegisterUnsigned( 1152 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1153 if (!success) 1154 return false; 1155 1156 EmulateInstruction::Context context; 1157 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1158 context.SetImmediateSigned(offset); 1159 if (!BranchTo(context, 64, pc + offset)) 1160 return false; 1161 } 1162 return true; 1163 } 1164 1165 bool EmulateInstructionARM64::EmulateTBZ(const uint32_t opcode) { 1166 #if 0 1167 integer t = UInt(Rt); 1168 integer datasize = if b5 == '1' then 64 else 32; 1169 integer bit_pos = UInt(b5:b40); 1170 bit bit_val = op; 1171 bits(64) offset = SignExtend(imm14:'00', 64); 1172 #endif 1173 1174 bool success = false; 1175 1176 uint32_t t = Bits32(opcode, 4, 0); 1177 uint32_t bit_pos = (Bit32(opcode, 31) << 6) | (Bits32(opcode, 23, 19)); 1178 uint32_t bit_val = Bit32(opcode, 24); 1179 int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2); 1180 1181 const uint64_t operand = 1182 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success); 1183 if (!success) 1184 return false; 1185 1186 if (m_ignore_conditions || Bit32(operand, bit_pos) == bit_val) { 1187 const uint64_t pc = ReadRegisterUnsigned( 1188 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1189 if (!success) 1190 return false; 1191 1192 EmulateInstruction::Context context; 1193 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1194 context.SetImmediateSigned(offset); 1195 if (!BranchTo(context, 64, pc + offset)) 1196 return false; 1197 } 1198 return true; 1199 } 1200