1 //===-- EmulateInstructionARM64.cpp ------------------------------*- C++-*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "EmulateInstructionARM64.h" 10 11 #include <stdlib.h> 12 13 #include "lldb/Core/Address.h" 14 #include "lldb/Core/PluginManager.h" 15 #include "lldb/Symbol/UnwindPlan.h" 16 #include "lldb/Utility/ArchSpec.h" 17 #include "lldb/Utility/ConstString.h" 18 #include "lldb/Utility/RegisterValue.h" 19 #include "lldb/Utility/Stream.h" 20 21 #include "Plugins/Process/Utility/ARMDefines.h" 22 #include "Plugins/Process/Utility/ARMUtils.h" 23 #include "Plugins/Process/Utility/lldb-arm64-register-enums.h" 24 25 #define GPR_OFFSET(idx) ((idx)*8) 26 #define GPR_OFFSET_NAME(reg) 0 27 #define FPU_OFFSET(idx) ((idx)*16) 28 #define FPU_OFFSET_NAME(reg) 0 29 #define EXC_OFFSET_NAME(reg) 0 30 #define DBG_OFFSET_NAME(reg) 0 31 #define DBG_OFFSET_NAME(reg) 0 32 #define DEFINE_DBG(re, y) \ 33 "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \ 34 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ 35 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM}, \ 36 nullptr, nullptr, nullptr, 0 37 38 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT 39 40 #include "Plugins/Process/Utility/RegisterInfos_arm64.h" 41 42 #include "llvm/ADT/STLExtras.h" 43 #include "llvm/Support/MathExtras.h" 44 45 #include "Plugins/Process/Utility/InstructionUtils.h" 46 47 using namespace lldb; 48 using namespace lldb_private; 49 50 static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo ®_info) { 51 if (reg_num >= llvm::array_lengthof(g_register_infos_arm64_le)) 52 return false; 53 reg_info = g_register_infos_arm64_le[reg_num]; 54 return true; 55 } 56 57 #define No_VFP 0 58 #define VFPv1 (1u << 1) 59 #define VFPv2 (1u << 2) 60 #define VFPv3 (1u << 3) 61 #define AdvancedSIMD (1u << 4) 62 63 #define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD) 64 #define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD) 65 #define VFPv2v3 (VFPv2 | VFPv3) 66 67 #define UInt(x) ((uint64_t)x) 68 #define SInt(x) ((int64_t)x) 69 #define bit bool 70 #define boolean bool 71 #define integer int64_t 72 73 static inline bool IsZero(uint64_t x) { return x == 0; } 74 75 static inline uint64_t NOT(uint64_t x) { return ~x; } 76 77 // LSL() 78 // ===== 79 80 static inline uint64_t LSL(uint64_t x, integer shift) { 81 if (shift == 0) 82 return x; 83 return x << shift; 84 } 85 86 // AddWithCarry() 87 // =============== 88 static inline uint64_t 89 AddWithCarry(uint32_t N, uint64_t x, uint64_t y, bit carry_in, 90 EmulateInstructionARM64::ProcState &proc_state) { 91 uint64_t unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in); 92 int64_t signed_sum = SInt(x) + SInt(y) + UInt(carry_in); 93 uint64_t result = unsigned_sum; 94 if (N < 64) 95 result = Bits64(result, N - 1, 0); 96 proc_state.N = Bit64(result, N - 1); 97 proc_state.Z = IsZero(result); 98 proc_state.C = UInt(result) == unsigned_sum; 99 proc_state.V = SInt(result) == signed_sum; 100 return result; 101 } 102 103 // ConstrainUnpredictable() 104 // ======================== 105 106 EmulateInstructionARM64::ConstraintType 107 ConstrainUnpredictable(EmulateInstructionARM64::Unpredictable which) { 108 EmulateInstructionARM64::ConstraintType result = 109 EmulateInstructionARM64::Constraint_UNKNOWN; 110 switch (which) { 111 case EmulateInstructionARM64::Unpredictable_WBOVERLAP: 112 case EmulateInstructionARM64::Unpredictable_LDPOVERLAP: 113 // TODO: don't know what to really do here? Pseudo code says: 114 // set result to one of above Constraint behaviours or UNDEFINED 115 break; 116 } 117 return result; 118 } 119 120 // 121 // EmulateInstructionARM implementation 122 // 123 124 void EmulateInstructionARM64::Initialize() { 125 PluginManager::RegisterPlugin(GetPluginNameStatic(), 126 GetPluginDescriptionStatic(), CreateInstance); 127 } 128 129 void EmulateInstructionARM64::Terminate() { 130 PluginManager::UnregisterPlugin(CreateInstance); 131 } 132 133 ConstString EmulateInstructionARM64::GetPluginNameStatic() { 134 ConstString g_plugin_name("lldb.emulate-instruction.arm64"); 135 return g_plugin_name; 136 } 137 138 lldb_private::ConstString EmulateInstructionARM64::GetPluginName() { 139 static ConstString g_plugin_name("EmulateInstructionARM64"); 140 return g_plugin_name; 141 } 142 143 const char *EmulateInstructionARM64::GetPluginDescriptionStatic() { 144 return "Emulate instructions for the ARM64 architecture."; 145 } 146 147 EmulateInstruction * 148 EmulateInstructionARM64::CreateInstance(const ArchSpec &arch, 149 InstructionType inst_type) { 150 if (EmulateInstructionARM64::SupportsEmulatingInstructionsOfTypeStatic( 151 inst_type)) { 152 if (arch.GetTriple().getArch() == llvm::Triple::aarch64) { 153 return new EmulateInstructionARM64(arch); 154 } 155 } 156 157 return nullptr; 158 } 159 160 bool EmulateInstructionARM64::SetTargetTriple(const ArchSpec &arch) { 161 if (arch.GetTriple().getArch() == llvm::Triple::arm) 162 return true; 163 else if (arch.GetTriple().getArch() == llvm::Triple::thumb) 164 return true; 165 166 return false; 167 } 168 169 bool EmulateInstructionARM64::GetRegisterInfo(RegisterKind reg_kind, 170 uint32_t reg_num, 171 RegisterInfo ®_info) { 172 if (reg_kind == eRegisterKindGeneric) { 173 switch (reg_num) { 174 case LLDB_REGNUM_GENERIC_PC: 175 reg_kind = eRegisterKindLLDB; 176 reg_num = gpr_pc_arm64; 177 break; 178 case LLDB_REGNUM_GENERIC_SP: 179 reg_kind = eRegisterKindLLDB; 180 reg_num = gpr_sp_arm64; 181 break; 182 case LLDB_REGNUM_GENERIC_FP: 183 reg_kind = eRegisterKindLLDB; 184 reg_num = gpr_fp_arm64; 185 break; 186 case LLDB_REGNUM_GENERIC_RA: 187 reg_kind = eRegisterKindLLDB; 188 reg_num = gpr_lr_arm64; 189 break; 190 case LLDB_REGNUM_GENERIC_FLAGS: 191 reg_kind = eRegisterKindLLDB; 192 reg_num = gpr_cpsr_arm64; 193 break; 194 195 default: 196 return false; 197 } 198 } 199 200 if (reg_kind == eRegisterKindLLDB) 201 return LLDBTableGetRegisterInfo(reg_num, reg_info); 202 return false; 203 } 204 205 EmulateInstructionARM64::Opcode * 206 EmulateInstructionARM64::GetOpcodeForInstruction(const uint32_t opcode) { 207 static EmulateInstructionARM64::Opcode g_opcodes[] = { 208 // Prologue instructions 209 210 // push register(s) 211 {0xff000000, 0xd1000000, No_VFP, 212 &EmulateInstructionARM64::EmulateADDSUBImm, 213 "SUB <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"}, 214 {0xff000000, 0xf1000000, No_VFP, 215 &EmulateInstructionARM64::EmulateADDSUBImm, 216 "SUBS <Xd>, <Xn|SP>, #<imm> {, <shift>}"}, 217 {0xff000000, 0x91000000, No_VFP, 218 &EmulateInstructionARM64::EmulateADDSUBImm, 219 "ADD <Xd|SP>, <Xn|SP>, #<imm> {, <shift>}"}, 220 {0xff000000, 0xb1000000, No_VFP, 221 &EmulateInstructionARM64::EmulateADDSUBImm, 222 "ADDS <Xd>, <Xn|SP>, #<imm> {, <shift>}"}, 223 224 {0xff000000, 0x51000000, No_VFP, 225 &EmulateInstructionARM64::EmulateADDSUBImm, 226 "SUB <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"}, 227 {0xff000000, 0x71000000, No_VFP, 228 &EmulateInstructionARM64::EmulateADDSUBImm, 229 "SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"}, 230 {0xff000000, 0x11000000, No_VFP, 231 &EmulateInstructionARM64::EmulateADDSUBImm, 232 "ADD <Wd|WSP>, <Wn|WSP>, #<imm> {, <shift>}"}, 233 {0xff000000, 0x31000000, No_VFP, 234 &EmulateInstructionARM64::EmulateADDSUBImm, 235 "ADDS <Wd>, <Wn|WSP>, #<imm> {, <shift>}"}, 236 237 {0xffc00000, 0x29000000, No_VFP, 238 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 239 "STP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"}, 240 {0xffc00000, 0xa9000000, No_VFP, 241 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 242 "STP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"}, 243 {0xffc00000, 0x2d000000, No_VFP, 244 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 245 "STP <St>, <St2>, [<Xn|SP>{, #<imm>}]"}, 246 {0xffc00000, 0x6d000000, No_VFP, 247 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 248 "STP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"}, 249 {0xffc00000, 0xad000000, No_VFP, 250 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 251 "STP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"}, 252 253 {0xffc00000, 0x29800000, No_VFP, 254 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 255 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 256 {0xffc00000, 0xa9800000, No_VFP, 257 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 258 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 259 {0xffc00000, 0x2d800000, No_VFP, 260 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 261 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 262 {0xffc00000, 0x6d800000, No_VFP, 263 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 264 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 265 {0xffc00000, 0xad800000, No_VFP, 266 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 267 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 268 269 {0xffc00000, 0x28800000, No_VFP, 270 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 271 "STP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 272 {0xffc00000, 0xa8800000, No_VFP, 273 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 274 "STP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 275 {0xffc00000, 0x2c800000, No_VFP, 276 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 277 "STP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 278 {0xffc00000, 0x6c800000, No_VFP, 279 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 280 "STP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 281 {0xffc00000, 0xac800000, No_VFP, 282 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 283 "STP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 284 285 {0xffc00000, 0x29400000, No_VFP, 286 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 287 "LDP <Wt>, <Wt2>, [<Xn|SP>{, #<imm>}]"}, 288 {0xffc00000, 0xa9400000, No_VFP, 289 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 290 "LDP <Xt>, <Xt2>, [<Xn|SP>{, #<imm>}]"}, 291 {0xffc00000, 0x2d400000, No_VFP, 292 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 293 "LDP <St>, <St2>, [<Xn|SP>{, #<imm>}]"}, 294 {0xffc00000, 0x6d400000, No_VFP, 295 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 296 "LDP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]"}, 297 {0xffc00000, 0xad400000, No_VFP, 298 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_OFF>, 299 "LDP <Qt>, <Qt2>, [<Xn|SP>{, #<imm>}]"}, 300 301 {0xffc00000, 0x29c00000, No_VFP, 302 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 303 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 304 {0xffc00000, 0xa9c00000, No_VFP, 305 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 306 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 307 {0xffc00000, 0x2dc00000, No_VFP, 308 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 309 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 310 {0xffc00000, 0x6dc00000, No_VFP, 311 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 312 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 313 {0xffc00000, 0xadc00000, No_VFP, 314 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_PRE>, 315 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 316 317 {0xffc00000, 0x28c00000, No_VFP, 318 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 319 "LDP <Wt>, <Wt2>, [<Xn|SP>, #<imm>]!"}, 320 {0xffc00000, 0xa8c00000, No_VFP, 321 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 322 "LDP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!"}, 323 {0xffc00000, 0x2cc00000, No_VFP, 324 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 325 "LDP <St>, <St2>, [<Xn|SP>, #<imm>]!"}, 326 {0xffc00000, 0x6cc00000, No_VFP, 327 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 328 "LDP <Dt>, <Dt2>, [<Xn|SP>, #<imm>]!"}, 329 {0xffc00000, 0xacc00000, No_VFP, 330 &EmulateInstructionARM64::EmulateLDPSTP<AddrMode_POST>, 331 "LDP <Qt>, <Qt2>, [<Xn|SP>, #<imm>]!"}, 332 333 {0xffe00c00, 0xb8000400, No_VFP, 334 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 335 "STR <Wt>, [<Xn|SP>], #<simm>"}, 336 {0xffe00c00, 0xf8000400, No_VFP, 337 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 338 "STR <Xt>, [<Xn|SP>], #<simm>"}, 339 {0xffe00c00, 0xb8000c00, No_VFP, 340 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 341 "STR <Wt>, [<Xn|SP>, #<simm>]!"}, 342 {0xffe00c00, 0xf8000c00, No_VFP, 343 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 344 "STR <Xt>, [<Xn|SP>, #<simm>]!"}, 345 {0xffc00000, 0xb9000000, No_VFP, 346 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 347 "STR <Wt>, [<Xn|SP>{, #<pimm>}]"}, 348 {0xffc00000, 0xf9000000, No_VFP, 349 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 350 "STR <Xt>, [<Xn|SP>{, #<pimm>}]"}, 351 352 {0xffe00c00, 0xb8400400, No_VFP, 353 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 354 "LDR <Wt>, [<Xn|SP>], #<simm>"}, 355 {0xffe00c00, 0xf8400400, No_VFP, 356 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_POST>, 357 "LDR <Xt>, [<Xn|SP>], #<simm>"}, 358 {0xffe00c00, 0xb8400c00, No_VFP, 359 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 360 "LDR <Wt>, [<Xn|SP>, #<simm>]!"}, 361 {0xffe00c00, 0xf8400c00, No_VFP, 362 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_PRE>, 363 "LDR <Xt>, [<Xn|SP>, #<simm>]!"}, 364 {0xffc00000, 0xb9400000, No_VFP, 365 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 366 "LDR <Wt>, [<Xn|SP>{, #<pimm>}]"}, 367 {0xffc00000, 0xf9400000, No_VFP, 368 &EmulateInstructionARM64::EmulateLDRSTRImm<AddrMode_OFF>, 369 "LDR <Xt>, [<Xn|SP>{, #<pimm>}]"}, 370 371 {0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB, 372 "B <label>"}, 373 {0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond, 374 "B.<cond> <label>"}, 375 {0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, 376 "CBZ <Wt>, <label>"}, 377 {0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ, 378 "CBNZ <Wt>, <label>"}, 379 {0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, 380 "TBZ <R><t>, #<imm>, <label>"}, 381 {0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ, 382 "TBNZ <R><t>, #<imm>, <label>"}, 383 384 }; 385 static const size_t k_num_arm_opcodes = llvm::array_lengthof(g_opcodes); 386 387 for (size_t i = 0; i < k_num_arm_opcodes; ++i) { 388 if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value) 389 return &g_opcodes[i]; 390 } 391 return nullptr; 392 } 393 394 bool EmulateInstructionARM64::ReadInstruction() { 395 bool success = false; 396 m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 397 LLDB_INVALID_ADDRESS, &success); 398 if (success) { 399 Context read_inst_context; 400 read_inst_context.type = eContextReadOpcode; 401 read_inst_context.SetNoArgs(); 402 m_opcode.SetOpcode32( 403 ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success), 404 GetByteOrder()); 405 } 406 if (!success) 407 m_addr = LLDB_INVALID_ADDRESS; 408 return success; 409 } 410 411 bool EmulateInstructionARM64::EvaluateInstruction(uint32_t evaluate_options) { 412 const uint32_t opcode = m_opcode.GetOpcode32(); 413 Opcode *opcode_data = GetOpcodeForInstruction(opcode); 414 if (opcode_data == nullptr) 415 return false; 416 417 // printf ("opcode template for 0x%8.8x: %s\n", opcode, opcode_data->name); 418 const bool auto_advance_pc = 419 evaluate_options & eEmulateInstructionOptionAutoAdvancePC; 420 m_ignore_conditions = 421 evaluate_options & eEmulateInstructionOptionIgnoreConditions; 422 423 bool success = false; 424 // if (m_opcode_cpsr == 0 || m_ignore_conditions == false) 425 // { 426 // m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindLLDB, 427 // gpr_cpsr_arm64, 428 // 0, 429 // &success); 430 // } 431 432 // Only return false if we are unable to read the CPSR if we care about 433 // conditions 434 if (!success && !m_ignore_conditions) 435 return false; 436 437 uint32_t orig_pc_value = 0; 438 if (auto_advance_pc) { 439 orig_pc_value = 440 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success); 441 if (!success) 442 return false; 443 } 444 445 // Call the Emulate... function. 446 success = (this->*opcode_data->callback)(opcode); 447 if (!success) 448 return false; 449 450 if (auto_advance_pc) { 451 uint32_t new_pc_value = 452 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success); 453 if (!success) 454 return false; 455 456 if (auto_advance_pc && (new_pc_value == orig_pc_value)) { 457 EmulateInstruction::Context context; 458 context.type = eContextAdvancePC; 459 context.SetNoArgs(); 460 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_pc_arm64, 461 orig_pc_value + 4)) 462 return false; 463 } 464 } 465 return true; 466 } 467 468 bool EmulateInstructionARM64::CreateFunctionEntryUnwind( 469 UnwindPlan &unwind_plan) { 470 unwind_plan.Clear(); 471 unwind_plan.SetRegisterKind(eRegisterKindLLDB); 472 473 UnwindPlan::RowSP row(new UnwindPlan::Row); 474 475 // Our previous Call Frame Address is the stack pointer 476 row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0); 477 478 unwind_plan.AppendRow(row); 479 unwind_plan.SetSourceName("EmulateInstructionARM64"); 480 unwind_plan.SetSourcedFromCompiler(eLazyBoolNo); 481 unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes); 482 unwind_plan.SetUnwindPlanForSignalTrap(eLazyBoolNo); 483 unwind_plan.SetReturnAddressRegister(gpr_lr_arm64); 484 return true; 485 } 486 487 uint32_t EmulateInstructionARM64::GetFramePointerRegisterNumber() const { 488 if (m_arch.GetTriple().isAndroid()) 489 return LLDB_INVALID_REGNUM; // Don't use frame pointer on android 490 491 return gpr_fp_arm64; 492 } 493 494 bool EmulateInstructionARM64::UsingAArch32() { 495 bool aarch32 = m_opcode_pstate.RW == 1; 496 // if !HaveAnyAArch32() then assert !aarch32; 497 // if HighestELUsingAArch32() then assert aarch32; 498 return aarch32; 499 } 500 501 bool EmulateInstructionARM64::BranchTo(const Context &context, uint32_t N, 502 addr_t target) { 503 #if 0 504 // Set program counter to a new address, with a branch reason hint for 505 // possible use by hardware fetching the next instruction. 506 BranchTo(bits(N) target, BranchType branch_type) 507 Hint_Branch(branch_type); 508 if N == 32 then 509 assert UsingAArch32(); 510 _PC = ZeroExtend(target); 511 else 512 assert N == 64 && !UsingAArch32(); 513 // Remove the tag bits from a tagged target 514 case PSTATE.EL of 515 when EL0, EL1 516 if target<55> == '1' && TCR_EL1.TBI1 == '1' then 517 target<63:56> = '11111111'; 518 if target<55> == '0' && TCR_EL1.TBI0 == '1' then 519 target<63:56> = '00000000'; 520 when EL2 521 if TCR_EL2.TBI == '1' then 522 target<63:56> = '00000000'; 523 when EL3 524 if TCR_EL3.TBI == '1' then 525 target<63:56> = '00000000'; 526 _PC = target<63:0>; 527 return; 528 #endif 529 530 addr_t addr; 531 532 // Hint_Branch(branch_type); 533 if (N == 32) { 534 if (!UsingAArch32()) 535 return false; 536 addr = target; 537 } else if (N == 64) { 538 if (UsingAArch32()) 539 return false; 540 // TODO: Remove the tag bits from a tagged target 541 addr = target; 542 } else 543 return false; 544 545 return WriteRegisterUnsigned(context, eRegisterKindGeneric, 546 LLDB_REGNUM_GENERIC_PC, addr); 547 } 548 549 bool EmulateInstructionARM64::ConditionHolds(const uint32_t cond) { 550 // If we are ignoring conditions, then always return true. this allows us to 551 // iterate over disassembly code and still emulate an instruction even if we 552 // don't have all the right bits set in the CPSR register... 553 if (m_ignore_conditions) 554 return true; 555 556 bool result = false; 557 switch (UnsignedBits(cond, 3, 1)) { 558 case 0: 559 result = (m_opcode_pstate.Z == 1); 560 break; 561 case 1: 562 result = (m_opcode_pstate.C == 1); 563 break; 564 case 2: 565 result = (m_opcode_pstate.N == 1); 566 break; 567 case 3: 568 result = (m_opcode_pstate.V == 1); 569 break; 570 case 4: 571 result = (m_opcode_pstate.C == 1 && m_opcode_pstate.Z == 0); 572 break; 573 case 5: 574 result = (m_opcode_pstate.N == m_opcode_pstate.V); 575 break; 576 case 6: 577 result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0); 578 break; 579 case 7: 580 // Always execute (cond == 0b1110, or the special 0b1111 which gives 581 // opcodes different meanings, but always means execution happens. 582 return true; 583 } 584 585 if (cond & 1) 586 result = !result; 587 return result; 588 } 589 590 bool EmulateInstructionARM64::EmulateADDSUBImm(const uint32_t opcode) { 591 // integer d = UInt(Rd); 592 // integer n = UInt(Rn); 593 // integer datasize = if sf == 1 then 64 else 32; 594 // boolean sub_op = (op == 1); 595 // boolean setflags = (S == 1); 596 // bits(datasize) imm; 597 // 598 // case shift of 599 // when '00' imm = ZeroExtend(imm12, datasize); 600 // when '01' imm = ZeroExtend(imm12 : Zeros(12), datasize); 601 // when '1x' UNDEFINED; 602 // 603 // 604 // bits(datasize) result; 605 // bits(datasize) operand1 = if n == 31 then SP[] else X[n]; 606 // bits(datasize) operand2 = imm; 607 // bits(4) nzcv; 608 // bit carry_in; 609 // 610 // if sub_op then 611 // operand2 = NOT(operand2); 612 // carry_in = 1; 613 // else 614 // carry_in = 0; 615 // 616 // (result, nzcv) = AddWithCarry(operand1, operand2, carry_in); 617 // 618 // if setflags then 619 // PSTATE.NZCV = nzcv; 620 // 621 // if d == 31 && !setflags then 622 // SP[] = result; 623 // else 624 // X[d] = result; 625 626 const uint32_t sf = Bit32(opcode, 31); 627 const uint32_t op = Bit32(opcode, 30); 628 const uint32_t S = Bit32(opcode, 29); 629 const uint32_t shift = Bits32(opcode, 23, 22); 630 const uint32_t imm12 = Bits32(opcode, 21, 10); 631 const uint32_t Rn = Bits32(opcode, 9, 5); 632 const uint32_t Rd = Bits32(opcode, 4, 0); 633 634 bool success = false; 635 636 const uint32_t d = UInt(Rd); 637 const uint32_t n = UInt(Rn); 638 const uint32_t datasize = (sf == 1) ? 64 : 32; 639 boolean sub_op = op == 1; 640 boolean setflags = S == 1; 641 uint64_t imm; 642 643 switch (shift) { 644 case 0: 645 imm = imm12; 646 break; 647 case 1: 648 imm = imm12 << 12; 649 break; 650 default: 651 return false; // UNDEFINED; 652 } 653 uint64_t result; 654 uint64_t operand1 = 655 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 656 uint64_t operand2 = imm; 657 bit carry_in; 658 659 if (sub_op) { 660 operand2 = NOT(operand2); 661 carry_in = true; 662 imm = -imm; // For the Register plug offset context below 663 } else { 664 carry_in = false; 665 } 666 667 ProcState proc_state; 668 669 result = AddWithCarry(datasize, operand1, operand2, carry_in, proc_state); 670 671 if (setflags) { 672 m_emulated_pstate.N = proc_state.N; 673 m_emulated_pstate.Z = proc_state.Z; 674 m_emulated_pstate.C = proc_state.C; 675 m_emulated_pstate.V = proc_state.V; 676 } 677 678 Context context; 679 RegisterInfo reg_info_Rn; 680 if (GetRegisterInfo(eRegisterKindLLDB, n, reg_info_Rn)) 681 context.SetRegisterPlusOffset(reg_info_Rn, imm); 682 683 if (n == GetFramePointerRegisterNumber() && d == gpr_sp_arm64 && !setflags) { 684 // 'mov sp, fp' - common epilogue instruction, CFA is now in terms of the 685 // stack pointer, instead of frame pointer. 686 context.type = EmulateInstruction::eContextRestoreStackPointer; 687 } else if ((n == gpr_sp_arm64 || n == GetFramePointerRegisterNumber()) && 688 d == gpr_sp_arm64 && !setflags) { 689 context.type = EmulateInstruction::eContextAdjustStackPointer; 690 } else if (d == GetFramePointerRegisterNumber() && n == gpr_sp_arm64 && 691 !setflags) { 692 context.type = EmulateInstruction::eContextSetFramePointer; 693 } else { 694 context.type = EmulateInstruction::eContextImmediate; 695 } 696 697 // If setflags && d == gpr_sp_arm64 then d = WZR/XZR. See CMN, CMP 698 if (!setflags || d != gpr_sp_arm64) 699 WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_x0_arm64 + d, result); 700 701 return false; 702 } 703 704 template <EmulateInstructionARM64::AddrMode a_mode> 705 bool EmulateInstructionARM64::EmulateLDPSTP(const uint32_t opcode) { 706 uint32_t opc = Bits32(opcode, 31, 30); 707 uint32_t V = Bit32(opcode, 26); 708 uint32_t L = Bit32(opcode, 22); 709 uint32_t imm7 = Bits32(opcode, 21, 15); 710 uint32_t Rt2 = Bits32(opcode, 14, 10); 711 uint32_t Rn = Bits32(opcode, 9, 5); 712 uint32_t Rt = Bits32(opcode, 4, 0); 713 714 integer n = UInt(Rn); 715 integer t = UInt(Rt); 716 integer t2 = UInt(Rt2); 717 uint64_t idx; 718 719 MemOp memop = L == 1 ? MemOp_LOAD : MemOp_STORE; 720 boolean vector = (V == 1); 721 // AccType acctype = AccType_NORMAL; 722 boolean is_signed = false; 723 boolean wback = a_mode != AddrMode_OFF; 724 boolean wb_unknown = false; 725 boolean rt_unknown = false; 726 integer scale; 727 integer size; 728 729 if (opc == 3) 730 return false; // UNDEFINED 731 732 if (vector) { 733 scale = 2 + UInt(opc); 734 } else { 735 scale = (opc & 2) ? 3 : 2; 736 is_signed = (opc & 1) != 0; 737 if (is_signed && memop == MemOp_STORE) 738 return false; // UNDEFINED 739 } 740 741 if (!vector && wback && ((t == n) || (t2 == n))) { 742 switch (ConstrainUnpredictable(Unpredictable_WBOVERLAP)) { 743 case Constraint_UNKNOWN: 744 wb_unknown = true; // writeback is UNKNOWN 745 break; 746 747 case Constraint_SUPPRESSWB: 748 wback = false; // writeback is suppressed 749 break; 750 751 case Constraint_NOP: 752 memop = MemOp_NOP; // do nothing 753 wback = false; 754 break; 755 756 case Constraint_NONE: 757 break; 758 } 759 } 760 761 if (memop == MemOp_LOAD && t == t2) { 762 switch (ConstrainUnpredictable(Unpredictable_LDPOVERLAP)) { 763 case Constraint_UNKNOWN: 764 rt_unknown = true; // result is UNKNOWN 765 break; 766 767 case Constraint_NOP: 768 memop = MemOp_NOP; // do nothing 769 wback = false; 770 break; 771 772 default: 773 break; 774 } 775 } 776 777 idx = LSL(llvm::SignExtend64<7>(imm7), scale); 778 size = (integer)1 << scale; 779 uint64_t datasize = size * 8; 780 uint64_t address; 781 uint64_t wb_address; 782 783 RegisterValue data_Rt; 784 RegisterValue data_Rt2; 785 786 // if (vector) 787 // CheckFPEnabled(false); 788 789 RegisterInfo reg_info_base; 790 RegisterInfo reg_info_Rt; 791 RegisterInfo reg_info_Rt2; 792 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base)) 793 return false; 794 795 if (vector) { 796 if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t, reg_info_Rt)) 797 return false; 798 if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2, reg_info_Rt2)) 799 return false; 800 } else { 801 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt)) 802 return false; 803 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2, reg_info_Rt2)) 804 return false; 805 } 806 807 bool success = false; 808 if (n == 31) { 809 // CheckSPAlignment(); 810 address = 811 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success); 812 } else 813 address = 814 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 815 816 wb_address = address + idx; 817 if (a_mode != AddrMode_POST) 818 address = wb_address; 819 820 Context context_t; 821 Context context_t2; 822 823 uint8_t buffer[RegisterValue::kMaxRegisterByteSize]; 824 Status error; 825 826 switch (memop) { 827 case MemOp_STORE: { 828 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 829 // based off of the sp 830 // or fp register 831 { 832 context_t.type = eContextPushRegisterOnStack; 833 context_t2.type = eContextPushRegisterOnStack; 834 } else { 835 context_t.type = eContextRegisterStore; 836 context_t2.type = eContextRegisterStore; 837 } 838 context_t.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 0); 839 context_t2.SetRegisterToRegisterPlusOffset(reg_info_Rt2, reg_info_base, 840 size); 841 842 if (!ReadRegister(®_info_Rt, data_Rt)) 843 return false; 844 845 if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 846 eByteOrderLittle, error) == 0) 847 return false; 848 849 if (!WriteMemory(context_t, address + 0, buffer, reg_info_Rt.byte_size)) 850 return false; 851 852 if (!ReadRegister(®_info_Rt2, data_Rt2)) 853 return false; 854 855 if (data_Rt2.GetAsMemoryData(®_info_Rt2, buffer, reg_info_Rt2.byte_size, 856 eByteOrderLittle, error) == 0) 857 return false; 858 859 if (!WriteMemory(context_t2, address + size, buffer, 860 reg_info_Rt2.byte_size)) 861 return false; 862 } break; 863 864 case MemOp_LOAD: { 865 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this load is 866 // based off of the sp 867 // or fp register 868 { 869 context_t.type = eContextPopRegisterOffStack; 870 context_t2.type = eContextPopRegisterOffStack; 871 } else { 872 context_t.type = eContextRegisterLoad; 873 context_t2.type = eContextRegisterLoad; 874 } 875 context_t.SetAddress(address); 876 context_t2.SetAddress(address + size); 877 878 if (rt_unknown) 879 memset(buffer, 'U', reg_info_Rt.byte_size); 880 else { 881 if (!ReadMemory(context_t, address, buffer, reg_info_Rt.byte_size)) 882 return false; 883 } 884 885 if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 886 eByteOrderLittle, error) == 0) 887 return false; 888 889 if (!vector && is_signed && !data_Rt.SignExtend(datasize)) 890 return false; 891 892 if (!WriteRegister(context_t, ®_info_Rt, data_Rt)) 893 return false; 894 895 if (!rt_unknown) { 896 if (!ReadMemory(context_t2, address + size, buffer, 897 reg_info_Rt2.byte_size)) 898 return false; 899 } 900 901 if (data_Rt2.SetFromMemoryData(®_info_Rt2, buffer, 902 reg_info_Rt2.byte_size, eByteOrderLittle, 903 error) == 0) 904 return false; 905 906 if (!vector && is_signed && !data_Rt2.SignExtend(datasize)) 907 return false; 908 909 if (!WriteRegister(context_t2, ®_info_Rt2, data_Rt2)) 910 return false; 911 } break; 912 913 default: 914 break; 915 } 916 917 if (wback) { 918 if (wb_unknown) 919 wb_address = LLDB_INVALID_ADDRESS; 920 Context context; 921 context.SetImmediateSigned(idx); 922 if (n == 31) 923 context.type = eContextAdjustStackPointer; 924 else 925 context.type = eContextAdjustBaseRegister; 926 WriteRegisterUnsigned(context, ®_info_base, wb_address); 927 } 928 return true; 929 } 930 931 template <EmulateInstructionARM64::AddrMode a_mode> 932 bool EmulateInstructionARM64::EmulateLDRSTRImm(const uint32_t opcode) { 933 uint32_t size = Bits32(opcode, 31, 30); 934 uint32_t opc = Bits32(opcode, 23, 22); 935 uint32_t n = Bits32(opcode, 9, 5); 936 uint32_t t = Bits32(opcode, 4, 0); 937 938 bool wback; 939 bool postindex; 940 uint64_t offset; 941 942 switch (a_mode) { 943 case AddrMode_POST: 944 wback = true; 945 postindex = true; 946 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); 947 break; 948 case AddrMode_PRE: 949 wback = true; 950 postindex = false; 951 offset = llvm::SignExtend64<9>(Bits32(opcode, 20, 12)); 952 break; 953 case AddrMode_OFF: 954 wback = false; 955 postindex = false; 956 offset = LSL(Bits32(opcode, 21, 10), size); 957 break; 958 } 959 960 MemOp memop; 961 962 if (Bit32(opc, 1) == 0) { 963 memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE; 964 } else { 965 memop = MemOp_LOAD; 966 if (size == 2 && Bit32(opc, 0) == 1) 967 return false; 968 } 969 970 Status error; 971 bool success = false; 972 uint64_t address; 973 uint8_t buffer[RegisterValue::kMaxRegisterByteSize]; 974 RegisterValue data_Rt; 975 976 if (n == 31) 977 address = 978 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success); 979 else 980 address = 981 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success); 982 983 if (!success) 984 return false; 985 986 if (!postindex) 987 address += offset; 988 989 RegisterInfo reg_info_base; 990 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base)) 991 return false; 992 993 RegisterInfo reg_info_Rt; 994 if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt)) 995 return false; 996 997 Context context; 998 switch (memop) { 999 case MemOp_STORE: 1000 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 1001 // based off of the sp 1002 // or fp register 1003 context.type = eContextPushRegisterOnStack; 1004 else 1005 context.type = eContextRegisterStore; 1006 context.SetRegisterToRegisterPlusOffset(reg_info_Rt, reg_info_base, 1007 postindex ? 0 : offset); 1008 1009 if (!ReadRegister(®_info_Rt, data_Rt)) 1010 return false; 1011 1012 if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 1013 eByteOrderLittle, error) == 0) 1014 return false; 1015 1016 if (!WriteMemory(context, address, buffer, reg_info_Rt.byte_size)) 1017 return false; 1018 break; 1019 1020 case MemOp_LOAD: 1021 if (n == 31 || n == GetFramePointerRegisterNumber()) // if this store is 1022 // based off of the sp 1023 // or fp register 1024 context.type = eContextPopRegisterOffStack; 1025 else 1026 context.type = eContextRegisterLoad; 1027 context.SetAddress(address); 1028 1029 if (!ReadMemory(context, address, buffer, reg_info_Rt.byte_size)) 1030 return false; 1031 1032 if (data_Rt.SetFromMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, 1033 eByteOrderLittle, error) == 0) 1034 return false; 1035 1036 if (!WriteRegister(context, ®_info_Rt, data_Rt)) 1037 return false; 1038 break; 1039 default: 1040 return false; 1041 } 1042 1043 if (wback) { 1044 if (postindex) 1045 address += offset; 1046 1047 if (n == 31) 1048 context.type = eContextAdjustStackPointer; 1049 else 1050 context.type = eContextAdjustBaseRegister; 1051 context.SetImmediateSigned(offset); 1052 1053 if (!WriteRegisterUnsigned(context, ®_info_base, address)) 1054 return false; 1055 } 1056 return true; 1057 } 1058 1059 bool EmulateInstructionARM64::EmulateB(const uint32_t opcode) { 1060 #if 0 1061 // ARM64 pseudo code... 1062 if branch_type == BranchType_CALL then X[30] = PC[] + 4; 1063 BranchTo(PC[] + offset, branch_type); 1064 #endif 1065 1066 bool success = false; 1067 1068 EmulateInstruction::Context context; 1069 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1070 const uint64_t pc = ReadRegisterUnsigned(eRegisterKindGeneric, 1071 LLDB_REGNUM_GENERIC_PC, 0, &success); 1072 if (!success) 1073 return false; 1074 1075 int64_t offset = llvm::SignExtend64<28>(Bits32(opcode, 25, 0) << 2); 1076 BranchType branch_type = Bit32(opcode, 31) ? BranchType_CALL : BranchType_JMP; 1077 addr_t target = pc + offset; 1078 context.SetImmediateSigned(offset); 1079 1080 switch (branch_type) { 1081 case BranchType_CALL: { 1082 addr_t x30 = pc + 4; 1083 if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_lr_arm64, x30)) 1084 return false; 1085 } break; 1086 case BranchType_JMP: 1087 break; 1088 default: 1089 return false; 1090 } 1091 1092 return BranchTo(context, 64, target); 1093 } 1094 1095 bool EmulateInstructionARM64::EmulateBcond(const uint32_t opcode) { 1096 #if 0 1097 // ARM64 pseudo code... 1098 bits(64) offset = SignExtend(imm19:'00', 64); 1099 bits(4) condition = cond; 1100 if ConditionHolds(condition) then 1101 BranchTo(PC[] + offset, BranchType_JMP); 1102 #endif 1103 1104 if (ConditionHolds(Bits32(opcode, 3, 0))) { 1105 bool success = false; 1106 1107 const uint64_t pc = ReadRegisterUnsigned( 1108 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1109 if (!success) 1110 return false; 1111 1112 int64_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 1113 addr_t target = pc + offset; 1114 1115 EmulateInstruction::Context context; 1116 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1117 context.SetImmediateSigned(offset); 1118 if (!BranchTo(context, 64, target)) 1119 return false; 1120 } 1121 return true; 1122 } 1123 1124 bool EmulateInstructionARM64::EmulateCBZ(const uint32_t opcode) { 1125 #if 0 1126 integer t = UInt(Rt); 1127 integer datasize = if sf == '1' then 64 else 32; 1128 boolean iszero = (op == '0'); 1129 bits(64) offset = SignExtend(imm19:'00', 64); 1130 1131 bits(datasize) operand1 = X[t]; 1132 if IsZero(operand1) == iszero then 1133 BranchTo(PC[] + offset, BranchType_JMP); 1134 #endif 1135 1136 bool success = false; 1137 1138 uint32_t t = Bits32(opcode, 4, 0); 1139 bool is_zero = Bit32(opcode, 24) == 0; 1140 int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); 1141 1142 const uint64_t operand = 1143 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success); 1144 if (!success) 1145 return false; 1146 1147 if (m_ignore_conditions || ((operand == 0) == is_zero)) { 1148 const uint64_t pc = ReadRegisterUnsigned( 1149 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1150 if (!success) 1151 return false; 1152 1153 EmulateInstruction::Context context; 1154 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1155 context.SetImmediateSigned(offset); 1156 if (!BranchTo(context, 64, pc + offset)) 1157 return false; 1158 } 1159 return true; 1160 } 1161 1162 bool EmulateInstructionARM64::EmulateTBZ(const uint32_t opcode) { 1163 #if 0 1164 integer t = UInt(Rt); 1165 integer datasize = if b5 == '1' then 64 else 32; 1166 integer bit_pos = UInt(b5:b40); 1167 bit bit_val = op; 1168 bits(64) offset = SignExtend(imm14:'00', 64); 1169 #endif 1170 1171 bool success = false; 1172 1173 uint32_t t = Bits32(opcode, 4, 0); 1174 uint32_t bit_pos = (Bit32(opcode, 31) << 6) | (Bits32(opcode, 23, 19)); 1175 uint32_t bit_val = Bit32(opcode, 24); 1176 int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2); 1177 1178 const uint64_t operand = 1179 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success); 1180 if (!success) 1181 return false; 1182 1183 if (m_ignore_conditions || Bit32(operand, bit_pos) == bit_val) { 1184 const uint64_t pc = ReadRegisterUnsigned( 1185 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success); 1186 if (!success) 1187 return false; 1188 1189 EmulateInstruction::Context context; 1190 context.type = EmulateInstruction::eContextRelativeBranchImmediate; 1191 context.SetImmediateSigned(offset); 1192 if (!BranchTo(context, 64, pc + offset)) 1193 return false; 1194 } 1195 return true; 1196 } 1197