1 //===- Target.cpp ---------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Machine-specific things, such as applying relocations, creation of 11 // GOT or PLT entries, etc., are handled in this file. 12 // 13 // Refer the ELF spec for the single letter variables, S, A or P, used 14 // in this file. 15 // 16 // Some functions defined in this file has "relaxTls" as part of their names. 17 // They do peephole optimization for TLS variables by rewriting instructions. 18 // They are not part of the ABI but optional optimization, so you can skip 19 // them if you are not interested in how TLS variables are optimized. 20 // See the following paper for the details. 21 // 22 // Ulrich Drepper, ELF Handling For Thread-Local Storage 23 // http://www.akkadia.org/drepper/tls.pdf 24 // 25 //===----------------------------------------------------------------------===// 26 27 #include "Target.h" 28 #include "Error.h" 29 #include "InputFiles.h" 30 #include "Memory.h" 31 #include "OutputSections.h" 32 #include "SymbolTable.h" 33 #include "Symbols.h" 34 #include "SyntheticSections.h" 35 #include "Thunks.h" 36 #include "Writer.h" 37 #include "llvm/ADT/ArrayRef.h" 38 #include "llvm/Object/ELF.h" 39 #include "llvm/Support/ELF.h" 40 #include "llvm/Support/Endian.h" 41 42 using namespace llvm; 43 using namespace llvm::object; 44 using namespace llvm::support::endian; 45 using namespace llvm::ELF; 46 47 std::string lld::toString(uint32_t Type) { 48 StringRef S = getELFRelocationTypeName(elf::Config->EMachine, Type); 49 if (S == "Unknown") 50 return ("Unknown (" + Twine(Type) + ")").str(); 51 return S; 52 } 53 54 namespace lld { 55 namespace elf { 56 57 TargetInfo *Target; 58 59 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); } 60 static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); } 61 62 template <class ELFT> static std::string getErrorLoc(uint8_t *Loc) { 63 for (InputSectionBase *D : InputSections) { 64 auto *IS = dyn_cast_or_null<InputSection>(D); 65 if (!IS || !IS->OutSec) 66 continue; 67 68 uint8_t *ISLoc = cast<OutputSection>(IS->OutSec)->Loc + IS->OutSecOff; 69 if (ISLoc <= Loc && Loc < ISLoc + IS->getSize()) 70 return IS->template getLocation<ELFT>(Loc - ISLoc) + ": "; 71 } 72 return ""; 73 } 74 75 static std::string getErrorLocation(uint8_t *Loc) { 76 switch (Config->EKind) { 77 case ELF32LEKind: 78 return getErrorLoc<ELF32LE>(Loc); 79 case ELF32BEKind: 80 return getErrorLoc<ELF32BE>(Loc); 81 case ELF64LEKind: 82 return getErrorLoc<ELF64LE>(Loc); 83 case ELF64BEKind: 84 return getErrorLoc<ELF64BE>(Loc); 85 default: 86 llvm_unreachable("unknown ELF type"); 87 } 88 } 89 90 template <unsigned N> 91 static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) { 92 if (!isInt<N>(V)) 93 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 94 " out of range"); 95 } 96 97 template <unsigned N> 98 static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 99 if (!isUInt<N>(V)) 100 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 101 " out of range"); 102 } 103 104 template <unsigned N> 105 static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 106 if (!isInt<N>(V) && !isUInt<N>(V)) 107 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 108 " out of range"); 109 } 110 111 template <unsigned N> 112 static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) { 113 if ((V & (N - 1)) != 0) 114 error(getErrorLocation(Loc) + "improper alignment for relocation " + 115 toString(Type)); 116 } 117 118 namespace { 119 class X86TargetInfo final : public TargetInfo { 120 public: 121 X86TargetInfo(); 122 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 123 int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 124 void writeGotPltHeader(uint8_t *Buf) const override; 125 uint32_t getDynRel(uint32_t Type) const override; 126 bool isTlsLocalDynamicRel(uint32_t Type) const override; 127 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 128 bool isTlsInitialExecRel(uint32_t Type) const override; 129 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 130 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 131 void writePltHeader(uint8_t *Buf) const override; 132 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 133 int32_t Index, unsigned RelOff) const override; 134 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 135 136 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 137 RelExpr Expr) const override; 138 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 139 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 140 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 141 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 142 }; 143 144 template <class ELFT> class X86_64TargetInfo final : public TargetInfo { 145 public: 146 X86_64TargetInfo(); 147 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 148 bool isPicRel(uint32_t Type) const override; 149 bool isTlsLocalDynamicRel(uint32_t Type) const override; 150 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 151 bool isTlsInitialExecRel(uint32_t Type) const override; 152 void writeGotPltHeader(uint8_t *Buf) const override; 153 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 154 void writePltHeader(uint8_t *Buf) const override; 155 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 156 int32_t Index, unsigned RelOff) const override; 157 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 158 159 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 160 RelExpr Expr) const override; 161 void relaxGot(uint8_t *Loc, uint64_t Val) const override; 162 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 163 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 164 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 165 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 166 167 private: 168 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op, 169 uint8_t ModRm) const; 170 }; 171 172 class PPCTargetInfo final : public TargetInfo { 173 public: 174 PPCTargetInfo(); 175 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 176 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 177 }; 178 179 class PPC64TargetInfo final : public TargetInfo { 180 public: 181 PPC64TargetInfo(); 182 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 183 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 184 int32_t Index, unsigned RelOff) const override; 185 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 186 }; 187 188 class AArch64TargetInfo final : public TargetInfo { 189 public: 190 AArch64TargetInfo(); 191 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 192 bool isPicRel(uint32_t Type) const override; 193 bool isTlsInitialExecRel(uint32_t Type) const override; 194 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 195 void writePltHeader(uint8_t *Buf) const override; 196 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 197 int32_t Index, unsigned RelOff) const override; 198 bool usesOnlyLowPageBits(uint32_t Type) const override; 199 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 200 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 201 RelExpr Expr) const override; 202 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 203 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 204 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 205 }; 206 207 class AMDGPUTargetInfo final : public TargetInfo { 208 public: 209 AMDGPUTargetInfo(); 210 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 211 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 212 }; 213 214 class ARMTargetInfo final : public TargetInfo { 215 public: 216 ARMTargetInfo(); 217 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 218 bool isPicRel(uint32_t Type) const override; 219 uint32_t getDynRel(uint32_t Type) const override; 220 int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 221 bool isTlsLocalDynamicRel(uint32_t Type) const override; 222 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 223 bool isTlsInitialExecRel(uint32_t Type) const override; 224 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 225 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 226 void writePltHeader(uint8_t *Buf) const override; 227 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 228 int32_t Index, unsigned RelOff) const override; 229 void addPltSymbols(InputSectionBase *IS, uint64_t Off) const override; 230 void addPltHeaderSymbols(InputSectionBase *ISD) const override; 231 bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File, 232 const SymbolBody &S) const override; 233 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 234 }; 235 236 template <class ELFT> class MipsTargetInfo final : public TargetInfo { 237 public: 238 MipsTargetInfo(); 239 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 240 int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 241 bool isPicRel(uint32_t Type) const override; 242 uint32_t getDynRel(uint32_t Type) const override; 243 bool isTlsLocalDynamicRel(uint32_t Type) const override; 244 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 245 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 246 void writePltHeader(uint8_t *Buf) const override; 247 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 248 int32_t Index, unsigned RelOff) const override; 249 bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File, 250 const SymbolBody &S) const override; 251 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 252 bool usesOnlyLowPageBits(uint32_t Type) const override; 253 }; 254 } // anonymous namespace 255 256 TargetInfo *createTarget() { 257 switch (Config->EMachine) { 258 case EM_386: 259 case EM_IAMCU: 260 return make<X86TargetInfo>(); 261 case EM_AARCH64: 262 return make<AArch64TargetInfo>(); 263 case EM_AMDGPU: 264 return make<AMDGPUTargetInfo>(); 265 case EM_ARM: 266 return make<ARMTargetInfo>(); 267 case EM_MIPS: 268 switch (Config->EKind) { 269 case ELF32LEKind: 270 return make<MipsTargetInfo<ELF32LE>>(); 271 case ELF32BEKind: 272 return make<MipsTargetInfo<ELF32BE>>(); 273 case ELF64LEKind: 274 return make<MipsTargetInfo<ELF64LE>>(); 275 case ELF64BEKind: 276 return make<MipsTargetInfo<ELF64BE>>(); 277 default: 278 fatal("unsupported MIPS target"); 279 } 280 case EM_PPC: 281 return make<PPCTargetInfo>(); 282 case EM_PPC64: 283 return make<PPC64TargetInfo>(); 284 case EM_X86_64: 285 if (Config->EKind == ELF32LEKind) 286 return make<X86_64TargetInfo<ELF32LE>>(); 287 return make<X86_64TargetInfo<ELF64LE>>(); 288 } 289 fatal("unknown target machine"); 290 } 291 292 TargetInfo::~TargetInfo() {} 293 294 int64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const { 295 return 0; 296 } 297 298 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; } 299 300 bool TargetInfo::needsThunk(RelExpr Expr, uint32_t RelocType, 301 const InputFile *File, const SymbolBody &S) const { 302 return false; 303 } 304 305 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; } 306 307 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; } 308 309 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { return false; } 310 311 void TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 312 writeGotPlt(Buf, S); 313 } 314 315 RelExpr TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 316 RelExpr Expr) const { 317 return Expr; 318 } 319 320 void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const { 321 llvm_unreachable("Should not have claimed to be relaxable"); 322 } 323 324 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 325 uint64_t Val) const { 326 llvm_unreachable("Should not have claimed to be relaxable"); 327 } 328 329 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 330 uint64_t Val) const { 331 llvm_unreachable("Should not have claimed to be relaxable"); 332 } 333 334 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 335 uint64_t Val) const { 336 llvm_unreachable("Should not have claimed to be relaxable"); 337 } 338 339 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 340 uint64_t Val) const { 341 llvm_unreachable("Should not have claimed to be relaxable"); 342 } 343 344 X86TargetInfo::X86TargetInfo() { 345 CopyRel = R_386_COPY; 346 GotRel = R_386_GLOB_DAT; 347 PltRel = R_386_JUMP_SLOT; 348 IRelativeRel = R_386_IRELATIVE; 349 RelativeRel = R_386_RELATIVE; 350 TlsGotRel = R_386_TLS_TPOFF; 351 TlsModuleIndexRel = R_386_TLS_DTPMOD32; 352 TlsOffsetRel = R_386_TLS_DTPOFF32; 353 GotEntrySize = 4; 354 GotPltEntrySize = 4; 355 PltEntrySize = 16; 356 PltHeaderSize = 16; 357 TlsGdRelaxSkip = 2; 358 } 359 360 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 361 switch (Type) { 362 case R_386_8: 363 case R_386_16: 364 case R_386_32: 365 case R_386_TLS_LDO_32: 366 return R_ABS; 367 case R_386_TLS_GD: 368 return R_TLSGD; 369 case R_386_TLS_LDM: 370 return R_TLSLD; 371 case R_386_PLT32: 372 return R_PLT_PC; 373 case R_386_PC8: 374 case R_386_PC16: 375 case R_386_PC32: 376 return R_PC; 377 case R_386_GOTPC: 378 return R_GOTONLY_PC_FROM_END; 379 case R_386_TLS_IE: 380 return R_GOT; 381 case R_386_GOT32: 382 case R_386_GOT32X: 383 case R_386_TLS_GOTIE: 384 return R_GOT_FROM_END; 385 case R_386_GOTOFF: 386 return R_GOTREL_FROM_END; 387 case R_386_TLS_LE: 388 return R_TLS; 389 case R_386_TLS_LE_32: 390 return R_NEG_TLS; 391 case R_386_NONE: 392 return R_NONE; 393 default: 394 error(toString(S.File) + ": unknown relocation type: " + toString(Type)); 395 return R_HINT; 396 } 397 } 398 399 RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 400 RelExpr Expr) const { 401 switch (Expr) { 402 default: 403 return Expr; 404 case R_RELAX_TLS_GD_TO_IE: 405 return R_RELAX_TLS_GD_TO_IE_END; 406 case R_RELAX_TLS_GD_TO_LE: 407 return R_RELAX_TLS_GD_TO_LE_NEG; 408 } 409 } 410 411 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const { 412 write32le(Buf, In<ELF32LE>::Dynamic->getVA()); 413 } 414 415 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const { 416 // Entries in .got.plt initially points back to the corresponding 417 // PLT entries with a fixed offset to skip the first instruction. 418 write32le(Buf, S.getPltVA<ELF32LE>() + 6); 419 } 420 421 void X86TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 422 // An x86 entry is the address of the ifunc resolver function. 423 write32le(Buf, S.getVA<ELF32LE>()); 424 } 425 426 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const { 427 if (Type == R_386_TLS_LE) 428 return R_386_TLS_TPOFF; 429 if (Type == R_386_TLS_LE_32) 430 return R_386_TLS_TPOFF32; 431 return Type; 432 } 433 434 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 435 return Type == R_386_TLS_GD; 436 } 437 438 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 439 return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM; 440 } 441 442 bool X86TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 443 return Type == R_386_TLS_IE || Type == R_386_TLS_GOTIE; 444 } 445 446 void X86TargetInfo::writePltHeader(uint8_t *Buf) const { 447 // Executable files and shared object files have 448 // separate procedure linkage tables. 449 if (Config->pic()) { 450 const uint8_t V[] = { 451 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl 4(%ebx) 452 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *8(%ebx) 453 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 454 }; 455 memcpy(Buf, V, sizeof(V)); 456 return; 457 } 458 459 const uint8_t PltData[] = { 460 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOT+4) 461 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOT+8) 462 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 463 }; 464 memcpy(Buf, PltData, sizeof(PltData)); 465 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 466 write32le(Buf + 2, Got + 4); 467 write32le(Buf + 8, Got + 8); 468 } 469 470 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 471 uint64_t PltEntryAddr, int32_t Index, 472 unsigned RelOff) const { 473 const uint8_t Inst[] = { 474 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx) 475 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset 476 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC 477 }; 478 memcpy(Buf, Inst, sizeof(Inst)); 479 480 // jmp *foo@GOT(%ebx) or jmp *foo_in_GOT 481 Buf[1] = Config->pic() ? 0xa3 : 0x25; 482 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 483 write32le(Buf + 2, Config->Shared ? GotEntryAddr - Got : GotEntryAddr); 484 write32le(Buf + 7, RelOff); 485 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 486 } 487 488 int64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf, 489 uint32_t Type) const { 490 switch (Type) { 491 default: 492 return 0; 493 case R_386_8: 494 case R_386_PC8: 495 return SignExtend64<8>(*Buf); 496 case R_386_16: 497 case R_386_PC16: 498 return SignExtend64<16>(read16le(Buf)); 499 case R_386_32: 500 case R_386_GOT32: 501 case R_386_GOT32X: 502 case R_386_GOTOFF: 503 case R_386_GOTPC: 504 case R_386_PC32: 505 case R_386_PLT32: 506 case R_386_TLS_LE: 507 return SignExtend64<32>(read32le(Buf)); 508 } 509 } 510 511 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 512 uint64_t Val) const { 513 // R_386_{PC,}{8,16} are not part of the i386 psABI, but they are 514 // being used for some 16-bit programs such as boot loaders, so 515 // we want to support them. 516 switch (Type) { 517 case R_386_8: 518 checkUInt<8>(Loc, Val, Type); 519 *Loc = Val; 520 break; 521 case R_386_PC8: 522 checkInt<8>(Loc, Val, Type); 523 *Loc = Val; 524 break; 525 case R_386_16: 526 checkUInt<16>(Loc, Val, Type); 527 write16le(Loc, Val); 528 break; 529 case R_386_PC16: 530 checkInt<16>(Loc, Val, Type); 531 write16le(Loc, Val); 532 break; 533 default: 534 checkInt<32>(Loc, Val, Type); 535 write32le(Loc, Val); 536 } 537 } 538 539 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 540 uint64_t Val) const { 541 // Convert 542 // leal x@tlsgd(, %ebx, 1), 543 // call __tls_get_addr@plt 544 // to 545 // movl %gs:0,%eax 546 // subl $x@ntpoff,%eax 547 const uint8_t Inst[] = { 548 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 549 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax 550 }; 551 memcpy(Loc - 3, Inst, sizeof(Inst)); 552 relocateOne(Loc + 5, R_386_32, Val); 553 } 554 555 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 556 uint64_t Val) const { 557 // Convert 558 // leal x@tlsgd(, %ebx, 1), 559 // call __tls_get_addr@plt 560 // to 561 // movl %gs:0, %eax 562 // addl x@gotntpoff(%ebx), %eax 563 const uint8_t Inst[] = { 564 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 565 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax 566 }; 567 memcpy(Loc - 3, Inst, sizeof(Inst)); 568 relocateOne(Loc + 5, R_386_32, Val); 569 } 570 571 // In some conditions, relocations can be optimized to avoid using GOT. 572 // This function does that for Initial Exec to Local Exec case. 573 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 574 uint64_t Val) const { 575 // Ulrich's document section 6.2 says that @gotntpoff can 576 // be used with MOVL or ADDL instructions. 577 // @indntpoff is similar to @gotntpoff, but for use in 578 // position dependent code. 579 uint8_t Reg = (Loc[-1] >> 3) & 7; 580 581 if (Type == R_386_TLS_IE) { 582 if (Loc[-1] == 0xa1) { 583 // "movl foo@indntpoff,%eax" -> "movl $foo,%eax" 584 // This case is different from the generic case below because 585 // this is a 5 byte instruction while below is 6 bytes. 586 Loc[-1] = 0xb8; 587 } else if (Loc[-2] == 0x8b) { 588 // "movl foo@indntpoff,%reg" -> "movl $foo,%reg" 589 Loc[-2] = 0xc7; 590 Loc[-1] = 0xc0 | Reg; 591 } else { 592 // "addl foo@indntpoff,%reg" -> "addl $foo,%reg" 593 Loc[-2] = 0x81; 594 Loc[-1] = 0xc0 | Reg; 595 } 596 } else { 597 assert(Type == R_386_TLS_GOTIE); 598 if (Loc[-2] == 0x8b) { 599 // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg" 600 Loc[-2] = 0xc7; 601 Loc[-1] = 0xc0 | Reg; 602 } else { 603 // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg" 604 Loc[-2] = 0x8d; 605 Loc[-1] = 0x80 | (Reg << 3) | Reg; 606 } 607 } 608 relocateOne(Loc, R_386_TLS_LE, Val); 609 } 610 611 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 612 uint64_t Val) const { 613 if (Type == R_386_TLS_LDO_32) { 614 relocateOne(Loc, R_386_TLS_LE, Val); 615 return; 616 } 617 618 // Convert 619 // leal foo(%reg),%eax 620 // call ___tls_get_addr 621 // to 622 // movl %gs:0,%eax 623 // nop 624 // leal 0(%esi,1),%esi 625 const uint8_t Inst[] = { 626 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax 627 0x90, // nop 628 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi 629 }; 630 memcpy(Loc - 2, Inst, sizeof(Inst)); 631 } 632 633 template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() { 634 CopyRel = R_X86_64_COPY; 635 GotRel = R_X86_64_GLOB_DAT; 636 PltRel = R_X86_64_JUMP_SLOT; 637 RelativeRel = R_X86_64_RELATIVE; 638 IRelativeRel = R_X86_64_IRELATIVE; 639 TlsGotRel = R_X86_64_TPOFF64; 640 TlsModuleIndexRel = R_X86_64_DTPMOD64; 641 TlsOffsetRel = R_X86_64_DTPOFF64; 642 GotEntrySize = 8; 643 GotPltEntrySize = 8; 644 PltEntrySize = 16; 645 PltHeaderSize = 16; 646 TlsGdRelaxSkip = 2; 647 // Align to the large page size (known as a superpage or huge page). 648 // FreeBSD automatically promotes large, superpage-aligned allocations. 649 DefaultImageBase = 0x200000; 650 } 651 652 template <class ELFT> 653 RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type, 654 const SymbolBody &S) const { 655 switch (Type) { 656 case R_X86_64_8: 657 case R_X86_64_16: 658 case R_X86_64_32: 659 case R_X86_64_32S: 660 case R_X86_64_64: 661 case R_X86_64_DTPOFF32: 662 case R_X86_64_DTPOFF64: 663 return R_ABS; 664 case R_X86_64_TPOFF32: 665 return R_TLS; 666 case R_X86_64_TLSLD: 667 return R_TLSLD_PC; 668 case R_X86_64_TLSGD: 669 return R_TLSGD_PC; 670 case R_X86_64_SIZE32: 671 case R_X86_64_SIZE64: 672 return R_SIZE; 673 case R_X86_64_PLT32: 674 return R_PLT_PC; 675 case R_X86_64_PC32: 676 case R_X86_64_PC64: 677 return R_PC; 678 case R_X86_64_GOT32: 679 case R_X86_64_GOT64: 680 return R_GOT_FROM_END; 681 case R_X86_64_GOTPCREL: 682 case R_X86_64_GOTPCRELX: 683 case R_X86_64_REX_GOTPCRELX: 684 case R_X86_64_GOTTPOFF: 685 return R_GOT_PC; 686 case R_X86_64_NONE: 687 return R_NONE; 688 default: 689 error(toString(S.File) + ": unknown relocation type: " + toString(Type)); 690 return R_HINT; 691 } 692 } 693 694 template <class ELFT> 695 void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const { 696 // The first entry holds the value of _DYNAMIC. It is not clear why that is 697 // required, but it is documented in the psabi and the glibc dynamic linker 698 // seems to use it (note that this is relevant for linking ld.so, not any 699 // other program). 700 write64le(Buf, In<ELFT>::Dynamic->getVA()); 701 } 702 703 template <class ELFT> 704 void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, 705 const SymbolBody &S) const { 706 // See comments in X86TargetInfo::writeGotPlt. 707 write32le(Buf, S.getPltVA<ELFT>() + 6); 708 } 709 710 template <class ELFT> 711 void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 712 const uint8_t PltData[] = { 713 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOT+8(%rip) 714 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOT+16(%rip) 715 0x0f, 0x1f, 0x40, 0x00 // nopl 0x0(rax) 716 }; 717 memcpy(Buf, PltData, sizeof(PltData)); 718 uint64_t Got = In<ELFT>::GotPlt->getVA(); 719 uint64_t Plt = In<ELFT>::Plt->getVA(); 720 write32le(Buf + 2, Got - Plt + 2); // GOT+8 721 write32le(Buf + 8, Got - Plt + 4); // GOT+16 722 } 723 724 template <class ELFT> 725 void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 726 uint64_t PltEntryAddr, int32_t Index, 727 unsigned RelOff) const { 728 const uint8_t Inst[] = { 729 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip) 730 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index> 731 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0] 732 }; 733 memcpy(Buf, Inst, sizeof(Inst)); 734 735 write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6); 736 write32le(Buf + 7, Index); 737 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 738 } 739 740 template <class ELFT> 741 bool X86_64TargetInfo<ELFT>::isPicRel(uint32_t Type) const { 742 return Type != R_X86_64_PC32 && Type != R_X86_64_32; 743 } 744 745 template <class ELFT> 746 bool X86_64TargetInfo<ELFT>::isTlsInitialExecRel(uint32_t Type) const { 747 return Type == R_X86_64_GOTTPOFF; 748 } 749 750 template <class ELFT> 751 bool X86_64TargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 752 return Type == R_X86_64_TLSGD; 753 } 754 755 template <class ELFT> 756 bool X86_64TargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 757 return Type == R_X86_64_DTPOFF32 || Type == R_X86_64_DTPOFF64 || 758 Type == R_X86_64_TLSLD; 759 } 760 761 template <class ELFT> 762 void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 763 uint64_t Val) const { 764 // Convert 765 // .byte 0x66 766 // leaq x@tlsgd(%rip), %rdi 767 // .word 0x6666 768 // rex64 769 // call __tls_get_addr@plt 770 // to 771 // mov %fs:0x0,%rax 772 // lea x@tpoff,%rax 773 const uint8_t Inst[] = { 774 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 775 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax 776 }; 777 memcpy(Loc - 4, Inst, sizeof(Inst)); 778 // The original code used a pc relative relocation and so we have to 779 // compensate for the -4 in had in the addend. 780 relocateOne(Loc + 8, R_X86_64_TPOFF32, Val + 4); 781 } 782 783 template <class ELFT> 784 void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 785 uint64_t Val) const { 786 // Convert 787 // .byte 0x66 788 // leaq x@tlsgd(%rip), %rdi 789 // .word 0x6666 790 // rex64 791 // call __tls_get_addr@plt 792 // to 793 // mov %fs:0x0,%rax 794 // addq x@tpoff,%rax 795 const uint8_t Inst[] = { 796 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 797 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax 798 }; 799 memcpy(Loc - 4, Inst, sizeof(Inst)); 800 // Both code sequences are PC relatives, but since we are moving the constant 801 // forward by 8 bytes we have to subtract the value by 8. 802 relocateOne(Loc + 8, R_X86_64_PC32, Val - 8); 803 } 804 805 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to 806 // R_X86_64_TPOFF32 so that it does not use GOT. 807 template <class ELFT> 808 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 809 uint64_t Val) const { 810 uint8_t *Inst = Loc - 3; 811 uint8_t Reg = Loc[-1] >> 3; 812 uint8_t *RegSlot = Loc - 1; 813 814 // Note that ADD with RSP or R12 is converted to ADD instead of LEA 815 // because LEA with these registers needs 4 bytes to encode and thus 816 // wouldn't fit the space. 817 818 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) { 819 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp" 820 memcpy(Inst, "\x48\x81\xc4", 3); 821 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) { 822 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12" 823 memcpy(Inst, "\x49\x81\xc4", 3); 824 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) { 825 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]" 826 memcpy(Inst, "\x4d\x8d", 2); 827 *RegSlot = 0x80 | (Reg << 3) | Reg; 828 } else if (memcmp(Inst, "\x48\x03", 2) == 0) { 829 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg" 830 memcpy(Inst, "\x48\x8d", 2); 831 *RegSlot = 0x80 | (Reg << 3) | Reg; 832 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) { 833 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]" 834 memcpy(Inst, "\x49\xc7", 2); 835 *RegSlot = 0xc0 | Reg; 836 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) { 837 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg" 838 memcpy(Inst, "\x48\xc7", 2); 839 *RegSlot = 0xc0 | Reg; 840 } else { 841 error(getErrorLocation(Loc - 3) + 842 "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only"); 843 } 844 845 // The original code used a PC relative relocation. 846 // Need to compensate for the -4 it had in the addend. 847 relocateOne(Loc, R_X86_64_TPOFF32, Val + 4); 848 } 849 850 template <class ELFT> 851 void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 852 uint64_t Val) const { 853 // Convert 854 // leaq bar@tlsld(%rip), %rdi 855 // callq __tls_get_addr@PLT 856 // leaq bar@dtpoff(%rax), %rcx 857 // to 858 // .word 0x6666 859 // .byte 0x66 860 // mov %fs:0,%rax 861 // leaq bar@tpoff(%rax), %rcx 862 if (Type == R_X86_64_DTPOFF64) { 863 write64le(Loc, Val); 864 return; 865 } 866 if (Type == R_X86_64_DTPOFF32) { 867 relocateOne(Loc, R_X86_64_TPOFF32, Val); 868 return; 869 } 870 871 const uint8_t Inst[] = { 872 0x66, 0x66, // .word 0x6666 873 0x66, // .byte 0x66 874 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax 875 }; 876 memcpy(Loc - 3, Inst, sizeof(Inst)); 877 } 878 879 template <class ELFT> 880 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 881 uint64_t Val) const { 882 switch (Type) { 883 case R_X86_64_8: 884 checkUInt<8>(Loc, Val, Type); 885 *Loc = Val; 886 break; 887 case R_X86_64_16: 888 checkUInt<16>(Loc, Val, Type); 889 write16le(Loc, Val); 890 break; 891 case R_X86_64_32: 892 checkUInt<32>(Loc, Val, Type); 893 write32le(Loc, Val); 894 break; 895 case R_X86_64_32S: 896 case R_X86_64_TPOFF32: 897 case R_X86_64_GOT32: 898 case R_X86_64_GOTPCREL: 899 case R_X86_64_GOTPCRELX: 900 case R_X86_64_REX_GOTPCRELX: 901 case R_X86_64_PC32: 902 case R_X86_64_GOTTPOFF: 903 case R_X86_64_PLT32: 904 case R_X86_64_TLSGD: 905 case R_X86_64_TLSLD: 906 case R_X86_64_DTPOFF32: 907 case R_X86_64_SIZE32: 908 checkInt<32>(Loc, Val, Type); 909 write32le(Loc, Val); 910 break; 911 case R_X86_64_64: 912 case R_X86_64_DTPOFF64: 913 case R_X86_64_GLOB_DAT: 914 case R_X86_64_PC64: 915 case R_X86_64_SIZE64: 916 case R_X86_64_GOT64: 917 write64le(Loc, Val); 918 break; 919 default: 920 llvm_unreachable("unexpected relocation"); 921 } 922 } 923 924 template <class ELFT> 925 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type, 926 const uint8_t *Data, 927 RelExpr RelExpr) const { 928 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX) 929 return RelExpr; 930 const uint8_t Op = Data[-2]; 931 const uint8_t ModRm = Data[-1]; 932 // FIXME: When PIC is disabled and foo is defined locally in the 933 // lower 32 bit address space, memory operand in mov can be converted into 934 // immediate operand. Otherwise, mov must be changed to lea. We support only 935 // latter relaxation at this moment. 936 if (Op == 0x8b) 937 return R_RELAX_GOT_PC; 938 // Relax call and jmp. 939 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25)) 940 return R_RELAX_GOT_PC; 941 942 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor. 943 // If PIC then no relaxation is available. 944 // We also don't relax test/binop instructions without REX byte, 945 // they are 32bit operations and not common to have. 946 assert(Type == R_X86_64_REX_GOTPCRELX); 947 return Config->pic() ? RelExpr : R_RELAX_GOT_PC_NOPIC; 948 } 949 950 // A subset of relaxations can only be applied for no-PIC. This method 951 // handles such relaxations. Instructions encoding information was taken from: 952 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2" 953 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/ 954 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf) 955 template <class ELFT> 956 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val, 957 uint8_t Op, uint8_t ModRm) const { 958 const uint8_t Rex = Loc[-3]; 959 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg". 960 if (Op == 0x85) { 961 // See "TEST-Logical Compare" (4-428 Vol. 2B), 962 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension). 963 964 // ModR/M byte has form XX YYY ZZZ, where 965 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1). 966 // XX has different meanings: 967 // 00: The operand's memory address is in reg1. 968 // 01: The operand's memory address is reg1 + a byte-sized displacement. 969 // 10: The operand's memory address is reg1 + a word-sized displacement. 970 // 11: The operand is reg1 itself. 971 // If an instruction requires only one operand, the unused reg2 field 972 // holds extra opcode bits rather than a register code 973 // 0xC0 == 11 000 000 binary. 974 // 0x38 == 00 111 000 binary. 975 // We transfer reg2 to reg1 here as operand. 976 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3). 977 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte. 978 979 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32 980 // See "TEST-Logical Compare" (4-428 Vol. 2B). 981 Loc[-2] = 0xf7; 982 983 // Move R bit to the B bit in REX byte. 984 // REX byte is encoded as 0100WRXB, where 985 // 0100 is 4bit fixed pattern. 986 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the 987 // default operand size is used (which is 32-bit for most but not all 988 // instructions). 989 // REX.R This 1-bit value is an extension to the MODRM.reg field. 990 // REX.X This 1-bit value is an extension to the SIB.index field. 991 // REX.B This 1-bit value is an extension to the MODRM.rm field or the 992 // SIB.base field. 993 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A). 994 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 995 relocateOne(Loc, R_X86_64_PC32, Val); 996 return; 997 } 998 999 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub 1000 // or xor operations. 1001 1002 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg". 1003 // Logic is close to one for test instruction above, but we also 1004 // write opcode extension here, see below for details. 1005 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte. 1006 1007 // Primary opcode is 0x81, opcode extension is one of: 1008 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB, 1009 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP. 1010 // This value was wrote to MODRM.reg in a line above. 1011 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15), 1012 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for 1013 // descriptions about each operation. 1014 Loc[-2] = 0x81; 1015 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 1016 relocateOne(Loc, R_X86_64_PC32, Val); 1017 } 1018 1019 template <class ELFT> 1020 void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const { 1021 const uint8_t Op = Loc[-2]; 1022 const uint8_t ModRm = Loc[-1]; 1023 1024 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg". 1025 if (Op == 0x8b) { 1026 Loc[-2] = 0x8d; 1027 relocateOne(Loc, R_X86_64_PC32, Val); 1028 return; 1029 } 1030 1031 if (Op != 0xff) { 1032 // We are relaxing a rip relative to an absolute, so compensate 1033 // for the old -4 addend. 1034 assert(!Config->pic()); 1035 relaxGotNoPic(Loc, Val + 4, Op, ModRm); 1036 return; 1037 } 1038 1039 // Convert call/jmp instructions. 1040 if (ModRm == 0x15) { 1041 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo". 1042 // Instead we convert to "addr32 call foo" where addr32 is an instruction 1043 // prefix. That makes result expression to be a single instruction. 1044 Loc[-2] = 0x67; // addr32 prefix 1045 Loc[-1] = 0xe8; // call 1046 relocateOne(Loc, R_X86_64_PC32, Val); 1047 return; 1048 } 1049 1050 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop". 1051 // jmp doesn't return, so it is fine to use nop here, it is just a stub. 1052 assert(ModRm == 0x25); 1053 Loc[-2] = 0xe9; // jmp 1054 Loc[3] = 0x90; // nop 1055 relocateOne(Loc - 1, R_X86_64_PC32, Val + 1); 1056 } 1057 1058 // Relocation masks following the #lo(value), #hi(value), #ha(value), 1059 // #higher(value), #highera(value), #highest(value), and #highesta(value) 1060 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 1061 // document. 1062 static uint16_t applyPPCLo(uint64_t V) { return V; } 1063 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; } 1064 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; } 1065 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; } 1066 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; } 1067 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; } 1068 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; } 1069 1070 PPCTargetInfo::PPCTargetInfo() {} 1071 1072 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1073 uint64_t Val) const { 1074 switch (Type) { 1075 case R_PPC_ADDR16_HA: 1076 write16be(Loc, applyPPCHa(Val)); 1077 break; 1078 case R_PPC_ADDR16_LO: 1079 write16be(Loc, applyPPCLo(Val)); 1080 break; 1081 case R_PPC_ADDR32: 1082 case R_PPC_REL32: 1083 write32be(Loc, Val); 1084 break; 1085 case R_PPC_REL24: 1086 or32be(Loc, Val & 0x3FFFFFC); 1087 break; 1088 default: 1089 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1090 } 1091 } 1092 1093 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1094 switch (Type) { 1095 case R_PPC_REL24: 1096 case R_PPC_REL32: 1097 return R_PC; 1098 default: 1099 return R_ABS; 1100 } 1101 } 1102 1103 PPC64TargetInfo::PPC64TargetInfo() { 1104 PltRel = GotRel = R_PPC64_GLOB_DAT; 1105 RelativeRel = R_PPC64_RELATIVE; 1106 GotEntrySize = 8; 1107 GotPltEntrySize = 8; 1108 PltEntrySize = 32; 1109 PltHeaderSize = 0; 1110 1111 // We need 64K pages (at least under glibc/Linux, the loader won't 1112 // set different permissions on a finer granularity than that). 1113 DefaultMaxPageSize = 65536; 1114 1115 // The PPC64 ELF ABI v1 spec, says: 1116 // 1117 // It is normally desirable to put segments with different characteristics 1118 // in separate 256 Mbyte portions of the address space, to give the 1119 // operating system full paging flexibility in the 64-bit address space. 1120 // 1121 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 1122 // use 0x10000000 as the starting address. 1123 DefaultImageBase = 0x10000000; 1124 } 1125 1126 static uint64_t PPC64TocOffset = 0x8000; 1127 1128 uint64_t getPPC64TocBase() { 1129 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 1130 // TOC starts where the first of these sections starts. We always create a 1131 // .got when we see a relocation that uses it, so for us the start is always 1132 // the .got. 1133 uint64_t TocVA = In<ELF64BE>::Got->getVA(); 1134 1135 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 1136 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 1137 // code (crt1.o) assumes that you can get from the TOC base to the 1138 // start of the .toc section with only a single (signed) 16-bit relocation. 1139 return TocVA + PPC64TocOffset; 1140 } 1141 1142 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1143 switch (Type) { 1144 default: 1145 return R_ABS; 1146 case R_PPC64_TOC16: 1147 case R_PPC64_TOC16_DS: 1148 case R_PPC64_TOC16_HA: 1149 case R_PPC64_TOC16_HI: 1150 case R_PPC64_TOC16_LO: 1151 case R_PPC64_TOC16_LO_DS: 1152 return R_GOTREL; 1153 case R_PPC64_TOC: 1154 return R_PPC_TOC; 1155 case R_PPC64_REL24: 1156 return R_PPC_PLT_OPD; 1157 } 1158 } 1159 1160 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1161 uint64_t PltEntryAddr, int32_t Index, 1162 unsigned RelOff) const { 1163 uint64_t Off = GotEntryAddr - getPPC64TocBase(); 1164 1165 // FIXME: What we should do, in theory, is get the offset of the function 1166 // descriptor in the .opd section, and use that as the offset from %r2 (the 1167 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will 1168 // be a pointer to the function descriptor in the .opd section. Using 1169 // this scheme is simpler, but requires an extra indirection per PLT dispatch. 1170 1171 write32be(Buf, 0xf8410028); // std %r2, 40(%r1) 1172 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha 1173 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11) 1174 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12) 1175 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11 1176 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12) 1177 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12) 1178 write32be(Buf + 28, 0x4e800420); // bctr 1179 } 1180 1181 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) { 1182 uint64_t V = Val - PPC64TocOffset; 1183 switch (Type) { 1184 case R_PPC64_TOC16: 1185 return {R_PPC64_ADDR16, V}; 1186 case R_PPC64_TOC16_DS: 1187 return {R_PPC64_ADDR16_DS, V}; 1188 case R_PPC64_TOC16_HA: 1189 return {R_PPC64_ADDR16_HA, V}; 1190 case R_PPC64_TOC16_HI: 1191 return {R_PPC64_ADDR16_HI, V}; 1192 case R_PPC64_TOC16_LO: 1193 return {R_PPC64_ADDR16_LO, V}; 1194 case R_PPC64_TOC16_LO_DS: 1195 return {R_PPC64_ADDR16_LO_DS, V}; 1196 default: 1197 return {Type, Val}; 1198 } 1199 } 1200 1201 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1202 uint64_t Val) const { 1203 // For a TOC-relative relocation, proceed in terms of the corresponding 1204 // ADDR16 relocation type. 1205 std::tie(Type, Val) = toAddr16Rel(Type, Val); 1206 1207 switch (Type) { 1208 case R_PPC64_ADDR14: { 1209 checkAlignment<4>(Loc, Val, Type); 1210 // Preserve the AA/LK bits in the branch instruction 1211 uint8_t AALK = Loc[3]; 1212 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 1213 break; 1214 } 1215 case R_PPC64_ADDR16: 1216 checkInt<16>(Loc, Val, Type); 1217 write16be(Loc, Val); 1218 break; 1219 case R_PPC64_ADDR16_DS: 1220 checkInt<16>(Loc, Val, Type); 1221 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3)); 1222 break; 1223 case R_PPC64_ADDR16_HA: 1224 case R_PPC64_REL16_HA: 1225 write16be(Loc, applyPPCHa(Val)); 1226 break; 1227 case R_PPC64_ADDR16_HI: 1228 case R_PPC64_REL16_HI: 1229 write16be(Loc, applyPPCHi(Val)); 1230 break; 1231 case R_PPC64_ADDR16_HIGHER: 1232 write16be(Loc, applyPPCHigher(Val)); 1233 break; 1234 case R_PPC64_ADDR16_HIGHERA: 1235 write16be(Loc, applyPPCHighera(Val)); 1236 break; 1237 case R_PPC64_ADDR16_HIGHEST: 1238 write16be(Loc, applyPPCHighest(Val)); 1239 break; 1240 case R_PPC64_ADDR16_HIGHESTA: 1241 write16be(Loc, applyPPCHighesta(Val)); 1242 break; 1243 case R_PPC64_ADDR16_LO: 1244 write16be(Loc, applyPPCLo(Val)); 1245 break; 1246 case R_PPC64_ADDR16_LO_DS: 1247 case R_PPC64_REL16_LO: 1248 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3)); 1249 break; 1250 case R_PPC64_ADDR32: 1251 case R_PPC64_REL32: 1252 checkInt<32>(Loc, Val, Type); 1253 write32be(Loc, Val); 1254 break; 1255 case R_PPC64_ADDR64: 1256 case R_PPC64_REL64: 1257 case R_PPC64_TOC: 1258 write64be(Loc, Val); 1259 break; 1260 case R_PPC64_REL24: { 1261 uint32_t Mask = 0x03FFFFFC; 1262 checkInt<24>(Loc, Val, Type); 1263 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask)); 1264 break; 1265 } 1266 default: 1267 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1268 } 1269 } 1270 1271 AArch64TargetInfo::AArch64TargetInfo() { 1272 CopyRel = R_AARCH64_COPY; 1273 RelativeRel = R_AARCH64_RELATIVE; 1274 IRelativeRel = R_AARCH64_IRELATIVE; 1275 GotRel = R_AARCH64_GLOB_DAT; 1276 PltRel = R_AARCH64_JUMP_SLOT; 1277 TlsDescRel = R_AARCH64_TLSDESC; 1278 TlsGotRel = R_AARCH64_TLS_TPREL64; 1279 GotEntrySize = 8; 1280 GotPltEntrySize = 8; 1281 PltEntrySize = 16; 1282 PltHeaderSize = 32; 1283 DefaultMaxPageSize = 65536; 1284 1285 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant 1286 // 1 of the tls structures and the tcb size is 16. 1287 TcbSize = 16; 1288 } 1289 1290 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type, 1291 const SymbolBody &S) const { 1292 switch (Type) { 1293 default: 1294 return R_ABS; 1295 case R_AARCH64_TLSDESC_ADR_PAGE21: 1296 return R_TLSDESC_PAGE; 1297 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1298 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1299 return R_TLSDESC; 1300 case R_AARCH64_TLSDESC_CALL: 1301 return R_TLSDESC_CALL; 1302 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1303 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1304 return R_TLS; 1305 case R_AARCH64_CALL26: 1306 case R_AARCH64_CONDBR19: 1307 case R_AARCH64_JUMP26: 1308 case R_AARCH64_TSTBR14: 1309 return R_PLT_PC; 1310 case R_AARCH64_PREL16: 1311 case R_AARCH64_PREL32: 1312 case R_AARCH64_PREL64: 1313 case R_AARCH64_ADR_PREL_LO21: 1314 return R_PC; 1315 case R_AARCH64_ADR_PREL_PG_HI21: 1316 return R_PAGE_PC; 1317 case R_AARCH64_LD64_GOT_LO12_NC: 1318 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1319 return R_GOT; 1320 case R_AARCH64_ADR_GOT_PAGE: 1321 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1322 return R_GOT_PAGE_PC; 1323 case R_AARCH64_NONE: 1324 return R_NONE; 1325 } 1326 } 1327 1328 RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 1329 RelExpr Expr) const { 1330 if (Expr == R_RELAX_TLS_GD_TO_IE) { 1331 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21) 1332 return R_RELAX_TLS_GD_TO_IE_PAGE_PC; 1333 return R_RELAX_TLS_GD_TO_IE_ABS; 1334 } 1335 return Expr; 1336 } 1337 1338 bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { 1339 switch (Type) { 1340 default: 1341 return false; 1342 case R_AARCH64_ADD_ABS_LO12_NC: 1343 case R_AARCH64_LD64_GOT_LO12_NC: 1344 case R_AARCH64_LDST128_ABS_LO12_NC: 1345 case R_AARCH64_LDST16_ABS_LO12_NC: 1346 case R_AARCH64_LDST32_ABS_LO12_NC: 1347 case R_AARCH64_LDST64_ABS_LO12_NC: 1348 case R_AARCH64_LDST8_ABS_LO12_NC: 1349 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1350 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1351 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1352 return true; 1353 } 1354 } 1355 1356 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1357 return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 || 1358 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; 1359 } 1360 1361 bool AArch64TargetInfo::isPicRel(uint32_t Type) const { 1362 return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64; 1363 } 1364 1365 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1366 write64le(Buf, In<ELF64LE>::Plt->getVA()); 1367 } 1368 1369 // Page(Expr) is the page address of the expression Expr, defined 1370 // as (Expr & ~0xFFF). (This applies even if the machine page size 1371 // supported by the platform has a different value.) 1372 uint64_t getAArch64Page(uint64_t Expr) { 1373 return Expr & (~static_cast<uint64_t>(0xFFF)); 1374 } 1375 1376 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const { 1377 const uint8_t PltData[] = { 1378 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 1379 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 1380 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 1381 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 1382 0x20, 0x02, 0x1f, 0xd6, // br x17 1383 0x1f, 0x20, 0x03, 0xd5, // nop 1384 0x1f, 0x20, 0x03, 0xd5, // nop 1385 0x1f, 0x20, 0x03, 0xd5 // nop 1386 }; 1387 memcpy(Buf, PltData, sizeof(PltData)); 1388 1389 uint64_t Got = In<ELF64LE>::GotPlt->getVA(); 1390 uint64_t Plt = In<ELF64LE>::Plt->getVA(); 1391 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 1392 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4)); 1393 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16); 1394 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16); 1395 } 1396 1397 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1398 uint64_t PltEntryAddr, int32_t Index, 1399 unsigned RelOff) const { 1400 const uint8_t Inst[] = { 1401 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 1402 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 1403 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n])) 1404 0x20, 0x02, 0x1f, 0xd6 // br x17 1405 }; 1406 memcpy(Buf, Inst, sizeof(Inst)); 1407 1408 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21, 1409 getAArch64Page(GotEntryAddr) - getAArch64Page(PltEntryAddr)); 1410 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotEntryAddr); 1411 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotEntryAddr); 1412 } 1413 1414 static void write32AArch64Addr(uint8_t *L, uint64_t Imm) { 1415 uint32_t ImmLo = (Imm & 0x3) << 29; 1416 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3; 1417 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3); 1418 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi); 1419 } 1420 1421 // Return the bits [Start, End] from Val shifted Start bits. 1422 // For instance, getBits(0xF0, 4, 8) returns 0xF. 1423 static uint64_t getBits(uint64_t Val, int Start, int End) { 1424 uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1; 1425 return (Val >> Start) & Mask; 1426 } 1427 1428 // Update the immediate field in a AARCH64 ldr, str, and add instruction. 1429 static void or32AArch64Imm(uint8_t *L, uint64_t Imm) { 1430 or32le(L, (Imm & 0xFFF) << 10); 1431 } 1432 1433 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1434 uint64_t Val) const { 1435 switch (Type) { 1436 case R_AARCH64_ABS16: 1437 case R_AARCH64_PREL16: 1438 checkIntUInt<16>(Loc, Val, Type); 1439 write16le(Loc, Val); 1440 break; 1441 case R_AARCH64_ABS32: 1442 case R_AARCH64_PREL32: 1443 checkIntUInt<32>(Loc, Val, Type); 1444 write32le(Loc, Val); 1445 break; 1446 case R_AARCH64_ABS64: 1447 case R_AARCH64_GLOB_DAT: 1448 case R_AARCH64_PREL64: 1449 write64le(Loc, Val); 1450 break; 1451 case R_AARCH64_ADD_ABS_LO12_NC: 1452 or32AArch64Imm(Loc, Val); 1453 break; 1454 case R_AARCH64_ADR_GOT_PAGE: 1455 case R_AARCH64_ADR_PREL_PG_HI21: 1456 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1457 case R_AARCH64_TLSDESC_ADR_PAGE21: 1458 checkInt<33>(Loc, Val, Type); 1459 write32AArch64Addr(Loc, Val >> 12); 1460 break; 1461 case R_AARCH64_ADR_PREL_LO21: 1462 checkInt<21>(Loc, Val, Type); 1463 write32AArch64Addr(Loc, Val); 1464 break; 1465 case R_AARCH64_CALL26: 1466 case R_AARCH64_JUMP26: 1467 checkInt<28>(Loc, Val, Type); 1468 or32le(Loc, (Val & 0x0FFFFFFC) >> 2); 1469 break; 1470 case R_AARCH64_CONDBR19: 1471 checkInt<21>(Loc, Val, Type); 1472 or32le(Loc, (Val & 0x1FFFFC) << 3); 1473 break; 1474 case R_AARCH64_LD64_GOT_LO12_NC: 1475 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1476 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1477 checkAlignment<8>(Loc, Val, Type); 1478 or32le(Loc, (Val & 0xFF8) << 7); 1479 break; 1480 case R_AARCH64_LDST8_ABS_LO12_NC: 1481 or32AArch64Imm(Loc, getBits(Val, 0, 11)); 1482 break; 1483 case R_AARCH64_LDST16_ABS_LO12_NC: 1484 or32AArch64Imm(Loc, getBits(Val, 1, 11)); 1485 break; 1486 case R_AARCH64_LDST32_ABS_LO12_NC: 1487 or32AArch64Imm(Loc, getBits(Val, 2, 11)); 1488 break; 1489 case R_AARCH64_LDST64_ABS_LO12_NC: 1490 or32AArch64Imm(Loc, getBits(Val, 3, 11)); 1491 break; 1492 case R_AARCH64_LDST128_ABS_LO12_NC: 1493 or32AArch64Imm(Loc, getBits(Val, 4, 11)); 1494 break; 1495 case R_AARCH64_MOVW_UABS_G0_NC: 1496 or32le(Loc, (Val & 0xFFFF) << 5); 1497 break; 1498 case R_AARCH64_MOVW_UABS_G1_NC: 1499 or32le(Loc, (Val & 0xFFFF0000) >> 11); 1500 break; 1501 case R_AARCH64_MOVW_UABS_G2_NC: 1502 or32le(Loc, (Val & 0xFFFF00000000) >> 27); 1503 break; 1504 case R_AARCH64_MOVW_UABS_G3: 1505 or32le(Loc, (Val & 0xFFFF000000000000) >> 43); 1506 break; 1507 case R_AARCH64_TSTBR14: 1508 checkInt<16>(Loc, Val, Type); 1509 or32le(Loc, (Val & 0xFFFC) << 3); 1510 break; 1511 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1512 checkInt<24>(Loc, Val, Type); 1513 or32AArch64Imm(Loc, Val >> 12); 1514 break; 1515 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1516 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1517 or32AArch64Imm(Loc, Val); 1518 break; 1519 default: 1520 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1521 } 1522 } 1523 1524 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 1525 uint64_t Val) const { 1526 // TLSDESC Global-Dynamic relocation are in the form: 1527 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1528 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1529 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1530 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1531 // blr x1 1532 // And it can optimized to: 1533 // movz x0, #0x0, lsl #16 1534 // movk x0, #0x10 1535 // nop 1536 // nop 1537 checkUInt<32>(Loc, Val, Type); 1538 1539 switch (Type) { 1540 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1541 case R_AARCH64_TLSDESC_CALL: 1542 write32le(Loc, 0xd503201f); // nop 1543 return; 1544 case R_AARCH64_TLSDESC_ADR_PAGE21: 1545 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz 1546 return; 1547 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1548 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk 1549 return; 1550 default: 1551 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1552 } 1553 } 1554 1555 void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 1556 uint64_t Val) const { 1557 // TLSDESC Global-Dynamic relocation are in the form: 1558 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1559 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1560 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1561 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1562 // blr x1 1563 // And it can optimized to: 1564 // adrp x0, :gottprel:v 1565 // ldr x0, [x0, :gottprel_lo12:v] 1566 // nop 1567 // nop 1568 1569 switch (Type) { 1570 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1571 case R_AARCH64_TLSDESC_CALL: 1572 write32le(Loc, 0xd503201f); // nop 1573 break; 1574 case R_AARCH64_TLSDESC_ADR_PAGE21: 1575 write32le(Loc, 0x90000000); // adrp 1576 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val); 1577 break; 1578 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1579 write32le(Loc, 0xf9400000); // ldr 1580 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val); 1581 break; 1582 default: 1583 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1584 } 1585 } 1586 1587 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 1588 uint64_t Val) const { 1589 checkUInt<32>(Loc, Val, Type); 1590 1591 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) { 1592 // Generate MOVZ. 1593 uint32_t RegNo = read32le(Loc) & 0x1f; 1594 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5)); 1595 return; 1596 } 1597 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) { 1598 // Generate MOVK. 1599 uint32_t RegNo = read32le(Loc) & 0x1f; 1600 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5)); 1601 return; 1602 } 1603 llvm_unreachable("invalid relocation for TLS IE to LE relaxation"); 1604 } 1605 1606 AMDGPUTargetInfo::AMDGPUTargetInfo() { 1607 RelativeRel = R_AMDGPU_REL64; 1608 GotRel = R_AMDGPU_ABS64; 1609 GotEntrySize = 8; 1610 } 1611 1612 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1613 uint64_t Val) const { 1614 switch (Type) { 1615 case R_AMDGPU_ABS32: 1616 case R_AMDGPU_GOTPCREL: 1617 case R_AMDGPU_GOTPCREL32_LO: 1618 case R_AMDGPU_REL32: 1619 case R_AMDGPU_REL32_LO: 1620 write32le(Loc, Val); 1621 break; 1622 case R_AMDGPU_ABS64: 1623 write64le(Loc, Val); 1624 break; 1625 case R_AMDGPU_GOTPCREL32_HI: 1626 case R_AMDGPU_REL32_HI: 1627 write32le(Loc, Val >> 32); 1628 break; 1629 default: 1630 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1631 } 1632 } 1633 1634 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1635 switch (Type) { 1636 case R_AMDGPU_ABS32: 1637 case R_AMDGPU_ABS64: 1638 return R_ABS; 1639 case R_AMDGPU_REL32: 1640 case R_AMDGPU_REL32_LO: 1641 case R_AMDGPU_REL32_HI: 1642 return R_PC; 1643 case R_AMDGPU_GOTPCREL: 1644 case R_AMDGPU_GOTPCREL32_LO: 1645 case R_AMDGPU_GOTPCREL32_HI: 1646 return R_GOT_PC; 1647 default: 1648 error(toString(S.File) + ": unknown relocation type: " + toString(Type)); 1649 return R_HINT; 1650 } 1651 } 1652 1653 ARMTargetInfo::ARMTargetInfo() { 1654 CopyRel = R_ARM_COPY; 1655 RelativeRel = R_ARM_RELATIVE; 1656 IRelativeRel = R_ARM_IRELATIVE; 1657 GotRel = R_ARM_GLOB_DAT; 1658 PltRel = R_ARM_JUMP_SLOT; 1659 TlsGotRel = R_ARM_TLS_TPOFF32; 1660 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32; 1661 TlsOffsetRel = R_ARM_TLS_DTPOFF32; 1662 GotEntrySize = 4; 1663 GotPltEntrySize = 4; 1664 PltEntrySize = 16; 1665 PltHeaderSize = 20; 1666 // ARM uses Variant 1 TLS 1667 TcbSize = 8; 1668 NeedsThunks = true; 1669 } 1670 1671 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1672 switch (Type) { 1673 default: 1674 return R_ABS; 1675 case R_ARM_THM_JUMP11: 1676 return R_PC; 1677 case R_ARM_CALL: 1678 case R_ARM_JUMP24: 1679 case R_ARM_PC24: 1680 case R_ARM_PLT32: 1681 case R_ARM_PREL31: 1682 case R_ARM_THM_JUMP19: 1683 case R_ARM_THM_JUMP24: 1684 case R_ARM_THM_CALL: 1685 return R_PLT_PC; 1686 case R_ARM_GOTOFF32: 1687 // (S + A) - GOT_ORG 1688 return R_GOTREL; 1689 case R_ARM_GOT_BREL: 1690 // GOT(S) + A - GOT_ORG 1691 return R_GOT_OFF; 1692 case R_ARM_GOT_PREL: 1693 case R_ARM_TLS_IE32: 1694 // GOT(S) + A - P 1695 return R_GOT_PC; 1696 case R_ARM_TARGET1: 1697 return Config->Target1Rel ? R_PC : R_ABS; 1698 case R_ARM_TARGET2: 1699 if (Config->Target2 == Target2Policy::Rel) 1700 return R_PC; 1701 if (Config->Target2 == Target2Policy::Abs) 1702 return R_ABS; 1703 return R_GOT_PC; 1704 case R_ARM_TLS_GD32: 1705 return R_TLSGD_PC; 1706 case R_ARM_TLS_LDM32: 1707 return R_TLSLD_PC; 1708 case R_ARM_BASE_PREL: 1709 // B(S) + A - P 1710 // FIXME: currently B(S) assumed to be .got, this may not hold for all 1711 // platforms. 1712 return R_GOTONLY_PC; 1713 case R_ARM_MOVW_PREL_NC: 1714 case R_ARM_MOVT_PREL: 1715 case R_ARM_REL32: 1716 case R_ARM_THM_MOVW_PREL_NC: 1717 case R_ARM_THM_MOVT_PREL: 1718 return R_PC; 1719 case R_ARM_NONE: 1720 return R_NONE; 1721 case R_ARM_TLS_LE32: 1722 return R_TLS; 1723 } 1724 } 1725 1726 bool ARMTargetInfo::isPicRel(uint32_t Type) const { 1727 return (Type == R_ARM_TARGET1 && !Config->Target1Rel) || 1728 (Type == R_ARM_ABS32); 1729 } 1730 1731 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const { 1732 if (Type == R_ARM_TARGET1 && !Config->Target1Rel) 1733 return R_ARM_ABS32; 1734 if (Type == R_ARM_ABS32) 1735 return Type; 1736 // Keep it going with a dummy value so that we can find more reloc errors. 1737 return R_ARM_ABS32; 1738 } 1739 1740 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1741 write32le(Buf, In<ELF32LE>::Plt->getVA()); 1742 } 1743 1744 void ARMTargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 1745 // An ARM entry is the address of the ifunc resolver function. 1746 write32le(Buf, S.getVA<ELF32LE>()); 1747 } 1748 1749 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const { 1750 const uint8_t PltData[] = { 1751 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]! 1752 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2 1753 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr 1754 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8] 1755 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8 1756 }; 1757 memcpy(Buf, PltData, sizeof(PltData)); 1758 uint64_t GotPlt = In<ELF32LE>::GotPlt->getVA(); 1759 uint64_t L1 = In<ELF32LE>::Plt->getVA() + 8; 1760 write32le(Buf + 16, GotPlt - L1 - 8); 1761 } 1762 1763 void ARMTargetInfo::addPltHeaderSymbols(InputSectionBase *ISD) const { 1764 auto *IS = cast<InputSection>(ISD); 1765 addSyntheticLocal<ELF32LE>("$a", STT_NOTYPE, 0, 0, IS); 1766 addSyntheticLocal<ELF32LE>("$d", STT_NOTYPE, 16, 0, IS); 1767 } 1768 1769 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1770 uint64_t PltEntryAddr, int32_t Index, 1771 unsigned RelOff) const { 1772 // FIXME: Using simple code sequence with simple relocations. 1773 // There is a more optimal sequence but it requires support for the group 1774 // relocations. See ELF for the ARM Architecture Appendix A.3 1775 const uint8_t PltData[] = { 1776 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2 1777 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc 1778 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip] 1779 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8 1780 }; 1781 memcpy(Buf, PltData, sizeof(PltData)); 1782 uint64_t L1 = PltEntryAddr + 4; 1783 write32le(Buf + 12, GotEntryAddr - L1 - 8); 1784 } 1785 1786 void ARMTargetInfo::addPltSymbols(InputSectionBase *ISD, uint64_t Off) const { 1787 auto *IS = cast<InputSection>(ISD); 1788 addSyntheticLocal<ELF32LE>("$a", STT_NOTYPE, Off, 0, IS); 1789 addSyntheticLocal<ELF32LE>("$d", STT_NOTYPE, Off + 12, 0, IS); 1790 } 1791 1792 bool ARMTargetInfo::needsThunk(RelExpr Expr, uint32_t RelocType, 1793 const InputFile *File, 1794 const SymbolBody &S) const { 1795 // If S is an undefined weak symbol in an executable we don't need a Thunk. 1796 // In a DSO calls to undefined symbols, including weak ones get PLT entries 1797 // which may need a thunk. 1798 if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak() && 1799 !Config->Shared) 1800 return false; 1801 // A state change from ARM to Thumb and vice versa must go through an 1802 // interworking thunk if the relocation type is not R_ARM_CALL or 1803 // R_ARM_THM_CALL. 1804 switch (RelocType) { 1805 case R_ARM_PC24: 1806 case R_ARM_PLT32: 1807 case R_ARM_JUMP24: 1808 // Source is ARM, all PLT entries are ARM so no interworking required. 1809 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb). 1810 if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1)) 1811 return true; 1812 break; 1813 case R_ARM_THM_JUMP19: 1814 case R_ARM_THM_JUMP24: 1815 // Source is Thumb, all PLT entries are ARM so interworking is required. 1816 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM). 1817 if (Expr == R_PLT_PC || ((S.getVA<ELF32LE>() & 1) == 0)) 1818 return true; 1819 break; 1820 } 1821 return false; 1822 } 1823 1824 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1825 uint64_t Val) const { 1826 switch (Type) { 1827 case R_ARM_ABS32: 1828 case R_ARM_BASE_PREL: 1829 case R_ARM_GLOB_DAT: 1830 case R_ARM_GOTOFF32: 1831 case R_ARM_GOT_BREL: 1832 case R_ARM_GOT_PREL: 1833 case R_ARM_REL32: 1834 case R_ARM_RELATIVE: 1835 case R_ARM_TARGET1: 1836 case R_ARM_TARGET2: 1837 case R_ARM_TLS_GD32: 1838 case R_ARM_TLS_IE32: 1839 case R_ARM_TLS_LDM32: 1840 case R_ARM_TLS_LDO32: 1841 case R_ARM_TLS_LE32: 1842 case R_ARM_TLS_TPOFF32: 1843 write32le(Loc, Val); 1844 break; 1845 case R_ARM_TLS_DTPMOD32: 1846 write32le(Loc, 1); 1847 break; 1848 case R_ARM_PREL31: 1849 checkInt<31>(Loc, Val, Type); 1850 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000)); 1851 break; 1852 case R_ARM_CALL: 1853 // R_ARM_CALL is used for BL and BLX instructions, depending on the 1854 // value of bit 0 of Val, we must select a BL or BLX instruction 1855 if (Val & 1) { 1856 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX. 1857 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' 1858 checkInt<26>(Loc, Val, Type); 1859 write32le(Loc, 0xfa000000 | // opcode 1860 ((Val & 2) << 23) | // H 1861 ((Val >> 2) & 0x00ffffff)); // imm24 1862 break; 1863 } 1864 if ((read32le(Loc) & 0xfe000000) == 0xfa000000) 1865 // BLX (always unconditional) instruction to an ARM Target, select an 1866 // unconditional BL. 1867 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff)); 1868 // fall through as BL encoding is shared with B 1869 case R_ARM_JUMP24: 1870 case R_ARM_PC24: 1871 case R_ARM_PLT32: 1872 checkInt<26>(Loc, Val, Type); 1873 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff)); 1874 break; 1875 case R_ARM_THM_JUMP11: 1876 checkInt<12>(Loc, Val, Type); 1877 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff)); 1878 break; 1879 case R_ARM_THM_JUMP19: 1880 // Encoding T3: Val = S:J2:J1:imm6:imm11:0 1881 checkInt<21>(Loc, Val, Type); 1882 write16le(Loc, 1883 (read16le(Loc) & 0xfbc0) | // opcode cond 1884 ((Val >> 10) & 0x0400) | // S 1885 ((Val >> 12) & 0x003f)); // imm6 1886 write16le(Loc + 2, 1887 0x8000 | // opcode 1888 ((Val >> 8) & 0x0800) | // J2 1889 ((Val >> 5) & 0x2000) | // J1 1890 ((Val >> 1) & 0x07ff)); // imm11 1891 break; 1892 case R_ARM_THM_CALL: 1893 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the 1894 // value of bit 0 of Val, we must select a BL or BLX instruction 1895 if ((Val & 1) == 0) { 1896 // Ensure BLX destination is 4-byte aligned. As BLX instruction may 1897 // only be two byte aligned. This must be done before overflow check 1898 Val = alignTo(Val, 4); 1899 } 1900 // Bit 12 is 0 for BLX, 1 for BL 1901 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12); 1902 // Fall through as rest of encoding is the same as B.W 1903 case R_ARM_THM_JUMP24: 1904 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 1905 // FIXME: Use of I1 and I2 require v6T2ops 1906 checkInt<25>(Loc, Val, Type); 1907 write16le(Loc, 1908 0xf000 | // opcode 1909 ((Val >> 14) & 0x0400) | // S 1910 ((Val >> 12) & 0x03ff)); // imm10 1911 write16le(Loc + 2, 1912 (read16le(Loc + 2) & 0xd000) | // opcode 1913 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1 1914 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2 1915 ((Val >> 1) & 0x07ff)); // imm11 1916 break; 1917 case R_ARM_MOVW_ABS_NC: 1918 case R_ARM_MOVW_PREL_NC: 1919 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) | 1920 (Val & 0x0fff)); 1921 break; 1922 case R_ARM_MOVT_ABS: 1923 case R_ARM_MOVT_PREL: 1924 checkInt<32>(Loc, Val, Type); 1925 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | 1926 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff)); 1927 break; 1928 case R_ARM_THM_MOVT_ABS: 1929 case R_ARM_THM_MOVT_PREL: 1930 // Encoding T1: A = imm4:i:imm3:imm8 1931 checkInt<32>(Loc, Val, Type); 1932 write16le(Loc, 1933 0xf2c0 | // opcode 1934 ((Val >> 17) & 0x0400) | // i 1935 ((Val >> 28) & 0x000f)); // imm4 1936 write16le(Loc + 2, 1937 (read16le(Loc + 2) & 0x8f00) | // opcode 1938 ((Val >> 12) & 0x7000) | // imm3 1939 ((Val >> 16) & 0x00ff)); // imm8 1940 break; 1941 case R_ARM_THM_MOVW_ABS_NC: 1942 case R_ARM_THM_MOVW_PREL_NC: 1943 // Encoding T3: A = imm4:i:imm3:imm8 1944 write16le(Loc, 1945 0xf240 | // opcode 1946 ((Val >> 1) & 0x0400) | // i 1947 ((Val >> 12) & 0x000f)); // imm4 1948 write16le(Loc + 2, 1949 (read16le(Loc + 2) & 0x8f00) | // opcode 1950 ((Val << 4) & 0x7000) | // imm3 1951 (Val & 0x00ff)); // imm8 1952 break; 1953 default: 1954 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1955 } 1956 } 1957 1958 int64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf, 1959 uint32_t Type) const { 1960 switch (Type) { 1961 default: 1962 return 0; 1963 case R_ARM_ABS32: 1964 case R_ARM_BASE_PREL: 1965 case R_ARM_GOTOFF32: 1966 case R_ARM_GOT_BREL: 1967 case R_ARM_GOT_PREL: 1968 case R_ARM_REL32: 1969 case R_ARM_TARGET1: 1970 case R_ARM_TARGET2: 1971 case R_ARM_TLS_GD32: 1972 case R_ARM_TLS_LDM32: 1973 case R_ARM_TLS_LDO32: 1974 case R_ARM_TLS_IE32: 1975 case R_ARM_TLS_LE32: 1976 return SignExtend64<32>(read32le(Buf)); 1977 case R_ARM_PREL31: 1978 return SignExtend64<31>(read32le(Buf)); 1979 case R_ARM_CALL: 1980 case R_ARM_JUMP24: 1981 case R_ARM_PC24: 1982 case R_ARM_PLT32: 1983 return SignExtend64<26>(read32le(Buf) << 2); 1984 case R_ARM_THM_JUMP11: 1985 return SignExtend64<12>(read16le(Buf) << 1); 1986 case R_ARM_THM_JUMP19: { 1987 // Encoding T3: A = S:J2:J1:imm10:imm6:0 1988 uint16_t Hi = read16le(Buf); 1989 uint16_t Lo = read16le(Buf + 2); 1990 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S 1991 ((Lo & 0x0800) << 8) | // J2 1992 ((Lo & 0x2000) << 5) | // J1 1993 ((Hi & 0x003f) << 12) | // imm6 1994 ((Lo & 0x07ff) << 1)); // imm11:0 1995 } 1996 case R_ARM_THM_CALL: 1997 case R_ARM_THM_JUMP24: { 1998 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 1999 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) 2000 // FIXME: I1 and I2 require v6T2ops 2001 uint16_t Hi = read16le(Buf); 2002 uint16_t Lo = read16le(Buf + 2); 2003 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S 2004 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1 2005 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2 2006 ((Hi & 0x003ff) << 12) | // imm0 2007 ((Lo & 0x007ff) << 1)); // imm11:0 2008 } 2009 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and 2010 // MOVT is in the range -32768 <= A < 32768 2011 case R_ARM_MOVW_ABS_NC: 2012 case R_ARM_MOVT_ABS: 2013 case R_ARM_MOVW_PREL_NC: 2014 case R_ARM_MOVT_PREL: { 2015 uint64_t Val = read32le(Buf) & 0x000f0fff; 2016 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff)); 2017 } 2018 case R_ARM_THM_MOVW_ABS_NC: 2019 case R_ARM_THM_MOVT_ABS: 2020 case R_ARM_THM_MOVW_PREL_NC: 2021 case R_ARM_THM_MOVT_PREL: { 2022 // Encoding T3: A = imm4:i:imm3:imm8 2023 uint16_t Hi = read16le(Buf); 2024 uint16_t Lo = read16le(Buf + 2); 2025 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4 2026 ((Hi & 0x0400) << 1) | // i 2027 ((Lo & 0x7000) >> 4) | // imm3 2028 (Lo & 0x00ff)); // imm8 2029 } 2030 } 2031 } 2032 2033 bool ARMTargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 2034 return Type == R_ARM_TLS_LDO32 || Type == R_ARM_TLS_LDM32; 2035 } 2036 2037 bool ARMTargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 2038 return Type == R_ARM_TLS_GD32; 2039 } 2040 2041 bool ARMTargetInfo::isTlsInitialExecRel(uint32_t Type) const { 2042 return Type == R_ARM_TLS_IE32; 2043 } 2044 2045 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() { 2046 GotPltHeaderEntriesNum = 2; 2047 DefaultMaxPageSize = 65536; 2048 GotEntrySize = sizeof(typename ELFT::uint); 2049 GotPltEntrySize = sizeof(typename ELFT::uint); 2050 PltEntrySize = 16; 2051 PltHeaderSize = 32; 2052 CopyRel = R_MIPS_COPY; 2053 PltRel = R_MIPS_JUMP_SLOT; 2054 NeedsThunks = true; 2055 if (ELFT::Is64Bits) { 2056 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 2057 TlsGotRel = R_MIPS_TLS_TPREL64; 2058 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 2059 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 2060 } else { 2061 RelativeRel = R_MIPS_REL32; 2062 TlsGotRel = R_MIPS_TLS_TPREL32; 2063 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 2064 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 2065 } 2066 } 2067 2068 template <class ELFT> 2069 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type, 2070 const SymbolBody &S) const { 2071 // See comment in the calculateMipsRelChain. 2072 if (ELFT::Is64Bits || Config->MipsN32Abi) 2073 Type &= 0xff; 2074 switch (Type) { 2075 default: 2076 return R_ABS; 2077 case R_MIPS_JALR: 2078 return R_HINT; 2079 case R_MIPS_GPREL16: 2080 case R_MIPS_GPREL32: 2081 return R_MIPS_GOTREL; 2082 case R_MIPS_26: 2083 return R_PLT; 2084 case R_MIPS_HI16: 2085 case R_MIPS_LO16: 2086 case R_MIPS_GOT_OFST: 2087 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 2088 // offset between start of function and 'gp' value which by default 2089 // equal to the start of .got section. In that case we consider these 2090 // relocations as relative. 2091 if (&S == ElfSym::MipsGpDisp) 2092 return R_PC; 2093 return R_ABS; 2094 case R_MIPS_PC32: 2095 case R_MIPS_PC16: 2096 case R_MIPS_PC19_S2: 2097 case R_MIPS_PC21_S2: 2098 case R_MIPS_PC26_S2: 2099 case R_MIPS_PCHI16: 2100 case R_MIPS_PCLO16: 2101 return R_PC; 2102 case R_MIPS_GOT16: 2103 if (S.isLocal()) 2104 return R_MIPS_GOT_LOCAL_PAGE; 2105 // fallthrough 2106 case R_MIPS_CALL16: 2107 case R_MIPS_GOT_DISP: 2108 case R_MIPS_TLS_GOTTPREL: 2109 return R_MIPS_GOT_OFF; 2110 case R_MIPS_CALL_HI16: 2111 case R_MIPS_CALL_LO16: 2112 case R_MIPS_GOT_HI16: 2113 case R_MIPS_GOT_LO16: 2114 return R_MIPS_GOT_OFF32; 2115 case R_MIPS_GOT_PAGE: 2116 return R_MIPS_GOT_LOCAL_PAGE; 2117 case R_MIPS_TLS_GD: 2118 return R_MIPS_TLSGD; 2119 case R_MIPS_TLS_LDM: 2120 return R_MIPS_TLSLD; 2121 } 2122 } 2123 2124 template <class ELFT> bool MipsTargetInfo<ELFT>::isPicRel(uint32_t Type) const { 2125 return Type == R_MIPS_32 || Type == R_MIPS_64; 2126 } 2127 2128 template <class ELFT> 2129 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const { 2130 return RelativeRel; 2131 } 2132 2133 template <class ELFT> 2134 bool MipsTargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 2135 return Type == R_MIPS_TLS_LDM; 2136 } 2137 2138 template <class ELFT> 2139 bool MipsTargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 2140 return Type == R_MIPS_TLS_GD; 2141 } 2142 2143 template <class ELFT> 2144 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 2145 write32<ELFT::TargetEndianness>(Buf, In<ELFT>::Plt->getVA()); 2146 } 2147 2148 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2149 static int64_t getPcRelocAddend(const uint8_t *Loc) { 2150 uint32_t Instr = read32<E>(Loc); 2151 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2152 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT); 2153 } 2154 2155 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2156 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) { 2157 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2158 uint32_t Instr = read32<E>(Loc); 2159 if (SHIFT > 0) 2160 checkAlignment<(1 << SHIFT)>(Loc, V, Type); 2161 checkInt<BSIZE + SHIFT>(Loc, V, Type); 2162 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask)); 2163 } 2164 2165 template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) { 2166 uint32_t Instr = read32<E>(Loc); 2167 uint16_t Res = ((V + 0x8000) >> 16) & 0xffff; 2168 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2169 } 2170 2171 template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) { 2172 uint32_t Instr = read32<E>(Loc); 2173 uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff; 2174 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2175 } 2176 2177 template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) { 2178 uint32_t Instr = read32<E>(Loc); 2179 uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff; 2180 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2181 } 2182 2183 template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) { 2184 uint32_t Instr = read32<E>(Loc); 2185 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff)); 2186 } 2187 2188 template <class ELFT> static bool isMipsR6() { 2189 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf); 2190 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH; 2191 return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6; 2192 } 2193 2194 template <class ELFT> 2195 void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 2196 const endianness E = ELFT::TargetEndianness; 2197 if (Config->MipsN32Abi) { 2198 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 2199 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 2200 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 2201 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 2202 } else { 2203 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 2204 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 2205 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 2206 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 2207 } 2208 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 2209 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 2210 write32<E>(Buf + 24, 0x0320f809); // jalr $25 2211 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 2212 uint64_t Got = In<ELFT>::GotPlt->getVA(); 2213 writeMipsHi16<E>(Buf, Got); 2214 writeMipsLo16<E>(Buf + 4, Got); 2215 writeMipsLo16<E>(Buf + 8, Got); 2216 } 2217 2218 template <class ELFT> 2219 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 2220 uint64_t PltEntryAddr, int32_t Index, 2221 unsigned RelOff) const { 2222 const endianness E = ELFT::TargetEndianness; 2223 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 2224 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 2225 // jr $25 2226 write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008); 2227 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 2228 writeMipsHi16<E>(Buf, GotEntryAddr); 2229 writeMipsLo16<E>(Buf + 4, GotEntryAddr); 2230 writeMipsLo16<E>(Buf + 12, GotEntryAddr); 2231 } 2232 2233 template <class ELFT> 2234 bool MipsTargetInfo<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, 2235 const InputFile *File, 2236 const SymbolBody &S) const { 2237 // Any MIPS PIC code function is invoked with its address in register $t9. 2238 // So if we have a branch instruction from non-PIC code to the PIC one 2239 // we cannot make the jump directly and need to create a small stubs 2240 // to save the target function address. 2241 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 2242 if (Type != R_MIPS_26) 2243 return false; 2244 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 2245 if (!F) 2246 return false; 2247 // If current file has PIC code, LA25 stub is not required. 2248 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 2249 return false; 2250 auto *D = dyn_cast<DefinedRegular>(&S); 2251 // LA25 is required if target file has PIC code 2252 // or target symbol is a PIC symbol. 2253 return D && D->isMipsPIC<ELFT>(); 2254 } 2255 2256 template <class ELFT> 2257 int64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf, 2258 uint32_t Type) const { 2259 const endianness E = ELFT::TargetEndianness; 2260 switch (Type) { 2261 default: 2262 return 0; 2263 case R_MIPS_32: 2264 case R_MIPS_GPREL32: 2265 case R_MIPS_TLS_DTPREL32: 2266 case R_MIPS_TLS_TPREL32: 2267 return SignExtend64<32>(read32<E>(Buf)); 2268 case R_MIPS_26: 2269 // FIXME (simon): If the relocation target symbol is not a PLT entry 2270 // we should use another expression for calculation: 2271 // ((A << 2) | (P & 0xf0000000)) >> 2 2272 return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2); 2273 case R_MIPS_GPREL16: 2274 case R_MIPS_LO16: 2275 case R_MIPS_PCLO16: 2276 case R_MIPS_TLS_DTPREL_HI16: 2277 case R_MIPS_TLS_DTPREL_LO16: 2278 case R_MIPS_TLS_TPREL_HI16: 2279 case R_MIPS_TLS_TPREL_LO16: 2280 return SignExtend64<16>(read32<E>(Buf)); 2281 case R_MIPS_PC16: 2282 return getPcRelocAddend<E, 16, 2>(Buf); 2283 case R_MIPS_PC19_S2: 2284 return getPcRelocAddend<E, 19, 2>(Buf); 2285 case R_MIPS_PC21_S2: 2286 return getPcRelocAddend<E, 21, 2>(Buf); 2287 case R_MIPS_PC26_S2: 2288 return getPcRelocAddend<E, 26, 2>(Buf); 2289 case R_MIPS_PC32: 2290 return getPcRelocAddend<E, 32, 0>(Buf); 2291 } 2292 } 2293 2294 static std::pair<uint32_t, uint64_t> 2295 calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) { 2296 // MIPS N64 ABI packs multiple relocations into the single relocation 2297 // record. In general, all up to three relocations can have arbitrary 2298 // types. In fact, Clang and GCC uses only a few combinations. For now, 2299 // we support two of them. That is allow to pass at least all LLVM 2300 // test suite cases. 2301 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 2302 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 2303 // The first relocation is a 'real' relocation which is calculated 2304 // using the corresponding symbol's value. The second and the third 2305 // relocations used to modify result of the first one: extend it to 2306 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 2307 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 2308 uint32_t Type2 = (Type >> 8) & 0xff; 2309 uint32_t Type3 = (Type >> 16) & 0xff; 2310 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 2311 return std::make_pair(Type, Val); 2312 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 2313 return std::make_pair(Type2, Val); 2314 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 2315 return std::make_pair(Type3, -Val); 2316 error(getErrorLocation(Loc) + "unsupported relocations combination " + 2317 Twine(Type)); 2318 return std::make_pair(Type & 0xff, Val); 2319 } 2320 2321 template <class ELFT> 2322 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 2323 uint64_t Val) const { 2324 const endianness E = ELFT::TargetEndianness; 2325 // Thread pointer and DRP offsets from the start of TLS data area. 2326 // https://www.linux-mips.org/wiki/NPTL 2327 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 2328 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64) 2329 Val -= 0x8000; 2330 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 2331 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64) 2332 Val -= 0x7000; 2333 if (ELFT::Is64Bits || Config->MipsN32Abi) 2334 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 2335 switch (Type) { 2336 case R_MIPS_32: 2337 case R_MIPS_GPREL32: 2338 case R_MIPS_TLS_DTPREL32: 2339 case R_MIPS_TLS_TPREL32: 2340 write32<E>(Loc, Val); 2341 break; 2342 case R_MIPS_64: 2343 case R_MIPS_TLS_DTPREL64: 2344 case R_MIPS_TLS_TPREL64: 2345 write64<E>(Loc, Val); 2346 break; 2347 case R_MIPS_26: 2348 write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff)); 2349 break; 2350 case R_MIPS_GOT16: 2351 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 2352 // is updated addend (not a GOT index). In that case write high 16 bits 2353 // to store a correct addend value. 2354 if (Config->Relocatable) 2355 writeMipsHi16<E>(Loc, Val); 2356 else { 2357 checkInt<16>(Loc, Val, Type); 2358 writeMipsLo16<E>(Loc, Val); 2359 } 2360 break; 2361 case R_MIPS_GOT_DISP: 2362 case R_MIPS_GOT_PAGE: 2363 case R_MIPS_GPREL16: 2364 case R_MIPS_TLS_GD: 2365 case R_MIPS_TLS_LDM: 2366 checkInt<16>(Loc, Val, Type); 2367 // fallthrough 2368 case R_MIPS_CALL16: 2369 case R_MIPS_CALL_LO16: 2370 case R_MIPS_GOT_LO16: 2371 case R_MIPS_GOT_OFST: 2372 case R_MIPS_LO16: 2373 case R_MIPS_PCLO16: 2374 case R_MIPS_TLS_DTPREL_LO16: 2375 case R_MIPS_TLS_GOTTPREL: 2376 case R_MIPS_TLS_TPREL_LO16: 2377 writeMipsLo16<E>(Loc, Val); 2378 break; 2379 case R_MIPS_CALL_HI16: 2380 case R_MIPS_GOT_HI16: 2381 case R_MIPS_HI16: 2382 case R_MIPS_PCHI16: 2383 case R_MIPS_TLS_DTPREL_HI16: 2384 case R_MIPS_TLS_TPREL_HI16: 2385 writeMipsHi16<E>(Loc, Val); 2386 break; 2387 case R_MIPS_HIGHER: 2388 writeMipsHigher<E>(Loc, Val); 2389 break; 2390 case R_MIPS_HIGHEST: 2391 writeMipsHighest<E>(Loc, Val); 2392 break; 2393 case R_MIPS_JALR: 2394 // Ignore this optimization relocation for now 2395 break; 2396 case R_MIPS_PC16: 2397 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val); 2398 break; 2399 case R_MIPS_PC19_S2: 2400 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val); 2401 break; 2402 case R_MIPS_PC21_S2: 2403 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val); 2404 break; 2405 case R_MIPS_PC26_S2: 2406 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val); 2407 break; 2408 case R_MIPS_PC32: 2409 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val); 2410 break; 2411 default: 2412 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 2413 } 2414 } 2415 2416 template <class ELFT> 2417 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const { 2418 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST; 2419 } 2420 } 2421 } 2422