1 //===- Target.cpp ---------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Machine-specific things, such as applying relocations, creation of 11 // GOT or PLT entries, etc., are handled in this file. 12 // 13 // Refer the ELF spec for the single letter variables, S, A or P, used 14 // in this file. 15 // 16 // Some functions defined in this file has "relaxTls" as part of their names. 17 // They do peephole optimization for TLS variables by rewriting instructions. 18 // They are not part of the ABI but optional optimization, so you can skip 19 // them if you are not interested in how TLS variables are optimized. 20 // See the following paper for the details. 21 // 22 // Ulrich Drepper, ELF Handling For Thread-Local Storage 23 // http://www.akkadia.org/drepper/tls.pdf 24 // 25 //===----------------------------------------------------------------------===// 26 27 #include "Target.h" 28 #include "Error.h" 29 #include "InputFiles.h" 30 #include "Memory.h" 31 #include "OutputSections.h" 32 #include "SymbolTable.h" 33 #include "Symbols.h" 34 #include "SyntheticSections.h" 35 #include "Thunks.h" 36 #include "Writer.h" 37 #include "llvm/ADT/ArrayRef.h" 38 #include "llvm/Object/ELF.h" 39 #include "llvm/Support/ELF.h" 40 #include "llvm/Support/Endian.h" 41 42 using namespace llvm; 43 using namespace llvm::object; 44 using namespace llvm::support::endian; 45 using namespace llvm::ELF; 46 47 std::string lld::toString(uint32_t Type) { 48 StringRef S = getELFRelocationTypeName(elf::Config->EMachine, Type); 49 if (S == "Unknown") 50 return ("Unknown (" + Twine(Type) + ")").str(); 51 return S; 52 } 53 54 namespace lld { 55 namespace elf { 56 57 TargetInfo *Target; 58 59 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); } 60 static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); } 61 62 template <class ELFT> static std::string getErrorLoc(uint8_t *Loc) { 63 for (InputSectionData *D : Symtab<ELFT>::X->Sections) { 64 auto *IS = dyn_cast_or_null<InputSection<ELFT>>(D); 65 if (!IS || !IS->OutSec) 66 continue; 67 68 uint8_t *ISLoc = cast<OutputSection<ELFT>>(IS->OutSec)->Loc + IS->OutSecOff; 69 if (ISLoc <= Loc && Loc < ISLoc + IS->getSize()) 70 return IS->getLocation(Loc - ISLoc) + ": "; 71 } 72 return ""; 73 } 74 75 static std::string getErrorLocation(uint8_t *Loc) { 76 switch (Config->EKind) { 77 case ELF32LEKind: 78 return getErrorLoc<ELF32LE>(Loc); 79 case ELF32BEKind: 80 return getErrorLoc<ELF32BE>(Loc); 81 case ELF64LEKind: 82 return getErrorLoc<ELF64LE>(Loc); 83 case ELF64BEKind: 84 return getErrorLoc<ELF64BE>(Loc); 85 default: 86 llvm_unreachable("unknown ELF type"); 87 } 88 } 89 90 template <unsigned N> 91 static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) { 92 if (!isInt<N>(V)) 93 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 94 " out of range"); 95 } 96 97 template <unsigned N> 98 static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 99 if (!isUInt<N>(V)) 100 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 101 " out of range"); 102 } 103 104 template <unsigned N> 105 static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 106 if (!isInt<N>(V) && !isUInt<N>(V)) 107 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 108 " out of range"); 109 } 110 111 template <unsigned N> 112 static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) { 113 if ((V & (N - 1)) != 0) 114 error(getErrorLocation(Loc) + "improper alignment for relocation " + 115 toString(Type)); 116 } 117 118 namespace { 119 class X86TargetInfo final : public TargetInfo { 120 public: 121 X86TargetInfo(); 122 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 123 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 124 void writeGotPltHeader(uint8_t *Buf) const override; 125 uint32_t getDynRel(uint32_t Type) const override; 126 bool isTlsLocalDynamicRel(uint32_t Type) const override; 127 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 128 bool isTlsInitialExecRel(uint32_t Type) const override; 129 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 130 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 131 void writePltHeader(uint8_t *Buf) const override; 132 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 133 int32_t Index, unsigned RelOff) const override; 134 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 135 136 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 137 RelExpr Expr) const override; 138 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 139 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 140 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 141 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 142 }; 143 144 template <class ELFT> class X86_64TargetInfo final : public TargetInfo { 145 public: 146 X86_64TargetInfo(); 147 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 148 bool isPicRel(uint32_t Type) const override; 149 bool isTlsLocalDynamicRel(uint32_t Type) const override; 150 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 151 bool isTlsInitialExecRel(uint32_t Type) const override; 152 void writeGotPltHeader(uint8_t *Buf) const override; 153 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 154 void writePltHeader(uint8_t *Buf) const override; 155 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 156 int32_t Index, unsigned RelOff) const override; 157 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 158 159 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 160 RelExpr Expr) const override; 161 void relaxGot(uint8_t *Loc, uint64_t Val) const override; 162 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 163 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 164 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 165 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 166 167 private: 168 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op, 169 uint8_t ModRm) const; 170 }; 171 172 class PPCTargetInfo final : public TargetInfo { 173 public: 174 PPCTargetInfo(); 175 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 176 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 177 }; 178 179 class PPC64TargetInfo final : public TargetInfo { 180 public: 181 PPC64TargetInfo(); 182 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 183 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 184 int32_t Index, unsigned RelOff) const override; 185 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 186 }; 187 188 class AArch64TargetInfo final : public TargetInfo { 189 public: 190 AArch64TargetInfo(); 191 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 192 bool isPicRel(uint32_t Type) const override; 193 bool isTlsInitialExecRel(uint32_t Type) const override; 194 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 195 void writePltHeader(uint8_t *Buf) const override; 196 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 197 int32_t Index, unsigned RelOff) const override; 198 bool usesOnlyLowPageBits(uint32_t Type) const override; 199 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 200 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 201 RelExpr Expr) const override; 202 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 203 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 204 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 205 }; 206 207 class AMDGPUTargetInfo final : public TargetInfo { 208 public: 209 AMDGPUTargetInfo(); 210 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 211 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 212 }; 213 214 class ARMTargetInfo final : public TargetInfo { 215 public: 216 ARMTargetInfo(); 217 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 218 bool isPicRel(uint32_t Type) const override; 219 uint32_t getDynRel(uint32_t Type) const override; 220 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 221 bool isTlsLocalDynamicRel(uint32_t Type) const override; 222 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 223 bool isTlsInitialExecRel(uint32_t Type) const override; 224 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 225 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 226 void writePltHeader(uint8_t *Buf) const override; 227 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 228 int32_t Index, unsigned RelOff) const override; 229 void addPltSymbols(InputSectionData *IS, uint64_t Off) const override; 230 void addPltHeaderSymbols(InputSectionData *ISD) const override; 231 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile *File, 232 const SymbolBody &S) const override; 233 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 234 }; 235 236 template <class ELFT> class MipsTargetInfo final : public TargetInfo { 237 public: 238 MipsTargetInfo(); 239 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 240 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 241 bool isPicRel(uint32_t Type) const override; 242 uint32_t getDynRel(uint32_t Type) const override; 243 bool isTlsLocalDynamicRel(uint32_t Type) const override; 244 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 245 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 246 void writePltHeader(uint8_t *Buf) const override; 247 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 248 int32_t Index, unsigned RelOff) const override; 249 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile *File, 250 const SymbolBody &S) const override; 251 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 252 bool usesOnlyLowPageBits(uint32_t Type) const override; 253 }; 254 } // anonymous namespace 255 256 TargetInfo *createTarget() { 257 switch (Config->EMachine) { 258 case EM_386: 259 case EM_IAMCU: 260 return make<X86TargetInfo>(); 261 case EM_AARCH64: 262 return make<AArch64TargetInfo>(); 263 case EM_AMDGPU: 264 return make<AMDGPUTargetInfo>(); 265 case EM_ARM: 266 return make<ARMTargetInfo>(); 267 case EM_MIPS: 268 switch (Config->EKind) { 269 case ELF32LEKind: 270 return make<MipsTargetInfo<ELF32LE>>(); 271 case ELF32BEKind: 272 return make<MipsTargetInfo<ELF32BE>>(); 273 case ELF64LEKind: 274 return make<MipsTargetInfo<ELF64LE>>(); 275 case ELF64BEKind: 276 return make<MipsTargetInfo<ELF64BE>>(); 277 default: 278 fatal("unsupported MIPS target"); 279 } 280 case EM_PPC: 281 return make<PPCTargetInfo>(); 282 case EM_PPC64: 283 return make<PPC64TargetInfo>(); 284 case EM_X86_64: 285 if (Config->EKind == ELF32LEKind) 286 return make<X86_64TargetInfo<ELF32LE>>(); 287 return make<X86_64TargetInfo<ELF64LE>>(); 288 } 289 fatal("unknown target machine"); 290 } 291 292 TargetInfo::~TargetInfo() {} 293 294 uint64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, 295 uint32_t Type) const { 296 return 0; 297 } 298 299 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; } 300 301 RelExpr TargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType, 302 const InputFile *File, 303 const SymbolBody &S) const { 304 return Expr; 305 } 306 307 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; } 308 309 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; } 310 311 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { return false; } 312 313 void TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 314 writeGotPlt(Buf, S); 315 } 316 317 RelExpr TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 318 RelExpr Expr) const { 319 return Expr; 320 } 321 322 void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const { 323 llvm_unreachable("Should not have claimed to be relaxable"); 324 } 325 326 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 327 uint64_t Val) const { 328 llvm_unreachable("Should not have claimed to be relaxable"); 329 } 330 331 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 332 uint64_t Val) const { 333 llvm_unreachable("Should not have claimed to be relaxable"); 334 } 335 336 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 337 uint64_t Val) const { 338 llvm_unreachable("Should not have claimed to be relaxable"); 339 } 340 341 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 342 uint64_t Val) const { 343 llvm_unreachable("Should not have claimed to be relaxable"); 344 } 345 346 X86TargetInfo::X86TargetInfo() { 347 CopyRel = R_386_COPY; 348 GotRel = R_386_GLOB_DAT; 349 PltRel = R_386_JUMP_SLOT; 350 IRelativeRel = R_386_IRELATIVE; 351 RelativeRel = R_386_RELATIVE; 352 TlsGotRel = R_386_TLS_TPOFF; 353 TlsModuleIndexRel = R_386_TLS_DTPMOD32; 354 TlsOffsetRel = R_386_TLS_DTPOFF32; 355 GotEntrySize = 4; 356 GotPltEntrySize = 4; 357 PltEntrySize = 16; 358 PltHeaderSize = 16; 359 TlsGdRelaxSkip = 2; 360 } 361 362 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 363 switch (Type) { 364 case R_386_8: 365 case R_386_16: 366 case R_386_32: 367 case R_386_TLS_LDO_32: 368 return R_ABS; 369 case R_386_TLS_GD: 370 return R_TLSGD; 371 case R_386_TLS_LDM: 372 return R_TLSLD; 373 case R_386_PLT32: 374 return R_PLT_PC; 375 case R_386_PC8: 376 case R_386_PC16: 377 case R_386_PC32: 378 return R_PC; 379 case R_386_GOTPC: 380 return R_GOTONLY_PC_FROM_END; 381 case R_386_TLS_IE: 382 return R_GOT; 383 case R_386_GOT32: 384 case R_386_GOT32X: 385 case R_386_TLS_GOTIE: 386 return R_GOT_FROM_END; 387 case R_386_GOTOFF: 388 return R_GOTREL_FROM_END; 389 case R_386_TLS_LE: 390 return R_TLS; 391 case R_386_TLS_LE_32: 392 return R_NEG_TLS; 393 case R_386_NONE: 394 return R_HINT; 395 default: 396 error("unknown relocation type: " + toString(Type)); 397 return R_HINT; 398 } 399 } 400 401 RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 402 RelExpr Expr) const { 403 switch (Expr) { 404 default: 405 return Expr; 406 case R_RELAX_TLS_GD_TO_IE: 407 return R_RELAX_TLS_GD_TO_IE_END; 408 case R_RELAX_TLS_GD_TO_LE: 409 return R_RELAX_TLS_GD_TO_LE_NEG; 410 } 411 } 412 413 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const { 414 write32le(Buf, In<ELF32LE>::Dynamic->getVA()); 415 } 416 417 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const { 418 // Entries in .got.plt initially points back to the corresponding 419 // PLT entries with a fixed offset to skip the first instruction. 420 write32le(Buf, S.getPltVA<ELF32LE>() + 6); 421 } 422 423 void X86TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 424 // An x86 entry is the address of the ifunc resolver function. 425 write32le(Buf, S.getVA<ELF32LE>()); 426 } 427 428 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const { 429 if (Type == R_386_TLS_LE) 430 return R_386_TLS_TPOFF; 431 if (Type == R_386_TLS_LE_32) 432 return R_386_TLS_TPOFF32; 433 return Type; 434 } 435 436 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 437 return Type == R_386_TLS_GD; 438 } 439 440 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 441 return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM; 442 } 443 444 bool X86TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 445 return Type == R_386_TLS_IE || Type == R_386_TLS_GOTIE; 446 } 447 448 void X86TargetInfo::writePltHeader(uint8_t *Buf) const { 449 // Executable files and shared object files have 450 // separate procedure linkage tables. 451 if (Config->Pic) { 452 const uint8_t V[] = { 453 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl 4(%ebx) 454 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *8(%ebx) 455 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 456 }; 457 memcpy(Buf, V, sizeof(V)); 458 return; 459 } 460 461 const uint8_t PltData[] = { 462 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOT+4) 463 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOT+8) 464 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 465 }; 466 memcpy(Buf, PltData, sizeof(PltData)); 467 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 468 write32le(Buf + 2, Got + 4); 469 write32le(Buf + 8, Got + 8); 470 } 471 472 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 473 uint64_t PltEntryAddr, int32_t Index, 474 unsigned RelOff) const { 475 const uint8_t Inst[] = { 476 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx) 477 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset 478 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC 479 }; 480 memcpy(Buf, Inst, sizeof(Inst)); 481 482 // jmp *foo@GOT(%ebx) or jmp *foo_in_GOT 483 Buf[1] = Config->Pic ? 0xa3 : 0x25; 484 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 485 write32le(Buf + 2, Config->Shared ? GotEntryAddr - Got : GotEntryAddr); 486 write32le(Buf + 7, RelOff); 487 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 488 } 489 490 uint64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf, 491 uint32_t Type) const { 492 switch (Type) { 493 default: 494 return 0; 495 case R_386_8: 496 case R_386_PC8: 497 return *Buf; 498 case R_386_16: 499 case R_386_PC16: 500 return read16le(Buf); 501 case R_386_32: 502 case R_386_GOT32: 503 case R_386_GOT32X: 504 case R_386_GOTOFF: 505 case R_386_GOTPC: 506 case R_386_PC32: 507 case R_386_PLT32: 508 case R_386_TLS_LE: 509 return read32le(Buf); 510 } 511 } 512 513 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 514 uint64_t Val) const { 515 checkInt<32>(Loc, Val, Type); 516 517 // R_386_{PC,}{8,16} are not part of the i386 psABI, but they are 518 // being used for some 16-bit programs such as boot loaders, so 519 // we want to support them. 520 if (Type == R_386_8 || Type == R_386_PC8) 521 *Loc = Val; 522 else if (Type == R_386_16 || Type == R_386_PC16) 523 write16le(Loc, Val); 524 else 525 write32le(Loc, Val); 526 } 527 528 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 529 uint64_t Val) const { 530 // Convert 531 // leal x@tlsgd(, %ebx, 1), 532 // call __tls_get_addr@plt 533 // to 534 // movl %gs:0,%eax 535 // subl $x@ntpoff,%eax 536 const uint8_t Inst[] = { 537 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 538 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax 539 }; 540 memcpy(Loc - 3, Inst, sizeof(Inst)); 541 relocateOne(Loc + 5, R_386_32, Val); 542 } 543 544 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 545 uint64_t Val) const { 546 // Convert 547 // leal x@tlsgd(, %ebx, 1), 548 // call __tls_get_addr@plt 549 // to 550 // movl %gs:0, %eax 551 // addl x@gotntpoff(%ebx), %eax 552 const uint8_t Inst[] = { 553 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 554 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax 555 }; 556 memcpy(Loc - 3, Inst, sizeof(Inst)); 557 relocateOne(Loc + 5, R_386_32, Val); 558 } 559 560 // In some conditions, relocations can be optimized to avoid using GOT. 561 // This function does that for Initial Exec to Local Exec case. 562 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 563 uint64_t Val) const { 564 // Ulrich's document section 6.2 says that @gotntpoff can 565 // be used with MOVL or ADDL instructions. 566 // @indntpoff is similar to @gotntpoff, but for use in 567 // position dependent code. 568 uint8_t Reg = (Loc[-1] >> 3) & 7; 569 570 if (Type == R_386_TLS_IE) { 571 if (Loc[-1] == 0xa1) { 572 // "movl foo@indntpoff,%eax" -> "movl $foo,%eax" 573 // This case is different from the generic case below because 574 // this is a 5 byte instruction while below is 6 bytes. 575 Loc[-1] = 0xb8; 576 } else if (Loc[-2] == 0x8b) { 577 // "movl foo@indntpoff,%reg" -> "movl $foo,%reg" 578 Loc[-2] = 0xc7; 579 Loc[-1] = 0xc0 | Reg; 580 } else { 581 // "addl foo@indntpoff,%reg" -> "addl $foo,%reg" 582 Loc[-2] = 0x81; 583 Loc[-1] = 0xc0 | Reg; 584 } 585 } else { 586 assert(Type == R_386_TLS_GOTIE); 587 if (Loc[-2] == 0x8b) { 588 // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg" 589 Loc[-2] = 0xc7; 590 Loc[-1] = 0xc0 | Reg; 591 } else { 592 // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg" 593 Loc[-2] = 0x8d; 594 Loc[-1] = 0x80 | (Reg << 3) | Reg; 595 } 596 } 597 relocateOne(Loc, R_386_TLS_LE, Val); 598 } 599 600 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 601 uint64_t Val) const { 602 if (Type == R_386_TLS_LDO_32) { 603 relocateOne(Loc, R_386_TLS_LE, Val); 604 return; 605 } 606 607 // Convert 608 // leal foo(%reg),%eax 609 // call ___tls_get_addr 610 // to 611 // movl %gs:0,%eax 612 // nop 613 // leal 0(%esi,1),%esi 614 const uint8_t Inst[] = { 615 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax 616 0x90, // nop 617 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi 618 }; 619 memcpy(Loc - 2, Inst, sizeof(Inst)); 620 } 621 622 template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() { 623 CopyRel = R_X86_64_COPY; 624 GotRel = R_X86_64_GLOB_DAT; 625 PltRel = R_X86_64_JUMP_SLOT; 626 RelativeRel = R_X86_64_RELATIVE; 627 IRelativeRel = R_X86_64_IRELATIVE; 628 TlsGotRel = R_X86_64_TPOFF64; 629 TlsModuleIndexRel = R_X86_64_DTPMOD64; 630 TlsOffsetRel = R_X86_64_DTPOFF64; 631 GotEntrySize = 8; 632 GotPltEntrySize = 8; 633 PltEntrySize = 16; 634 PltHeaderSize = 16; 635 TlsGdRelaxSkip = 2; 636 // Align to the large page size (known as a superpage or huge page). 637 // FreeBSD automatically promotes large, superpage-aligned allocations. 638 DefaultImageBase = 0x200000; 639 } 640 641 template <class ELFT> 642 RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type, 643 const SymbolBody &S) const { 644 switch (Type) { 645 case R_X86_64_8: 646 case R_X86_64_32: 647 case R_X86_64_32S: 648 case R_X86_64_64: 649 case R_X86_64_DTPOFF32: 650 case R_X86_64_DTPOFF64: 651 return R_ABS; 652 case R_X86_64_TPOFF32: 653 return R_TLS; 654 case R_X86_64_TLSLD: 655 return R_TLSLD_PC; 656 case R_X86_64_TLSGD: 657 return R_TLSGD_PC; 658 case R_X86_64_SIZE32: 659 case R_X86_64_SIZE64: 660 return R_SIZE; 661 case R_X86_64_PLT32: 662 return R_PLT_PC; 663 case R_X86_64_PC32: 664 case R_X86_64_PC64: 665 return R_PC; 666 case R_X86_64_GOT32: 667 case R_X86_64_GOT64: 668 return R_GOT_FROM_END; 669 case R_X86_64_GOTPCREL: 670 case R_X86_64_GOTPCRELX: 671 case R_X86_64_REX_GOTPCRELX: 672 case R_X86_64_GOTTPOFF: 673 return R_GOT_PC; 674 case R_X86_64_NONE: 675 return R_HINT; 676 default: 677 error("unknown relocation type: " + toString(Type)); 678 return R_HINT; 679 } 680 } 681 682 template <class ELFT> 683 void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const { 684 // The first entry holds the value of _DYNAMIC. It is not clear why that is 685 // required, but it is documented in the psabi and the glibc dynamic linker 686 // seems to use it (note that this is relevant for linking ld.so, not any 687 // other program). 688 write64le(Buf, In<ELFT>::Dynamic->getVA()); 689 } 690 691 template <class ELFT> 692 void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, 693 const SymbolBody &S) const { 694 // See comments in X86TargetInfo::writeGotPlt. 695 write32le(Buf, S.getPltVA<ELFT>() + 6); 696 } 697 698 template <class ELFT> 699 void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 700 const uint8_t PltData[] = { 701 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOT+8(%rip) 702 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOT+16(%rip) 703 0x0f, 0x1f, 0x40, 0x00 // nopl 0x0(rax) 704 }; 705 memcpy(Buf, PltData, sizeof(PltData)); 706 uint64_t Got = In<ELFT>::GotPlt->getVA(); 707 uint64_t Plt = In<ELFT>::Plt->getVA(); 708 write32le(Buf + 2, Got - Plt + 2); // GOT+8 709 write32le(Buf + 8, Got - Plt + 4); // GOT+16 710 } 711 712 template <class ELFT> 713 void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 714 uint64_t PltEntryAddr, int32_t Index, 715 unsigned RelOff) const { 716 const uint8_t Inst[] = { 717 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip) 718 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index> 719 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0] 720 }; 721 memcpy(Buf, Inst, sizeof(Inst)); 722 723 write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6); 724 write32le(Buf + 7, Index); 725 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 726 } 727 728 template <class ELFT> 729 bool X86_64TargetInfo<ELFT>::isPicRel(uint32_t Type) const { 730 return Type != R_X86_64_PC32 && Type != R_X86_64_32; 731 } 732 733 template <class ELFT> 734 bool X86_64TargetInfo<ELFT>::isTlsInitialExecRel(uint32_t Type) const { 735 return Type == R_X86_64_GOTTPOFF; 736 } 737 738 template <class ELFT> 739 bool X86_64TargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 740 return Type == R_X86_64_TLSGD; 741 } 742 743 template <class ELFT> 744 bool X86_64TargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 745 return Type == R_X86_64_DTPOFF32 || Type == R_X86_64_DTPOFF64 || 746 Type == R_X86_64_TLSLD; 747 } 748 749 template <class ELFT> 750 void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 751 uint64_t Val) const { 752 // Convert 753 // .byte 0x66 754 // leaq x@tlsgd(%rip), %rdi 755 // .word 0x6666 756 // rex64 757 // call __tls_get_addr@plt 758 // to 759 // mov %fs:0x0,%rax 760 // lea x@tpoff,%rax 761 const uint8_t Inst[] = { 762 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 763 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax 764 }; 765 memcpy(Loc - 4, Inst, sizeof(Inst)); 766 // The original code used a pc relative relocation and so we have to 767 // compensate for the -4 in had in the addend. 768 relocateOne(Loc + 8, R_X86_64_TPOFF32, Val + 4); 769 } 770 771 template <class ELFT> 772 void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 773 uint64_t Val) const { 774 // Convert 775 // .byte 0x66 776 // leaq x@tlsgd(%rip), %rdi 777 // .word 0x6666 778 // rex64 779 // call __tls_get_addr@plt 780 // to 781 // mov %fs:0x0,%rax 782 // addq x@tpoff,%rax 783 const uint8_t Inst[] = { 784 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 785 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax 786 }; 787 memcpy(Loc - 4, Inst, sizeof(Inst)); 788 // Both code sequences are PC relatives, but since we are moving the constant 789 // forward by 8 bytes we have to subtract the value by 8. 790 relocateOne(Loc + 8, R_X86_64_PC32, Val - 8); 791 } 792 793 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to 794 // R_X86_64_TPOFF32 so that it does not use GOT. 795 template <class ELFT> 796 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 797 uint64_t Val) const { 798 uint8_t *Inst = Loc - 3; 799 uint8_t Reg = Loc[-1] >> 3; 800 uint8_t *RegSlot = Loc - 1; 801 802 // Note that ADD with RSP or R12 is converted to ADD instead of LEA 803 // because LEA with these registers needs 4 bytes to encode and thus 804 // wouldn't fit the space. 805 806 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) { 807 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp" 808 memcpy(Inst, "\x48\x81\xc4", 3); 809 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) { 810 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12" 811 memcpy(Inst, "\x49\x81\xc4", 3); 812 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) { 813 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]" 814 memcpy(Inst, "\x4d\x8d", 2); 815 *RegSlot = 0x80 | (Reg << 3) | Reg; 816 } else if (memcmp(Inst, "\x48\x03", 2) == 0) { 817 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg" 818 memcpy(Inst, "\x48\x8d", 2); 819 *RegSlot = 0x80 | (Reg << 3) | Reg; 820 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) { 821 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]" 822 memcpy(Inst, "\x49\xc7", 2); 823 *RegSlot = 0xc0 | Reg; 824 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) { 825 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg" 826 memcpy(Inst, "\x48\xc7", 2); 827 *RegSlot = 0xc0 | Reg; 828 } else { 829 error(getErrorLocation(Loc - 3) + 830 "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only"); 831 } 832 833 // The original code used a PC relative relocation. 834 // Need to compensate for the -4 it had in the addend. 835 relocateOne(Loc, R_X86_64_TPOFF32, Val + 4); 836 } 837 838 template <class ELFT> 839 void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 840 uint64_t Val) const { 841 // Convert 842 // leaq bar@tlsld(%rip), %rdi 843 // callq __tls_get_addr@PLT 844 // leaq bar@dtpoff(%rax), %rcx 845 // to 846 // .word 0x6666 847 // .byte 0x66 848 // mov %fs:0,%rax 849 // leaq bar@tpoff(%rax), %rcx 850 if (Type == R_X86_64_DTPOFF64) { 851 write64le(Loc, Val); 852 return; 853 } 854 if (Type == R_X86_64_DTPOFF32) { 855 relocateOne(Loc, R_X86_64_TPOFF32, Val); 856 return; 857 } 858 859 const uint8_t Inst[] = { 860 0x66, 0x66, // .word 0x6666 861 0x66, // .byte 0x66 862 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax 863 }; 864 memcpy(Loc - 3, Inst, sizeof(Inst)); 865 } 866 867 template <class ELFT> 868 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 869 uint64_t Val) const { 870 switch (Type) { 871 case R_X86_64_8: 872 checkUInt<8>(Loc, Val, Type); 873 *Loc = Val; 874 break; 875 case R_X86_64_32: 876 checkUInt<32>(Loc, Val, Type); 877 write32le(Loc, Val); 878 break; 879 case R_X86_64_32S: 880 case R_X86_64_TPOFF32: 881 case R_X86_64_GOT32: 882 case R_X86_64_GOTPCREL: 883 case R_X86_64_GOTPCRELX: 884 case R_X86_64_REX_GOTPCRELX: 885 case R_X86_64_PC32: 886 case R_X86_64_GOTTPOFF: 887 case R_X86_64_PLT32: 888 case R_X86_64_TLSGD: 889 case R_X86_64_TLSLD: 890 case R_X86_64_DTPOFF32: 891 case R_X86_64_SIZE32: 892 checkInt<32>(Loc, Val, Type); 893 write32le(Loc, Val); 894 break; 895 case R_X86_64_64: 896 case R_X86_64_DTPOFF64: 897 case R_X86_64_GLOB_DAT: 898 case R_X86_64_PC64: 899 case R_X86_64_SIZE64: 900 case R_X86_64_GOT64: 901 write64le(Loc, Val); 902 break; 903 default: 904 llvm_unreachable("unexpected relocation"); 905 } 906 } 907 908 template <class ELFT> 909 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type, 910 const uint8_t *Data, 911 RelExpr RelExpr) const { 912 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX) 913 return RelExpr; 914 const uint8_t Op = Data[-2]; 915 const uint8_t ModRm = Data[-1]; 916 // FIXME: When PIC is disabled and foo is defined locally in the 917 // lower 32 bit address space, memory operand in mov can be converted into 918 // immediate operand. Otherwise, mov must be changed to lea. We support only 919 // latter relaxation at this moment. 920 if (Op == 0x8b) 921 return R_RELAX_GOT_PC; 922 // Relax call and jmp. 923 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25)) 924 return R_RELAX_GOT_PC; 925 926 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor. 927 // If PIC then no relaxation is available. 928 // We also don't relax test/binop instructions without REX byte, 929 // they are 32bit operations and not common to have. 930 assert(Type == R_X86_64_REX_GOTPCRELX); 931 return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC; 932 } 933 934 // A subset of relaxations can only be applied for no-PIC. This method 935 // handles such relaxations. Instructions encoding information was taken from: 936 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2" 937 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/ 938 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf) 939 template <class ELFT> 940 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val, 941 uint8_t Op, uint8_t ModRm) const { 942 const uint8_t Rex = Loc[-3]; 943 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg". 944 if (Op == 0x85) { 945 // See "TEST-Logical Compare" (4-428 Vol. 2B), 946 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension). 947 948 // ModR/M byte has form XX YYY ZZZ, where 949 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1). 950 // XX has different meanings: 951 // 00: The operand's memory address is in reg1. 952 // 01: The operand's memory address is reg1 + a byte-sized displacement. 953 // 10: The operand's memory address is reg1 + a word-sized displacement. 954 // 11: The operand is reg1 itself. 955 // If an instruction requires only one operand, the unused reg2 field 956 // holds extra opcode bits rather than a register code 957 // 0xC0 == 11 000 000 binary. 958 // 0x38 == 00 111 000 binary. 959 // We transfer reg2 to reg1 here as operand. 960 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3). 961 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte. 962 963 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32 964 // See "TEST-Logical Compare" (4-428 Vol. 2B). 965 Loc[-2] = 0xf7; 966 967 // Move R bit to the B bit in REX byte. 968 // REX byte is encoded as 0100WRXB, where 969 // 0100 is 4bit fixed pattern. 970 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the 971 // default operand size is used (which is 32-bit for most but not all 972 // instructions). 973 // REX.R This 1-bit value is an extension to the MODRM.reg field. 974 // REX.X This 1-bit value is an extension to the SIB.index field. 975 // REX.B This 1-bit value is an extension to the MODRM.rm field or the 976 // SIB.base field. 977 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A). 978 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 979 relocateOne(Loc, R_X86_64_PC32, Val); 980 return; 981 } 982 983 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub 984 // or xor operations. 985 986 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg". 987 // Logic is close to one for test instruction above, but we also 988 // write opcode extension here, see below for details. 989 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte. 990 991 // Primary opcode is 0x81, opcode extension is one of: 992 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB, 993 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP. 994 // This value was wrote to MODRM.reg in a line above. 995 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15), 996 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for 997 // descriptions about each operation. 998 Loc[-2] = 0x81; 999 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 1000 relocateOne(Loc, R_X86_64_PC32, Val); 1001 } 1002 1003 template <class ELFT> 1004 void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const { 1005 const uint8_t Op = Loc[-2]; 1006 const uint8_t ModRm = Loc[-1]; 1007 1008 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg". 1009 if (Op == 0x8b) { 1010 Loc[-2] = 0x8d; 1011 relocateOne(Loc, R_X86_64_PC32, Val); 1012 return; 1013 } 1014 1015 if (Op != 0xff) { 1016 // We are relaxing a rip relative to an absolute, so compensate 1017 // for the old -4 addend. 1018 assert(!Config->Pic); 1019 relaxGotNoPic(Loc, Val + 4, Op, ModRm); 1020 return; 1021 } 1022 1023 // Convert call/jmp instructions. 1024 if (ModRm == 0x15) { 1025 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo". 1026 // Instead we convert to "addr32 call foo" where addr32 is an instruction 1027 // prefix. That makes result expression to be a single instruction. 1028 Loc[-2] = 0x67; // addr32 prefix 1029 Loc[-1] = 0xe8; // call 1030 relocateOne(Loc, R_X86_64_PC32, Val); 1031 return; 1032 } 1033 1034 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop". 1035 // jmp doesn't return, so it is fine to use nop here, it is just a stub. 1036 assert(ModRm == 0x25); 1037 Loc[-2] = 0xe9; // jmp 1038 Loc[3] = 0x90; // nop 1039 relocateOne(Loc - 1, R_X86_64_PC32, Val + 1); 1040 } 1041 1042 // Relocation masks following the #lo(value), #hi(value), #ha(value), 1043 // #higher(value), #highera(value), #highest(value), and #highesta(value) 1044 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 1045 // document. 1046 static uint16_t applyPPCLo(uint64_t V) { return V; } 1047 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; } 1048 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; } 1049 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; } 1050 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; } 1051 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; } 1052 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; } 1053 1054 PPCTargetInfo::PPCTargetInfo() {} 1055 1056 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1057 uint64_t Val) const { 1058 switch (Type) { 1059 case R_PPC_ADDR16_HA: 1060 write16be(Loc, applyPPCHa(Val)); 1061 break; 1062 case R_PPC_ADDR16_LO: 1063 write16be(Loc, applyPPCLo(Val)); 1064 break; 1065 case R_PPC_ADDR32: 1066 case R_PPC_REL32: 1067 write32be(Loc, Val); 1068 break; 1069 case R_PPC_REL24: 1070 or32be(Loc, Val & 0x3FFFFFC); 1071 break; 1072 default: 1073 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1074 } 1075 } 1076 1077 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1078 switch (Type) { 1079 case R_PPC_REL24: 1080 case R_PPC_REL32: 1081 return R_PC; 1082 default: 1083 return R_ABS; 1084 } 1085 } 1086 1087 PPC64TargetInfo::PPC64TargetInfo() { 1088 PltRel = GotRel = R_PPC64_GLOB_DAT; 1089 RelativeRel = R_PPC64_RELATIVE; 1090 GotEntrySize = 8; 1091 GotPltEntrySize = 8; 1092 PltEntrySize = 32; 1093 PltHeaderSize = 0; 1094 1095 // We need 64K pages (at least under glibc/Linux, the loader won't 1096 // set different permissions on a finer granularity than that). 1097 DefaultMaxPageSize = 65536; 1098 1099 // The PPC64 ELF ABI v1 spec, says: 1100 // 1101 // It is normally desirable to put segments with different characteristics 1102 // in separate 256 Mbyte portions of the address space, to give the 1103 // operating system full paging flexibility in the 64-bit address space. 1104 // 1105 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 1106 // use 0x10000000 as the starting address. 1107 DefaultImageBase = 0x10000000; 1108 } 1109 1110 static uint64_t PPC64TocOffset = 0x8000; 1111 1112 uint64_t getPPC64TocBase() { 1113 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 1114 // TOC starts where the first of these sections starts. We always create a 1115 // .got when we see a relocation that uses it, so for us the start is always 1116 // the .got. 1117 uint64_t TocVA = In<ELF64BE>::Got->getVA(); 1118 1119 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 1120 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 1121 // code (crt1.o) assumes that you can get from the TOC base to the 1122 // start of the .toc section with only a single (signed) 16-bit relocation. 1123 return TocVA + PPC64TocOffset; 1124 } 1125 1126 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1127 switch (Type) { 1128 default: 1129 return R_ABS; 1130 case R_PPC64_TOC16: 1131 case R_PPC64_TOC16_DS: 1132 case R_PPC64_TOC16_HA: 1133 case R_PPC64_TOC16_HI: 1134 case R_PPC64_TOC16_LO: 1135 case R_PPC64_TOC16_LO_DS: 1136 return R_GOTREL; 1137 case R_PPC64_TOC: 1138 return R_PPC_TOC; 1139 case R_PPC64_REL24: 1140 return R_PPC_PLT_OPD; 1141 } 1142 } 1143 1144 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1145 uint64_t PltEntryAddr, int32_t Index, 1146 unsigned RelOff) const { 1147 uint64_t Off = GotEntryAddr - getPPC64TocBase(); 1148 1149 // FIXME: What we should do, in theory, is get the offset of the function 1150 // descriptor in the .opd section, and use that as the offset from %r2 (the 1151 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will 1152 // be a pointer to the function descriptor in the .opd section. Using 1153 // this scheme is simpler, but requires an extra indirection per PLT dispatch. 1154 1155 write32be(Buf, 0xf8410028); // std %r2, 40(%r1) 1156 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha 1157 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11) 1158 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12) 1159 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11 1160 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12) 1161 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12) 1162 write32be(Buf + 28, 0x4e800420); // bctr 1163 } 1164 1165 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) { 1166 uint64_t V = Val - PPC64TocOffset; 1167 switch (Type) { 1168 case R_PPC64_TOC16: 1169 return {R_PPC64_ADDR16, V}; 1170 case R_PPC64_TOC16_DS: 1171 return {R_PPC64_ADDR16_DS, V}; 1172 case R_PPC64_TOC16_HA: 1173 return {R_PPC64_ADDR16_HA, V}; 1174 case R_PPC64_TOC16_HI: 1175 return {R_PPC64_ADDR16_HI, V}; 1176 case R_PPC64_TOC16_LO: 1177 return {R_PPC64_ADDR16_LO, V}; 1178 case R_PPC64_TOC16_LO_DS: 1179 return {R_PPC64_ADDR16_LO_DS, V}; 1180 default: 1181 return {Type, Val}; 1182 } 1183 } 1184 1185 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1186 uint64_t Val) const { 1187 // For a TOC-relative relocation, proceed in terms of the corresponding 1188 // ADDR16 relocation type. 1189 std::tie(Type, Val) = toAddr16Rel(Type, Val); 1190 1191 switch (Type) { 1192 case R_PPC64_ADDR14: { 1193 checkAlignment<4>(Loc, Val, Type); 1194 // Preserve the AA/LK bits in the branch instruction 1195 uint8_t AALK = Loc[3]; 1196 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 1197 break; 1198 } 1199 case R_PPC64_ADDR16: 1200 checkInt<16>(Loc, Val, Type); 1201 write16be(Loc, Val); 1202 break; 1203 case R_PPC64_ADDR16_DS: 1204 checkInt<16>(Loc, Val, Type); 1205 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3)); 1206 break; 1207 case R_PPC64_ADDR16_HA: 1208 case R_PPC64_REL16_HA: 1209 write16be(Loc, applyPPCHa(Val)); 1210 break; 1211 case R_PPC64_ADDR16_HI: 1212 case R_PPC64_REL16_HI: 1213 write16be(Loc, applyPPCHi(Val)); 1214 break; 1215 case R_PPC64_ADDR16_HIGHER: 1216 write16be(Loc, applyPPCHigher(Val)); 1217 break; 1218 case R_PPC64_ADDR16_HIGHERA: 1219 write16be(Loc, applyPPCHighera(Val)); 1220 break; 1221 case R_PPC64_ADDR16_HIGHEST: 1222 write16be(Loc, applyPPCHighest(Val)); 1223 break; 1224 case R_PPC64_ADDR16_HIGHESTA: 1225 write16be(Loc, applyPPCHighesta(Val)); 1226 break; 1227 case R_PPC64_ADDR16_LO: 1228 write16be(Loc, applyPPCLo(Val)); 1229 break; 1230 case R_PPC64_ADDR16_LO_DS: 1231 case R_PPC64_REL16_LO: 1232 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3)); 1233 break; 1234 case R_PPC64_ADDR32: 1235 case R_PPC64_REL32: 1236 checkInt<32>(Loc, Val, Type); 1237 write32be(Loc, Val); 1238 break; 1239 case R_PPC64_ADDR64: 1240 case R_PPC64_REL64: 1241 case R_PPC64_TOC: 1242 write64be(Loc, Val); 1243 break; 1244 case R_PPC64_REL24: { 1245 uint32_t Mask = 0x03FFFFFC; 1246 checkInt<24>(Loc, Val, Type); 1247 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask)); 1248 break; 1249 } 1250 default: 1251 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1252 } 1253 } 1254 1255 AArch64TargetInfo::AArch64TargetInfo() { 1256 CopyRel = R_AARCH64_COPY; 1257 RelativeRel = R_AARCH64_RELATIVE; 1258 IRelativeRel = R_AARCH64_IRELATIVE; 1259 GotRel = R_AARCH64_GLOB_DAT; 1260 PltRel = R_AARCH64_JUMP_SLOT; 1261 TlsDescRel = R_AARCH64_TLSDESC; 1262 TlsGotRel = R_AARCH64_TLS_TPREL64; 1263 GotEntrySize = 8; 1264 GotPltEntrySize = 8; 1265 PltEntrySize = 16; 1266 PltHeaderSize = 32; 1267 DefaultMaxPageSize = 65536; 1268 1269 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant 1270 // 1 of the tls structures and the tcb size is 16. 1271 TcbSize = 16; 1272 } 1273 1274 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type, 1275 const SymbolBody &S) const { 1276 switch (Type) { 1277 default: 1278 return R_ABS; 1279 case R_AARCH64_TLSDESC_ADR_PAGE21: 1280 return R_TLSDESC_PAGE; 1281 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1282 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1283 return R_TLSDESC; 1284 case R_AARCH64_TLSDESC_CALL: 1285 return R_TLSDESC_CALL; 1286 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1287 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1288 return R_TLS; 1289 case R_AARCH64_CALL26: 1290 case R_AARCH64_CONDBR19: 1291 case R_AARCH64_JUMP26: 1292 case R_AARCH64_TSTBR14: 1293 return R_PLT_PC; 1294 case R_AARCH64_PREL16: 1295 case R_AARCH64_PREL32: 1296 case R_AARCH64_PREL64: 1297 case R_AARCH64_ADR_PREL_LO21: 1298 return R_PC; 1299 case R_AARCH64_ADR_PREL_PG_HI21: 1300 return R_PAGE_PC; 1301 case R_AARCH64_LD64_GOT_LO12_NC: 1302 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1303 return R_GOT; 1304 case R_AARCH64_ADR_GOT_PAGE: 1305 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1306 return R_GOT_PAGE_PC; 1307 } 1308 } 1309 1310 RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 1311 RelExpr Expr) const { 1312 if (Expr == R_RELAX_TLS_GD_TO_IE) { 1313 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21) 1314 return R_RELAX_TLS_GD_TO_IE_PAGE_PC; 1315 return R_RELAX_TLS_GD_TO_IE_ABS; 1316 } 1317 return Expr; 1318 } 1319 1320 bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { 1321 switch (Type) { 1322 default: 1323 return false; 1324 case R_AARCH64_ADD_ABS_LO12_NC: 1325 case R_AARCH64_LD64_GOT_LO12_NC: 1326 case R_AARCH64_LDST128_ABS_LO12_NC: 1327 case R_AARCH64_LDST16_ABS_LO12_NC: 1328 case R_AARCH64_LDST32_ABS_LO12_NC: 1329 case R_AARCH64_LDST64_ABS_LO12_NC: 1330 case R_AARCH64_LDST8_ABS_LO12_NC: 1331 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1332 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1333 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1334 return true; 1335 } 1336 } 1337 1338 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1339 return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 || 1340 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; 1341 } 1342 1343 bool AArch64TargetInfo::isPicRel(uint32_t Type) const { 1344 return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64; 1345 } 1346 1347 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1348 write64le(Buf, In<ELF64LE>::Plt->getVA()); 1349 } 1350 1351 // Page(Expr) is the page address of the expression Expr, defined 1352 // as (Expr & ~0xFFF). (This applies even if the machine page size 1353 // supported by the platform has a different value.) 1354 uint64_t getAArch64Page(uint64_t Expr) { 1355 return Expr & (~static_cast<uint64_t>(0xFFF)); 1356 } 1357 1358 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const { 1359 const uint8_t PltData[] = { 1360 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 1361 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 1362 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 1363 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 1364 0x20, 0x02, 0x1f, 0xd6, // br x17 1365 0x1f, 0x20, 0x03, 0xd5, // nop 1366 0x1f, 0x20, 0x03, 0xd5, // nop 1367 0x1f, 0x20, 0x03, 0xd5 // nop 1368 }; 1369 memcpy(Buf, PltData, sizeof(PltData)); 1370 1371 uint64_t Got = In<ELF64LE>::GotPlt->getVA(); 1372 uint64_t Plt = In<ELF64LE>::Plt->getVA(); 1373 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 1374 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4)); 1375 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16); 1376 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16); 1377 } 1378 1379 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1380 uint64_t PltEntryAddr, int32_t Index, 1381 unsigned RelOff) const { 1382 const uint8_t Inst[] = { 1383 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 1384 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 1385 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n])) 1386 0x20, 0x02, 0x1f, 0xd6 // br x17 1387 }; 1388 memcpy(Buf, Inst, sizeof(Inst)); 1389 1390 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21, 1391 getAArch64Page(GotEntryAddr) - getAArch64Page(PltEntryAddr)); 1392 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotEntryAddr); 1393 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotEntryAddr); 1394 } 1395 1396 static void write32AArch64Addr(uint8_t *L, uint64_t Imm) { 1397 uint32_t ImmLo = (Imm & 0x3) << 29; 1398 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3; 1399 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3); 1400 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi); 1401 } 1402 1403 // Return the bits [Start, End] from Val shifted Start bits. 1404 // For instance, getBits(0xF0, 4, 8) returns 0xF. 1405 static uint64_t getBits(uint64_t Val, int Start, int End) { 1406 uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1; 1407 return (Val >> Start) & Mask; 1408 } 1409 1410 // Update the immediate field in a AARCH64 ldr, str, and add instruction. 1411 static void or32AArch64Imm(uint8_t *L, uint64_t Imm) { 1412 or32le(L, (Imm & 0xFFF) << 10); 1413 } 1414 1415 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1416 uint64_t Val) const { 1417 switch (Type) { 1418 case R_AARCH64_ABS16: 1419 case R_AARCH64_PREL16: 1420 checkIntUInt<16>(Loc, Val, Type); 1421 write16le(Loc, Val); 1422 break; 1423 case R_AARCH64_ABS32: 1424 case R_AARCH64_PREL32: 1425 checkIntUInt<32>(Loc, Val, Type); 1426 write32le(Loc, Val); 1427 break; 1428 case R_AARCH64_ABS64: 1429 case R_AARCH64_GLOB_DAT: 1430 case R_AARCH64_PREL64: 1431 write64le(Loc, Val); 1432 break; 1433 case R_AARCH64_ADD_ABS_LO12_NC: 1434 or32AArch64Imm(Loc, Val); 1435 break; 1436 case R_AARCH64_ADR_GOT_PAGE: 1437 case R_AARCH64_ADR_PREL_PG_HI21: 1438 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1439 case R_AARCH64_TLSDESC_ADR_PAGE21: 1440 checkInt<33>(Loc, Val, Type); 1441 write32AArch64Addr(Loc, Val >> 12); 1442 break; 1443 case R_AARCH64_ADR_PREL_LO21: 1444 checkInt<21>(Loc, Val, Type); 1445 write32AArch64Addr(Loc, Val); 1446 break; 1447 case R_AARCH64_CALL26: 1448 case R_AARCH64_JUMP26: 1449 checkInt<28>(Loc, Val, Type); 1450 or32le(Loc, (Val & 0x0FFFFFFC) >> 2); 1451 break; 1452 case R_AARCH64_CONDBR19: 1453 checkInt<21>(Loc, Val, Type); 1454 or32le(Loc, (Val & 0x1FFFFC) << 3); 1455 break; 1456 case R_AARCH64_LD64_GOT_LO12_NC: 1457 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1458 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1459 checkAlignment<8>(Loc, Val, Type); 1460 or32le(Loc, (Val & 0xFF8) << 7); 1461 break; 1462 case R_AARCH64_LDST8_ABS_LO12_NC: 1463 or32AArch64Imm(Loc, getBits(Val, 0, 11)); 1464 break; 1465 case R_AARCH64_LDST16_ABS_LO12_NC: 1466 or32AArch64Imm(Loc, getBits(Val, 1, 11)); 1467 break; 1468 case R_AARCH64_LDST32_ABS_LO12_NC: 1469 or32AArch64Imm(Loc, getBits(Val, 2, 11)); 1470 break; 1471 case R_AARCH64_LDST64_ABS_LO12_NC: 1472 or32AArch64Imm(Loc, getBits(Val, 3, 11)); 1473 break; 1474 case R_AARCH64_LDST128_ABS_LO12_NC: 1475 or32AArch64Imm(Loc, getBits(Val, 4, 11)); 1476 break; 1477 case R_AARCH64_MOVW_UABS_G0_NC: 1478 or32le(Loc, (Val & 0xFFFF) << 5); 1479 break; 1480 case R_AARCH64_MOVW_UABS_G1_NC: 1481 or32le(Loc, (Val & 0xFFFF0000) >> 11); 1482 break; 1483 case R_AARCH64_MOVW_UABS_G2_NC: 1484 or32le(Loc, (Val & 0xFFFF00000000) >> 27); 1485 break; 1486 case R_AARCH64_MOVW_UABS_G3: 1487 or32le(Loc, (Val & 0xFFFF000000000000) >> 43); 1488 break; 1489 case R_AARCH64_TSTBR14: 1490 checkInt<16>(Loc, Val, Type); 1491 or32le(Loc, (Val & 0xFFFC) << 3); 1492 break; 1493 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1494 checkInt<24>(Loc, Val, Type); 1495 or32AArch64Imm(Loc, Val >> 12); 1496 break; 1497 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1498 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1499 or32AArch64Imm(Loc, Val); 1500 break; 1501 default: 1502 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1503 } 1504 } 1505 1506 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 1507 uint64_t Val) const { 1508 // TLSDESC Global-Dynamic relocation are in the form: 1509 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1510 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1511 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1512 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1513 // blr x1 1514 // And it can optimized to: 1515 // movz x0, #0x0, lsl #16 1516 // movk x0, #0x10 1517 // nop 1518 // nop 1519 checkUInt<32>(Loc, Val, Type); 1520 1521 switch (Type) { 1522 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1523 case R_AARCH64_TLSDESC_CALL: 1524 write32le(Loc, 0xd503201f); // nop 1525 return; 1526 case R_AARCH64_TLSDESC_ADR_PAGE21: 1527 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz 1528 return; 1529 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1530 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk 1531 return; 1532 default: 1533 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1534 } 1535 } 1536 1537 void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 1538 uint64_t Val) const { 1539 // TLSDESC Global-Dynamic relocation are in the form: 1540 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1541 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1542 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1543 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1544 // blr x1 1545 // And it can optimized to: 1546 // adrp x0, :gottprel:v 1547 // ldr x0, [x0, :gottprel_lo12:v] 1548 // nop 1549 // nop 1550 1551 switch (Type) { 1552 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1553 case R_AARCH64_TLSDESC_CALL: 1554 write32le(Loc, 0xd503201f); // nop 1555 break; 1556 case R_AARCH64_TLSDESC_ADR_PAGE21: 1557 write32le(Loc, 0x90000000); // adrp 1558 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val); 1559 break; 1560 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1561 write32le(Loc, 0xf9400000); // ldr 1562 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val); 1563 break; 1564 default: 1565 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1566 } 1567 } 1568 1569 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 1570 uint64_t Val) const { 1571 checkUInt<32>(Loc, Val, Type); 1572 1573 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) { 1574 // Generate MOVZ. 1575 uint32_t RegNo = read32le(Loc) & 0x1f; 1576 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5)); 1577 return; 1578 } 1579 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) { 1580 // Generate MOVK. 1581 uint32_t RegNo = read32le(Loc) & 0x1f; 1582 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5)); 1583 return; 1584 } 1585 llvm_unreachable("invalid relocation for TLS IE to LE relaxation"); 1586 } 1587 1588 AMDGPUTargetInfo::AMDGPUTargetInfo() { 1589 RelativeRel = R_AMDGPU_REL64; 1590 GotRel = R_AMDGPU_ABS64; 1591 GotEntrySize = 8; 1592 } 1593 1594 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1595 uint64_t Val) const { 1596 switch (Type) { 1597 case R_AMDGPU_ABS32: 1598 case R_AMDGPU_GOTPCREL: 1599 case R_AMDGPU_GOTPCREL32_LO: 1600 case R_AMDGPU_REL32: 1601 case R_AMDGPU_REL32_LO: 1602 write32le(Loc, Val); 1603 break; 1604 case R_AMDGPU_ABS64: 1605 write64le(Loc, Val); 1606 break; 1607 case R_AMDGPU_GOTPCREL32_HI: 1608 case R_AMDGPU_REL32_HI: 1609 write32le(Loc, Val >> 32); 1610 break; 1611 default: 1612 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1613 } 1614 } 1615 1616 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1617 switch (Type) { 1618 case R_AMDGPU_ABS32: 1619 case R_AMDGPU_ABS64: 1620 return R_ABS; 1621 case R_AMDGPU_REL32: 1622 case R_AMDGPU_REL32_LO: 1623 case R_AMDGPU_REL32_HI: 1624 return R_PC; 1625 case R_AMDGPU_GOTPCREL: 1626 case R_AMDGPU_GOTPCREL32_LO: 1627 case R_AMDGPU_GOTPCREL32_HI: 1628 return R_GOT_PC; 1629 default: 1630 error("unknown relocation type: " + toString(Type)); 1631 return R_HINT; 1632 } 1633 } 1634 1635 ARMTargetInfo::ARMTargetInfo() { 1636 CopyRel = R_ARM_COPY; 1637 RelativeRel = R_ARM_RELATIVE; 1638 IRelativeRel = R_ARM_IRELATIVE; 1639 GotRel = R_ARM_GLOB_DAT; 1640 PltRel = R_ARM_JUMP_SLOT; 1641 TlsGotRel = R_ARM_TLS_TPOFF32; 1642 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32; 1643 TlsOffsetRel = R_ARM_TLS_DTPOFF32; 1644 GotEntrySize = 4; 1645 GotPltEntrySize = 4; 1646 PltEntrySize = 16; 1647 PltHeaderSize = 20; 1648 // ARM uses Variant 1 TLS 1649 TcbSize = 8; 1650 NeedsThunks = true; 1651 } 1652 1653 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1654 switch (Type) { 1655 default: 1656 return R_ABS; 1657 case R_ARM_THM_JUMP11: 1658 return R_PC; 1659 case R_ARM_CALL: 1660 case R_ARM_JUMP24: 1661 case R_ARM_PC24: 1662 case R_ARM_PLT32: 1663 case R_ARM_PREL31: 1664 case R_ARM_THM_JUMP19: 1665 case R_ARM_THM_JUMP24: 1666 case R_ARM_THM_CALL: 1667 return R_PLT_PC; 1668 case R_ARM_GOTOFF32: 1669 // (S + A) - GOT_ORG 1670 return R_GOTREL; 1671 case R_ARM_GOT_BREL: 1672 // GOT(S) + A - GOT_ORG 1673 return R_GOT_OFF; 1674 case R_ARM_GOT_PREL: 1675 case R_ARM_TLS_IE32: 1676 // GOT(S) + A - P 1677 return R_GOT_PC; 1678 case R_ARM_TARGET1: 1679 return Config->Target1Rel ? R_PC : R_ABS; 1680 case R_ARM_TARGET2: 1681 if (Config->Target2 == Target2Policy::Rel) 1682 return R_PC; 1683 if (Config->Target2 == Target2Policy::Abs) 1684 return R_ABS; 1685 return R_GOT_PC; 1686 case R_ARM_TLS_GD32: 1687 return R_TLSGD_PC; 1688 case R_ARM_TLS_LDM32: 1689 return R_TLSLD_PC; 1690 case R_ARM_BASE_PREL: 1691 // B(S) + A - P 1692 // FIXME: currently B(S) assumed to be .got, this may not hold for all 1693 // platforms. 1694 return R_GOTONLY_PC; 1695 case R_ARM_MOVW_PREL_NC: 1696 case R_ARM_MOVT_PREL: 1697 case R_ARM_REL32: 1698 case R_ARM_THM_MOVW_PREL_NC: 1699 case R_ARM_THM_MOVT_PREL: 1700 return R_PC; 1701 case R_ARM_NONE: 1702 return R_HINT; 1703 case R_ARM_TLS_LE32: 1704 return R_TLS; 1705 } 1706 } 1707 1708 bool ARMTargetInfo::isPicRel(uint32_t Type) const { 1709 return (Type == R_ARM_TARGET1 && !Config->Target1Rel) || 1710 (Type == R_ARM_ABS32); 1711 } 1712 1713 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const { 1714 if (Type == R_ARM_TARGET1 && !Config->Target1Rel) 1715 return R_ARM_ABS32; 1716 if (Type == R_ARM_ABS32) 1717 return Type; 1718 // Keep it going with a dummy value so that we can find more reloc errors. 1719 return R_ARM_ABS32; 1720 } 1721 1722 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1723 write32le(Buf, In<ELF32LE>::Plt->getVA()); 1724 } 1725 1726 void ARMTargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 1727 // An ARM entry is the address of the ifunc resolver function. 1728 write32le(Buf, S.getVA<ELF32LE>()); 1729 } 1730 1731 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const { 1732 const uint8_t PltData[] = { 1733 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]! 1734 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2 1735 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr 1736 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8] 1737 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8 1738 }; 1739 memcpy(Buf, PltData, sizeof(PltData)); 1740 uint64_t GotPlt = In<ELF32LE>::GotPlt->getVA(); 1741 uint64_t L1 = In<ELF32LE>::Plt->getVA() + 8; 1742 write32le(Buf + 16, GotPlt - L1 - 8); 1743 } 1744 1745 void ARMTargetInfo::addPltHeaderSymbols(InputSectionData *ISD) const { 1746 auto *IS = cast<InputSection<ELF32LE>>(ISD); 1747 addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS); 1748 addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS); 1749 } 1750 1751 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1752 uint64_t PltEntryAddr, int32_t Index, 1753 unsigned RelOff) const { 1754 // FIXME: Using simple code sequence with simple relocations. 1755 // There is a more optimal sequence but it requires support for the group 1756 // relocations. See ELF for the ARM Architecture Appendix A.3 1757 const uint8_t PltData[] = { 1758 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2 1759 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc 1760 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip] 1761 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8 1762 }; 1763 memcpy(Buf, PltData, sizeof(PltData)); 1764 uint64_t L1 = PltEntryAddr + 4; 1765 write32le(Buf + 12, GotEntryAddr - L1 - 8); 1766 } 1767 1768 void ARMTargetInfo::addPltSymbols(InputSectionData *ISD, uint64_t Off) const { 1769 auto *IS = cast<InputSection<ELF32LE>>(ISD); 1770 addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS); 1771 addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS); 1772 } 1773 1774 RelExpr ARMTargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType, 1775 const InputFile *File, 1776 const SymbolBody &S) const { 1777 // If S is an undefined weak symbol in an executable we don't need a Thunk. 1778 // In a DSO calls to undefined symbols, including weak ones get PLT entries 1779 // which may need a thunk. 1780 if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak() && 1781 !Config->Shared) 1782 return Expr; 1783 // A state change from ARM to Thumb and vice versa must go through an 1784 // interworking thunk if the relocation type is not R_ARM_CALL or 1785 // R_ARM_THM_CALL. 1786 switch (RelocType) { 1787 case R_ARM_PC24: 1788 case R_ARM_PLT32: 1789 case R_ARM_JUMP24: 1790 // Source is ARM, all PLT entries are ARM so no interworking required. 1791 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb). 1792 if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1)) 1793 return R_THUNK_PC; 1794 break; 1795 case R_ARM_THM_JUMP19: 1796 case R_ARM_THM_JUMP24: 1797 // Source is Thumb, all PLT entries are ARM so interworking is required. 1798 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM). 1799 if (Expr == R_PLT_PC) 1800 return R_THUNK_PLT_PC; 1801 if ((S.getVA<ELF32LE>() & 1) == 0) 1802 return R_THUNK_PC; 1803 break; 1804 } 1805 return Expr; 1806 } 1807 1808 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1809 uint64_t Val) const { 1810 switch (Type) { 1811 case R_ARM_ABS32: 1812 case R_ARM_BASE_PREL: 1813 case R_ARM_GLOB_DAT: 1814 case R_ARM_GOTOFF32: 1815 case R_ARM_GOT_BREL: 1816 case R_ARM_GOT_PREL: 1817 case R_ARM_REL32: 1818 case R_ARM_RELATIVE: 1819 case R_ARM_TARGET1: 1820 case R_ARM_TARGET2: 1821 case R_ARM_TLS_GD32: 1822 case R_ARM_TLS_IE32: 1823 case R_ARM_TLS_LDM32: 1824 case R_ARM_TLS_LDO32: 1825 case R_ARM_TLS_LE32: 1826 case R_ARM_TLS_TPOFF32: 1827 write32le(Loc, Val); 1828 break; 1829 case R_ARM_TLS_DTPMOD32: 1830 write32le(Loc, 1); 1831 break; 1832 case R_ARM_PREL31: 1833 checkInt<31>(Loc, Val, Type); 1834 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000)); 1835 break; 1836 case R_ARM_CALL: 1837 // R_ARM_CALL is used for BL and BLX instructions, depending on the 1838 // value of bit 0 of Val, we must select a BL or BLX instruction 1839 if (Val & 1) { 1840 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX. 1841 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' 1842 checkInt<26>(Loc, Val, Type); 1843 write32le(Loc, 0xfa000000 | // opcode 1844 ((Val & 2) << 23) | // H 1845 ((Val >> 2) & 0x00ffffff)); // imm24 1846 break; 1847 } 1848 if ((read32le(Loc) & 0xfe000000) == 0xfa000000) 1849 // BLX (always unconditional) instruction to an ARM Target, select an 1850 // unconditional BL. 1851 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff)); 1852 // fall through as BL encoding is shared with B 1853 case R_ARM_JUMP24: 1854 case R_ARM_PC24: 1855 case R_ARM_PLT32: 1856 checkInt<26>(Loc, Val, Type); 1857 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff)); 1858 break; 1859 case R_ARM_THM_JUMP11: 1860 checkInt<12>(Loc, Val, Type); 1861 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff)); 1862 break; 1863 case R_ARM_THM_JUMP19: 1864 // Encoding T3: Val = S:J2:J1:imm6:imm11:0 1865 checkInt<21>(Loc, Val, Type); 1866 write16le(Loc, 1867 (read16le(Loc) & 0xfbc0) | // opcode cond 1868 ((Val >> 10) & 0x0400) | // S 1869 ((Val >> 12) & 0x003f)); // imm6 1870 write16le(Loc + 2, 1871 0x8000 | // opcode 1872 ((Val >> 8) & 0x0800) | // J2 1873 ((Val >> 5) & 0x2000) | // J1 1874 ((Val >> 1) & 0x07ff)); // imm11 1875 break; 1876 case R_ARM_THM_CALL: 1877 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the 1878 // value of bit 0 of Val, we must select a BL or BLX instruction 1879 if ((Val & 1) == 0) { 1880 // Ensure BLX destination is 4-byte aligned. As BLX instruction may 1881 // only be two byte aligned. This must be done before overflow check 1882 Val = alignTo(Val, 4); 1883 } 1884 // Bit 12 is 0 for BLX, 1 for BL 1885 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12); 1886 // Fall through as rest of encoding is the same as B.W 1887 case R_ARM_THM_JUMP24: 1888 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 1889 // FIXME: Use of I1 and I2 require v6T2ops 1890 checkInt<25>(Loc, Val, Type); 1891 write16le(Loc, 1892 0xf000 | // opcode 1893 ((Val >> 14) & 0x0400) | // S 1894 ((Val >> 12) & 0x03ff)); // imm10 1895 write16le(Loc + 2, 1896 (read16le(Loc + 2) & 0xd000) | // opcode 1897 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1 1898 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2 1899 ((Val >> 1) & 0x07ff)); // imm11 1900 break; 1901 case R_ARM_MOVW_ABS_NC: 1902 case R_ARM_MOVW_PREL_NC: 1903 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) | 1904 (Val & 0x0fff)); 1905 break; 1906 case R_ARM_MOVT_ABS: 1907 case R_ARM_MOVT_PREL: 1908 checkInt<32>(Loc, Val, Type); 1909 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | 1910 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff)); 1911 break; 1912 case R_ARM_THM_MOVT_ABS: 1913 case R_ARM_THM_MOVT_PREL: 1914 // Encoding T1: A = imm4:i:imm3:imm8 1915 checkInt<32>(Loc, Val, Type); 1916 write16le(Loc, 1917 0xf2c0 | // opcode 1918 ((Val >> 17) & 0x0400) | // i 1919 ((Val >> 28) & 0x000f)); // imm4 1920 write16le(Loc + 2, 1921 (read16le(Loc + 2) & 0x8f00) | // opcode 1922 ((Val >> 12) & 0x7000) | // imm3 1923 ((Val >> 16) & 0x00ff)); // imm8 1924 break; 1925 case R_ARM_THM_MOVW_ABS_NC: 1926 case R_ARM_THM_MOVW_PREL_NC: 1927 // Encoding T3: A = imm4:i:imm3:imm8 1928 write16le(Loc, 1929 0xf240 | // opcode 1930 ((Val >> 1) & 0x0400) | // i 1931 ((Val >> 12) & 0x000f)); // imm4 1932 write16le(Loc + 2, 1933 (read16le(Loc + 2) & 0x8f00) | // opcode 1934 ((Val << 4) & 0x7000) | // imm3 1935 (Val & 0x00ff)); // imm8 1936 break; 1937 default: 1938 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1939 } 1940 } 1941 1942 uint64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf, 1943 uint32_t Type) const { 1944 switch (Type) { 1945 default: 1946 return 0; 1947 case R_ARM_ABS32: 1948 case R_ARM_BASE_PREL: 1949 case R_ARM_GOTOFF32: 1950 case R_ARM_GOT_BREL: 1951 case R_ARM_GOT_PREL: 1952 case R_ARM_REL32: 1953 case R_ARM_TARGET1: 1954 case R_ARM_TARGET2: 1955 case R_ARM_TLS_GD32: 1956 case R_ARM_TLS_LDM32: 1957 case R_ARM_TLS_LDO32: 1958 case R_ARM_TLS_IE32: 1959 case R_ARM_TLS_LE32: 1960 return SignExtend64<32>(read32le(Buf)); 1961 case R_ARM_PREL31: 1962 return SignExtend64<31>(read32le(Buf)); 1963 case R_ARM_CALL: 1964 case R_ARM_JUMP24: 1965 case R_ARM_PC24: 1966 case R_ARM_PLT32: 1967 return SignExtend64<26>(read32le(Buf) << 2); 1968 case R_ARM_THM_JUMP11: 1969 return SignExtend64<12>(read16le(Buf) << 1); 1970 case R_ARM_THM_JUMP19: { 1971 // Encoding T3: A = S:J2:J1:imm10:imm6:0 1972 uint16_t Hi = read16le(Buf); 1973 uint16_t Lo = read16le(Buf + 2); 1974 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S 1975 ((Lo & 0x0800) << 8) | // J2 1976 ((Lo & 0x2000) << 5) | // J1 1977 ((Hi & 0x003f) << 12) | // imm6 1978 ((Lo & 0x07ff) << 1)); // imm11:0 1979 } 1980 case R_ARM_THM_CALL: 1981 case R_ARM_THM_JUMP24: { 1982 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 1983 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) 1984 // FIXME: I1 and I2 require v6T2ops 1985 uint16_t Hi = read16le(Buf); 1986 uint16_t Lo = read16le(Buf + 2); 1987 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S 1988 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1 1989 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2 1990 ((Hi & 0x003ff) << 12) | // imm0 1991 ((Lo & 0x007ff) << 1)); // imm11:0 1992 } 1993 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and 1994 // MOVT is in the range -32768 <= A < 32768 1995 case R_ARM_MOVW_ABS_NC: 1996 case R_ARM_MOVT_ABS: 1997 case R_ARM_MOVW_PREL_NC: 1998 case R_ARM_MOVT_PREL: { 1999 uint64_t Val = read32le(Buf) & 0x000f0fff; 2000 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff)); 2001 } 2002 case R_ARM_THM_MOVW_ABS_NC: 2003 case R_ARM_THM_MOVT_ABS: 2004 case R_ARM_THM_MOVW_PREL_NC: 2005 case R_ARM_THM_MOVT_PREL: { 2006 // Encoding T3: A = imm4:i:imm3:imm8 2007 uint16_t Hi = read16le(Buf); 2008 uint16_t Lo = read16le(Buf + 2); 2009 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4 2010 ((Hi & 0x0400) << 1) | // i 2011 ((Lo & 0x7000) >> 4) | // imm3 2012 (Lo & 0x00ff)); // imm8 2013 } 2014 } 2015 } 2016 2017 bool ARMTargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 2018 return Type == R_ARM_TLS_LDO32 || Type == R_ARM_TLS_LDM32; 2019 } 2020 2021 bool ARMTargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 2022 return Type == R_ARM_TLS_GD32; 2023 } 2024 2025 bool ARMTargetInfo::isTlsInitialExecRel(uint32_t Type) const { 2026 return Type == R_ARM_TLS_IE32; 2027 } 2028 2029 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() { 2030 GotPltHeaderEntriesNum = 2; 2031 DefaultMaxPageSize = 65536; 2032 GotEntrySize = sizeof(typename ELFT::uint); 2033 GotPltEntrySize = sizeof(typename ELFT::uint); 2034 PltEntrySize = 16; 2035 PltHeaderSize = 32; 2036 CopyRel = R_MIPS_COPY; 2037 PltRel = R_MIPS_JUMP_SLOT; 2038 NeedsThunks = true; 2039 if (ELFT::Is64Bits) { 2040 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 2041 TlsGotRel = R_MIPS_TLS_TPREL64; 2042 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 2043 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 2044 } else { 2045 RelativeRel = R_MIPS_REL32; 2046 TlsGotRel = R_MIPS_TLS_TPREL32; 2047 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 2048 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 2049 } 2050 } 2051 2052 template <class ELFT> 2053 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type, 2054 const SymbolBody &S) const { 2055 // See comment in the calculateMipsRelChain. 2056 if (ELFT::Is64Bits || Config->MipsN32Abi) 2057 Type &= 0xff; 2058 switch (Type) { 2059 default: 2060 return R_ABS; 2061 case R_MIPS_JALR: 2062 return R_HINT; 2063 case R_MIPS_GPREL16: 2064 case R_MIPS_GPREL32: 2065 return R_MIPS_GOTREL; 2066 case R_MIPS_26: 2067 return R_PLT; 2068 case R_MIPS_HI16: 2069 case R_MIPS_LO16: 2070 case R_MIPS_GOT_OFST: 2071 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 2072 // offset between start of function and 'gp' value which by default 2073 // equal to the start of .got section. In that case we consider these 2074 // relocations as relative. 2075 if (&S == ElfSym<ELFT>::MipsGpDisp) 2076 return R_PC; 2077 return R_ABS; 2078 case R_MIPS_PC32: 2079 case R_MIPS_PC16: 2080 case R_MIPS_PC19_S2: 2081 case R_MIPS_PC21_S2: 2082 case R_MIPS_PC26_S2: 2083 case R_MIPS_PCHI16: 2084 case R_MIPS_PCLO16: 2085 return R_PC; 2086 case R_MIPS_GOT16: 2087 if (S.isLocal()) 2088 return R_MIPS_GOT_LOCAL_PAGE; 2089 // fallthrough 2090 case R_MIPS_CALL16: 2091 case R_MIPS_GOT_DISP: 2092 case R_MIPS_TLS_GOTTPREL: 2093 return R_MIPS_GOT_OFF; 2094 case R_MIPS_CALL_HI16: 2095 case R_MIPS_CALL_LO16: 2096 case R_MIPS_GOT_HI16: 2097 case R_MIPS_GOT_LO16: 2098 return R_MIPS_GOT_OFF32; 2099 case R_MIPS_GOT_PAGE: 2100 return R_MIPS_GOT_LOCAL_PAGE; 2101 case R_MIPS_TLS_GD: 2102 return R_MIPS_TLSGD; 2103 case R_MIPS_TLS_LDM: 2104 return R_MIPS_TLSLD; 2105 } 2106 } 2107 2108 template <class ELFT> bool MipsTargetInfo<ELFT>::isPicRel(uint32_t Type) const { 2109 return Type == R_MIPS_32 || Type == R_MIPS_64; 2110 } 2111 2112 template <class ELFT> 2113 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const { 2114 return RelativeRel; 2115 } 2116 2117 template <class ELFT> 2118 bool MipsTargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 2119 return Type == R_MIPS_TLS_LDM; 2120 } 2121 2122 template <class ELFT> 2123 bool MipsTargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 2124 return Type == R_MIPS_TLS_GD; 2125 } 2126 2127 template <class ELFT> 2128 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 2129 write32<ELFT::TargetEndianness>(Buf, In<ELFT>::Plt->getVA()); 2130 } 2131 2132 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2133 static int64_t getPcRelocAddend(const uint8_t *Loc) { 2134 uint32_t Instr = read32<E>(Loc); 2135 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2136 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT); 2137 } 2138 2139 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2140 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) { 2141 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2142 uint32_t Instr = read32<E>(Loc); 2143 if (SHIFT > 0) 2144 checkAlignment<(1 << SHIFT)>(Loc, V, Type); 2145 checkInt<BSIZE + SHIFT>(Loc, V, Type); 2146 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask)); 2147 } 2148 2149 template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) { 2150 uint32_t Instr = read32<E>(Loc); 2151 uint16_t Res = ((V + 0x8000) >> 16) & 0xffff; 2152 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2153 } 2154 2155 template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) { 2156 uint32_t Instr = read32<E>(Loc); 2157 uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff; 2158 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2159 } 2160 2161 template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) { 2162 uint32_t Instr = read32<E>(Loc); 2163 uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff; 2164 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2165 } 2166 2167 template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) { 2168 uint32_t Instr = read32<E>(Loc); 2169 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff)); 2170 } 2171 2172 template <class ELFT> static bool isMipsR6() { 2173 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf); 2174 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH; 2175 return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6; 2176 } 2177 2178 template <class ELFT> 2179 void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 2180 const endianness E = ELFT::TargetEndianness; 2181 if (Config->MipsN32Abi) { 2182 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 2183 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 2184 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 2185 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 2186 } else { 2187 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 2188 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 2189 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 2190 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 2191 } 2192 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 2193 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 2194 write32<E>(Buf + 24, 0x0320f809); // jalr $25 2195 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 2196 uint64_t Got = In<ELFT>::GotPlt->getVA(); 2197 writeMipsHi16<E>(Buf, Got); 2198 writeMipsLo16<E>(Buf + 4, Got); 2199 writeMipsLo16<E>(Buf + 8, Got); 2200 } 2201 2202 template <class ELFT> 2203 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 2204 uint64_t PltEntryAddr, int32_t Index, 2205 unsigned RelOff) const { 2206 const endianness E = ELFT::TargetEndianness; 2207 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 2208 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 2209 // jr $25 2210 write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008); 2211 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 2212 writeMipsHi16<E>(Buf, GotEntryAddr); 2213 writeMipsLo16<E>(Buf + 4, GotEntryAddr); 2214 writeMipsLo16<E>(Buf + 12, GotEntryAddr); 2215 } 2216 2217 template <class ELFT> 2218 RelExpr MipsTargetInfo<ELFT>::getThunkExpr(RelExpr Expr, uint32_t Type, 2219 const InputFile *File, 2220 const SymbolBody &S) const { 2221 // Any MIPS PIC code function is invoked with its address in register $t9. 2222 // So if we have a branch instruction from non-PIC code to the PIC one 2223 // we cannot make the jump directly and need to create a small stubs 2224 // to save the target function address. 2225 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 2226 if (Type != R_MIPS_26) 2227 return Expr; 2228 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 2229 if (!F) 2230 return Expr; 2231 // If current file has PIC code, LA25 stub is not required. 2232 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 2233 return Expr; 2234 auto *D = dyn_cast<DefinedRegular<ELFT>>(&S); 2235 // LA25 is required if target file has PIC code 2236 // or target symbol is a PIC symbol. 2237 return D && D->isMipsPIC() ? R_THUNK_ABS : Expr; 2238 } 2239 2240 template <class ELFT> 2241 uint64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf, 2242 uint32_t Type) const { 2243 const endianness E = ELFT::TargetEndianness; 2244 switch (Type) { 2245 default: 2246 return 0; 2247 case R_MIPS_32: 2248 case R_MIPS_GPREL32: 2249 case R_MIPS_TLS_DTPREL32: 2250 case R_MIPS_TLS_TPREL32: 2251 return read32<E>(Buf); 2252 case R_MIPS_26: 2253 // FIXME (simon): If the relocation target symbol is not a PLT entry 2254 // we should use another expression for calculation: 2255 // ((A << 2) | (P & 0xf0000000)) >> 2 2256 return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2); 2257 case R_MIPS_GPREL16: 2258 case R_MIPS_LO16: 2259 case R_MIPS_PCLO16: 2260 case R_MIPS_TLS_DTPREL_HI16: 2261 case R_MIPS_TLS_DTPREL_LO16: 2262 case R_MIPS_TLS_TPREL_HI16: 2263 case R_MIPS_TLS_TPREL_LO16: 2264 return SignExtend64<16>(read32<E>(Buf)); 2265 case R_MIPS_PC16: 2266 return getPcRelocAddend<E, 16, 2>(Buf); 2267 case R_MIPS_PC19_S2: 2268 return getPcRelocAddend<E, 19, 2>(Buf); 2269 case R_MIPS_PC21_S2: 2270 return getPcRelocAddend<E, 21, 2>(Buf); 2271 case R_MIPS_PC26_S2: 2272 return getPcRelocAddend<E, 26, 2>(Buf); 2273 case R_MIPS_PC32: 2274 return getPcRelocAddend<E, 32, 0>(Buf); 2275 } 2276 } 2277 2278 static std::pair<uint32_t, uint64_t> 2279 calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) { 2280 // MIPS N64 ABI packs multiple relocations into the single relocation 2281 // record. In general, all up to three relocations can have arbitrary 2282 // types. In fact, Clang and GCC uses only a few combinations. For now, 2283 // we support two of them. That is allow to pass at least all LLVM 2284 // test suite cases. 2285 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 2286 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 2287 // The first relocation is a 'real' relocation which is calculated 2288 // using the corresponding symbol's value. The second and the third 2289 // relocations used to modify result of the first one: extend it to 2290 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 2291 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 2292 uint32_t Type2 = (Type >> 8) & 0xff; 2293 uint32_t Type3 = (Type >> 16) & 0xff; 2294 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 2295 return std::make_pair(Type, Val); 2296 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 2297 return std::make_pair(Type2, Val); 2298 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 2299 return std::make_pair(Type3, -Val); 2300 error(getErrorLocation(Loc) + "unsupported relocations combination " + 2301 Twine(Type)); 2302 return std::make_pair(Type & 0xff, Val); 2303 } 2304 2305 template <class ELFT> 2306 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 2307 uint64_t Val) const { 2308 const endianness E = ELFT::TargetEndianness; 2309 // Thread pointer and DRP offsets from the start of TLS data area. 2310 // https://www.linux-mips.org/wiki/NPTL 2311 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 2312 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64) 2313 Val -= 0x8000; 2314 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 2315 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64) 2316 Val -= 0x7000; 2317 if (ELFT::Is64Bits || Config->MipsN32Abi) 2318 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 2319 switch (Type) { 2320 case R_MIPS_32: 2321 case R_MIPS_GPREL32: 2322 case R_MIPS_TLS_DTPREL32: 2323 case R_MIPS_TLS_TPREL32: 2324 write32<E>(Loc, Val); 2325 break; 2326 case R_MIPS_64: 2327 case R_MIPS_TLS_DTPREL64: 2328 case R_MIPS_TLS_TPREL64: 2329 write64<E>(Loc, Val); 2330 break; 2331 case R_MIPS_26: 2332 write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff)); 2333 break; 2334 case R_MIPS_GOT_DISP: 2335 case R_MIPS_GOT_PAGE: 2336 case R_MIPS_GOT16: 2337 case R_MIPS_GPREL16: 2338 case R_MIPS_TLS_GD: 2339 case R_MIPS_TLS_LDM: 2340 checkInt<16>(Loc, Val, Type); 2341 // fallthrough 2342 case R_MIPS_CALL16: 2343 case R_MIPS_CALL_LO16: 2344 case R_MIPS_GOT_LO16: 2345 case R_MIPS_GOT_OFST: 2346 case R_MIPS_LO16: 2347 case R_MIPS_PCLO16: 2348 case R_MIPS_TLS_DTPREL_LO16: 2349 case R_MIPS_TLS_GOTTPREL: 2350 case R_MIPS_TLS_TPREL_LO16: 2351 writeMipsLo16<E>(Loc, Val); 2352 break; 2353 case R_MIPS_CALL_HI16: 2354 case R_MIPS_GOT_HI16: 2355 case R_MIPS_HI16: 2356 case R_MIPS_PCHI16: 2357 case R_MIPS_TLS_DTPREL_HI16: 2358 case R_MIPS_TLS_TPREL_HI16: 2359 writeMipsHi16<E>(Loc, Val); 2360 break; 2361 case R_MIPS_HIGHER: 2362 writeMipsHigher<E>(Loc, Val); 2363 break; 2364 case R_MIPS_HIGHEST: 2365 writeMipsHighest<E>(Loc, Val); 2366 break; 2367 case R_MIPS_JALR: 2368 // Ignore this optimization relocation for now 2369 break; 2370 case R_MIPS_PC16: 2371 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val); 2372 break; 2373 case R_MIPS_PC19_S2: 2374 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val); 2375 break; 2376 case R_MIPS_PC21_S2: 2377 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val); 2378 break; 2379 case R_MIPS_PC26_S2: 2380 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val); 2381 break; 2382 case R_MIPS_PC32: 2383 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val); 2384 break; 2385 default: 2386 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 2387 } 2388 } 2389 2390 template <class ELFT> 2391 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const { 2392 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST; 2393 } 2394 } 2395 } 2396