1 //===- Target.cpp ---------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Machine-specific things, such as applying relocations, creation of 11 // GOT or PLT entries, etc., are handled in this file. 12 // 13 // Refer the ELF spec for the single letter variables, S, A or P, used 14 // in this file. 15 // 16 // Some functions defined in this file has "relaxTls" as part of their names. 17 // They do peephole optimization for TLS variables by rewriting instructions. 18 // They are not part of the ABI but optional optimization, so you can skip 19 // them if you are not interested in how TLS variables are optimized. 20 // See the following paper for the details. 21 // 22 // Ulrich Drepper, ELF Handling For Thread-Local Storage 23 // http://www.akkadia.org/drepper/tls.pdf 24 // 25 //===----------------------------------------------------------------------===// 26 27 #include "Target.h" 28 #include "Error.h" 29 #include "InputFiles.h" 30 #include "Memory.h" 31 #include "OutputSections.h" 32 #include "SymbolTable.h" 33 #include "Symbols.h" 34 #include "SyntheticSections.h" 35 #include "Thunks.h" 36 #include "Writer.h" 37 #include "llvm/ADT/ArrayRef.h" 38 #include "llvm/Object/ELF.h" 39 #include "llvm/Support/ELF.h" 40 #include "llvm/Support/Endian.h" 41 42 using namespace llvm; 43 using namespace llvm::object; 44 using namespace llvm::support::endian; 45 using namespace llvm::ELF; 46 47 std::string lld::toString(uint32_t Type) { 48 return getELFRelocationTypeName(elf::Config->EMachine, Type); 49 } 50 51 namespace lld { 52 namespace elf { 53 54 TargetInfo *Target; 55 56 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); } 57 static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); } 58 59 template <class ELFT> static std::string getErrorLoc(uint8_t *Loc) { 60 for (InputSectionData *D : Symtab<ELFT>::X->Sections) { 61 auto *IS = dyn_cast_or_null<InputSection<ELFT>>(D); 62 if (!IS || !IS->OutSec) 63 continue; 64 65 uint8_t *ISLoc = cast<OutputSection<ELFT>>(IS->OutSec)->Loc + IS->OutSecOff; 66 if (ISLoc <= Loc && Loc < ISLoc + IS->getSize()) 67 return IS->getLocation(Loc - ISLoc) + ": "; 68 } 69 return ""; 70 } 71 72 static std::string getErrorLocation(uint8_t *Loc) { 73 switch (Config->EKind) { 74 case ELF32LEKind: 75 return getErrorLoc<ELF32LE>(Loc); 76 case ELF32BEKind: 77 return getErrorLoc<ELF32BE>(Loc); 78 case ELF64LEKind: 79 return getErrorLoc<ELF64LE>(Loc); 80 case ELF64BEKind: 81 return getErrorLoc<ELF64BE>(Loc); 82 default: 83 llvm_unreachable("unknown ELF type"); 84 } 85 } 86 87 template <unsigned N> 88 static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) { 89 if (!isInt<N>(V)) 90 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 91 " out of range"); 92 } 93 94 template <unsigned N> 95 static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 96 if (!isUInt<N>(V)) 97 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 98 " out of range"); 99 } 100 101 template <unsigned N> 102 static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 103 if (!isInt<N>(V) && !isUInt<N>(V)) 104 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 105 " out of range"); 106 } 107 108 template <unsigned N> 109 static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) { 110 if ((V & (N - 1)) != 0) 111 error(getErrorLocation(Loc) + "improper alignment for relocation " + 112 toString(Type)); 113 } 114 115 namespace { 116 class X86TargetInfo final : public TargetInfo { 117 public: 118 X86TargetInfo(); 119 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 120 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 121 void writeGotPltHeader(uint8_t *Buf) const override; 122 uint32_t getDynRel(uint32_t Type) const override; 123 bool isTlsLocalDynamicRel(uint32_t Type) const override; 124 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 125 bool isTlsInitialExecRel(uint32_t Type) const override; 126 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 127 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 128 void writePltHeader(uint8_t *Buf) const override; 129 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 130 int32_t Index, unsigned RelOff) const override; 131 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 132 133 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 134 RelExpr Expr) const override; 135 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 136 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 137 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 138 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 139 }; 140 141 template <class ELFT> class X86_64TargetInfo final : public TargetInfo { 142 public: 143 X86_64TargetInfo(); 144 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 145 bool isPicRel(uint32_t Type) const override; 146 bool isTlsLocalDynamicRel(uint32_t Type) const override; 147 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 148 bool isTlsInitialExecRel(uint32_t Type) const override; 149 void writeGotPltHeader(uint8_t *Buf) const override; 150 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 151 void writePltHeader(uint8_t *Buf) const override; 152 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 153 int32_t Index, unsigned RelOff) const override; 154 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 155 156 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 157 RelExpr Expr) const override; 158 void relaxGot(uint8_t *Loc, uint64_t Val) const override; 159 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 160 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 161 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 162 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 163 164 private: 165 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op, 166 uint8_t ModRm) const; 167 }; 168 169 class PPCTargetInfo final : public TargetInfo { 170 public: 171 PPCTargetInfo(); 172 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 173 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 174 }; 175 176 class PPC64TargetInfo final : public TargetInfo { 177 public: 178 PPC64TargetInfo(); 179 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 180 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 181 int32_t Index, unsigned RelOff) const override; 182 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 183 }; 184 185 class AArch64TargetInfo final : public TargetInfo { 186 public: 187 AArch64TargetInfo(); 188 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 189 bool isPicRel(uint32_t Type) const override; 190 bool isTlsInitialExecRel(uint32_t Type) const override; 191 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 192 void writePltHeader(uint8_t *Buf) const override; 193 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 194 int32_t Index, unsigned RelOff) const override; 195 bool usesOnlyLowPageBits(uint32_t Type) const override; 196 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 197 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 198 RelExpr Expr) const override; 199 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 200 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 201 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 202 }; 203 204 class AMDGPUTargetInfo final : public TargetInfo { 205 public: 206 AMDGPUTargetInfo(); 207 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 208 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 209 }; 210 211 class ARMTargetInfo final : public TargetInfo { 212 public: 213 ARMTargetInfo(); 214 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 215 bool isPicRel(uint32_t Type) const override; 216 uint32_t getDynRel(uint32_t Type) const override; 217 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 218 bool isTlsLocalDynamicRel(uint32_t Type) const override; 219 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 220 bool isTlsInitialExecRel(uint32_t Type) const override; 221 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 222 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 223 void writePltHeader(uint8_t *Buf) const override; 224 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 225 int32_t Index, unsigned RelOff) const override; 226 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File, 227 const SymbolBody &S) const override; 228 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 229 }; 230 231 template <class ELFT> class MipsTargetInfo final : public TargetInfo { 232 public: 233 MipsTargetInfo(); 234 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 235 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 236 bool isPicRel(uint32_t Type) const override; 237 uint32_t getDynRel(uint32_t Type) const override; 238 bool isTlsLocalDynamicRel(uint32_t Type) const override; 239 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 240 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 241 void writePltHeader(uint8_t *Buf) const override; 242 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 243 int32_t Index, unsigned RelOff) const override; 244 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File, 245 const SymbolBody &S) const override; 246 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 247 bool usesOnlyLowPageBits(uint32_t Type) const override; 248 }; 249 } // anonymous namespace 250 251 TargetInfo *createTarget() { 252 switch (Config->EMachine) { 253 case EM_386: 254 case EM_IAMCU: 255 return make<X86TargetInfo>(); 256 case EM_AARCH64: 257 return make<AArch64TargetInfo>(); 258 case EM_AMDGPU: 259 return make<AMDGPUTargetInfo>(); 260 case EM_ARM: 261 return make<ARMTargetInfo>(); 262 case EM_MIPS: 263 switch (Config->EKind) { 264 case ELF32LEKind: 265 return make<MipsTargetInfo<ELF32LE>>(); 266 case ELF32BEKind: 267 return make<MipsTargetInfo<ELF32BE>>(); 268 case ELF64LEKind: 269 return make<MipsTargetInfo<ELF64LE>>(); 270 case ELF64BEKind: 271 return make<MipsTargetInfo<ELF64BE>>(); 272 default: 273 fatal("unsupported MIPS target"); 274 } 275 case EM_PPC: 276 return make<PPCTargetInfo>(); 277 case EM_PPC64: 278 return make<PPC64TargetInfo>(); 279 case EM_X86_64: 280 if (Config->EKind == ELF32LEKind) 281 return make<X86_64TargetInfo<ELF32LE>>(); 282 return make<X86_64TargetInfo<ELF64LE>>(); 283 } 284 fatal("unknown target machine"); 285 } 286 287 TargetInfo::~TargetInfo() {} 288 289 uint64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, 290 uint32_t Type) const { 291 return 0; 292 } 293 294 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; } 295 296 RelExpr TargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType, 297 const InputFile &File, 298 const SymbolBody &S) const { 299 return Expr; 300 } 301 302 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; } 303 304 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; } 305 306 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { return false; } 307 308 void TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 309 writeGotPlt(Buf, S); 310 } 311 312 RelExpr TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 313 RelExpr Expr) const { 314 return Expr; 315 } 316 317 void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const { 318 llvm_unreachable("Should not have claimed to be relaxable"); 319 } 320 321 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 322 uint64_t Val) const { 323 llvm_unreachable("Should not have claimed to be relaxable"); 324 } 325 326 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 327 uint64_t Val) const { 328 llvm_unreachable("Should not have claimed to be relaxable"); 329 } 330 331 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 332 uint64_t Val) const { 333 llvm_unreachable("Should not have claimed to be relaxable"); 334 } 335 336 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 337 uint64_t Val) const { 338 llvm_unreachable("Should not have claimed to be relaxable"); 339 } 340 341 X86TargetInfo::X86TargetInfo() { 342 CopyRel = R_386_COPY; 343 GotRel = R_386_GLOB_DAT; 344 PltRel = R_386_JUMP_SLOT; 345 IRelativeRel = R_386_IRELATIVE; 346 RelativeRel = R_386_RELATIVE; 347 TlsGotRel = R_386_TLS_TPOFF; 348 TlsModuleIndexRel = R_386_TLS_DTPMOD32; 349 TlsOffsetRel = R_386_TLS_DTPOFF32; 350 GotEntrySize = 4; 351 GotPltEntrySize = 4; 352 PltEntrySize = 16; 353 PltHeaderSize = 16; 354 TlsGdRelaxSkip = 2; 355 } 356 357 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 358 switch (Type) { 359 case R_386_16: 360 case R_386_32: 361 case R_386_TLS_LDO_32: 362 return R_ABS; 363 case R_386_TLS_GD: 364 return R_TLSGD; 365 case R_386_TLS_LDM: 366 return R_TLSLD; 367 case R_386_PLT32: 368 return R_PLT_PC; 369 case R_386_PC16: 370 case R_386_PC32: 371 return R_PC; 372 case R_386_GOTPC: 373 return R_GOTONLY_PC_FROM_END; 374 case R_386_TLS_IE: 375 return R_GOT; 376 case R_386_GOT32: 377 case R_386_GOT32X: 378 case R_386_TLS_GOTIE: 379 return R_GOT_FROM_END; 380 case R_386_GOTOFF: 381 return R_GOTREL_FROM_END; 382 case R_386_TLS_LE: 383 return R_TLS; 384 case R_386_TLS_LE_32: 385 return R_NEG_TLS; 386 case R_386_NONE: 387 return R_HINT; 388 default: 389 error("do not know how to handle relocation " + toString(Type) + " (" + 390 Twine(Type) + ")"); 391 return R_HINT; 392 } 393 } 394 395 RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 396 RelExpr Expr) const { 397 switch (Expr) { 398 default: 399 return Expr; 400 case R_RELAX_TLS_GD_TO_IE: 401 return R_RELAX_TLS_GD_TO_IE_END; 402 case R_RELAX_TLS_GD_TO_LE: 403 return R_RELAX_TLS_GD_TO_LE_NEG; 404 } 405 } 406 407 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const { 408 write32le(Buf, In<ELF32LE>::Dynamic->getVA()); 409 } 410 411 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const { 412 // Entries in .got.plt initially points back to the corresponding 413 // PLT entries with a fixed offset to skip the first instruction. 414 write32le(Buf, S.getPltVA<ELF32LE>() + 6); 415 } 416 417 void X86TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 418 // An x86 entry is the address of the ifunc resolver function. 419 write32le(Buf, S.getVA<ELF32LE>()); 420 } 421 422 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const { 423 if (Type == R_386_TLS_LE) 424 return R_386_TLS_TPOFF; 425 if (Type == R_386_TLS_LE_32) 426 return R_386_TLS_TPOFF32; 427 return Type; 428 } 429 430 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 431 return Type == R_386_TLS_GD; 432 } 433 434 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 435 return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM; 436 } 437 438 bool X86TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 439 return Type == R_386_TLS_IE || Type == R_386_TLS_GOTIE; 440 } 441 442 void X86TargetInfo::writePltHeader(uint8_t *Buf) const { 443 // Executable files and shared object files have 444 // separate procedure linkage tables. 445 if (Config->Pic) { 446 const uint8_t V[] = { 447 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl 4(%ebx) 448 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *8(%ebx) 449 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 450 }; 451 memcpy(Buf, V, sizeof(V)); 452 return; 453 } 454 455 const uint8_t PltData[] = { 456 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOT+4) 457 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOT+8) 458 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 459 }; 460 memcpy(Buf, PltData, sizeof(PltData)); 461 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 462 write32le(Buf + 2, Got + 4); 463 write32le(Buf + 8, Got + 8); 464 } 465 466 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 467 uint64_t PltEntryAddr, int32_t Index, 468 unsigned RelOff) const { 469 const uint8_t Inst[] = { 470 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx) 471 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset 472 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC 473 }; 474 memcpy(Buf, Inst, sizeof(Inst)); 475 476 // jmp *foo@GOT(%ebx) or jmp *foo_in_GOT 477 Buf[1] = Config->Pic ? 0xa3 : 0x25; 478 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 479 write32le(Buf + 2, Config->Shared ? GotEntryAddr - Got : GotEntryAddr); 480 write32le(Buf + 7, RelOff); 481 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 482 } 483 484 uint64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf, 485 uint32_t Type) const { 486 switch (Type) { 487 default: 488 return 0; 489 case R_386_16: 490 case R_386_PC16: 491 return read16le(Buf); 492 case R_386_32: 493 case R_386_GOT32: 494 case R_386_GOT32X: 495 case R_386_GOTOFF: 496 case R_386_GOTPC: 497 case R_386_PC32: 498 case R_386_PLT32: 499 case R_386_TLS_LE: 500 return read32le(Buf); 501 } 502 } 503 504 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 505 uint64_t Val) const { 506 checkInt<32>(Loc, Val, Type); 507 508 // R_386_PC16 and R_386_16 are not part of the current i386 psABI. They are 509 // used by 16-bit x86 objects, like boot loaders. 510 if (Type == R_386_16 || Type == R_386_PC16) { 511 write16le(Loc, Val); 512 return; 513 } 514 write32le(Loc, Val); 515 } 516 517 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 518 uint64_t Val) const { 519 // Convert 520 // leal x@tlsgd(, %ebx, 1), 521 // call __tls_get_addr@plt 522 // to 523 // movl %gs:0,%eax 524 // subl $x@ntpoff,%eax 525 const uint8_t Inst[] = { 526 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 527 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax 528 }; 529 memcpy(Loc - 3, Inst, sizeof(Inst)); 530 relocateOne(Loc + 5, R_386_32, Val); 531 } 532 533 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 534 uint64_t Val) const { 535 // Convert 536 // leal x@tlsgd(, %ebx, 1), 537 // call __tls_get_addr@plt 538 // to 539 // movl %gs:0, %eax 540 // addl x@gotntpoff(%ebx), %eax 541 const uint8_t Inst[] = { 542 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 543 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax 544 }; 545 memcpy(Loc - 3, Inst, sizeof(Inst)); 546 relocateOne(Loc + 5, R_386_32, Val); 547 } 548 549 // In some conditions, relocations can be optimized to avoid using GOT. 550 // This function does that for Initial Exec to Local Exec case. 551 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 552 uint64_t Val) const { 553 // Ulrich's document section 6.2 says that @gotntpoff can 554 // be used with MOVL or ADDL instructions. 555 // @indntpoff is similar to @gotntpoff, but for use in 556 // position dependent code. 557 uint8_t Reg = (Loc[-1] >> 3) & 7; 558 559 if (Type == R_386_TLS_IE) { 560 if (Loc[-1] == 0xa1) { 561 // "movl foo@indntpoff,%eax" -> "movl $foo,%eax" 562 // This case is different from the generic case below because 563 // this is a 5 byte instruction while below is 6 bytes. 564 Loc[-1] = 0xb8; 565 } else if (Loc[-2] == 0x8b) { 566 // "movl foo@indntpoff,%reg" -> "movl $foo,%reg" 567 Loc[-2] = 0xc7; 568 Loc[-1] = 0xc0 | Reg; 569 } else { 570 // "addl foo@indntpoff,%reg" -> "addl $foo,%reg" 571 Loc[-2] = 0x81; 572 Loc[-1] = 0xc0 | Reg; 573 } 574 } else { 575 assert(Type == R_386_TLS_GOTIE); 576 if (Loc[-2] == 0x8b) { 577 // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg" 578 Loc[-2] = 0xc7; 579 Loc[-1] = 0xc0 | Reg; 580 } else { 581 // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg" 582 Loc[-2] = 0x8d; 583 Loc[-1] = 0x80 | (Reg << 3) | Reg; 584 } 585 } 586 relocateOne(Loc, R_386_TLS_LE, Val); 587 } 588 589 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 590 uint64_t Val) const { 591 if (Type == R_386_TLS_LDO_32) { 592 relocateOne(Loc, R_386_TLS_LE, Val); 593 return; 594 } 595 596 // Convert 597 // leal foo(%reg),%eax 598 // call ___tls_get_addr 599 // to 600 // movl %gs:0,%eax 601 // nop 602 // leal 0(%esi,1),%esi 603 const uint8_t Inst[] = { 604 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax 605 0x90, // nop 606 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi 607 }; 608 memcpy(Loc - 2, Inst, sizeof(Inst)); 609 } 610 611 template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() { 612 CopyRel = R_X86_64_COPY; 613 GotRel = R_X86_64_GLOB_DAT; 614 PltRel = R_X86_64_JUMP_SLOT; 615 RelativeRel = R_X86_64_RELATIVE; 616 IRelativeRel = R_X86_64_IRELATIVE; 617 TlsGotRel = R_X86_64_TPOFF64; 618 TlsModuleIndexRel = R_X86_64_DTPMOD64; 619 TlsOffsetRel = R_X86_64_DTPOFF64; 620 GotEntrySize = 8; 621 GotPltEntrySize = 8; 622 PltEntrySize = 16; 623 PltHeaderSize = 16; 624 TlsGdRelaxSkip = 2; 625 // Align to the large page size (known as a superpage or huge page). 626 // FreeBSD automatically promotes large, superpage-aligned allocations. 627 DefaultImageBase = 0x200000; 628 } 629 630 template <class ELFT> 631 RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type, 632 const SymbolBody &S) const { 633 switch (Type) { 634 default: 635 return R_ABS; 636 case R_X86_64_TPOFF32: 637 return R_TLS; 638 case R_X86_64_TLSLD: 639 return R_TLSLD_PC; 640 case R_X86_64_TLSGD: 641 return R_TLSGD_PC; 642 case R_X86_64_SIZE32: 643 case R_X86_64_SIZE64: 644 return R_SIZE; 645 case R_X86_64_PLT32: 646 return R_PLT_PC; 647 case R_X86_64_PC32: 648 case R_X86_64_PC64: 649 return R_PC; 650 case R_X86_64_GOT32: 651 case R_X86_64_GOT64: 652 return R_GOT_FROM_END; 653 case R_X86_64_GOTPCREL: 654 case R_X86_64_GOTPCRELX: 655 case R_X86_64_REX_GOTPCRELX: 656 case R_X86_64_GOTTPOFF: 657 return R_GOT_PC; 658 case R_X86_64_NONE: 659 return R_HINT; 660 } 661 } 662 663 template <class ELFT> 664 void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const { 665 // The first entry holds the value of _DYNAMIC. It is not clear why that is 666 // required, but it is documented in the psabi and the glibc dynamic linker 667 // seems to use it (note that this is relevant for linking ld.so, not any 668 // other program). 669 write64le(Buf, In<ELFT>::Dynamic->getVA()); 670 } 671 672 template <class ELFT> 673 void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, 674 const SymbolBody &S) const { 675 // See comments in X86TargetInfo::writeGotPlt. 676 write32le(Buf, S.getPltVA<ELFT>() + 6); 677 } 678 679 template <class ELFT> 680 void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 681 const uint8_t PltData[] = { 682 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOT+8(%rip) 683 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOT+16(%rip) 684 0x0f, 0x1f, 0x40, 0x00 // nopl 0x0(rax) 685 }; 686 memcpy(Buf, PltData, sizeof(PltData)); 687 uint64_t Got = In<ELFT>::GotPlt->getVA(); 688 uint64_t Plt = In<ELFT>::Plt->getVA(); 689 write32le(Buf + 2, Got - Plt + 2); // GOT+8 690 write32le(Buf + 8, Got - Plt + 4); // GOT+16 691 } 692 693 template <class ELFT> 694 void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 695 uint64_t PltEntryAddr, int32_t Index, 696 unsigned RelOff) const { 697 const uint8_t Inst[] = { 698 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip) 699 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index> 700 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0] 701 }; 702 memcpy(Buf, Inst, sizeof(Inst)); 703 704 write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6); 705 write32le(Buf + 7, Index); 706 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 707 } 708 709 template <class ELFT> 710 bool X86_64TargetInfo<ELFT>::isPicRel(uint32_t Type) const { 711 return Type != R_X86_64_PC32 && Type != R_X86_64_32; 712 } 713 714 template <class ELFT> 715 bool X86_64TargetInfo<ELFT>::isTlsInitialExecRel(uint32_t Type) const { 716 return Type == R_X86_64_GOTTPOFF; 717 } 718 719 template <class ELFT> 720 bool X86_64TargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 721 return Type == R_X86_64_TLSGD; 722 } 723 724 template <class ELFT> 725 bool X86_64TargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 726 return Type == R_X86_64_DTPOFF32 || Type == R_X86_64_DTPOFF64 || 727 Type == R_X86_64_TLSLD; 728 } 729 730 template <class ELFT> 731 void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 732 uint64_t Val) const { 733 // Convert 734 // .byte 0x66 735 // leaq x@tlsgd(%rip), %rdi 736 // .word 0x6666 737 // rex64 738 // call __tls_get_addr@plt 739 // to 740 // mov %fs:0x0,%rax 741 // lea x@tpoff,%rax 742 const uint8_t Inst[] = { 743 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 744 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax 745 }; 746 memcpy(Loc - 4, Inst, sizeof(Inst)); 747 // The original code used a pc relative relocation and so we have to 748 // compensate for the -4 in had in the addend. 749 relocateOne(Loc + 8, R_X86_64_TPOFF32, Val + 4); 750 } 751 752 template <class ELFT> 753 void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 754 uint64_t Val) const { 755 // Convert 756 // .byte 0x66 757 // leaq x@tlsgd(%rip), %rdi 758 // .word 0x6666 759 // rex64 760 // call __tls_get_addr@plt 761 // to 762 // mov %fs:0x0,%rax 763 // addq x@tpoff,%rax 764 const uint8_t Inst[] = { 765 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 766 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax 767 }; 768 memcpy(Loc - 4, Inst, sizeof(Inst)); 769 // Both code sequences are PC relatives, but since we are moving the constant 770 // forward by 8 bytes we have to subtract the value by 8. 771 relocateOne(Loc + 8, R_X86_64_PC32, Val - 8); 772 } 773 774 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to 775 // R_X86_64_TPOFF32 so that it does not use GOT. 776 template <class ELFT> 777 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 778 uint64_t Val) const { 779 uint8_t *Inst = Loc - 3; 780 uint8_t Reg = Loc[-1] >> 3; 781 uint8_t *RegSlot = Loc - 1; 782 783 // Note that ADD with RSP or R12 is converted to ADD instead of LEA 784 // because LEA with these registers needs 4 bytes to encode and thus 785 // wouldn't fit the space. 786 787 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) { 788 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp" 789 memcpy(Inst, "\x48\x81\xc4", 3); 790 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) { 791 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12" 792 memcpy(Inst, "\x49\x81\xc4", 3); 793 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) { 794 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]" 795 memcpy(Inst, "\x4d\x8d", 2); 796 *RegSlot = 0x80 | (Reg << 3) | Reg; 797 } else if (memcmp(Inst, "\x48\x03", 2) == 0) { 798 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg" 799 memcpy(Inst, "\x48\x8d", 2); 800 *RegSlot = 0x80 | (Reg << 3) | Reg; 801 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) { 802 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]" 803 memcpy(Inst, "\x49\xc7", 2); 804 *RegSlot = 0xc0 | Reg; 805 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) { 806 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg" 807 memcpy(Inst, "\x48\xc7", 2); 808 *RegSlot = 0xc0 | Reg; 809 } else { 810 error(getErrorLocation(Loc - 3) + 811 "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only"); 812 } 813 814 // The original code used a PC relative relocation. 815 // Need to compensate for the -4 it had in the addend. 816 relocateOne(Loc, R_X86_64_TPOFF32, Val + 4); 817 } 818 819 template <class ELFT> 820 void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 821 uint64_t Val) const { 822 // Convert 823 // leaq bar@tlsld(%rip), %rdi 824 // callq __tls_get_addr@PLT 825 // leaq bar@dtpoff(%rax), %rcx 826 // to 827 // .word 0x6666 828 // .byte 0x66 829 // mov %fs:0,%rax 830 // leaq bar@tpoff(%rax), %rcx 831 if (Type == R_X86_64_DTPOFF64) { 832 write64le(Loc, Val); 833 return; 834 } 835 if (Type == R_X86_64_DTPOFF32) { 836 relocateOne(Loc, R_X86_64_TPOFF32, Val); 837 return; 838 } 839 840 const uint8_t Inst[] = { 841 0x66, 0x66, // .word 0x6666 842 0x66, // .byte 0x66 843 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax 844 }; 845 memcpy(Loc - 3, Inst, sizeof(Inst)); 846 } 847 848 template <class ELFT> 849 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 850 uint64_t Val) const { 851 switch (Type) { 852 case R_X86_64_32: 853 checkUInt<32>(Loc, Val, Type); 854 write32le(Loc, Val); 855 break; 856 case R_X86_64_32S: 857 case R_X86_64_TPOFF32: 858 case R_X86_64_GOT32: 859 case R_X86_64_GOTPCREL: 860 case R_X86_64_GOTPCRELX: 861 case R_X86_64_REX_GOTPCRELX: 862 case R_X86_64_PC32: 863 case R_X86_64_GOTTPOFF: 864 case R_X86_64_PLT32: 865 case R_X86_64_TLSGD: 866 case R_X86_64_TLSLD: 867 case R_X86_64_DTPOFF32: 868 case R_X86_64_SIZE32: 869 checkInt<32>(Loc, Val, Type); 870 write32le(Loc, Val); 871 break; 872 case R_X86_64_64: 873 case R_X86_64_DTPOFF64: 874 case R_X86_64_GLOB_DAT: 875 case R_X86_64_PC64: 876 case R_X86_64_SIZE64: 877 case R_X86_64_GOT64: 878 write64le(Loc, Val); 879 break; 880 default: 881 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 882 } 883 } 884 885 template <class ELFT> 886 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type, 887 const uint8_t *Data, 888 RelExpr RelExpr) const { 889 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX) 890 return RelExpr; 891 const uint8_t Op = Data[-2]; 892 const uint8_t ModRm = Data[-1]; 893 // FIXME: When PIC is disabled and foo is defined locally in the 894 // lower 32 bit address space, memory operand in mov can be converted into 895 // immediate operand. Otherwise, mov must be changed to lea. We support only 896 // latter relaxation at this moment. 897 if (Op == 0x8b) 898 return R_RELAX_GOT_PC; 899 // Relax call and jmp. 900 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25)) 901 return R_RELAX_GOT_PC; 902 903 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor. 904 // If PIC then no relaxation is available. 905 // We also don't relax test/binop instructions without REX byte, 906 // they are 32bit operations and not common to have. 907 assert(Type == R_X86_64_REX_GOTPCRELX); 908 return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC; 909 } 910 911 // A subset of relaxations can only be applied for no-PIC. This method 912 // handles such relaxations. Instructions encoding information was taken from: 913 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2" 914 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/ 915 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf) 916 template <class ELFT> 917 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val, 918 uint8_t Op, uint8_t ModRm) const { 919 const uint8_t Rex = Loc[-3]; 920 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg". 921 if (Op == 0x85) { 922 // See "TEST-Logical Compare" (4-428 Vol. 2B), 923 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension). 924 925 // ModR/M byte has form XX YYY ZZZ, where 926 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1). 927 // XX has different meanings: 928 // 00: The operand's memory address is in reg1. 929 // 01: The operand's memory address is reg1 + a byte-sized displacement. 930 // 10: The operand's memory address is reg1 + a word-sized displacement. 931 // 11: The operand is reg1 itself. 932 // If an instruction requires only one operand, the unused reg2 field 933 // holds extra opcode bits rather than a register code 934 // 0xC0 == 11 000 000 binary. 935 // 0x38 == 00 111 000 binary. 936 // We transfer reg2 to reg1 here as operand. 937 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3). 938 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte. 939 940 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32 941 // See "TEST-Logical Compare" (4-428 Vol. 2B). 942 Loc[-2] = 0xf7; 943 944 // Move R bit to the B bit in REX byte. 945 // REX byte is encoded as 0100WRXB, where 946 // 0100 is 4bit fixed pattern. 947 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the 948 // default operand size is used (which is 32-bit for most but not all 949 // instructions). 950 // REX.R This 1-bit value is an extension to the MODRM.reg field. 951 // REX.X This 1-bit value is an extension to the SIB.index field. 952 // REX.B This 1-bit value is an extension to the MODRM.rm field or the 953 // SIB.base field. 954 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A). 955 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 956 relocateOne(Loc, R_X86_64_PC32, Val); 957 return; 958 } 959 960 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub 961 // or xor operations. 962 963 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg". 964 // Logic is close to one for test instruction above, but we also 965 // write opcode extension here, see below for details. 966 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte. 967 968 // Primary opcode is 0x81, opcode extension is one of: 969 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB, 970 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP. 971 // This value was wrote to MODRM.reg in a line above. 972 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15), 973 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for 974 // descriptions about each operation. 975 Loc[-2] = 0x81; 976 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 977 relocateOne(Loc, R_X86_64_PC32, Val); 978 } 979 980 template <class ELFT> 981 void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const { 982 const uint8_t Op = Loc[-2]; 983 const uint8_t ModRm = Loc[-1]; 984 985 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg". 986 if (Op == 0x8b) { 987 Loc[-2] = 0x8d; 988 relocateOne(Loc, R_X86_64_PC32, Val); 989 return; 990 } 991 992 if (Op != 0xff) { 993 // We are relaxing a rip relative to an absolute, so compensate 994 // for the old -4 addend. 995 assert(!Config->Pic); 996 relaxGotNoPic(Loc, Val + 4, Op, ModRm); 997 return; 998 } 999 1000 // Convert call/jmp instructions. 1001 if (ModRm == 0x15) { 1002 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo". 1003 // Instead we convert to "addr32 call foo" where addr32 is an instruction 1004 // prefix. That makes result expression to be a single instruction. 1005 Loc[-2] = 0x67; // addr32 prefix 1006 Loc[-1] = 0xe8; // call 1007 relocateOne(Loc, R_X86_64_PC32, Val); 1008 return; 1009 } 1010 1011 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop". 1012 // jmp doesn't return, so it is fine to use nop here, it is just a stub. 1013 assert(ModRm == 0x25); 1014 Loc[-2] = 0xe9; // jmp 1015 Loc[3] = 0x90; // nop 1016 relocateOne(Loc - 1, R_X86_64_PC32, Val + 1); 1017 } 1018 1019 // Relocation masks following the #lo(value), #hi(value), #ha(value), 1020 // #higher(value), #highera(value), #highest(value), and #highesta(value) 1021 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 1022 // document. 1023 static uint16_t applyPPCLo(uint64_t V) { return V; } 1024 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; } 1025 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; } 1026 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; } 1027 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; } 1028 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; } 1029 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; } 1030 1031 PPCTargetInfo::PPCTargetInfo() {} 1032 1033 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1034 uint64_t Val) const { 1035 switch (Type) { 1036 case R_PPC_ADDR16_HA: 1037 write16be(Loc, applyPPCHa(Val)); 1038 break; 1039 case R_PPC_ADDR16_LO: 1040 write16be(Loc, applyPPCLo(Val)); 1041 break; 1042 case R_PPC_ADDR32: 1043 case R_PPC_REL32: 1044 write32be(Loc, Val); 1045 break; 1046 case R_PPC_REL24: 1047 or32be(Loc, Val & 0x3FFFFFC); 1048 break; 1049 default: 1050 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1051 } 1052 } 1053 1054 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1055 switch (Type) { 1056 case R_PPC_REL24: 1057 case R_PPC_REL32: 1058 return R_PC; 1059 default: 1060 return R_ABS; 1061 } 1062 } 1063 1064 PPC64TargetInfo::PPC64TargetInfo() { 1065 PltRel = GotRel = R_PPC64_GLOB_DAT; 1066 RelativeRel = R_PPC64_RELATIVE; 1067 GotEntrySize = 8; 1068 GotPltEntrySize = 8; 1069 PltEntrySize = 32; 1070 PltHeaderSize = 0; 1071 1072 // We need 64K pages (at least under glibc/Linux, the loader won't 1073 // set different permissions on a finer granularity than that). 1074 DefaultMaxPageSize = 65536; 1075 1076 // The PPC64 ELF ABI v1 spec, says: 1077 // 1078 // It is normally desirable to put segments with different characteristics 1079 // in separate 256 Mbyte portions of the address space, to give the 1080 // operating system full paging flexibility in the 64-bit address space. 1081 // 1082 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 1083 // use 0x10000000 as the starting address. 1084 DefaultImageBase = 0x10000000; 1085 } 1086 1087 static uint64_t PPC64TocOffset = 0x8000; 1088 1089 uint64_t getPPC64TocBase() { 1090 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 1091 // TOC starts where the first of these sections starts. We always create a 1092 // .got when we see a relocation that uses it, so for us the start is always 1093 // the .got. 1094 uint64_t TocVA = In<ELF64BE>::Got->getVA(); 1095 1096 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 1097 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 1098 // code (crt1.o) assumes that you can get from the TOC base to the 1099 // start of the .toc section with only a single (signed) 16-bit relocation. 1100 return TocVA + PPC64TocOffset; 1101 } 1102 1103 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1104 switch (Type) { 1105 default: 1106 return R_ABS; 1107 case R_PPC64_TOC16: 1108 case R_PPC64_TOC16_DS: 1109 case R_PPC64_TOC16_HA: 1110 case R_PPC64_TOC16_HI: 1111 case R_PPC64_TOC16_LO: 1112 case R_PPC64_TOC16_LO_DS: 1113 return R_GOTREL; 1114 case R_PPC64_TOC: 1115 return R_PPC_TOC; 1116 case R_PPC64_REL24: 1117 return R_PPC_PLT_OPD; 1118 } 1119 } 1120 1121 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1122 uint64_t PltEntryAddr, int32_t Index, 1123 unsigned RelOff) const { 1124 uint64_t Off = GotEntryAddr - getPPC64TocBase(); 1125 1126 // FIXME: What we should do, in theory, is get the offset of the function 1127 // descriptor in the .opd section, and use that as the offset from %r2 (the 1128 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will 1129 // be a pointer to the function descriptor in the .opd section. Using 1130 // this scheme is simpler, but requires an extra indirection per PLT dispatch. 1131 1132 write32be(Buf, 0xf8410028); // std %r2, 40(%r1) 1133 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha 1134 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11) 1135 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12) 1136 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11 1137 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12) 1138 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12) 1139 write32be(Buf + 28, 0x4e800420); // bctr 1140 } 1141 1142 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) { 1143 uint64_t V = Val - PPC64TocOffset; 1144 switch (Type) { 1145 case R_PPC64_TOC16: 1146 return {R_PPC64_ADDR16, V}; 1147 case R_PPC64_TOC16_DS: 1148 return {R_PPC64_ADDR16_DS, V}; 1149 case R_PPC64_TOC16_HA: 1150 return {R_PPC64_ADDR16_HA, V}; 1151 case R_PPC64_TOC16_HI: 1152 return {R_PPC64_ADDR16_HI, V}; 1153 case R_PPC64_TOC16_LO: 1154 return {R_PPC64_ADDR16_LO, V}; 1155 case R_PPC64_TOC16_LO_DS: 1156 return {R_PPC64_ADDR16_LO_DS, V}; 1157 default: 1158 return {Type, Val}; 1159 } 1160 } 1161 1162 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1163 uint64_t Val) const { 1164 // For a TOC-relative relocation, proceed in terms of the corresponding 1165 // ADDR16 relocation type. 1166 std::tie(Type, Val) = toAddr16Rel(Type, Val); 1167 1168 switch (Type) { 1169 case R_PPC64_ADDR14: { 1170 checkAlignment<4>(Loc, Val, Type); 1171 // Preserve the AA/LK bits in the branch instruction 1172 uint8_t AALK = Loc[3]; 1173 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 1174 break; 1175 } 1176 case R_PPC64_ADDR16: 1177 checkInt<16>(Loc, Val, Type); 1178 write16be(Loc, Val); 1179 break; 1180 case R_PPC64_ADDR16_DS: 1181 checkInt<16>(Loc, Val, Type); 1182 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3)); 1183 break; 1184 case R_PPC64_ADDR16_HA: 1185 case R_PPC64_REL16_HA: 1186 write16be(Loc, applyPPCHa(Val)); 1187 break; 1188 case R_PPC64_ADDR16_HI: 1189 case R_PPC64_REL16_HI: 1190 write16be(Loc, applyPPCHi(Val)); 1191 break; 1192 case R_PPC64_ADDR16_HIGHER: 1193 write16be(Loc, applyPPCHigher(Val)); 1194 break; 1195 case R_PPC64_ADDR16_HIGHERA: 1196 write16be(Loc, applyPPCHighera(Val)); 1197 break; 1198 case R_PPC64_ADDR16_HIGHEST: 1199 write16be(Loc, applyPPCHighest(Val)); 1200 break; 1201 case R_PPC64_ADDR16_HIGHESTA: 1202 write16be(Loc, applyPPCHighesta(Val)); 1203 break; 1204 case R_PPC64_ADDR16_LO: 1205 write16be(Loc, applyPPCLo(Val)); 1206 break; 1207 case R_PPC64_ADDR16_LO_DS: 1208 case R_PPC64_REL16_LO: 1209 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3)); 1210 break; 1211 case R_PPC64_ADDR32: 1212 case R_PPC64_REL32: 1213 checkInt<32>(Loc, Val, Type); 1214 write32be(Loc, Val); 1215 break; 1216 case R_PPC64_ADDR64: 1217 case R_PPC64_REL64: 1218 case R_PPC64_TOC: 1219 write64be(Loc, Val); 1220 break; 1221 case R_PPC64_REL24: { 1222 uint32_t Mask = 0x03FFFFFC; 1223 checkInt<24>(Loc, Val, Type); 1224 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask)); 1225 break; 1226 } 1227 default: 1228 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1229 } 1230 } 1231 1232 AArch64TargetInfo::AArch64TargetInfo() { 1233 CopyRel = R_AARCH64_COPY; 1234 RelativeRel = R_AARCH64_RELATIVE; 1235 IRelativeRel = R_AARCH64_IRELATIVE; 1236 GotRel = R_AARCH64_GLOB_DAT; 1237 PltRel = R_AARCH64_JUMP_SLOT; 1238 TlsDescRel = R_AARCH64_TLSDESC; 1239 TlsGotRel = R_AARCH64_TLS_TPREL64; 1240 GotEntrySize = 8; 1241 GotPltEntrySize = 8; 1242 PltEntrySize = 16; 1243 PltHeaderSize = 32; 1244 DefaultMaxPageSize = 65536; 1245 1246 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant 1247 // 1 of the tls structures and the tcb size is 16. 1248 TcbSize = 16; 1249 } 1250 1251 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type, 1252 const SymbolBody &S) const { 1253 switch (Type) { 1254 default: 1255 return R_ABS; 1256 case R_AARCH64_TLSDESC_ADR_PAGE21: 1257 return R_TLSDESC_PAGE; 1258 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1259 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1260 return R_TLSDESC; 1261 case R_AARCH64_TLSDESC_CALL: 1262 return R_TLSDESC_CALL; 1263 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1264 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1265 return R_TLS; 1266 case R_AARCH64_CALL26: 1267 case R_AARCH64_CONDBR19: 1268 case R_AARCH64_JUMP26: 1269 case R_AARCH64_TSTBR14: 1270 return R_PLT_PC; 1271 case R_AARCH64_PREL16: 1272 case R_AARCH64_PREL32: 1273 case R_AARCH64_PREL64: 1274 case R_AARCH64_ADR_PREL_LO21: 1275 return R_PC; 1276 case R_AARCH64_ADR_PREL_PG_HI21: 1277 return R_PAGE_PC; 1278 case R_AARCH64_LD64_GOT_LO12_NC: 1279 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1280 return R_GOT; 1281 case R_AARCH64_ADR_GOT_PAGE: 1282 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1283 return R_GOT_PAGE_PC; 1284 } 1285 } 1286 1287 RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 1288 RelExpr Expr) const { 1289 if (Expr == R_RELAX_TLS_GD_TO_IE) { 1290 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21) 1291 return R_RELAX_TLS_GD_TO_IE_PAGE_PC; 1292 return R_RELAX_TLS_GD_TO_IE_ABS; 1293 } 1294 return Expr; 1295 } 1296 1297 bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { 1298 switch (Type) { 1299 default: 1300 return false; 1301 case R_AARCH64_ADD_ABS_LO12_NC: 1302 case R_AARCH64_LD64_GOT_LO12_NC: 1303 case R_AARCH64_LDST128_ABS_LO12_NC: 1304 case R_AARCH64_LDST16_ABS_LO12_NC: 1305 case R_AARCH64_LDST32_ABS_LO12_NC: 1306 case R_AARCH64_LDST64_ABS_LO12_NC: 1307 case R_AARCH64_LDST8_ABS_LO12_NC: 1308 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1309 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1310 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1311 return true; 1312 } 1313 } 1314 1315 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1316 return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 || 1317 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; 1318 } 1319 1320 bool AArch64TargetInfo::isPicRel(uint32_t Type) const { 1321 return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64; 1322 } 1323 1324 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1325 write64le(Buf, In<ELF64LE>::Plt->getVA()); 1326 } 1327 1328 // Page(Expr) is the page address of the expression Expr, defined 1329 // as (Expr & ~0xFFF). (This applies even if the machine page size 1330 // supported by the platform has a different value.) 1331 uint64_t getAArch64Page(uint64_t Expr) { 1332 return Expr & (~static_cast<uint64_t>(0xFFF)); 1333 } 1334 1335 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const { 1336 const uint8_t PltData[] = { 1337 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 1338 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 1339 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 1340 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 1341 0x20, 0x02, 0x1f, 0xd6, // br x17 1342 0x1f, 0x20, 0x03, 0xd5, // nop 1343 0x1f, 0x20, 0x03, 0xd5, // nop 1344 0x1f, 0x20, 0x03, 0xd5 // nop 1345 }; 1346 memcpy(Buf, PltData, sizeof(PltData)); 1347 1348 uint64_t Got = In<ELF64LE>::GotPlt->getVA(); 1349 uint64_t Plt = In<ELF64LE>::Plt->getVA(); 1350 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 1351 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4)); 1352 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16); 1353 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16); 1354 } 1355 1356 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1357 uint64_t PltEntryAddr, int32_t Index, 1358 unsigned RelOff) const { 1359 const uint8_t Inst[] = { 1360 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 1361 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 1362 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n])) 1363 0x20, 0x02, 0x1f, 0xd6 // br x17 1364 }; 1365 memcpy(Buf, Inst, sizeof(Inst)); 1366 1367 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21, 1368 getAArch64Page(GotEntryAddr) - getAArch64Page(PltEntryAddr)); 1369 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotEntryAddr); 1370 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotEntryAddr); 1371 } 1372 1373 static void write32AArch64Addr(uint8_t *L, uint64_t Imm) { 1374 uint32_t ImmLo = (Imm & 0x3) << 29; 1375 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3; 1376 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3); 1377 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi); 1378 } 1379 1380 // Return the bits [Start, End] from Val shifted Start bits. 1381 // For instance, getBits(0xF0, 4, 8) returns 0xF. 1382 static uint64_t getBits(uint64_t Val, int Start, int End) { 1383 uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1; 1384 return (Val >> Start) & Mask; 1385 } 1386 1387 // Update the immediate field in a AARCH64 ldr, str, and add instruction. 1388 static void or32AArch64Imm(uint8_t *L, uint64_t Imm) { 1389 or32le(L, (Imm & 0xFFF) << 10); 1390 } 1391 1392 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1393 uint64_t Val) const { 1394 switch (Type) { 1395 case R_AARCH64_ABS16: 1396 case R_AARCH64_PREL16: 1397 checkIntUInt<16>(Loc, Val, Type); 1398 write16le(Loc, Val); 1399 break; 1400 case R_AARCH64_ABS32: 1401 case R_AARCH64_PREL32: 1402 checkIntUInt<32>(Loc, Val, Type); 1403 write32le(Loc, Val); 1404 break; 1405 case R_AARCH64_ABS64: 1406 case R_AARCH64_GLOB_DAT: 1407 case R_AARCH64_PREL64: 1408 write64le(Loc, Val); 1409 break; 1410 case R_AARCH64_ADD_ABS_LO12_NC: 1411 or32AArch64Imm(Loc, Val); 1412 break; 1413 case R_AARCH64_ADR_GOT_PAGE: 1414 case R_AARCH64_ADR_PREL_PG_HI21: 1415 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1416 case R_AARCH64_TLSDESC_ADR_PAGE21: 1417 checkInt<33>(Loc, Val, Type); 1418 write32AArch64Addr(Loc, Val >> 12); 1419 break; 1420 case R_AARCH64_ADR_PREL_LO21: 1421 checkInt<21>(Loc, Val, Type); 1422 write32AArch64Addr(Loc, Val); 1423 break; 1424 case R_AARCH64_CALL26: 1425 case R_AARCH64_JUMP26: 1426 checkInt<28>(Loc, Val, Type); 1427 or32le(Loc, (Val & 0x0FFFFFFC) >> 2); 1428 break; 1429 case R_AARCH64_CONDBR19: 1430 checkInt<21>(Loc, Val, Type); 1431 or32le(Loc, (Val & 0x1FFFFC) << 3); 1432 break; 1433 case R_AARCH64_LD64_GOT_LO12_NC: 1434 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1435 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1436 checkAlignment<8>(Loc, Val, Type); 1437 or32le(Loc, (Val & 0xFF8) << 7); 1438 break; 1439 case R_AARCH64_LDST8_ABS_LO12_NC: 1440 or32AArch64Imm(Loc, getBits(Val, 0, 11)); 1441 break; 1442 case R_AARCH64_LDST16_ABS_LO12_NC: 1443 or32AArch64Imm(Loc, getBits(Val, 1, 11)); 1444 break; 1445 case R_AARCH64_LDST32_ABS_LO12_NC: 1446 or32AArch64Imm(Loc, getBits(Val, 2, 11)); 1447 break; 1448 case R_AARCH64_LDST64_ABS_LO12_NC: 1449 or32AArch64Imm(Loc, getBits(Val, 3, 11)); 1450 break; 1451 case R_AARCH64_LDST128_ABS_LO12_NC: 1452 or32AArch64Imm(Loc, getBits(Val, 4, 11)); 1453 break; 1454 case R_AARCH64_MOVW_UABS_G0_NC: 1455 or32le(Loc, (Val & 0xFFFF) << 5); 1456 break; 1457 case R_AARCH64_MOVW_UABS_G1_NC: 1458 or32le(Loc, (Val & 0xFFFF0000) >> 11); 1459 break; 1460 case R_AARCH64_MOVW_UABS_G2_NC: 1461 or32le(Loc, (Val & 0xFFFF00000000) >> 27); 1462 break; 1463 case R_AARCH64_MOVW_UABS_G3: 1464 or32le(Loc, (Val & 0xFFFF000000000000) >> 43); 1465 break; 1466 case R_AARCH64_TSTBR14: 1467 checkInt<16>(Loc, Val, Type); 1468 or32le(Loc, (Val & 0xFFFC) << 3); 1469 break; 1470 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1471 checkInt<24>(Loc, Val, Type); 1472 or32AArch64Imm(Loc, Val >> 12); 1473 break; 1474 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1475 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1476 or32AArch64Imm(Loc, Val); 1477 break; 1478 default: 1479 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1480 } 1481 } 1482 1483 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 1484 uint64_t Val) const { 1485 // TLSDESC Global-Dynamic relocation are in the form: 1486 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1487 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1488 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1489 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1490 // blr x1 1491 // And it can optimized to: 1492 // movz x0, #0x0, lsl #16 1493 // movk x0, #0x10 1494 // nop 1495 // nop 1496 checkUInt<32>(Loc, Val, Type); 1497 1498 switch (Type) { 1499 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1500 case R_AARCH64_TLSDESC_CALL: 1501 write32le(Loc, 0xd503201f); // nop 1502 return; 1503 case R_AARCH64_TLSDESC_ADR_PAGE21: 1504 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz 1505 return; 1506 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1507 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk 1508 return; 1509 default: 1510 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1511 } 1512 } 1513 1514 void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 1515 uint64_t Val) const { 1516 // TLSDESC Global-Dynamic relocation are in the form: 1517 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1518 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1519 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1520 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1521 // blr x1 1522 // And it can optimized to: 1523 // adrp x0, :gottprel:v 1524 // ldr x0, [x0, :gottprel_lo12:v] 1525 // nop 1526 // nop 1527 1528 switch (Type) { 1529 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1530 case R_AARCH64_TLSDESC_CALL: 1531 write32le(Loc, 0xd503201f); // nop 1532 break; 1533 case R_AARCH64_TLSDESC_ADR_PAGE21: 1534 write32le(Loc, 0x90000000); // adrp 1535 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val); 1536 break; 1537 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1538 write32le(Loc, 0xf9400000); // ldr 1539 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val); 1540 break; 1541 default: 1542 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1543 } 1544 } 1545 1546 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 1547 uint64_t Val) const { 1548 checkUInt<32>(Loc, Val, Type); 1549 1550 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) { 1551 // Generate MOVZ. 1552 uint32_t RegNo = read32le(Loc) & 0x1f; 1553 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5)); 1554 return; 1555 } 1556 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) { 1557 // Generate MOVK. 1558 uint32_t RegNo = read32le(Loc) & 0x1f; 1559 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5)); 1560 return; 1561 } 1562 llvm_unreachable("invalid relocation for TLS IE to LE relaxation"); 1563 } 1564 1565 AMDGPUTargetInfo::AMDGPUTargetInfo() { 1566 RelativeRel = R_AMDGPU_REL64; 1567 GotRel = R_AMDGPU_ABS64; 1568 GotEntrySize = 8; 1569 } 1570 1571 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1572 uint64_t Val) const { 1573 switch (Type) { 1574 case R_AMDGPU_ABS32: 1575 case R_AMDGPU_GOTPCREL: 1576 case R_AMDGPU_GOTPCREL32_LO: 1577 case R_AMDGPU_REL32: 1578 case R_AMDGPU_REL32_LO: 1579 write32le(Loc, Val); 1580 break; 1581 case R_AMDGPU_ABS64: 1582 write64le(Loc, Val); 1583 break; 1584 case R_AMDGPU_GOTPCREL32_HI: 1585 case R_AMDGPU_REL32_HI: 1586 write32le(Loc, Val >> 32); 1587 break; 1588 default: 1589 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1590 } 1591 } 1592 1593 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1594 switch (Type) { 1595 case R_AMDGPU_ABS32: 1596 case R_AMDGPU_ABS64: 1597 return R_ABS; 1598 case R_AMDGPU_REL32: 1599 case R_AMDGPU_REL32_LO: 1600 case R_AMDGPU_REL32_HI: 1601 return R_PC; 1602 case R_AMDGPU_GOTPCREL: 1603 case R_AMDGPU_GOTPCREL32_LO: 1604 case R_AMDGPU_GOTPCREL32_HI: 1605 return R_GOT_PC; 1606 default: 1607 fatal("do not know how to handle relocation " + Twine(Type)); 1608 } 1609 } 1610 1611 ARMTargetInfo::ARMTargetInfo() { 1612 CopyRel = R_ARM_COPY; 1613 RelativeRel = R_ARM_RELATIVE; 1614 IRelativeRel = R_ARM_IRELATIVE; 1615 GotRel = R_ARM_GLOB_DAT; 1616 PltRel = R_ARM_JUMP_SLOT; 1617 TlsGotRel = R_ARM_TLS_TPOFF32; 1618 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32; 1619 TlsOffsetRel = R_ARM_TLS_DTPOFF32; 1620 GotEntrySize = 4; 1621 GotPltEntrySize = 4; 1622 PltEntrySize = 16; 1623 PltHeaderSize = 20; 1624 // ARM uses Variant 1 TLS 1625 TcbSize = 8; 1626 NeedsThunks = true; 1627 } 1628 1629 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1630 switch (Type) { 1631 default: 1632 return R_ABS; 1633 case R_ARM_THM_JUMP11: 1634 return R_PC; 1635 case R_ARM_CALL: 1636 case R_ARM_JUMP24: 1637 case R_ARM_PC24: 1638 case R_ARM_PLT32: 1639 case R_ARM_PREL31: 1640 case R_ARM_THM_JUMP19: 1641 case R_ARM_THM_JUMP24: 1642 case R_ARM_THM_CALL: 1643 return R_PLT_PC; 1644 case R_ARM_GOTOFF32: 1645 // (S + A) - GOT_ORG 1646 return R_GOTREL; 1647 case R_ARM_GOT_BREL: 1648 // GOT(S) + A - GOT_ORG 1649 return R_GOT_OFF; 1650 case R_ARM_GOT_PREL: 1651 case R_ARM_TLS_IE32: 1652 // GOT(S) + A - P 1653 return R_GOT_PC; 1654 case R_ARM_TARGET1: 1655 return Config->Target1Rel ? R_PC : R_ABS; 1656 case R_ARM_TARGET2: 1657 if (Config->Target2 == Target2Policy::Rel) 1658 return R_PC; 1659 if (Config->Target2 == Target2Policy::Abs) 1660 return R_ABS; 1661 return R_GOT_PC; 1662 case R_ARM_TLS_GD32: 1663 return R_TLSGD_PC; 1664 case R_ARM_TLS_LDM32: 1665 return R_TLSLD_PC; 1666 case R_ARM_BASE_PREL: 1667 // B(S) + A - P 1668 // FIXME: currently B(S) assumed to be .got, this may not hold for all 1669 // platforms. 1670 return R_GOTONLY_PC; 1671 case R_ARM_MOVW_PREL_NC: 1672 case R_ARM_MOVT_PREL: 1673 case R_ARM_REL32: 1674 case R_ARM_THM_MOVW_PREL_NC: 1675 case R_ARM_THM_MOVT_PREL: 1676 return R_PC; 1677 case R_ARM_NONE: 1678 return R_HINT; 1679 case R_ARM_TLS_LE32: 1680 return R_TLS; 1681 } 1682 } 1683 1684 bool ARMTargetInfo::isPicRel(uint32_t Type) const { 1685 return (Type == R_ARM_TARGET1 && !Config->Target1Rel) || 1686 (Type == R_ARM_ABS32); 1687 } 1688 1689 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const { 1690 if (Type == R_ARM_TARGET1 && !Config->Target1Rel) 1691 return R_ARM_ABS32; 1692 if (Type == R_ARM_ABS32) 1693 return Type; 1694 // Keep it going with a dummy value so that we can find more reloc errors. 1695 return R_ARM_ABS32; 1696 } 1697 1698 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1699 write32le(Buf, In<ELF32LE>::Plt->getVA()); 1700 } 1701 1702 void ARMTargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 1703 // An ARM entry is the address of the ifunc resolver function. 1704 write32le(Buf, S.getVA<ELF32LE>()); 1705 } 1706 1707 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const { 1708 const uint8_t PltData[] = { 1709 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]! 1710 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2 1711 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr 1712 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8] 1713 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8 1714 }; 1715 memcpy(Buf, PltData, sizeof(PltData)); 1716 uint64_t GotPlt = In<ELF32LE>::GotPlt->getVA(); 1717 uint64_t L1 = In<ELF32LE>::Plt->getVA() + 8; 1718 write32le(Buf + 16, GotPlt - L1 - 8); 1719 } 1720 1721 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1722 uint64_t PltEntryAddr, int32_t Index, 1723 unsigned RelOff) const { 1724 // FIXME: Using simple code sequence with simple relocations. 1725 // There is a more optimal sequence but it requires support for the group 1726 // relocations. See ELF for the ARM Architecture Appendix A.3 1727 const uint8_t PltData[] = { 1728 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2 1729 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc 1730 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip] 1731 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8 1732 }; 1733 memcpy(Buf, PltData, sizeof(PltData)); 1734 uint64_t L1 = PltEntryAddr + 4; 1735 write32le(Buf + 12, GotEntryAddr - L1 - 8); 1736 } 1737 1738 RelExpr ARMTargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType, 1739 const InputFile &File, 1740 const SymbolBody &S) const { 1741 // If S is an undefined weak symbol in an executable we don't need a Thunk. 1742 // In a DSO calls to undefined symbols, including weak ones get PLT entries 1743 // which may need a thunk. 1744 if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak() 1745 && !Config->Shared) 1746 return Expr; 1747 // A state change from ARM to Thumb and vice versa must go through an 1748 // interworking thunk if the relocation type is not R_ARM_CALL or 1749 // R_ARM_THM_CALL. 1750 switch (RelocType) { 1751 case R_ARM_PC24: 1752 case R_ARM_PLT32: 1753 case R_ARM_JUMP24: 1754 // Source is ARM, all PLT entries are ARM so no interworking required. 1755 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb). 1756 if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1)) 1757 return R_THUNK_PC; 1758 break; 1759 case R_ARM_THM_JUMP19: 1760 case R_ARM_THM_JUMP24: 1761 // Source is Thumb, all PLT entries are ARM so interworking is required. 1762 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM). 1763 if (Expr == R_PLT_PC) 1764 return R_THUNK_PLT_PC; 1765 if ((S.getVA<ELF32LE>() & 1) == 0) 1766 return R_THUNK_PC; 1767 break; 1768 } 1769 return Expr; 1770 } 1771 1772 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1773 uint64_t Val) const { 1774 switch (Type) { 1775 case R_ARM_ABS32: 1776 case R_ARM_BASE_PREL: 1777 case R_ARM_GLOB_DAT: 1778 case R_ARM_GOTOFF32: 1779 case R_ARM_GOT_BREL: 1780 case R_ARM_GOT_PREL: 1781 case R_ARM_REL32: 1782 case R_ARM_RELATIVE: 1783 case R_ARM_TARGET1: 1784 case R_ARM_TARGET2: 1785 case R_ARM_TLS_GD32: 1786 case R_ARM_TLS_IE32: 1787 case R_ARM_TLS_LDM32: 1788 case R_ARM_TLS_LDO32: 1789 case R_ARM_TLS_LE32: 1790 case R_ARM_TLS_TPOFF32: 1791 write32le(Loc, Val); 1792 break; 1793 case R_ARM_TLS_DTPMOD32: 1794 write32le(Loc, 1); 1795 break; 1796 case R_ARM_PREL31: 1797 checkInt<31>(Loc, Val, Type); 1798 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000)); 1799 break; 1800 case R_ARM_CALL: 1801 // R_ARM_CALL is used for BL and BLX instructions, depending on the 1802 // value of bit 0 of Val, we must select a BL or BLX instruction 1803 if (Val & 1) { 1804 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX. 1805 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' 1806 checkInt<26>(Loc, Val, Type); 1807 write32le(Loc, 0xfa000000 | // opcode 1808 ((Val & 2) << 23) | // H 1809 ((Val >> 2) & 0x00ffffff)); // imm24 1810 break; 1811 } 1812 if ((read32le(Loc) & 0xfe000000) == 0xfa000000) 1813 // BLX (always unconditional) instruction to an ARM Target, select an 1814 // unconditional BL. 1815 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff)); 1816 // fall through as BL encoding is shared with B 1817 case R_ARM_JUMP24: 1818 case R_ARM_PC24: 1819 case R_ARM_PLT32: 1820 checkInt<26>(Loc, Val, Type); 1821 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff)); 1822 break; 1823 case R_ARM_THM_JUMP11: 1824 checkInt<12>(Loc, Val, Type); 1825 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff)); 1826 break; 1827 case R_ARM_THM_JUMP19: 1828 // Encoding T3: Val = S:J2:J1:imm6:imm11:0 1829 checkInt<21>(Loc, Val, Type); 1830 write16le(Loc, 1831 (read16le(Loc) & 0xfbc0) | // opcode cond 1832 ((Val >> 10) & 0x0400) | // S 1833 ((Val >> 12) & 0x003f)); // imm6 1834 write16le(Loc + 2, 1835 0x8000 | // opcode 1836 ((Val >> 8) & 0x0800) | // J2 1837 ((Val >> 5) & 0x2000) | // J1 1838 ((Val >> 1) & 0x07ff)); // imm11 1839 break; 1840 case R_ARM_THM_CALL: 1841 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the 1842 // value of bit 0 of Val, we must select a BL or BLX instruction 1843 if ((Val & 1) == 0) { 1844 // Ensure BLX destination is 4-byte aligned. As BLX instruction may 1845 // only be two byte aligned. This must be done before overflow check 1846 Val = alignTo(Val, 4); 1847 } 1848 // Bit 12 is 0 for BLX, 1 for BL 1849 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12); 1850 // Fall through as rest of encoding is the same as B.W 1851 case R_ARM_THM_JUMP24: 1852 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 1853 // FIXME: Use of I1 and I2 require v6T2ops 1854 checkInt<25>(Loc, Val, Type); 1855 write16le(Loc, 1856 0xf000 | // opcode 1857 ((Val >> 14) & 0x0400) | // S 1858 ((Val >> 12) & 0x03ff)); // imm10 1859 write16le(Loc + 2, 1860 (read16le(Loc + 2) & 0xd000) | // opcode 1861 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1 1862 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2 1863 ((Val >> 1) & 0x07ff)); // imm11 1864 break; 1865 case R_ARM_MOVW_ABS_NC: 1866 case R_ARM_MOVW_PREL_NC: 1867 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) | 1868 (Val & 0x0fff)); 1869 break; 1870 case R_ARM_MOVT_ABS: 1871 case R_ARM_MOVT_PREL: 1872 checkInt<32>(Loc, Val, Type); 1873 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | 1874 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff)); 1875 break; 1876 case R_ARM_THM_MOVT_ABS: 1877 case R_ARM_THM_MOVT_PREL: 1878 // Encoding T1: A = imm4:i:imm3:imm8 1879 checkInt<32>(Loc, Val, Type); 1880 write16le(Loc, 1881 0xf2c0 | // opcode 1882 ((Val >> 17) & 0x0400) | // i 1883 ((Val >> 28) & 0x000f)); // imm4 1884 write16le(Loc + 2, 1885 (read16le(Loc + 2) & 0x8f00) | // opcode 1886 ((Val >> 12) & 0x7000) | // imm3 1887 ((Val >> 16) & 0x00ff)); // imm8 1888 break; 1889 case R_ARM_THM_MOVW_ABS_NC: 1890 case R_ARM_THM_MOVW_PREL_NC: 1891 // Encoding T3: A = imm4:i:imm3:imm8 1892 write16le(Loc, 1893 0xf240 | // opcode 1894 ((Val >> 1) & 0x0400) | // i 1895 ((Val >> 12) & 0x000f)); // imm4 1896 write16le(Loc + 2, 1897 (read16le(Loc + 2) & 0x8f00) | // opcode 1898 ((Val << 4) & 0x7000) | // imm3 1899 (Val & 0x00ff)); // imm8 1900 break; 1901 default: 1902 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1903 } 1904 } 1905 1906 uint64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf, 1907 uint32_t Type) const { 1908 switch (Type) { 1909 default: 1910 return 0; 1911 case R_ARM_ABS32: 1912 case R_ARM_BASE_PREL: 1913 case R_ARM_GOTOFF32: 1914 case R_ARM_GOT_BREL: 1915 case R_ARM_GOT_PREL: 1916 case R_ARM_REL32: 1917 case R_ARM_TARGET1: 1918 case R_ARM_TARGET2: 1919 case R_ARM_TLS_GD32: 1920 case R_ARM_TLS_LDM32: 1921 case R_ARM_TLS_LDO32: 1922 case R_ARM_TLS_IE32: 1923 case R_ARM_TLS_LE32: 1924 return SignExtend64<32>(read32le(Buf)); 1925 case R_ARM_PREL31: 1926 return SignExtend64<31>(read32le(Buf)); 1927 case R_ARM_CALL: 1928 case R_ARM_JUMP24: 1929 case R_ARM_PC24: 1930 case R_ARM_PLT32: 1931 return SignExtend64<26>(read32le(Buf) << 2); 1932 case R_ARM_THM_JUMP11: 1933 return SignExtend64<12>(read16le(Buf) << 1); 1934 case R_ARM_THM_JUMP19: { 1935 // Encoding T3: A = S:J2:J1:imm10:imm6:0 1936 uint16_t Hi = read16le(Buf); 1937 uint16_t Lo = read16le(Buf + 2); 1938 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S 1939 ((Lo & 0x0800) << 8) | // J2 1940 ((Lo & 0x2000) << 5) | // J1 1941 ((Hi & 0x003f) << 12) | // imm6 1942 ((Lo & 0x07ff) << 1)); // imm11:0 1943 } 1944 case R_ARM_THM_CALL: 1945 case R_ARM_THM_JUMP24: { 1946 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 1947 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) 1948 // FIXME: I1 and I2 require v6T2ops 1949 uint16_t Hi = read16le(Buf); 1950 uint16_t Lo = read16le(Buf + 2); 1951 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S 1952 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1 1953 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2 1954 ((Hi & 0x003ff) << 12) | // imm0 1955 ((Lo & 0x007ff) << 1)); // imm11:0 1956 } 1957 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and 1958 // MOVT is in the range -32768 <= A < 32768 1959 case R_ARM_MOVW_ABS_NC: 1960 case R_ARM_MOVT_ABS: 1961 case R_ARM_MOVW_PREL_NC: 1962 case R_ARM_MOVT_PREL: { 1963 uint64_t Val = read32le(Buf) & 0x000f0fff; 1964 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff)); 1965 } 1966 case R_ARM_THM_MOVW_ABS_NC: 1967 case R_ARM_THM_MOVT_ABS: 1968 case R_ARM_THM_MOVW_PREL_NC: 1969 case R_ARM_THM_MOVT_PREL: { 1970 // Encoding T3: A = imm4:i:imm3:imm8 1971 uint16_t Hi = read16le(Buf); 1972 uint16_t Lo = read16le(Buf + 2); 1973 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4 1974 ((Hi & 0x0400) << 1) | // i 1975 ((Lo & 0x7000) >> 4) | // imm3 1976 (Lo & 0x00ff)); // imm8 1977 } 1978 } 1979 } 1980 1981 bool ARMTargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 1982 return Type == R_ARM_TLS_LDO32 || Type == R_ARM_TLS_LDM32; 1983 } 1984 1985 bool ARMTargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 1986 return Type == R_ARM_TLS_GD32; 1987 } 1988 1989 bool ARMTargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1990 return Type == R_ARM_TLS_IE32; 1991 } 1992 1993 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() { 1994 GotPltHeaderEntriesNum = 2; 1995 DefaultMaxPageSize = 65536; 1996 GotEntrySize = sizeof(typename ELFT::uint); 1997 GotPltEntrySize = sizeof(typename ELFT::uint); 1998 PltEntrySize = 16; 1999 PltHeaderSize = 32; 2000 CopyRel = R_MIPS_COPY; 2001 PltRel = R_MIPS_JUMP_SLOT; 2002 NeedsThunks = true; 2003 if (ELFT::Is64Bits) { 2004 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 2005 TlsGotRel = R_MIPS_TLS_TPREL64; 2006 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 2007 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 2008 } else { 2009 RelativeRel = R_MIPS_REL32; 2010 TlsGotRel = R_MIPS_TLS_TPREL32; 2011 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 2012 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 2013 } 2014 } 2015 2016 template <class ELFT> 2017 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type, 2018 const SymbolBody &S) const { 2019 // See comment in the calculateMipsRelChain. 2020 if (ELFT::Is64Bits || Config->MipsN32Abi) 2021 Type &= 0xff; 2022 switch (Type) { 2023 default: 2024 return R_ABS; 2025 case R_MIPS_JALR: 2026 return R_HINT; 2027 case R_MIPS_GPREL16: 2028 case R_MIPS_GPREL32: 2029 return R_MIPS_GOTREL; 2030 case R_MIPS_26: 2031 return R_PLT; 2032 case R_MIPS_HI16: 2033 case R_MIPS_LO16: 2034 case R_MIPS_GOT_OFST: 2035 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 2036 // offset between start of function and 'gp' value which by default 2037 // equal to the start of .got section. In that case we consider these 2038 // relocations as relative. 2039 if (&S == ElfSym<ELFT>::MipsGpDisp) 2040 return R_PC; 2041 return R_ABS; 2042 case R_MIPS_PC32: 2043 case R_MIPS_PC16: 2044 case R_MIPS_PC19_S2: 2045 case R_MIPS_PC21_S2: 2046 case R_MIPS_PC26_S2: 2047 case R_MIPS_PCHI16: 2048 case R_MIPS_PCLO16: 2049 return R_PC; 2050 case R_MIPS_GOT16: 2051 if (S.isLocal()) 2052 return R_MIPS_GOT_LOCAL_PAGE; 2053 // fallthrough 2054 case R_MIPS_CALL16: 2055 case R_MIPS_GOT_DISP: 2056 case R_MIPS_TLS_GOTTPREL: 2057 return R_MIPS_GOT_OFF; 2058 case R_MIPS_CALL_HI16: 2059 case R_MIPS_CALL_LO16: 2060 case R_MIPS_GOT_HI16: 2061 case R_MIPS_GOT_LO16: 2062 return R_MIPS_GOT_OFF32; 2063 case R_MIPS_GOT_PAGE: 2064 return R_MIPS_GOT_LOCAL_PAGE; 2065 case R_MIPS_TLS_GD: 2066 return R_MIPS_TLSGD; 2067 case R_MIPS_TLS_LDM: 2068 return R_MIPS_TLSLD; 2069 } 2070 } 2071 2072 template <class ELFT> bool MipsTargetInfo<ELFT>::isPicRel(uint32_t Type) const { 2073 return Type == R_MIPS_32 || Type == R_MIPS_64; 2074 } 2075 2076 template <class ELFT> 2077 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const { 2078 return RelativeRel; 2079 } 2080 2081 template <class ELFT> 2082 bool MipsTargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 2083 return Type == R_MIPS_TLS_LDM; 2084 } 2085 2086 template <class ELFT> 2087 bool MipsTargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 2088 return Type == R_MIPS_TLS_GD; 2089 } 2090 2091 template <class ELFT> 2092 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 2093 write32<ELFT::TargetEndianness>(Buf, In<ELFT>::Plt->getVA()); 2094 } 2095 2096 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2097 static int64_t getPcRelocAddend(const uint8_t *Loc) { 2098 uint32_t Instr = read32<E>(Loc); 2099 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2100 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT); 2101 } 2102 2103 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2104 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) { 2105 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2106 uint32_t Instr = read32<E>(Loc); 2107 if (SHIFT > 0) 2108 checkAlignment<(1 << SHIFT)>(Loc, V, Type); 2109 checkInt<BSIZE + SHIFT>(Loc, V, Type); 2110 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask)); 2111 } 2112 2113 template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) { 2114 uint32_t Instr = read32<E>(Loc); 2115 uint16_t Res = ((V + 0x8000) >> 16) & 0xffff; 2116 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2117 } 2118 2119 template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) { 2120 uint32_t Instr = read32<E>(Loc); 2121 uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff; 2122 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2123 } 2124 2125 template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) { 2126 uint32_t Instr = read32<E>(Loc); 2127 uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff; 2128 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2129 } 2130 2131 template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) { 2132 uint32_t Instr = read32<E>(Loc); 2133 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff)); 2134 } 2135 2136 template <class ELFT> static bool isMipsR6() { 2137 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf); 2138 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH; 2139 return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6; 2140 } 2141 2142 template <class ELFT> 2143 void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 2144 const endianness E = ELFT::TargetEndianness; 2145 if (Config->MipsN32Abi) { 2146 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 2147 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 2148 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 2149 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 2150 } else { 2151 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 2152 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 2153 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 2154 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 2155 } 2156 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 2157 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 2158 write32<E>(Buf + 24, 0x0320f809); // jalr $25 2159 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 2160 uint64_t Got = In<ELFT>::GotPlt->getVA(); 2161 writeMipsHi16<E>(Buf, Got); 2162 writeMipsLo16<E>(Buf + 4, Got); 2163 writeMipsLo16<E>(Buf + 8, Got); 2164 } 2165 2166 template <class ELFT> 2167 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 2168 uint64_t PltEntryAddr, int32_t Index, 2169 unsigned RelOff) const { 2170 const endianness E = ELFT::TargetEndianness; 2171 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 2172 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 2173 // jr $25 2174 write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008); 2175 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 2176 writeMipsHi16<E>(Buf, GotEntryAddr); 2177 writeMipsLo16<E>(Buf + 4, GotEntryAddr); 2178 writeMipsLo16<E>(Buf + 12, GotEntryAddr); 2179 } 2180 2181 template <class ELFT> 2182 RelExpr MipsTargetInfo<ELFT>::getThunkExpr(RelExpr Expr, uint32_t Type, 2183 const InputFile &File, 2184 const SymbolBody &S) const { 2185 // Any MIPS PIC code function is invoked with its address in register $t9. 2186 // So if we have a branch instruction from non-PIC code to the PIC one 2187 // we cannot make the jump directly and need to create a small stubs 2188 // to save the target function address. 2189 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 2190 if (Type != R_MIPS_26) 2191 return Expr; 2192 auto *F = dyn_cast<ELFFileBase<ELFT>>(&File); 2193 if (!F) 2194 return Expr; 2195 // If current file has PIC code, LA25 stub is not required. 2196 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 2197 return Expr; 2198 auto *D = dyn_cast<DefinedRegular<ELFT>>(&S); 2199 // LA25 is required if target file has PIC code 2200 // or target symbol is a PIC symbol. 2201 return D && D->isMipsPIC() ? R_THUNK_ABS : Expr; 2202 } 2203 2204 template <class ELFT> 2205 uint64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf, 2206 uint32_t Type) const { 2207 const endianness E = ELFT::TargetEndianness; 2208 switch (Type) { 2209 default: 2210 return 0; 2211 case R_MIPS_32: 2212 case R_MIPS_GPREL32: 2213 case R_MIPS_TLS_DTPREL32: 2214 case R_MIPS_TLS_TPREL32: 2215 return read32<E>(Buf); 2216 case R_MIPS_26: 2217 // FIXME (simon): If the relocation target symbol is not a PLT entry 2218 // we should use another expression for calculation: 2219 // ((A << 2) | (P & 0xf0000000)) >> 2 2220 return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2); 2221 case R_MIPS_GPREL16: 2222 case R_MIPS_LO16: 2223 case R_MIPS_PCLO16: 2224 case R_MIPS_TLS_DTPREL_HI16: 2225 case R_MIPS_TLS_DTPREL_LO16: 2226 case R_MIPS_TLS_TPREL_HI16: 2227 case R_MIPS_TLS_TPREL_LO16: 2228 return SignExtend64<16>(read32<E>(Buf)); 2229 case R_MIPS_PC16: 2230 return getPcRelocAddend<E, 16, 2>(Buf); 2231 case R_MIPS_PC19_S2: 2232 return getPcRelocAddend<E, 19, 2>(Buf); 2233 case R_MIPS_PC21_S2: 2234 return getPcRelocAddend<E, 21, 2>(Buf); 2235 case R_MIPS_PC26_S2: 2236 return getPcRelocAddend<E, 26, 2>(Buf); 2237 case R_MIPS_PC32: 2238 return getPcRelocAddend<E, 32, 0>(Buf); 2239 } 2240 } 2241 2242 static std::pair<uint32_t, uint64_t> 2243 calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) { 2244 // MIPS N64 ABI packs multiple relocations into the single relocation 2245 // record. In general, all up to three relocations can have arbitrary 2246 // types. In fact, Clang and GCC uses only a few combinations. For now, 2247 // we support two of them. That is allow to pass at least all LLVM 2248 // test suite cases. 2249 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 2250 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 2251 // The first relocation is a 'real' relocation which is calculated 2252 // using the corresponding symbol's value. The second and the third 2253 // relocations used to modify result of the first one: extend it to 2254 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 2255 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 2256 uint32_t Type2 = (Type >> 8) & 0xff; 2257 uint32_t Type3 = (Type >> 16) & 0xff; 2258 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 2259 return std::make_pair(Type, Val); 2260 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 2261 return std::make_pair(Type2, Val); 2262 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 2263 return std::make_pair(Type3, -Val); 2264 error(getErrorLocation(Loc) + "unsupported relocations combination " + 2265 Twine(Type)); 2266 return std::make_pair(Type & 0xff, Val); 2267 } 2268 2269 template <class ELFT> 2270 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 2271 uint64_t Val) const { 2272 const endianness E = ELFT::TargetEndianness; 2273 // Thread pointer and DRP offsets from the start of TLS data area. 2274 // https://www.linux-mips.org/wiki/NPTL 2275 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 2276 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64) 2277 Val -= 0x8000; 2278 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 2279 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64) 2280 Val -= 0x7000; 2281 if (ELFT::Is64Bits || Config->MipsN32Abi) 2282 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 2283 switch (Type) { 2284 case R_MIPS_32: 2285 case R_MIPS_GPREL32: 2286 case R_MIPS_TLS_DTPREL32: 2287 case R_MIPS_TLS_TPREL32: 2288 write32<E>(Loc, Val); 2289 break; 2290 case R_MIPS_64: 2291 case R_MIPS_TLS_DTPREL64: 2292 case R_MIPS_TLS_TPREL64: 2293 write64<E>(Loc, Val); 2294 break; 2295 case R_MIPS_26: 2296 write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff)); 2297 break; 2298 case R_MIPS_GOT_DISP: 2299 case R_MIPS_GOT_PAGE: 2300 case R_MIPS_GOT16: 2301 case R_MIPS_GPREL16: 2302 case R_MIPS_TLS_GD: 2303 case R_MIPS_TLS_LDM: 2304 checkInt<16>(Loc, Val, Type); 2305 // fallthrough 2306 case R_MIPS_CALL16: 2307 case R_MIPS_CALL_LO16: 2308 case R_MIPS_GOT_LO16: 2309 case R_MIPS_GOT_OFST: 2310 case R_MIPS_LO16: 2311 case R_MIPS_PCLO16: 2312 case R_MIPS_TLS_DTPREL_LO16: 2313 case R_MIPS_TLS_GOTTPREL: 2314 case R_MIPS_TLS_TPREL_LO16: 2315 writeMipsLo16<E>(Loc, Val); 2316 break; 2317 case R_MIPS_CALL_HI16: 2318 case R_MIPS_GOT_HI16: 2319 case R_MIPS_HI16: 2320 case R_MIPS_PCHI16: 2321 case R_MIPS_TLS_DTPREL_HI16: 2322 case R_MIPS_TLS_TPREL_HI16: 2323 writeMipsHi16<E>(Loc, Val); 2324 break; 2325 case R_MIPS_HIGHER: 2326 writeMipsHigher<E>(Loc, Val); 2327 break; 2328 case R_MIPS_HIGHEST: 2329 writeMipsHighest<E>(Loc, Val); 2330 break; 2331 case R_MIPS_JALR: 2332 // Ignore this optimization relocation for now 2333 break; 2334 case R_MIPS_PC16: 2335 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val); 2336 break; 2337 case R_MIPS_PC19_S2: 2338 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val); 2339 break; 2340 case R_MIPS_PC21_S2: 2341 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val); 2342 break; 2343 case R_MIPS_PC26_S2: 2344 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val); 2345 break; 2346 case R_MIPS_PC32: 2347 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val); 2348 break; 2349 default: 2350 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 2351 } 2352 } 2353 2354 template <class ELFT> 2355 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const { 2356 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST; 2357 } 2358 } 2359 } 2360