1 //===- Target.cpp ---------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Machine-specific things, such as applying relocations, creation of 11 // GOT or PLT entries, etc., are handled in this file. 12 // 13 // Refer the ELF spec for the single letter variables, S, A or P, used 14 // in this file. 15 // 16 // Some functions defined in this file has "relaxTls" as part of their names. 17 // They do peephole optimization for TLS variables by rewriting instructions. 18 // They are not part of the ABI but optional optimization, so you can skip 19 // them if you are not interested in how TLS variables are optimized. 20 // See the following paper for the details. 21 // 22 // Ulrich Drepper, ELF Handling For Thread-Local Storage 23 // http://www.akkadia.org/drepper/tls.pdf 24 // 25 //===----------------------------------------------------------------------===// 26 27 #include "Target.h" 28 #include "Error.h" 29 #include "InputFiles.h" 30 #include "Memory.h" 31 #include "OutputSections.h" 32 #include "SymbolTable.h" 33 #include "Symbols.h" 34 #include "SyntheticSections.h" 35 #include "Thunks.h" 36 #include "Writer.h" 37 #include "llvm/ADT/ArrayRef.h" 38 #include "llvm/BinaryFormat/ELF.h" 39 #include "llvm/Object/ELF.h" 40 #include "llvm/Support/Endian.h" 41 42 using namespace llvm; 43 using namespace llvm::object; 44 using namespace llvm::support::endian; 45 using namespace llvm::ELF; 46 47 std::string lld::toString(uint32_t Type) { 48 StringRef S = getELFRelocationTypeName(elf::Config->EMachine, Type); 49 if (S == "Unknown") 50 return ("Unknown (" + Twine(Type) + ")").str(); 51 return S; 52 } 53 54 namespace lld { 55 namespace elf { 56 57 TargetInfo *Target; 58 59 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); } 60 static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); } 61 62 template <class ELFT> static std::string getErrorLoc(const uint8_t *Loc) { 63 for (InputSectionBase *D : InputSections) { 64 auto *IS = dyn_cast_or_null<InputSection>(D); 65 if (!IS || !IS->getParent()) 66 continue; 67 68 uint8_t *ISLoc = IS->getParent()->Loc + IS->OutSecOff; 69 if (ISLoc <= Loc && Loc < ISLoc + IS->getSize()) 70 return IS->template getLocation<ELFT>(Loc - ISLoc) + ": "; 71 } 72 return ""; 73 } 74 75 static std::string getErrorLocation(const uint8_t *Loc) { 76 switch (Config->EKind) { 77 case ELF32LEKind: 78 return getErrorLoc<ELF32LE>(Loc); 79 case ELF32BEKind: 80 return getErrorLoc<ELF32BE>(Loc); 81 case ELF64LEKind: 82 return getErrorLoc<ELF64LE>(Loc); 83 case ELF64BEKind: 84 return getErrorLoc<ELF64BE>(Loc); 85 default: 86 llvm_unreachable("unknown ELF type"); 87 } 88 } 89 90 template <unsigned N> 91 static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) { 92 if (!isInt<N>(V)) 93 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 94 " out of range"); 95 } 96 97 template <unsigned N> 98 static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 99 if (!isUInt<N>(V)) 100 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 101 " out of range"); 102 } 103 104 template <unsigned N> 105 static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 106 if (!isInt<N>(V) && !isUInt<N>(V)) 107 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 108 " out of range"); 109 } 110 111 template <unsigned N> 112 static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) { 113 if ((V & (N - 1)) != 0) 114 error(getErrorLocation(Loc) + "improper alignment for relocation " + 115 toString(Type)); 116 } 117 118 namespace { 119 class X86TargetInfo final : public TargetInfo { 120 public: 121 X86TargetInfo(); 122 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, 123 const uint8_t *Loc) const override; 124 int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 125 void writeGotPltHeader(uint8_t *Buf) const override; 126 uint32_t getDynRel(uint32_t Type) const override; 127 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 128 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 129 void writePltHeader(uint8_t *Buf) const override; 130 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 131 int32_t Index, unsigned RelOff) const override; 132 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 133 134 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 135 RelExpr Expr) const override; 136 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 137 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 138 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 139 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 140 }; 141 142 template <class ELFT> class X86_64TargetInfo final : public TargetInfo { 143 public: 144 X86_64TargetInfo(); 145 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, 146 const uint8_t *Loc) const override; 147 bool isPicRel(uint32_t Type) const override; 148 void writeGotPltHeader(uint8_t *Buf) const override; 149 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 150 void writePltHeader(uint8_t *Buf) const override; 151 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 152 int32_t Index, unsigned RelOff) const override; 153 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 154 155 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 156 RelExpr Expr) const override; 157 void relaxGot(uint8_t *Loc, uint64_t Val) const override; 158 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 159 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 160 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 161 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 162 163 private: 164 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op, 165 uint8_t ModRm) const; 166 }; 167 168 class PPCTargetInfo final : public TargetInfo { 169 public: 170 PPCTargetInfo(); 171 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 172 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, 173 const uint8_t *Loc) const override; 174 }; 175 176 class PPC64TargetInfo final : public TargetInfo { 177 public: 178 PPC64TargetInfo(); 179 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, 180 const uint8_t *Loc) const override; 181 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 182 int32_t Index, unsigned RelOff) const override; 183 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 184 }; 185 186 class AArch64TargetInfo final : public TargetInfo { 187 public: 188 AArch64TargetInfo(); 189 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, 190 const uint8_t *Loc) const override; 191 bool isPicRel(uint32_t Type) const override; 192 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 193 void writePltHeader(uint8_t *Buf) const override; 194 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 195 int32_t Index, unsigned RelOff) const override; 196 bool usesOnlyLowPageBits(uint32_t Type) const override; 197 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 198 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 199 RelExpr Expr) const override; 200 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 201 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 202 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 203 }; 204 205 class AMDGPUTargetInfo final : public TargetInfo { 206 public: 207 AMDGPUTargetInfo(); 208 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 209 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, 210 const uint8_t *Loc) const override; 211 }; 212 213 class ARMTargetInfo final : public TargetInfo { 214 public: 215 ARMTargetInfo(); 216 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, 217 const uint8_t *Loc) const override; 218 bool isPicRel(uint32_t Type) const override; 219 uint32_t getDynRel(uint32_t Type) const override; 220 int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 221 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 222 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 223 void writePltHeader(uint8_t *Buf) const override; 224 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 225 int32_t Index, unsigned RelOff) const override; 226 void addPltSymbols(InputSectionBase *IS, uint64_t Off) const override; 227 void addPltHeaderSymbols(InputSectionBase *ISD) const override; 228 bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File, 229 const SymbolBody &S) const override; 230 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 231 }; 232 233 template <class ELFT> class MipsTargetInfo final : public TargetInfo { 234 public: 235 MipsTargetInfo(); 236 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, 237 const uint8_t *Loc) const override; 238 int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 239 bool isPicRel(uint32_t Type) const override; 240 uint32_t getDynRel(uint32_t Type) const override; 241 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 242 void writePltHeader(uint8_t *Buf) const override; 243 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 244 int32_t Index, unsigned RelOff) const override; 245 bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File, 246 const SymbolBody &S) const override; 247 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 248 bool usesOnlyLowPageBits(uint32_t Type) const override; 249 }; 250 } // anonymous namespace 251 252 TargetInfo *createTarget() { 253 switch (Config->EMachine) { 254 case EM_386: 255 case EM_IAMCU: 256 return make<X86TargetInfo>(); 257 case EM_AARCH64: 258 return make<AArch64TargetInfo>(); 259 case EM_AMDGPU: 260 return make<AMDGPUTargetInfo>(); 261 case EM_ARM: 262 return make<ARMTargetInfo>(); 263 case EM_MIPS: 264 switch (Config->EKind) { 265 case ELF32LEKind: 266 return make<MipsTargetInfo<ELF32LE>>(); 267 case ELF32BEKind: 268 return make<MipsTargetInfo<ELF32BE>>(); 269 case ELF64LEKind: 270 return make<MipsTargetInfo<ELF64LE>>(); 271 case ELF64BEKind: 272 return make<MipsTargetInfo<ELF64BE>>(); 273 default: 274 fatal("unsupported MIPS target"); 275 } 276 case EM_PPC: 277 return make<PPCTargetInfo>(); 278 case EM_PPC64: 279 return make<PPC64TargetInfo>(); 280 case EM_X86_64: 281 if (Config->EKind == ELF32LEKind) 282 return make<X86_64TargetInfo<ELF32LE>>(); 283 return make<X86_64TargetInfo<ELF64LE>>(); 284 } 285 fatal("unknown target machine"); 286 } 287 288 TargetInfo::~TargetInfo() {} 289 290 int64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const { 291 return 0; 292 } 293 294 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; } 295 296 bool TargetInfo::needsThunk(RelExpr Expr, uint32_t RelocType, 297 const InputFile *File, const SymbolBody &S) const { 298 return false; 299 } 300 301 void TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 302 writeGotPlt(Buf, S); 303 } 304 305 RelExpr TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 306 RelExpr Expr) const { 307 return Expr; 308 } 309 310 void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const { 311 llvm_unreachable("Should not have claimed to be relaxable"); 312 } 313 314 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 315 uint64_t Val) const { 316 llvm_unreachable("Should not have claimed to be relaxable"); 317 } 318 319 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 320 uint64_t Val) const { 321 llvm_unreachable("Should not have claimed to be relaxable"); 322 } 323 324 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 325 uint64_t Val) const { 326 llvm_unreachable("Should not have claimed to be relaxable"); 327 } 328 329 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 330 uint64_t Val) const { 331 llvm_unreachable("Should not have claimed to be relaxable"); 332 } 333 334 X86TargetInfo::X86TargetInfo() { 335 CopyRel = R_386_COPY; 336 GotRel = R_386_GLOB_DAT; 337 PltRel = R_386_JUMP_SLOT; 338 IRelativeRel = R_386_IRELATIVE; 339 RelativeRel = R_386_RELATIVE; 340 TlsGotRel = R_386_TLS_TPOFF; 341 TlsModuleIndexRel = R_386_TLS_DTPMOD32; 342 TlsOffsetRel = R_386_TLS_DTPOFF32; 343 GotEntrySize = 4; 344 GotPltEntrySize = 4; 345 PltEntrySize = 16; 346 PltHeaderSize = 16; 347 TlsGdRelaxSkip = 2; 348 // 0xCC is the "int3" (call debug exception handler) instruction. 349 TrapInstr = 0xcccccccc; 350 } 351 352 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S, 353 const uint8_t *Loc) const { 354 switch (Type) { 355 case R_386_8: 356 case R_386_16: 357 case R_386_32: 358 case R_386_TLS_LDO_32: 359 return R_ABS; 360 case R_386_TLS_GD: 361 return R_TLSGD; 362 case R_386_TLS_LDM: 363 return R_TLSLD; 364 case R_386_PLT32: 365 return R_PLT_PC; 366 case R_386_PC8: 367 case R_386_PC16: 368 case R_386_PC32: 369 return R_PC; 370 case R_386_GOTPC: 371 return R_GOTONLY_PC_FROM_END; 372 case R_386_TLS_IE: 373 return R_GOT; 374 case R_386_GOT32: 375 case R_386_GOT32X: 376 // These relocations can be calculated in two different ways. 377 // Usual calculation is G + A - GOT what means an offset in GOT table 378 // (R_GOT_FROM_END). When instruction pointed by relocation has no base 379 // register, then relocations can be used when PIC code is disabled. In that 380 // case calculation is G + A, it resolves to an address of entry in GOT 381 // (R_GOT) and not an offset. 382 // 383 // To check that instruction has no base register we scan ModR/M byte. 384 // See "Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte" 385 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/ 386 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf) 387 if ((Loc[-1] & 0xc7) != 0x5) 388 return R_GOT_FROM_END; 389 if (Config->Pic) 390 error(toString(S.File) + ": relocation " + toString(Type) + " against '" + 391 S.getName() + 392 "' without base register can not be used when PIC enabled"); 393 return R_GOT; 394 case R_386_TLS_GOTIE: 395 return R_GOT_FROM_END; 396 case R_386_GOTOFF: 397 return R_GOTREL_FROM_END; 398 case R_386_TLS_LE: 399 return R_TLS; 400 case R_386_TLS_LE_32: 401 return R_NEG_TLS; 402 case R_386_NONE: 403 return R_NONE; 404 default: 405 error(toString(S.File) + ": unknown relocation type: " + toString(Type)); 406 return R_HINT; 407 } 408 } 409 410 RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 411 RelExpr Expr) const { 412 switch (Expr) { 413 default: 414 return Expr; 415 case R_RELAX_TLS_GD_TO_IE: 416 return R_RELAX_TLS_GD_TO_IE_END; 417 case R_RELAX_TLS_GD_TO_LE: 418 return R_RELAX_TLS_GD_TO_LE_NEG; 419 } 420 } 421 422 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const { 423 write32le(Buf, InX::Dynamic->getVA()); 424 } 425 426 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const { 427 // Entries in .got.plt initially points back to the corresponding 428 // PLT entries with a fixed offset to skip the first instruction. 429 write32le(Buf, S.getPltVA() + 6); 430 } 431 432 void X86TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 433 // An x86 entry is the address of the ifunc resolver function. 434 write32le(Buf, S.getVA()); 435 } 436 437 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const { 438 if (Type == R_386_TLS_LE) 439 return R_386_TLS_TPOFF; 440 if (Type == R_386_TLS_LE_32) 441 return R_386_TLS_TPOFF32; 442 return Type; 443 } 444 445 void X86TargetInfo::writePltHeader(uint8_t *Buf) const { 446 if (Config->Pic) { 447 const uint8_t V[] = { 448 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl GOTPLT+4(%ebx) 449 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *GOTPLT+8(%ebx) 450 0x90, 0x90, 0x90, 0x90 // nop 451 }; 452 memcpy(Buf, V, sizeof(V)); 453 454 uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize(); 455 uint32_t GotPlt = InX::GotPlt->getVA() - Ebx; 456 write32le(Buf + 2, GotPlt + 4); 457 write32le(Buf + 8, GotPlt + 8); 458 return; 459 } 460 461 const uint8_t PltData[] = { 462 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOTPLT+4) 463 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOTPLT+8) 464 0x90, 0x90, 0x90, 0x90 // nop 465 }; 466 memcpy(Buf, PltData, sizeof(PltData)); 467 uint32_t GotPlt = InX::GotPlt->getVA(); 468 write32le(Buf + 2, GotPlt + 4); 469 write32le(Buf + 8, GotPlt + 8); 470 } 471 472 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 473 uint64_t PltEntryAddr, int32_t Index, 474 unsigned RelOff) const { 475 const uint8_t Inst[] = { 476 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx) 477 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset 478 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC 479 }; 480 memcpy(Buf, Inst, sizeof(Inst)); 481 482 if (Config->Pic) { 483 // jmp *foo@GOT(%ebx) 484 uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize(); 485 Buf[1] = 0xa3; 486 write32le(Buf + 2, GotPltEntryAddr - Ebx); 487 } else { 488 // jmp *foo_in_GOT 489 Buf[1] = 0x25; 490 write32le(Buf + 2, GotPltEntryAddr); 491 } 492 493 write32le(Buf + 7, RelOff); 494 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 495 } 496 497 int64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf, 498 uint32_t Type) const { 499 switch (Type) { 500 default: 501 return 0; 502 case R_386_8: 503 case R_386_PC8: 504 return SignExtend64<8>(*Buf); 505 case R_386_16: 506 case R_386_PC16: 507 return SignExtend64<16>(read16le(Buf)); 508 case R_386_32: 509 case R_386_GOT32: 510 case R_386_GOT32X: 511 case R_386_GOTOFF: 512 case R_386_GOTPC: 513 case R_386_PC32: 514 case R_386_PLT32: 515 case R_386_TLS_LDO_32: 516 case R_386_TLS_LE: 517 return SignExtend64<32>(read32le(Buf)); 518 } 519 } 520 521 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 522 uint64_t Val) const { 523 // R_386_{PC,}{8,16} are not part of the i386 psABI, but they are 524 // being used for some 16-bit programs such as boot loaders, so 525 // we want to support them. 526 switch (Type) { 527 case R_386_8: 528 checkUInt<8>(Loc, Val, Type); 529 *Loc = Val; 530 break; 531 case R_386_PC8: 532 checkInt<8>(Loc, Val, Type); 533 *Loc = Val; 534 break; 535 case R_386_16: 536 checkUInt<16>(Loc, Val, Type); 537 write16le(Loc, Val); 538 break; 539 case R_386_PC16: 540 checkInt<16>(Loc, Val, Type); 541 write16le(Loc, Val); 542 break; 543 default: 544 checkInt<32>(Loc, Val, Type); 545 write32le(Loc, Val); 546 } 547 } 548 549 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 550 uint64_t Val) const { 551 // Convert 552 // leal x@tlsgd(, %ebx, 1), 553 // call __tls_get_addr@plt 554 // to 555 // movl %gs:0,%eax 556 // subl $x@ntpoff,%eax 557 const uint8_t Inst[] = { 558 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 559 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax 560 }; 561 memcpy(Loc - 3, Inst, sizeof(Inst)); 562 write32le(Loc + 5, Val); 563 } 564 565 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 566 uint64_t Val) const { 567 // Convert 568 // leal x@tlsgd(, %ebx, 1), 569 // call __tls_get_addr@plt 570 // to 571 // movl %gs:0, %eax 572 // addl x@gotntpoff(%ebx), %eax 573 const uint8_t Inst[] = { 574 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 575 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax 576 }; 577 memcpy(Loc - 3, Inst, sizeof(Inst)); 578 write32le(Loc + 5, Val); 579 } 580 581 // In some conditions, relocations can be optimized to avoid using GOT. 582 // This function does that for Initial Exec to Local Exec case. 583 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 584 uint64_t Val) const { 585 // Ulrich's document section 6.2 says that @gotntpoff can 586 // be used with MOVL or ADDL instructions. 587 // @indntpoff is similar to @gotntpoff, but for use in 588 // position dependent code. 589 uint8_t Reg = (Loc[-1] >> 3) & 7; 590 591 if (Type == R_386_TLS_IE) { 592 if (Loc[-1] == 0xa1) { 593 // "movl foo@indntpoff,%eax" -> "movl $foo,%eax" 594 // This case is different from the generic case below because 595 // this is a 5 byte instruction while below is 6 bytes. 596 Loc[-1] = 0xb8; 597 } else if (Loc[-2] == 0x8b) { 598 // "movl foo@indntpoff,%reg" -> "movl $foo,%reg" 599 Loc[-2] = 0xc7; 600 Loc[-1] = 0xc0 | Reg; 601 } else { 602 // "addl foo@indntpoff,%reg" -> "addl $foo,%reg" 603 Loc[-2] = 0x81; 604 Loc[-1] = 0xc0 | Reg; 605 } 606 } else { 607 assert(Type == R_386_TLS_GOTIE); 608 if (Loc[-2] == 0x8b) { 609 // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg" 610 Loc[-2] = 0xc7; 611 Loc[-1] = 0xc0 | Reg; 612 } else { 613 // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg" 614 Loc[-2] = 0x8d; 615 Loc[-1] = 0x80 | (Reg << 3) | Reg; 616 } 617 } 618 write32le(Loc, Val); 619 } 620 621 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 622 uint64_t Val) const { 623 if (Type == R_386_TLS_LDO_32) { 624 write32le(Loc, Val); 625 return; 626 } 627 628 // Convert 629 // leal foo(%reg),%eax 630 // call ___tls_get_addr 631 // to 632 // movl %gs:0,%eax 633 // nop 634 // leal 0(%esi,1),%esi 635 const uint8_t Inst[] = { 636 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax 637 0x90, // nop 638 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi 639 }; 640 memcpy(Loc - 2, Inst, sizeof(Inst)); 641 } 642 643 template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() { 644 CopyRel = R_X86_64_COPY; 645 GotRel = R_X86_64_GLOB_DAT; 646 PltRel = R_X86_64_JUMP_SLOT; 647 RelativeRel = R_X86_64_RELATIVE; 648 IRelativeRel = R_X86_64_IRELATIVE; 649 TlsGotRel = R_X86_64_TPOFF64; 650 TlsModuleIndexRel = R_X86_64_DTPMOD64; 651 TlsOffsetRel = R_X86_64_DTPOFF64; 652 GotEntrySize = 8; 653 GotPltEntrySize = 8; 654 PltEntrySize = 16; 655 PltHeaderSize = 16; 656 TlsGdRelaxSkip = 2; 657 // Align to the large page size (known as a superpage or huge page). 658 // FreeBSD automatically promotes large, superpage-aligned allocations. 659 DefaultImageBase = 0x200000; 660 // 0xCC is the "int3" (call debug exception handler) instruction. 661 TrapInstr = 0xcccccccc; 662 } 663 664 template <class ELFT> 665 RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S, 666 const uint8_t *Loc) const { 667 switch (Type) { 668 case R_X86_64_8: 669 case R_X86_64_16: 670 case R_X86_64_32: 671 case R_X86_64_32S: 672 case R_X86_64_64: 673 case R_X86_64_DTPOFF32: 674 case R_X86_64_DTPOFF64: 675 return R_ABS; 676 case R_X86_64_TPOFF32: 677 return R_TLS; 678 case R_X86_64_TLSLD: 679 return R_TLSLD_PC; 680 case R_X86_64_TLSGD: 681 return R_TLSGD_PC; 682 case R_X86_64_SIZE32: 683 case R_X86_64_SIZE64: 684 return R_SIZE; 685 case R_X86_64_PLT32: 686 return R_PLT_PC; 687 case R_X86_64_PC32: 688 case R_X86_64_PC64: 689 return R_PC; 690 case R_X86_64_GOT32: 691 case R_X86_64_GOT64: 692 return R_GOT_FROM_END; 693 case R_X86_64_GOTPCREL: 694 case R_X86_64_GOTPCRELX: 695 case R_X86_64_REX_GOTPCRELX: 696 case R_X86_64_GOTTPOFF: 697 return R_GOT_PC; 698 case R_X86_64_NONE: 699 return R_NONE; 700 default: 701 error(toString(S.File) + ": unknown relocation type: " + toString(Type)); 702 return R_HINT; 703 } 704 } 705 706 template <class ELFT> 707 void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const { 708 // The first entry holds the value of _DYNAMIC. It is not clear why that is 709 // required, but it is documented in the psabi and the glibc dynamic linker 710 // seems to use it (note that this is relevant for linking ld.so, not any 711 // other program). 712 write64le(Buf, InX::Dynamic->getVA()); 713 } 714 715 template <class ELFT> 716 void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, 717 const SymbolBody &S) const { 718 // See comments in X86TargetInfo::writeGotPlt. 719 write32le(Buf, S.getPltVA() + 6); 720 } 721 722 template <class ELFT> 723 void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 724 const uint8_t PltData[] = { 725 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOTPLT+8(%rip) 726 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOTPLT+16(%rip) 727 0x0f, 0x1f, 0x40, 0x00 // nop 728 }; 729 memcpy(Buf, PltData, sizeof(PltData)); 730 uint64_t GotPlt = InX::GotPlt->getVA(); 731 uint64_t Plt = InX::Plt->getVA(); 732 write32le(Buf + 2, GotPlt - Plt + 2); // GOTPLT+8 733 write32le(Buf + 8, GotPlt - Plt + 4); // GOTPLT+16 734 } 735 736 template <class ELFT> 737 void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 738 uint64_t PltEntryAddr, int32_t Index, 739 unsigned RelOff) const { 740 const uint8_t Inst[] = { 741 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip) 742 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index> 743 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0] 744 }; 745 memcpy(Buf, Inst, sizeof(Inst)); 746 747 write32le(Buf + 2, GotPltEntryAddr - PltEntryAddr - 6); 748 write32le(Buf + 7, Index); 749 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 750 } 751 752 template <class ELFT> 753 bool X86_64TargetInfo<ELFT>::isPicRel(uint32_t Type) const { 754 return Type != R_X86_64_PC32 && Type != R_X86_64_32 && 755 Type != R_X86_64_TPOFF32; 756 } 757 758 template <class ELFT> 759 void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 760 uint64_t Val) const { 761 // Convert 762 // .byte 0x66 763 // leaq x@tlsgd(%rip), %rdi 764 // .word 0x6666 765 // rex64 766 // call __tls_get_addr@plt 767 // to 768 // mov %fs:0x0,%rax 769 // lea x@tpoff,%rax 770 const uint8_t Inst[] = { 771 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 772 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax 773 }; 774 memcpy(Loc - 4, Inst, sizeof(Inst)); 775 776 // The original code used a pc relative relocation and so we have to 777 // compensate for the -4 in had in the addend. 778 write32le(Loc + 8, Val + 4); 779 } 780 781 template <class ELFT> 782 void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 783 uint64_t Val) const { 784 // Convert 785 // .byte 0x66 786 // leaq x@tlsgd(%rip), %rdi 787 // .word 0x6666 788 // rex64 789 // call __tls_get_addr@plt 790 // to 791 // mov %fs:0x0,%rax 792 // addq x@tpoff,%rax 793 const uint8_t Inst[] = { 794 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 795 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax 796 }; 797 memcpy(Loc - 4, Inst, sizeof(Inst)); 798 799 // Both code sequences are PC relatives, but since we are moving the constant 800 // forward by 8 bytes we have to subtract the value by 8. 801 write32le(Loc + 8, Val - 8); 802 } 803 804 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to 805 // R_X86_64_TPOFF32 so that it does not use GOT. 806 template <class ELFT> 807 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 808 uint64_t Val) const { 809 uint8_t *Inst = Loc - 3; 810 uint8_t Reg = Loc[-1] >> 3; 811 uint8_t *RegSlot = Loc - 1; 812 813 // Note that ADD with RSP or R12 is converted to ADD instead of LEA 814 // because LEA with these registers needs 4 bytes to encode and thus 815 // wouldn't fit the space. 816 817 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) { 818 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp" 819 memcpy(Inst, "\x48\x81\xc4", 3); 820 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) { 821 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12" 822 memcpy(Inst, "\x49\x81\xc4", 3); 823 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) { 824 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]" 825 memcpy(Inst, "\x4d\x8d", 2); 826 *RegSlot = 0x80 | (Reg << 3) | Reg; 827 } else if (memcmp(Inst, "\x48\x03", 2) == 0) { 828 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg" 829 memcpy(Inst, "\x48\x8d", 2); 830 *RegSlot = 0x80 | (Reg << 3) | Reg; 831 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) { 832 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]" 833 memcpy(Inst, "\x49\xc7", 2); 834 *RegSlot = 0xc0 | Reg; 835 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) { 836 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg" 837 memcpy(Inst, "\x48\xc7", 2); 838 *RegSlot = 0xc0 | Reg; 839 } else { 840 error(getErrorLocation(Loc - 3) + 841 "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only"); 842 } 843 844 // The original code used a PC relative relocation. 845 // Need to compensate for the -4 it had in the addend. 846 write32le(Loc, Val + 4); 847 } 848 849 template <class ELFT> 850 void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 851 uint64_t Val) const { 852 // Convert 853 // leaq bar@tlsld(%rip), %rdi 854 // callq __tls_get_addr@PLT 855 // leaq bar@dtpoff(%rax), %rcx 856 // to 857 // .word 0x6666 858 // .byte 0x66 859 // mov %fs:0,%rax 860 // leaq bar@tpoff(%rax), %rcx 861 if (Type == R_X86_64_DTPOFF64) { 862 write64le(Loc, Val); 863 return; 864 } 865 if (Type == R_X86_64_DTPOFF32) { 866 write32le(Loc, Val); 867 return; 868 } 869 870 const uint8_t Inst[] = { 871 0x66, 0x66, // .word 0x6666 872 0x66, // .byte 0x66 873 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax 874 }; 875 memcpy(Loc - 3, Inst, sizeof(Inst)); 876 } 877 878 template <class ELFT> 879 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 880 uint64_t Val) const { 881 switch (Type) { 882 case R_X86_64_8: 883 checkUInt<8>(Loc, Val, Type); 884 *Loc = Val; 885 break; 886 case R_X86_64_16: 887 checkUInt<16>(Loc, Val, Type); 888 write16le(Loc, Val); 889 break; 890 case R_X86_64_32: 891 checkUInt<32>(Loc, Val, Type); 892 write32le(Loc, Val); 893 break; 894 case R_X86_64_32S: 895 case R_X86_64_TPOFF32: 896 case R_X86_64_GOT32: 897 case R_X86_64_GOTPCREL: 898 case R_X86_64_GOTPCRELX: 899 case R_X86_64_REX_GOTPCRELX: 900 case R_X86_64_PC32: 901 case R_X86_64_GOTTPOFF: 902 case R_X86_64_PLT32: 903 case R_X86_64_TLSGD: 904 case R_X86_64_TLSLD: 905 case R_X86_64_DTPOFF32: 906 case R_X86_64_SIZE32: 907 checkInt<32>(Loc, Val, Type); 908 write32le(Loc, Val); 909 break; 910 case R_X86_64_64: 911 case R_X86_64_DTPOFF64: 912 case R_X86_64_GLOB_DAT: 913 case R_X86_64_PC64: 914 case R_X86_64_SIZE64: 915 case R_X86_64_GOT64: 916 write64le(Loc, Val); 917 break; 918 default: 919 llvm_unreachable("unexpected relocation"); 920 } 921 } 922 923 template <class ELFT> 924 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type, 925 const uint8_t *Data, 926 RelExpr RelExpr) const { 927 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX) 928 return RelExpr; 929 const uint8_t Op = Data[-2]; 930 const uint8_t ModRm = Data[-1]; 931 932 // FIXME: When PIC is disabled and foo is defined locally in the 933 // lower 32 bit address space, memory operand in mov can be converted into 934 // immediate operand. Otherwise, mov must be changed to lea. We support only 935 // latter relaxation at this moment. 936 if (Op == 0x8b) 937 return R_RELAX_GOT_PC; 938 939 // Relax call and jmp. 940 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25)) 941 return R_RELAX_GOT_PC; 942 943 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor. 944 // If PIC then no relaxation is available. 945 // We also don't relax test/binop instructions without REX byte, 946 // they are 32bit operations and not common to have. 947 assert(Type == R_X86_64_REX_GOTPCRELX); 948 return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC; 949 } 950 951 // A subset of relaxations can only be applied for no-PIC. This method 952 // handles such relaxations. Instructions encoding information was taken from: 953 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2" 954 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/ 955 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf) 956 template <class ELFT> 957 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val, 958 uint8_t Op, uint8_t ModRm) const { 959 const uint8_t Rex = Loc[-3]; 960 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg". 961 if (Op == 0x85) { 962 // See "TEST-Logical Compare" (4-428 Vol. 2B), 963 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension). 964 965 // ModR/M byte has form XX YYY ZZZ, where 966 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1). 967 // XX has different meanings: 968 // 00: The operand's memory address is in reg1. 969 // 01: The operand's memory address is reg1 + a byte-sized displacement. 970 // 10: The operand's memory address is reg1 + a word-sized displacement. 971 // 11: The operand is reg1 itself. 972 // If an instruction requires only one operand, the unused reg2 field 973 // holds extra opcode bits rather than a register code 974 // 0xC0 == 11 000 000 binary. 975 // 0x38 == 00 111 000 binary. 976 // We transfer reg2 to reg1 here as operand. 977 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3). 978 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte. 979 980 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32 981 // See "TEST-Logical Compare" (4-428 Vol. 2B). 982 Loc[-2] = 0xf7; 983 984 // Move R bit to the B bit in REX byte. 985 // REX byte is encoded as 0100WRXB, where 986 // 0100 is 4bit fixed pattern. 987 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the 988 // default operand size is used (which is 32-bit for most but not all 989 // instructions). 990 // REX.R This 1-bit value is an extension to the MODRM.reg field. 991 // REX.X This 1-bit value is an extension to the SIB.index field. 992 // REX.B This 1-bit value is an extension to the MODRM.rm field or the 993 // SIB.base field. 994 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A). 995 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 996 write32le(Loc, Val); 997 return; 998 } 999 1000 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub 1001 // or xor operations. 1002 1003 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg". 1004 // Logic is close to one for test instruction above, but we also 1005 // write opcode extension here, see below for details. 1006 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte. 1007 1008 // Primary opcode is 0x81, opcode extension is one of: 1009 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB, 1010 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP. 1011 // This value was wrote to MODRM.reg in a line above. 1012 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15), 1013 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for 1014 // descriptions about each operation. 1015 Loc[-2] = 0x81; 1016 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 1017 write32le(Loc, Val); 1018 } 1019 1020 template <class ELFT> 1021 void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const { 1022 const uint8_t Op = Loc[-2]; 1023 const uint8_t ModRm = Loc[-1]; 1024 1025 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg". 1026 if (Op == 0x8b) { 1027 Loc[-2] = 0x8d; 1028 write32le(Loc, Val); 1029 return; 1030 } 1031 1032 if (Op != 0xff) { 1033 // We are relaxing a rip relative to an absolute, so compensate 1034 // for the old -4 addend. 1035 assert(!Config->Pic); 1036 relaxGotNoPic(Loc, Val + 4, Op, ModRm); 1037 return; 1038 } 1039 1040 // Convert call/jmp instructions. 1041 if (ModRm == 0x15) { 1042 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo". 1043 // Instead we convert to "addr32 call foo" where addr32 is an instruction 1044 // prefix. That makes result expression to be a single instruction. 1045 Loc[-2] = 0x67; // addr32 prefix 1046 Loc[-1] = 0xe8; // call 1047 write32le(Loc, Val); 1048 return; 1049 } 1050 1051 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop". 1052 // jmp doesn't return, so it is fine to use nop here, it is just a stub. 1053 assert(ModRm == 0x25); 1054 Loc[-2] = 0xe9; // jmp 1055 Loc[3] = 0x90; // nop 1056 write32le(Loc - 1, Val + 1); 1057 } 1058 1059 // Relocation masks following the #lo(value), #hi(value), #ha(value), 1060 // #higher(value), #highera(value), #highest(value), and #highesta(value) 1061 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 1062 // document. 1063 static uint16_t applyPPCLo(uint64_t V) { return V; } 1064 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; } 1065 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; } 1066 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; } 1067 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; } 1068 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; } 1069 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; } 1070 1071 PPCTargetInfo::PPCTargetInfo() {} 1072 1073 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1074 uint64_t Val) const { 1075 switch (Type) { 1076 case R_PPC_ADDR16_HA: 1077 write16be(Loc, applyPPCHa(Val)); 1078 break; 1079 case R_PPC_ADDR16_LO: 1080 write16be(Loc, applyPPCLo(Val)); 1081 break; 1082 case R_PPC_ADDR32: 1083 case R_PPC_REL32: 1084 write32be(Loc, Val); 1085 break; 1086 case R_PPC_REL24: 1087 or32be(Loc, Val & 0x3FFFFFC); 1088 break; 1089 default: 1090 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1091 } 1092 } 1093 1094 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S, 1095 const uint8_t *Loc) const { 1096 switch (Type) { 1097 case R_PPC_REL24: 1098 case R_PPC_REL32: 1099 return R_PC; 1100 default: 1101 return R_ABS; 1102 } 1103 } 1104 1105 PPC64TargetInfo::PPC64TargetInfo() { 1106 PltRel = GotRel = R_PPC64_GLOB_DAT; 1107 RelativeRel = R_PPC64_RELATIVE; 1108 GotEntrySize = 8; 1109 GotPltEntrySize = 8; 1110 PltEntrySize = 32; 1111 PltHeaderSize = 0; 1112 1113 // We need 64K pages (at least under glibc/Linux, the loader won't 1114 // set different permissions on a finer granularity than that). 1115 DefaultMaxPageSize = 65536; 1116 1117 // The PPC64 ELF ABI v1 spec, says: 1118 // 1119 // It is normally desirable to put segments with different characteristics 1120 // in separate 256 Mbyte portions of the address space, to give the 1121 // operating system full paging flexibility in the 64-bit address space. 1122 // 1123 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 1124 // use 0x10000000 as the starting address. 1125 DefaultImageBase = 0x10000000; 1126 } 1127 1128 static uint64_t PPC64TocOffset = 0x8000; 1129 1130 uint64_t getPPC64TocBase() { 1131 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 1132 // TOC starts where the first of these sections starts. We always create a 1133 // .got when we see a relocation that uses it, so for us the start is always 1134 // the .got. 1135 uint64_t TocVA = InX::Got->getVA(); 1136 1137 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 1138 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 1139 // code (crt1.o) assumes that you can get from the TOC base to the 1140 // start of the .toc section with only a single (signed) 16-bit relocation. 1141 return TocVA + PPC64TocOffset; 1142 } 1143 1144 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S, 1145 const uint8_t *Loc) const { 1146 switch (Type) { 1147 default: 1148 return R_ABS; 1149 case R_PPC64_TOC16: 1150 case R_PPC64_TOC16_DS: 1151 case R_PPC64_TOC16_HA: 1152 case R_PPC64_TOC16_HI: 1153 case R_PPC64_TOC16_LO: 1154 case R_PPC64_TOC16_LO_DS: 1155 return R_GOTREL; 1156 case R_PPC64_TOC: 1157 return R_PPC_TOC; 1158 case R_PPC64_REL24: 1159 return R_PPC_PLT_OPD; 1160 } 1161 } 1162 1163 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 1164 uint64_t PltEntryAddr, int32_t Index, 1165 unsigned RelOff) const { 1166 uint64_t Off = GotPltEntryAddr - getPPC64TocBase(); 1167 1168 // FIXME: What we should do, in theory, is get the offset of the function 1169 // descriptor in the .opd section, and use that as the offset from %r2 (the 1170 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will 1171 // be a pointer to the function descriptor in the .opd section. Using 1172 // this scheme is simpler, but requires an extra indirection per PLT dispatch. 1173 1174 write32be(Buf, 0xf8410028); // std %r2, 40(%r1) 1175 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha 1176 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11) 1177 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12) 1178 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11 1179 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12) 1180 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12) 1181 write32be(Buf + 28, 0x4e800420); // bctr 1182 } 1183 1184 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) { 1185 uint64_t V = Val - PPC64TocOffset; 1186 switch (Type) { 1187 case R_PPC64_TOC16: 1188 return {R_PPC64_ADDR16, V}; 1189 case R_PPC64_TOC16_DS: 1190 return {R_PPC64_ADDR16_DS, V}; 1191 case R_PPC64_TOC16_HA: 1192 return {R_PPC64_ADDR16_HA, V}; 1193 case R_PPC64_TOC16_HI: 1194 return {R_PPC64_ADDR16_HI, V}; 1195 case R_PPC64_TOC16_LO: 1196 return {R_PPC64_ADDR16_LO, V}; 1197 case R_PPC64_TOC16_LO_DS: 1198 return {R_PPC64_ADDR16_LO_DS, V}; 1199 default: 1200 return {Type, Val}; 1201 } 1202 } 1203 1204 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1205 uint64_t Val) const { 1206 // For a TOC-relative relocation, proceed in terms of the corresponding 1207 // ADDR16 relocation type. 1208 std::tie(Type, Val) = toAddr16Rel(Type, Val); 1209 1210 switch (Type) { 1211 case R_PPC64_ADDR14: { 1212 checkAlignment<4>(Loc, Val, Type); 1213 // Preserve the AA/LK bits in the branch instruction 1214 uint8_t AALK = Loc[3]; 1215 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 1216 break; 1217 } 1218 case R_PPC64_ADDR16: 1219 checkInt<16>(Loc, Val, Type); 1220 write16be(Loc, Val); 1221 break; 1222 case R_PPC64_ADDR16_DS: 1223 checkInt<16>(Loc, Val, Type); 1224 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3)); 1225 break; 1226 case R_PPC64_ADDR16_HA: 1227 case R_PPC64_REL16_HA: 1228 write16be(Loc, applyPPCHa(Val)); 1229 break; 1230 case R_PPC64_ADDR16_HI: 1231 case R_PPC64_REL16_HI: 1232 write16be(Loc, applyPPCHi(Val)); 1233 break; 1234 case R_PPC64_ADDR16_HIGHER: 1235 write16be(Loc, applyPPCHigher(Val)); 1236 break; 1237 case R_PPC64_ADDR16_HIGHERA: 1238 write16be(Loc, applyPPCHighera(Val)); 1239 break; 1240 case R_PPC64_ADDR16_HIGHEST: 1241 write16be(Loc, applyPPCHighest(Val)); 1242 break; 1243 case R_PPC64_ADDR16_HIGHESTA: 1244 write16be(Loc, applyPPCHighesta(Val)); 1245 break; 1246 case R_PPC64_ADDR16_LO: 1247 write16be(Loc, applyPPCLo(Val)); 1248 break; 1249 case R_PPC64_ADDR16_LO_DS: 1250 case R_PPC64_REL16_LO: 1251 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3)); 1252 break; 1253 case R_PPC64_ADDR32: 1254 case R_PPC64_REL32: 1255 checkInt<32>(Loc, Val, Type); 1256 write32be(Loc, Val); 1257 break; 1258 case R_PPC64_ADDR64: 1259 case R_PPC64_REL64: 1260 case R_PPC64_TOC: 1261 write64be(Loc, Val); 1262 break; 1263 case R_PPC64_REL24: { 1264 uint32_t Mask = 0x03FFFFFC; 1265 checkInt<24>(Loc, Val, Type); 1266 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask)); 1267 break; 1268 } 1269 default: 1270 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1271 } 1272 } 1273 1274 AArch64TargetInfo::AArch64TargetInfo() { 1275 CopyRel = R_AARCH64_COPY; 1276 RelativeRel = R_AARCH64_RELATIVE; 1277 IRelativeRel = R_AARCH64_IRELATIVE; 1278 GotRel = R_AARCH64_GLOB_DAT; 1279 PltRel = R_AARCH64_JUMP_SLOT; 1280 TlsDescRel = R_AARCH64_TLSDESC; 1281 TlsGotRel = R_AARCH64_TLS_TPREL64; 1282 GotEntrySize = 8; 1283 GotPltEntrySize = 8; 1284 PltEntrySize = 16; 1285 PltHeaderSize = 32; 1286 DefaultMaxPageSize = 65536; 1287 1288 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant 1289 // 1 of the tls structures and the tcb size is 16. 1290 TcbSize = 16; 1291 } 1292 1293 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S, 1294 const uint8_t *Loc) const { 1295 switch (Type) { 1296 default: 1297 return R_ABS; 1298 case R_AARCH64_TLSDESC_ADR_PAGE21: 1299 return R_TLSDESC_PAGE; 1300 case R_AARCH64_TLSDESC_LD64_LO12: 1301 case R_AARCH64_TLSDESC_ADD_LO12: 1302 return R_TLSDESC; 1303 case R_AARCH64_TLSDESC_CALL: 1304 return R_TLSDESC_CALL; 1305 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1306 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1307 return R_TLS; 1308 case R_AARCH64_CALL26: 1309 case R_AARCH64_CONDBR19: 1310 case R_AARCH64_JUMP26: 1311 case R_AARCH64_TSTBR14: 1312 return R_PLT_PC; 1313 case R_AARCH64_PREL16: 1314 case R_AARCH64_PREL32: 1315 case R_AARCH64_PREL64: 1316 case R_AARCH64_ADR_PREL_LO21: 1317 return R_PC; 1318 case R_AARCH64_ADR_PREL_PG_HI21: 1319 return R_PAGE_PC; 1320 case R_AARCH64_LD64_GOT_LO12_NC: 1321 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1322 return R_GOT; 1323 case R_AARCH64_ADR_GOT_PAGE: 1324 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1325 return R_GOT_PAGE_PC; 1326 case R_AARCH64_NONE: 1327 return R_NONE; 1328 } 1329 } 1330 1331 RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 1332 RelExpr Expr) const { 1333 if (Expr == R_RELAX_TLS_GD_TO_IE) { 1334 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21) 1335 return R_RELAX_TLS_GD_TO_IE_PAGE_PC; 1336 return R_RELAX_TLS_GD_TO_IE_ABS; 1337 } 1338 return Expr; 1339 } 1340 1341 bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { 1342 switch (Type) { 1343 default: 1344 return false; 1345 case R_AARCH64_ADD_ABS_LO12_NC: 1346 case R_AARCH64_LD64_GOT_LO12_NC: 1347 case R_AARCH64_LDST128_ABS_LO12_NC: 1348 case R_AARCH64_LDST16_ABS_LO12_NC: 1349 case R_AARCH64_LDST32_ABS_LO12_NC: 1350 case R_AARCH64_LDST64_ABS_LO12_NC: 1351 case R_AARCH64_LDST8_ABS_LO12_NC: 1352 case R_AARCH64_TLSDESC_ADD_LO12: 1353 case R_AARCH64_TLSDESC_LD64_LO12: 1354 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1355 return true; 1356 } 1357 } 1358 1359 bool AArch64TargetInfo::isPicRel(uint32_t Type) const { 1360 return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64; 1361 } 1362 1363 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1364 write64le(Buf, InX::Plt->getVA()); 1365 } 1366 1367 // Page(Expr) is the page address of the expression Expr, defined 1368 // as (Expr & ~0xFFF). (This applies even if the machine page size 1369 // supported by the platform has a different value.) 1370 uint64_t getAArch64Page(uint64_t Expr) { 1371 return Expr & (~static_cast<uint64_t>(0xFFF)); 1372 } 1373 1374 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const { 1375 const uint8_t PltData[] = { 1376 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 1377 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 1378 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 1379 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 1380 0x20, 0x02, 0x1f, 0xd6, // br x17 1381 0x1f, 0x20, 0x03, 0xd5, // nop 1382 0x1f, 0x20, 0x03, 0xd5, // nop 1383 0x1f, 0x20, 0x03, 0xd5 // nop 1384 }; 1385 memcpy(Buf, PltData, sizeof(PltData)); 1386 1387 uint64_t Got = InX::GotPlt->getVA(); 1388 uint64_t Plt = InX::Plt->getVA(); 1389 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 1390 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4)); 1391 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16); 1392 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16); 1393 } 1394 1395 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 1396 uint64_t PltEntryAddr, int32_t Index, 1397 unsigned RelOff) const { 1398 const uint8_t Inst[] = { 1399 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 1400 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 1401 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n])) 1402 0x20, 0x02, 0x1f, 0xd6 // br x17 1403 }; 1404 memcpy(Buf, Inst, sizeof(Inst)); 1405 1406 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21, 1407 getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr)); 1408 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr); 1409 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr); 1410 } 1411 1412 static void write32AArch64Addr(uint8_t *L, uint64_t Imm) { 1413 uint32_t ImmLo = (Imm & 0x3) << 29; 1414 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3; 1415 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3); 1416 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi); 1417 } 1418 1419 // Return the bits [Start, End] from Val shifted Start bits. 1420 // For instance, getBits(0xF0, 4, 8) returns 0xF. 1421 static uint64_t getBits(uint64_t Val, int Start, int End) { 1422 uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1; 1423 return (Val >> Start) & Mask; 1424 } 1425 1426 // Update the immediate field in a AARCH64 ldr, str, and add instruction. 1427 static void or32AArch64Imm(uint8_t *L, uint64_t Imm) { 1428 or32le(L, (Imm & 0xFFF) << 10); 1429 } 1430 1431 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1432 uint64_t Val) const { 1433 switch (Type) { 1434 case R_AARCH64_ABS16: 1435 case R_AARCH64_PREL16: 1436 checkIntUInt<16>(Loc, Val, Type); 1437 write16le(Loc, Val); 1438 break; 1439 case R_AARCH64_ABS32: 1440 case R_AARCH64_PREL32: 1441 checkIntUInt<32>(Loc, Val, Type); 1442 write32le(Loc, Val); 1443 break; 1444 case R_AARCH64_ABS64: 1445 case R_AARCH64_GLOB_DAT: 1446 case R_AARCH64_PREL64: 1447 write64le(Loc, Val); 1448 break; 1449 case R_AARCH64_ADD_ABS_LO12_NC: 1450 or32AArch64Imm(Loc, Val); 1451 break; 1452 case R_AARCH64_ADR_GOT_PAGE: 1453 case R_AARCH64_ADR_PREL_PG_HI21: 1454 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1455 case R_AARCH64_TLSDESC_ADR_PAGE21: 1456 checkInt<33>(Loc, Val, Type); 1457 write32AArch64Addr(Loc, Val >> 12); 1458 break; 1459 case R_AARCH64_ADR_PREL_LO21: 1460 checkInt<21>(Loc, Val, Type); 1461 write32AArch64Addr(Loc, Val); 1462 break; 1463 case R_AARCH64_CALL26: 1464 case R_AARCH64_JUMP26: 1465 checkInt<28>(Loc, Val, Type); 1466 or32le(Loc, (Val & 0x0FFFFFFC) >> 2); 1467 break; 1468 case R_AARCH64_CONDBR19: 1469 checkInt<21>(Loc, Val, Type); 1470 or32le(Loc, (Val & 0x1FFFFC) << 3); 1471 break; 1472 case R_AARCH64_LD64_GOT_LO12_NC: 1473 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1474 case R_AARCH64_TLSDESC_LD64_LO12: 1475 checkAlignment<8>(Loc, Val, Type); 1476 or32le(Loc, (Val & 0xFF8) << 7); 1477 break; 1478 case R_AARCH64_LDST8_ABS_LO12_NC: 1479 or32AArch64Imm(Loc, getBits(Val, 0, 11)); 1480 break; 1481 case R_AARCH64_LDST16_ABS_LO12_NC: 1482 or32AArch64Imm(Loc, getBits(Val, 1, 11)); 1483 break; 1484 case R_AARCH64_LDST32_ABS_LO12_NC: 1485 or32AArch64Imm(Loc, getBits(Val, 2, 11)); 1486 break; 1487 case R_AARCH64_LDST64_ABS_LO12_NC: 1488 or32AArch64Imm(Loc, getBits(Val, 3, 11)); 1489 break; 1490 case R_AARCH64_LDST128_ABS_LO12_NC: 1491 or32AArch64Imm(Loc, getBits(Val, 4, 11)); 1492 break; 1493 case R_AARCH64_MOVW_UABS_G0_NC: 1494 or32le(Loc, (Val & 0xFFFF) << 5); 1495 break; 1496 case R_AARCH64_MOVW_UABS_G1_NC: 1497 or32le(Loc, (Val & 0xFFFF0000) >> 11); 1498 break; 1499 case R_AARCH64_MOVW_UABS_G2_NC: 1500 or32le(Loc, (Val & 0xFFFF00000000) >> 27); 1501 break; 1502 case R_AARCH64_MOVW_UABS_G3: 1503 or32le(Loc, (Val & 0xFFFF000000000000) >> 43); 1504 break; 1505 case R_AARCH64_TSTBR14: 1506 checkInt<16>(Loc, Val, Type); 1507 or32le(Loc, (Val & 0xFFFC) << 3); 1508 break; 1509 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1510 checkInt<24>(Loc, Val, Type); 1511 or32AArch64Imm(Loc, Val >> 12); 1512 break; 1513 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1514 case R_AARCH64_TLSDESC_ADD_LO12: 1515 or32AArch64Imm(Loc, Val); 1516 break; 1517 default: 1518 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1519 } 1520 } 1521 1522 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 1523 uint64_t Val) const { 1524 // TLSDESC Global-Dynamic relocation are in the form: 1525 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1526 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12] 1527 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12] 1528 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1529 // blr x1 1530 // And it can optimized to: 1531 // movz x0, #0x0, lsl #16 1532 // movk x0, #0x10 1533 // nop 1534 // nop 1535 checkUInt<32>(Loc, Val, Type); 1536 1537 switch (Type) { 1538 case R_AARCH64_TLSDESC_ADD_LO12: 1539 case R_AARCH64_TLSDESC_CALL: 1540 write32le(Loc, 0xd503201f); // nop 1541 return; 1542 case R_AARCH64_TLSDESC_ADR_PAGE21: 1543 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz 1544 return; 1545 case R_AARCH64_TLSDESC_LD64_LO12: 1546 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk 1547 return; 1548 default: 1549 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1550 } 1551 } 1552 1553 void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 1554 uint64_t Val) const { 1555 // TLSDESC Global-Dynamic relocation are in the form: 1556 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1557 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12] 1558 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12] 1559 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1560 // blr x1 1561 // And it can optimized to: 1562 // adrp x0, :gottprel:v 1563 // ldr x0, [x0, :gottprel_lo12:v] 1564 // nop 1565 // nop 1566 1567 switch (Type) { 1568 case R_AARCH64_TLSDESC_ADD_LO12: 1569 case R_AARCH64_TLSDESC_CALL: 1570 write32le(Loc, 0xd503201f); // nop 1571 break; 1572 case R_AARCH64_TLSDESC_ADR_PAGE21: 1573 write32le(Loc, 0x90000000); // adrp 1574 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val); 1575 break; 1576 case R_AARCH64_TLSDESC_LD64_LO12: 1577 write32le(Loc, 0xf9400000); // ldr 1578 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val); 1579 break; 1580 default: 1581 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1582 } 1583 } 1584 1585 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 1586 uint64_t Val) const { 1587 checkUInt<32>(Loc, Val, Type); 1588 1589 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) { 1590 // Generate MOVZ. 1591 uint32_t RegNo = read32le(Loc) & 0x1f; 1592 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5)); 1593 return; 1594 } 1595 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) { 1596 // Generate MOVK. 1597 uint32_t RegNo = read32le(Loc) & 0x1f; 1598 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5)); 1599 return; 1600 } 1601 llvm_unreachable("invalid relocation for TLS IE to LE relaxation"); 1602 } 1603 1604 AMDGPUTargetInfo::AMDGPUTargetInfo() { 1605 RelativeRel = R_AMDGPU_REL64; 1606 GotRel = R_AMDGPU_ABS64; 1607 GotEntrySize = 8; 1608 } 1609 1610 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1611 uint64_t Val) const { 1612 switch (Type) { 1613 case R_AMDGPU_ABS32: 1614 case R_AMDGPU_GOTPCREL: 1615 case R_AMDGPU_GOTPCREL32_LO: 1616 case R_AMDGPU_REL32: 1617 case R_AMDGPU_REL32_LO: 1618 write32le(Loc, Val); 1619 break; 1620 case R_AMDGPU_ABS64: 1621 write64le(Loc, Val); 1622 break; 1623 case R_AMDGPU_GOTPCREL32_HI: 1624 case R_AMDGPU_REL32_HI: 1625 write32le(Loc, Val >> 32); 1626 break; 1627 default: 1628 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1629 } 1630 } 1631 1632 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S, 1633 const uint8_t *Loc) const { 1634 switch (Type) { 1635 case R_AMDGPU_ABS32: 1636 case R_AMDGPU_ABS64: 1637 return R_ABS; 1638 case R_AMDGPU_REL32: 1639 case R_AMDGPU_REL32_LO: 1640 case R_AMDGPU_REL32_HI: 1641 return R_PC; 1642 case R_AMDGPU_GOTPCREL: 1643 case R_AMDGPU_GOTPCREL32_LO: 1644 case R_AMDGPU_GOTPCREL32_HI: 1645 return R_GOT_PC; 1646 default: 1647 error(toString(S.File) + ": unknown relocation type: " + toString(Type)); 1648 return R_HINT; 1649 } 1650 } 1651 1652 ARMTargetInfo::ARMTargetInfo() { 1653 CopyRel = R_ARM_COPY; 1654 RelativeRel = R_ARM_RELATIVE; 1655 IRelativeRel = R_ARM_IRELATIVE; 1656 GotRel = R_ARM_GLOB_DAT; 1657 PltRel = R_ARM_JUMP_SLOT; 1658 TlsGotRel = R_ARM_TLS_TPOFF32; 1659 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32; 1660 TlsOffsetRel = R_ARM_TLS_DTPOFF32; 1661 GotEntrySize = 4; 1662 GotPltEntrySize = 4; 1663 PltEntrySize = 16; 1664 PltHeaderSize = 20; 1665 // ARM uses Variant 1 TLS 1666 TcbSize = 8; 1667 NeedsThunks = true; 1668 } 1669 1670 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S, 1671 const uint8_t *Loc) const { 1672 switch (Type) { 1673 default: 1674 return R_ABS; 1675 case R_ARM_THM_JUMP11: 1676 return R_PC; 1677 case R_ARM_CALL: 1678 case R_ARM_JUMP24: 1679 case R_ARM_PC24: 1680 case R_ARM_PLT32: 1681 case R_ARM_PREL31: 1682 case R_ARM_THM_JUMP19: 1683 case R_ARM_THM_JUMP24: 1684 case R_ARM_THM_CALL: 1685 return R_PLT_PC; 1686 case R_ARM_GOTOFF32: 1687 // (S + A) - GOT_ORG 1688 return R_GOTREL; 1689 case R_ARM_GOT_BREL: 1690 // GOT(S) + A - GOT_ORG 1691 return R_GOT_OFF; 1692 case R_ARM_GOT_PREL: 1693 case R_ARM_TLS_IE32: 1694 // GOT(S) + A - P 1695 return R_GOT_PC; 1696 case R_ARM_SBREL32: 1697 return R_ARM_SBREL; 1698 case R_ARM_TARGET1: 1699 return Config->Target1Rel ? R_PC : R_ABS; 1700 case R_ARM_TARGET2: 1701 if (Config->Target2 == Target2Policy::Rel) 1702 return R_PC; 1703 if (Config->Target2 == Target2Policy::Abs) 1704 return R_ABS; 1705 return R_GOT_PC; 1706 case R_ARM_TLS_GD32: 1707 return R_TLSGD_PC; 1708 case R_ARM_TLS_LDM32: 1709 return R_TLSLD_PC; 1710 case R_ARM_BASE_PREL: 1711 // B(S) + A - P 1712 // FIXME: currently B(S) assumed to be .got, this may not hold for all 1713 // platforms. 1714 return R_GOTONLY_PC; 1715 case R_ARM_MOVW_PREL_NC: 1716 case R_ARM_MOVT_PREL: 1717 case R_ARM_REL32: 1718 case R_ARM_THM_MOVW_PREL_NC: 1719 case R_ARM_THM_MOVT_PREL: 1720 return R_PC; 1721 case R_ARM_NONE: 1722 return R_NONE; 1723 case R_ARM_TLS_LE32: 1724 return R_TLS; 1725 } 1726 } 1727 1728 bool ARMTargetInfo::isPicRel(uint32_t Type) const { 1729 return (Type == R_ARM_TARGET1 && !Config->Target1Rel) || 1730 (Type == R_ARM_ABS32); 1731 } 1732 1733 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const { 1734 if (Type == R_ARM_TARGET1 && !Config->Target1Rel) 1735 return R_ARM_ABS32; 1736 if (Type == R_ARM_ABS32) 1737 return Type; 1738 // Keep it going with a dummy value so that we can find more reloc errors. 1739 return R_ARM_ABS32; 1740 } 1741 1742 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1743 write32le(Buf, InX::Plt->getVA()); 1744 } 1745 1746 void ARMTargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 1747 // An ARM entry is the address of the ifunc resolver function. 1748 write32le(Buf, S.getVA()); 1749 } 1750 1751 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const { 1752 const uint8_t PltData[] = { 1753 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]! 1754 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2 1755 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr 1756 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8] 1757 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8 1758 }; 1759 memcpy(Buf, PltData, sizeof(PltData)); 1760 uint64_t GotPlt = InX::GotPlt->getVA(); 1761 uint64_t L1 = InX::Plt->getVA() + 8; 1762 write32le(Buf + 16, GotPlt - L1 - 8); 1763 } 1764 1765 void ARMTargetInfo::addPltHeaderSymbols(InputSectionBase *ISD) const { 1766 auto *IS = cast<InputSection>(ISD); 1767 addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS); 1768 addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS); 1769 } 1770 1771 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 1772 uint64_t PltEntryAddr, int32_t Index, 1773 unsigned RelOff) const { 1774 // FIXME: Using simple code sequence with simple relocations. 1775 // There is a more optimal sequence but it requires support for the group 1776 // relocations. See ELF for the ARM Architecture Appendix A.3 1777 const uint8_t PltData[] = { 1778 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2 1779 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc 1780 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip] 1781 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8 1782 }; 1783 memcpy(Buf, PltData, sizeof(PltData)); 1784 uint64_t L1 = PltEntryAddr + 4; 1785 write32le(Buf + 12, GotPltEntryAddr - L1 - 8); 1786 } 1787 1788 void ARMTargetInfo::addPltSymbols(InputSectionBase *ISD, uint64_t Off) const { 1789 auto *IS = cast<InputSection>(ISD); 1790 addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS); 1791 addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS); 1792 } 1793 1794 bool ARMTargetInfo::needsThunk(RelExpr Expr, uint32_t RelocType, 1795 const InputFile *File, 1796 const SymbolBody &S) const { 1797 // If S is an undefined weak symbol in an executable we don't need a Thunk. 1798 // In a DSO calls to undefined symbols, including weak ones get PLT entries 1799 // which may need a thunk. 1800 if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak() && 1801 !Config->Shared) 1802 return false; 1803 // A state change from ARM to Thumb and vice versa must go through an 1804 // interworking thunk if the relocation type is not R_ARM_CALL or 1805 // R_ARM_THM_CALL. 1806 switch (RelocType) { 1807 case R_ARM_PC24: 1808 case R_ARM_PLT32: 1809 case R_ARM_JUMP24: 1810 // Source is ARM, all PLT entries are ARM so no interworking required. 1811 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb). 1812 if (Expr == R_PC && ((S.getVA() & 1) == 1)) 1813 return true; 1814 break; 1815 case R_ARM_THM_JUMP19: 1816 case R_ARM_THM_JUMP24: 1817 // Source is Thumb, all PLT entries are ARM so interworking is required. 1818 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM). 1819 if (Expr == R_PLT_PC || ((S.getVA() & 1) == 0)) 1820 return true; 1821 break; 1822 } 1823 return false; 1824 } 1825 1826 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1827 uint64_t Val) const { 1828 switch (Type) { 1829 case R_ARM_ABS32: 1830 case R_ARM_BASE_PREL: 1831 case R_ARM_GLOB_DAT: 1832 case R_ARM_GOTOFF32: 1833 case R_ARM_GOT_BREL: 1834 case R_ARM_GOT_PREL: 1835 case R_ARM_REL32: 1836 case R_ARM_RELATIVE: 1837 case R_ARM_SBREL32: 1838 case R_ARM_TARGET1: 1839 case R_ARM_TARGET2: 1840 case R_ARM_TLS_GD32: 1841 case R_ARM_TLS_IE32: 1842 case R_ARM_TLS_LDM32: 1843 case R_ARM_TLS_LDO32: 1844 case R_ARM_TLS_LE32: 1845 case R_ARM_TLS_TPOFF32: 1846 case R_ARM_TLS_DTPOFF32: 1847 write32le(Loc, Val); 1848 break; 1849 case R_ARM_TLS_DTPMOD32: 1850 write32le(Loc, 1); 1851 break; 1852 case R_ARM_PREL31: 1853 checkInt<31>(Loc, Val, Type); 1854 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000)); 1855 break; 1856 case R_ARM_CALL: 1857 // R_ARM_CALL is used for BL and BLX instructions, depending on the 1858 // value of bit 0 of Val, we must select a BL or BLX instruction 1859 if (Val & 1) { 1860 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX. 1861 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' 1862 checkInt<26>(Loc, Val, Type); 1863 write32le(Loc, 0xfa000000 | // opcode 1864 ((Val & 2) << 23) | // H 1865 ((Val >> 2) & 0x00ffffff)); // imm24 1866 break; 1867 } 1868 if ((read32le(Loc) & 0xfe000000) == 0xfa000000) 1869 // BLX (always unconditional) instruction to an ARM Target, select an 1870 // unconditional BL. 1871 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff)); 1872 // fall through as BL encoding is shared with B 1873 LLVM_FALLTHROUGH; 1874 case R_ARM_JUMP24: 1875 case R_ARM_PC24: 1876 case R_ARM_PLT32: 1877 checkInt<26>(Loc, Val, Type); 1878 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff)); 1879 break; 1880 case R_ARM_THM_JUMP11: 1881 checkInt<12>(Loc, Val, Type); 1882 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff)); 1883 break; 1884 case R_ARM_THM_JUMP19: 1885 // Encoding T3: Val = S:J2:J1:imm6:imm11:0 1886 checkInt<21>(Loc, Val, Type); 1887 write16le(Loc, 1888 (read16le(Loc) & 0xfbc0) | // opcode cond 1889 ((Val >> 10) & 0x0400) | // S 1890 ((Val >> 12) & 0x003f)); // imm6 1891 write16le(Loc + 2, 1892 0x8000 | // opcode 1893 ((Val >> 8) & 0x0800) | // J2 1894 ((Val >> 5) & 0x2000) | // J1 1895 ((Val >> 1) & 0x07ff)); // imm11 1896 break; 1897 case R_ARM_THM_CALL: 1898 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the 1899 // value of bit 0 of Val, we must select a BL or BLX instruction 1900 if ((Val & 1) == 0) { 1901 // Ensure BLX destination is 4-byte aligned. As BLX instruction may 1902 // only be two byte aligned. This must be done before overflow check 1903 Val = alignTo(Val, 4); 1904 } 1905 // Bit 12 is 0 for BLX, 1 for BL 1906 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12); 1907 // Fall through as rest of encoding is the same as B.W 1908 LLVM_FALLTHROUGH; 1909 case R_ARM_THM_JUMP24: 1910 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 1911 // FIXME: Use of I1 and I2 require v6T2ops 1912 checkInt<25>(Loc, Val, Type); 1913 write16le(Loc, 1914 0xf000 | // opcode 1915 ((Val >> 14) & 0x0400) | // S 1916 ((Val >> 12) & 0x03ff)); // imm10 1917 write16le(Loc + 2, 1918 (read16le(Loc + 2) & 0xd000) | // opcode 1919 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1 1920 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2 1921 ((Val >> 1) & 0x07ff)); // imm11 1922 break; 1923 case R_ARM_MOVW_ABS_NC: 1924 case R_ARM_MOVW_PREL_NC: 1925 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) | 1926 (Val & 0x0fff)); 1927 break; 1928 case R_ARM_MOVT_ABS: 1929 case R_ARM_MOVT_PREL: 1930 checkInt<32>(Loc, Val, Type); 1931 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | 1932 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff)); 1933 break; 1934 case R_ARM_THM_MOVT_ABS: 1935 case R_ARM_THM_MOVT_PREL: 1936 // Encoding T1: A = imm4:i:imm3:imm8 1937 checkInt<32>(Loc, Val, Type); 1938 write16le(Loc, 1939 0xf2c0 | // opcode 1940 ((Val >> 17) & 0x0400) | // i 1941 ((Val >> 28) & 0x000f)); // imm4 1942 write16le(Loc + 2, 1943 (read16le(Loc + 2) & 0x8f00) | // opcode 1944 ((Val >> 12) & 0x7000) | // imm3 1945 ((Val >> 16) & 0x00ff)); // imm8 1946 break; 1947 case R_ARM_THM_MOVW_ABS_NC: 1948 case R_ARM_THM_MOVW_PREL_NC: 1949 // Encoding T3: A = imm4:i:imm3:imm8 1950 write16le(Loc, 1951 0xf240 | // opcode 1952 ((Val >> 1) & 0x0400) | // i 1953 ((Val >> 12) & 0x000f)); // imm4 1954 write16le(Loc + 2, 1955 (read16le(Loc + 2) & 0x8f00) | // opcode 1956 ((Val << 4) & 0x7000) | // imm3 1957 (Val & 0x00ff)); // imm8 1958 break; 1959 default: 1960 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1961 } 1962 } 1963 1964 int64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf, 1965 uint32_t Type) const { 1966 switch (Type) { 1967 default: 1968 return 0; 1969 case R_ARM_ABS32: 1970 case R_ARM_BASE_PREL: 1971 case R_ARM_GOTOFF32: 1972 case R_ARM_GOT_BREL: 1973 case R_ARM_GOT_PREL: 1974 case R_ARM_REL32: 1975 case R_ARM_TARGET1: 1976 case R_ARM_TARGET2: 1977 case R_ARM_TLS_GD32: 1978 case R_ARM_TLS_LDM32: 1979 case R_ARM_TLS_LDO32: 1980 case R_ARM_TLS_IE32: 1981 case R_ARM_TLS_LE32: 1982 return SignExtend64<32>(read32le(Buf)); 1983 case R_ARM_PREL31: 1984 return SignExtend64<31>(read32le(Buf)); 1985 case R_ARM_CALL: 1986 case R_ARM_JUMP24: 1987 case R_ARM_PC24: 1988 case R_ARM_PLT32: 1989 return SignExtend64<26>(read32le(Buf) << 2); 1990 case R_ARM_THM_JUMP11: 1991 return SignExtend64<12>(read16le(Buf) << 1); 1992 case R_ARM_THM_JUMP19: { 1993 // Encoding T3: A = S:J2:J1:imm10:imm6:0 1994 uint16_t Hi = read16le(Buf); 1995 uint16_t Lo = read16le(Buf + 2); 1996 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S 1997 ((Lo & 0x0800) << 8) | // J2 1998 ((Lo & 0x2000) << 5) | // J1 1999 ((Hi & 0x003f) << 12) | // imm6 2000 ((Lo & 0x07ff) << 1)); // imm11:0 2001 } 2002 case R_ARM_THM_CALL: 2003 case R_ARM_THM_JUMP24: { 2004 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 2005 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) 2006 // FIXME: I1 and I2 require v6T2ops 2007 uint16_t Hi = read16le(Buf); 2008 uint16_t Lo = read16le(Buf + 2); 2009 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S 2010 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1 2011 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2 2012 ((Hi & 0x003ff) << 12) | // imm0 2013 ((Lo & 0x007ff) << 1)); // imm11:0 2014 } 2015 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and 2016 // MOVT is in the range -32768 <= A < 32768 2017 case R_ARM_MOVW_ABS_NC: 2018 case R_ARM_MOVT_ABS: 2019 case R_ARM_MOVW_PREL_NC: 2020 case R_ARM_MOVT_PREL: { 2021 uint64_t Val = read32le(Buf) & 0x000f0fff; 2022 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff)); 2023 } 2024 case R_ARM_THM_MOVW_ABS_NC: 2025 case R_ARM_THM_MOVT_ABS: 2026 case R_ARM_THM_MOVW_PREL_NC: 2027 case R_ARM_THM_MOVT_PREL: { 2028 // Encoding T3: A = imm4:i:imm3:imm8 2029 uint16_t Hi = read16le(Buf); 2030 uint16_t Lo = read16le(Buf + 2); 2031 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4 2032 ((Hi & 0x0400) << 1) | // i 2033 ((Lo & 0x7000) >> 4) | // imm3 2034 (Lo & 0x00ff)); // imm8 2035 } 2036 } 2037 } 2038 2039 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() { 2040 GotPltHeaderEntriesNum = 2; 2041 DefaultMaxPageSize = 65536; 2042 GotEntrySize = sizeof(typename ELFT::uint); 2043 GotPltEntrySize = sizeof(typename ELFT::uint); 2044 PltEntrySize = 16; 2045 PltHeaderSize = 32; 2046 CopyRel = R_MIPS_COPY; 2047 PltRel = R_MIPS_JUMP_SLOT; 2048 NeedsThunks = true; 2049 if (ELFT::Is64Bits) { 2050 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 2051 TlsGotRel = R_MIPS_TLS_TPREL64; 2052 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 2053 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 2054 } else { 2055 RelativeRel = R_MIPS_REL32; 2056 TlsGotRel = R_MIPS_TLS_TPREL32; 2057 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 2058 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 2059 } 2060 } 2061 2062 template <class ELFT> 2063 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S, 2064 const uint8_t *Loc) const { 2065 // See comment in the calculateMipsRelChain. 2066 if (ELFT::Is64Bits || Config->MipsN32Abi) 2067 Type &= 0xff; 2068 switch (Type) { 2069 default: 2070 return R_ABS; 2071 case R_MIPS_JALR: 2072 return R_HINT; 2073 case R_MIPS_GPREL16: 2074 case R_MIPS_GPREL32: 2075 return R_MIPS_GOTREL; 2076 case R_MIPS_26: 2077 return R_PLT; 2078 case R_MIPS_HI16: 2079 case R_MIPS_LO16: 2080 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 2081 // offset between start of function and 'gp' value which by default 2082 // equal to the start of .got section. In that case we consider these 2083 // relocations as relative. 2084 if (&S == ElfSym::MipsGpDisp) 2085 return R_MIPS_GOT_GP_PC; 2086 if (&S == ElfSym::MipsLocalGp) 2087 return R_MIPS_GOT_GP; 2088 // fallthrough 2089 case R_MIPS_GOT_OFST: 2090 return R_ABS; 2091 case R_MIPS_PC32: 2092 case R_MIPS_PC16: 2093 case R_MIPS_PC19_S2: 2094 case R_MIPS_PC21_S2: 2095 case R_MIPS_PC26_S2: 2096 case R_MIPS_PCHI16: 2097 case R_MIPS_PCLO16: 2098 return R_PC; 2099 case R_MIPS_GOT16: 2100 if (S.isLocal()) 2101 return R_MIPS_GOT_LOCAL_PAGE; 2102 // fallthrough 2103 case R_MIPS_CALL16: 2104 case R_MIPS_GOT_DISP: 2105 case R_MIPS_TLS_GOTTPREL: 2106 return R_MIPS_GOT_OFF; 2107 case R_MIPS_CALL_HI16: 2108 case R_MIPS_CALL_LO16: 2109 case R_MIPS_GOT_HI16: 2110 case R_MIPS_GOT_LO16: 2111 return R_MIPS_GOT_OFF32; 2112 case R_MIPS_GOT_PAGE: 2113 return R_MIPS_GOT_LOCAL_PAGE; 2114 case R_MIPS_TLS_GD: 2115 return R_MIPS_TLSGD; 2116 case R_MIPS_TLS_LDM: 2117 return R_MIPS_TLSLD; 2118 } 2119 } 2120 2121 template <class ELFT> bool MipsTargetInfo<ELFT>::isPicRel(uint32_t Type) const { 2122 return Type == R_MIPS_32 || Type == R_MIPS_64; 2123 } 2124 2125 template <class ELFT> 2126 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const { 2127 return RelativeRel; 2128 } 2129 2130 template <class ELFT> 2131 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 2132 write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA()); 2133 } 2134 2135 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2136 static int64_t getPcRelocAddend(const uint8_t *Loc) { 2137 uint32_t Instr = read32<E>(Loc); 2138 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2139 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT); 2140 } 2141 2142 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2143 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) { 2144 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2145 uint32_t Instr = read32<E>(Loc); 2146 if (SHIFT > 0) 2147 checkAlignment<(1 << SHIFT)>(Loc, V, Type); 2148 checkInt<BSIZE + SHIFT>(Loc, V, Type); 2149 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask)); 2150 } 2151 2152 template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) { 2153 uint32_t Instr = read32<E>(Loc); 2154 uint16_t Res = ((V + 0x8000) >> 16) & 0xffff; 2155 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2156 } 2157 2158 template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) { 2159 uint32_t Instr = read32<E>(Loc); 2160 uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff; 2161 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2162 } 2163 2164 template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) { 2165 uint32_t Instr = read32<E>(Loc); 2166 uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff; 2167 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2168 } 2169 2170 template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) { 2171 uint32_t Instr = read32<E>(Loc); 2172 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff)); 2173 } 2174 2175 template <class ELFT> static bool isMipsR6() { 2176 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf); 2177 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH; 2178 return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6; 2179 } 2180 2181 template <class ELFT> 2182 void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 2183 const endianness E = ELFT::TargetEndianness; 2184 if (Config->MipsN32Abi) { 2185 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 2186 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 2187 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 2188 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 2189 } else { 2190 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 2191 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 2192 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 2193 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 2194 } 2195 2196 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 2197 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 2198 write32<E>(Buf + 24, 0x0320f809); // jalr $25 2199 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 2200 2201 uint64_t GotPlt = InX::GotPlt->getVA(); 2202 writeMipsHi16<E>(Buf, GotPlt); 2203 writeMipsLo16<E>(Buf + 4, GotPlt); 2204 writeMipsLo16<E>(Buf + 8, GotPlt); 2205 } 2206 2207 template <class ELFT> 2208 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 2209 uint64_t PltEntryAddr, int32_t Index, 2210 unsigned RelOff) const { 2211 const endianness E = ELFT::TargetEndianness; 2212 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 2213 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 2214 // jr $25 2215 write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008); 2216 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 2217 writeMipsHi16<E>(Buf, GotPltEntryAddr); 2218 writeMipsLo16<E>(Buf + 4, GotPltEntryAddr); 2219 writeMipsLo16<E>(Buf + 12, GotPltEntryAddr); 2220 } 2221 2222 template <class ELFT> 2223 bool MipsTargetInfo<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, 2224 const InputFile *File, 2225 const SymbolBody &S) const { 2226 // Any MIPS PIC code function is invoked with its address in register $t9. 2227 // So if we have a branch instruction from non-PIC code to the PIC one 2228 // we cannot make the jump directly and need to create a small stubs 2229 // to save the target function address. 2230 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 2231 if (Type != R_MIPS_26) 2232 return false; 2233 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 2234 if (!F) 2235 return false; 2236 // If current file has PIC code, LA25 stub is not required. 2237 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 2238 return false; 2239 auto *D = dyn_cast<DefinedRegular>(&S); 2240 // LA25 is required if target file has PIC code 2241 // or target symbol is a PIC symbol. 2242 return D && D->isMipsPIC<ELFT>(); 2243 } 2244 2245 template <class ELFT> 2246 int64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf, 2247 uint32_t Type) const { 2248 const endianness E = ELFT::TargetEndianness; 2249 switch (Type) { 2250 default: 2251 return 0; 2252 case R_MIPS_32: 2253 case R_MIPS_GPREL32: 2254 case R_MIPS_TLS_DTPREL32: 2255 case R_MIPS_TLS_TPREL32: 2256 return SignExtend64<32>(read32<E>(Buf)); 2257 case R_MIPS_26: 2258 // FIXME (simon): If the relocation target symbol is not a PLT entry 2259 // we should use another expression for calculation: 2260 // ((A << 2) | (P & 0xf0000000)) >> 2 2261 return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2); 2262 case R_MIPS_GPREL16: 2263 case R_MIPS_LO16: 2264 case R_MIPS_PCLO16: 2265 case R_MIPS_TLS_DTPREL_HI16: 2266 case R_MIPS_TLS_DTPREL_LO16: 2267 case R_MIPS_TLS_TPREL_HI16: 2268 case R_MIPS_TLS_TPREL_LO16: 2269 return SignExtend64<16>(read32<E>(Buf)); 2270 case R_MIPS_PC16: 2271 return getPcRelocAddend<E, 16, 2>(Buf); 2272 case R_MIPS_PC19_S2: 2273 return getPcRelocAddend<E, 19, 2>(Buf); 2274 case R_MIPS_PC21_S2: 2275 return getPcRelocAddend<E, 21, 2>(Buf); 2276 case R_MIPS_PC26_S2: 2277 return getPcRelocAddend<E, 26, 2>(Buf); 2278 case R_MIPS_PC32: 2279 return getPcRelocAddend<E, 32, 0>(Buf); 2280 } 2281 } 2282 2283 static std::pair<uint32_t, uint64_t> 2284 calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) { 2285 // MIPS N64 ABI packs multiple relocations into the single relocation 2286 // record. In general, all up to three relocations can have arbitrary 2287 // types. In fact, Clang and GCC uses only a few combinations. For now, 2288 // we support two of them. That is allow to pass at least all LLVM 2289 // test suite cases. 2290 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 2291 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 2292 // The first relocation is a 'real' relocation which is calculated 2293 // using the corresponding symbol's value. The second and the third 2294 // relocations used to modify result of the first one: extend it to 2295 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 2296 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 2297 uint32_t Type2 = (Type >> 8) & 0xff; 2298 uint32_t Type3 = (Type >> 16) & 0xff; 2299 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 2300 return std::make_pair(Type, Val); 2301 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 2302 return std::make_pair(Type2, Val); 2303 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 2304 return std::make_pair(Type3, -Val); 2305 error(getErrorLocation(Loc) + "unsupported relocations combination " + 2306 Twine(Type)); 2307 return std::make_pair(Type & 0xff, Val); 2308 } 2309 2310 template <class ELFT> 2311 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 2312 uint64_t Val) const { 2313 const endianness E = ELFT::TargetEndianness; 2314 // Thread pointer and DRP offsets from the start of TLS data area. 2315 // https://www.linux-mips.org/wiki/NPTL 2316 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 2317 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64) 2318 Val -= 0x8000; 2319 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 2320 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64) 2321 Val -= 0x7000; 2322 if (ELFT::Is64Bits || Config->MipsN32Abi) 2323 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 2324 switch (Type) { 2325 case R_MIPS_32: 2326 case R_MIPS_GPREL32: 2327 case R_MIPS_TLS_DTPREL32: 2328 case R_MIPS_TLS_TPREL32: 2329 write32<E>(Loc, Val); 2330 break; 2331 case R_MIPS_64: 2332 case R_MIPS_TLS_DTPREL64: 2333 case R_MIPS_TLS_TPREL64: 2334 write64<E>(Loc, Val); 2335 break; 2336 case R_MIPS_26: 2337 write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff)); 2338 break; 2339 case R_MIPS_GOT16: 2340 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 2341 // is updated addend (not a GOT index). In that case write high 16 bits 2342 // to store a correct addend value. 2343 if (Config->Relocatable) 2344 writeMipsHi16<E>(Loc, Val); 2345 else { 2346 checkInt<16>(Loc, Val, Type); 2347 writeMipsLo16<E>(Loc, Val); 2348 } 2349 break; 2350 case R_MIPS_GOT_DISP: 2351 case R_MIPS_GOT_PAGE: 2352 case R_MIPS_GPREL16: 2353 case R_MIPS_TLS_GD: 2354 case R_MIPS_TLS_LDM: 2355 checkInt<16>(Loc, Val, Type); 2356 // fallthrough 2357 case R_MIPS_CALL16: 2358 case R_MIPS_CALL_LO16: 2359 case R_MIPS_GOT_LO16: 2360 case R_MIPS_GOT_OFST: 2361 case R_MIPS_LO16: 2362 case R_MIPS_PCLO16: 2363 case R_MIPS_TLS_DTPREL_LO16: 2364 case R_MIPS_TLS_GOTTPREL: 2365 case R_MIPS_TLS_TPREL_LO16: 2366 writeMipsLo16<E>(Loc, Val); 2367 break; 2368 case R_MIPS_CALL_HI16: 2369 case R_MIPS_GOT_HI16: 2370 case R_MIPS_HI16: 2371 case R_MIPS_PCHI16: 2372 case R_MIPS_TLS_DTPREL_HI16: 2373 case R_MIPS_TLS_TPREL_HI16: 2374 writeMipsHi16<E>(Loc, Val); 2375 break; 2376 case R_MIPS_HIGHER: 2377 writeMipsHigher<E>(Loc, Val); 2378 break; 2379 case R_MIPS_HIGHEST: 2380 writeMipsHighest<E>(Loc, Val); 2381 break; 2382 case R_MIPS_JALR: 2383 // Ignore this optimization relocation for now 2384 break; 2385 case R_MIPS_PC16: 2386 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val); 2387 break; 2388 case R_MIPS_PC19_S2: 2389 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val); 2390 break; 2391 case R_MIPS_PC21_S2: 2392 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val); 2393 break; 2394 case R_MIPS_PC26_S2: 2395 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val); 2396 break; 2397 case R_MIPS_PC32: 2398 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val); 2399 break; 2400 default: 2401 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 2402 } 2403 } 2404 2405 template <class ELFT> 2406 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const { 2407 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST; 2408 } 2409 } 2410 } 2411