1 //===- Target.cpp ---------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Machine-specific things, such as applying relocations, creation of 11 // GOT or PLT entries, etc., are handled in this file. 12 // 13 // Refer the ELF spec for the single letter variables, S, A or P, used 14 // in this file. 15 // 16 // Some functions defined in this file has "relaxTls" as part of their names. 17 // They do peephole optimization for TLS variables by rewriting instructions. 18 // They are not part of the ABI but optional optimization, so you can skip 19 // them if you are not interested in how TLS variables are optimized. 20 // See the following paper for the details. 21 // 22 // Ulrich Drepper, ELF Handling For Thread-Local Storage 23 // http://www.akkadia.org/drepper/tls.pdf 24 // 25 //===----------------------------------------------------------------------===// 26 27 #include "Target.h" 28 #include "Error.h" 29 #include "InputFiles.h" 30 #include "OutputSections.h" 31 #include "Symbols.h" 32 #include "SyntheticSections.h" 33 #include "Thunks.h" 34 #include "Writer.h" 35 #include "lld/Support/Memory.h" 36 #include "llvm/ADT/ArrayRef.h" 37 #include "llvm/Object/ELF.h" 38 #include "llvm/Support/ELF.h" 39 #include "llvm/Support/Endian.h" 40 41 using namespace llvm; 42 using namespace llvm::object; 43 using namespace llvm::support::endian; 44 using namespace llvm::ELF; 45 46 namespace lld { 47 namespace elf { 48 49 TargetInfo *Target; 50 51 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); } 52 static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); } 53 54 std::string toString(uint32_t Type) { 55 return getELFRelocationTypeName(Config->EMachine, Type); 56 } 57 58 template <unsigned N> 59 static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) { 60 if (!isInt<N>(V)) 61 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 62 " out of range"); 63 } 64 65 template <unsigned N> 66 static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 67 if (!isUInt<N>(V)) 68 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 69 " out of range"); 70 } 71 72 template <unsigned N> 73 static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 74 if (!isInt<N>(V) && !isUInt<N>(V)) 75 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 76 " out of range"); 77 } 78 79 template <unsigned N> 80 static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) { 81 if ((V & (N - 1)) != 0) 82 error(getErrorLocation(Loc) + "improper alignment for relocation " + 83 toString(Type)); 84 } 85 86 namespace { 87 class X86TargetInfo final : public TargetInfo { 88 public: 89 X86TargetInfo(); 90 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 91 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 92 void writeGotPltHeader(uint8_t *Buf) const override; 93 uint32_t getDynRel(uint32_t Type) const override; 94 bool isTlsLocalDynamicRel(uint32_t Type) const override; 95 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 96 bool isTlsInitialExecRel(uint32_t Type) const override; 97 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 98 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 99 void writePltHeader(uint8_t *Buf) const override; 100 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 101 int32_t Index, unsigned RelOff) const override; 102 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 103 104 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 105 RelExpr Expr) const override; 106 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 107 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 108 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 109 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 110 }; 111 112 template <class ELFT> class X86_64TargetInfo final : public TargetInfo { 113 public: 114 X86_64TargetInfo(); 115 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 116 bool isPicRel(uint32_t Type) const override; 117 bool isTlsLocalDynamicRel(uint32_t Type) const override; 118 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 119 bool isTlsInitialExecRel(uint32_t Type) const override; 120 void writeGotPltHeader(uint8_t *Buf) const override; 121 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 122 void writePltHeader(uint8_t *Buf) const override; 123 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 124 int32_t Index, unsigned RelOff) const override; 125 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 126 127 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 128 RelExpr Expr) const override; 129 void relaxGot(uint8_t *Loc, uint64_t Val) const override; 130 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 131 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 132 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 133 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 134 135 private: 136 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op, 137 uint8_t ModRm) const; 138 }; 139 140 class PPCTargetInfo final : public TargetInfo { 141 public: 142 PPCTargetInfo(); 143 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 144 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 145 }; 146 147 class PPC64TargetInfo final : public TargetInfo { 148 public: 149 PPC64TargetInfo(); 150 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 151 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 152 int32_t Index, unsigned RelOff) const override; 153 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 154 }; 155 156 class AArch64TargetInfo final : public TargetInfo { 157 public: 158 AArch64TargetInfo(); 159 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 160 bool isPicRel(uint32_t Type) const override; 161 bool isTlsInitialExecRel(uint32_t Type) const override; 162 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 163 void writePltHeader(uint8_t *Buf) const override; 164 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 165 int32_t Index, unsigned RelOff) const override; 166 bool usesOnlyLowPageBits(uint32_t Type) const override; 167 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 168 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 169 RelExpr Expr) const override; 170 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 171 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 172 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 173 }; 174 175 class AMDGPUTargetInfo final : public TargetInfo { 176 public: 177 AMDGPUTargetInfo(); 178 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 179 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 180 }; 181 182 class ARMTargetInfo final : public TargetInfo { 183 public: 184 ARMTargetInfo(); 185 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 186 bool isPicRel(uint32_t Type) const override; 187 uint32_t getDynRel(uint32_t Type) const override; 188 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 189 bool isTlsLocalDynamicRel(uint32_t Type) const override; 190 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 191 bool isTlsInitialExecRel(uint32_t Type) const override; 192 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 193 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 194 void writePltHeader(uint8_t *Buf) const override; 195 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 196 int32_t Index, unsigned RelOff) const override; 197 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File, 198 const SymbolBody &S) const override; 199 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 200 }; 201 202 template <class ELFT> class MipsTargetInfo final : public TargetInfo { 203 public: 204 MipsTargetInfo(); 205 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 206 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 207 bool isPicRel(uint32_t Type) const override; 208 uint32_t getDynRel(uint32_t Type) const override; 209 bool isTlsLocalDynamicRel(uint32_t Type) const override; 210 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 211 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 212 void writePltHeader(uint8_t *Buf) const override; 213 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 214 int32_t Index, unsigned RelOff) const override; 215 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File, 216 const SymbolBody &S) const override; 217 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 218 bool usesOnlyLowPageBits(uint32_t Type) const override; 219 }; 220 } // anonymous namespace 221 222 TargetInfo *createTarget() { 223 switch (Config->EMachine) { 224 case EM_386: 225 case EM_IAMCU: 226 return make<X86TargetInfo>(); 227 case EM_AARCH64: 228 return make<AArch64TargetInfo>(); 229 case EM_AMDGPU: 230 return make<AMDGPUTargetInfo>(); 231 case EM_ARM: 232 return make<ARMTargetInfo>(); 233 case EM_MIPS: 234 switch (Config->EKind) { 235 case ELF32LEKind: 236 return make<MipsTargetInfo<ELF32LE>>(); 237 case ELF32BEKind: 238 return make<MipsTargetInfo<ELF32BE>>(); 239 case ELF64LEKind: 240 return make<MipsTargetInfo<ELF64LE>>(); 241 case ELF64BEKind: 242 return make<MipsTargetInfo<ELF64BE>>(); 243 default: 244 fatal("unsupported MIPS target"); 245 } 246 case EM_PPC: 247 return make<PPCTargetInfo>(); 248 case EM_PPC64: 249 return make<PPC64TargetInfo>(); 250 case EM_X86_64: 251 if (Config->EKind == ELF32LEKind) 252 return make<X86_64TargetInfo<ELF32LE>>(); 253 return make<X86_64TargetInfo<ELF64LE>>(); 254 } 255 fatal("unknown target machine"); 256 } 257 258 TargetInfo::~TargetInfo() {} 259 260 uint64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, 261 uint32_t Type) const { 262 return 0; 263 } 264 265 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; } 266 267 RelExpr TargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType, 268 const InputFile &File, 269 const SymbolBody &S) const { 270 return Expr; 271 } 272 273 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; } 274 275 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; } 276 277 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { return false; } 278 279 void TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 280 writeGotPlt(Buf, S); 281 } 282 283 RelExpr TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 284 RelExpr Expr) const { 285 return Expr; 286 } 287 288 void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const { 289 llvm_unreachable("Should not have claimed to be relaxable"); 290 } 291 292 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 293 uint64_t Val) const { 294 llvm_unreachable("Should not have claimed to be relaxable"); 295 } 296 297 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 298 uint64_t Val) const { 299 llvm_unreachable("Should not have claimed to be relaxable"); 300 } 301 302 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 303 uint64_t Val) const { 304 llvm_unreachable("Should not have claimed to be relaxable"); 305 } 306 307 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 308 uint64_t Val) const { 309 llvm_unreachable("Should not have claimed to be relaxable"); 310 } 311 312 X86TargetInfo::X86TargetInfo() { 313 CopyRel = R_386_COPY; 314 GotRel = R_386_GLOB_DAT; 315 PltRel = R_386_JUMP_SLOT; 316 IRelativeRel = R_386_IRELATIVE; 317 RelativeRel = R_386_RELATIVE; 318 TlsGotRel = R_386_TLS_TPOFF; 319 TlsModuleIndexRel = R_386_TLS_DTPMOD32; 320 TlsOffsetRel = R_386_TLS_DTPOFF32; 321 GotEntrySize = 4; 322 GotPltEntrySize = 4; 323 PltEntrySize = 16; 324 PltHeaderSize = 16; 325 TlsGdRelaxSkip = 2; 326 } 327 328 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 329 switch (Type) { 330 default: 331 return R_ABS; 332 case R_386_TLS_GD: 333 return R_TLSGD; 334 case R_386_TLS_LDM: 335 return R_TLSLD; 336 case R_386_PLT32: 337 return R_PLT_PC; 338 case R_386_PC16: 339 case R_386_PC32: 340 return R_PC; 341 case R_386_GOTPC: 342 return R_GOTONLY_PC_FROM_END; 343 case R_386_TLS_IE: 344 return R_GOT; 345 case R_386_GOT32: 346 case R_386_GOT32X: 347 case R_386_TLS_GOTIE: 348 return R_GOT_FROM_END; 349 case R_386_GOTOFF: 350 return R_GOTREL_FROM_END; 351 case R_386_TLS_LE: 352 return R_TLS; 353 case R_386_TLS_LE_32: 354 return R_NEG_TLS; 355 } 356 } 357 358 RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 359 RelExpr Expr) const { 360 switch (Expr) { 361 default: 362 return Expr; 363 case R_RELAX_TLS_GD_TO_IE: 364 return R_RELAX_TLS_GD_TO_IE_END; 365 case R_RELAX_TLS_GD_TO_LE: 366 return R_RELAX_TLS_GD_TO_LE_NEG; 367 } 368 } 369 370 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const { 371 write32le(Buf, In<ELF32LE>::Dynamic->getVA()); 372 } 373 374 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const { 375 // Entries in .got.plt initially points back to the corresponding 376 // PLT entries with a fixed offset to skip the first instruction. 377 write32le(Buf, S.getPltVA<ELF32LE>() + 6); 378 } 379 380 void X86TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 381 // An x86 entry is the address of the ifunc resolver function. 382 write32le(Buf, S.getVA<ELF32LE>()); 383 } 384 385 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const { 386 if (Type == R_386_TLS_LE) 387 return R_386_TLS_TPOFF; 388 if (Type == R_386_TLS_LE_32) 389 return R_386_TLS_TPOFF32; 390 return Type; 391 } 392 393 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 394 return Type == R_386_TLS_GD; 395 } 396 397 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 398 return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM; 399 } 400 401 bool X86TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 402 return Type == R_386_TLS_IE || Type == R_386_TLS_GOTIE; 403 } 404 405 void X86TargetInfo::writePltHeader(uint8_t *Buf) const { 406 // Executable files and shared object files have 407 // separate procedure linkage tables. 408 if (Config->Pic) { 409 const uint8_t V[] = { 410 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl 4(%ebx) 411 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *8(%ebx) 412 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 413 }; 414 memcpy(Buf, V, sizeof(V)); 415 return; 416 } 417 418 const uint8_t PltData[] = { 419 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOT+4) 420 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOT+8) 421 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 422 }; 423 memcpy(Buf, PltData, sizeof(PltData)); 424 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 425 write32le(Buf + 2, Got + 4); 426 write32le(Buf + 8, Got + 8); 427 } 428 429 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 430 uint64_t PltEntryAddr, int32_t Index, 431 unsigned RelOff) const { 432 const uint8_t Inst[] = { 433 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx) 434 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset 435 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC 436 }; 437 memcpy(Buf, Inst, sizeof(Inst)); 438 439 // jmp *foo@GOT(%ebx) or jmp *foo_in_GOT 440 Buf[1] = Config->Pic ? 0xa3 : 0x25; 441 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 442 write32le(Buf + 2, Config->Shared ? GotEntryAddr - Got : GotEntryAddr); 443 write32le(Buf + 7, RelOff); 444 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 445 } 446 447 uint64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf, 448 uint32_t Type) const { 449 switch (Type) { 450 default: 451 return 0; 452 case R_386_16: 453 case R_386_PC16: 454 return read16le(Buf); 455 case R_386_32: 456 case R_386_GOT32: 457 case R_386_GOT32X: 458 case R_386_GOTOFF: 459 case R_386_GOTPC: 460 case R_386_PC32: 461 case R_386_PLT32: 462 case R_386_TLS_LE: 463 return read32le(Buf); 464 } 465 } 466 467 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 468 uint64_t Val) const { 469 checkInt<32>(Loc, Val, Type); 470 471 // R_386_PC16 and R_386_16 are not part of the current i386 psABI. They are 472 // used by 16-bit x86 objects, like boot loaders. 473 if (Type == R_386_16 || Type == R_386_PC16) { 474 write16le(Loc, Val); 475 return; 476 } 477 write32le(Loc, Val); 478 } 479 480 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 481 uint64_t Val) const { 482 // Convert 483 // leal x@tlsgd(, %ebx, 1), 484 // call __tls_get_addr@plt 485 // to 486 // movl %gs:0,%eax 487 // subl $x@ntpoff,%eax 488 const uint8_t Inst[] = { 489 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 490 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax 491 }; 492 memcpy(Loc - 3, Inst, sizeof(Inst)); 493 relocateOne(Loc + 5, R_386_32, Val); 494 } 495 496 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 497 uint64_t Val) const { 498 // Convert 499 // leal x@tlsgd(, %ebx, 1), 500 // call __tls_get_addr@plt 501 // to 502 // movl %gs:0, %eax 503 // addl x@gotntpoff(%ebx), %eax 504 const uint8_t Inst[] = { 505 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 506 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax 507 }; 508 memcpy(Loc - 3, Inst, sizeof(Inst)); 509 relocateOne(Loc + 5, R_386_32, Val); 510 } 511 512 // In some conditions, relocations can be optimized to avoid using GOT. 513 // This function does that for Initial Exec to Local Exec case. 514 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 515 uint64_t Val) const { 516 // Ulrich's document section 6.2 says that @gotntpoff can 517 // be used with MOVL or ADDL instructions. 518 // @indntpoff is similar to @gotntpoff, but for use in 519 // position dependent code. 520 uint8_t Reg = (Loc[-1] >> 3) & 7; 521 522 if (Type == R_386_TLS_IE) { 523 if (Loc[-1] == 0xa1) { 524 // "movl foo@indntpoff,%eax" -> "movl $foo,%eax" 525 // This case is different from the generic case below because 526 // this is a 5 byte instruction while below is 6 bytes. 527 Loc[-1] = 0xb8; 528 } else if (Loc[-2] == 0x8b) { 529 // "movl foo@indntpoff,%reg" -> "movl $foo,%reg" 530 Loc[-2] = 0xc7; 531 Loc[-1] = 0xc0 | Reg; 532 } else { 533 // "addl foo@indntpoff,%reg" -> "addl $foo,%reg" 534 Loc[-2] = 0x81; 535 Loc[-1] = 0xc0 | Reg; 536 } 537 } else { 538 assert(Type == R_386_TLS_GOTIE); 539 if (Loc[-2] == 0x8b) { 540 // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg" 541 Loc[-2] = 0xc7; 542 Loc[-1] = 0xc0 | Reg; 543 } else { 544 // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg" 545 Loc[-2] = 0x8d; 546 Loc[-1] = 0x80 | (Reg << 3) | Reg; 547 } 548 } 549 relocateOne(Loc, R_386_TLS_LE, Val); 550 } 551 552 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 553 uint64_t Val) const { 554 if (Type == R_386_TLS_LDO_32) { 555 relocateOne(Loc, R_386_TLS_LE, Val); 556 return; 557 } 558 559 // Convert 560 // leal foo(%reg),%eax 561 // call ___tls_get_addr 562 // to 563 // movl %gs:0,%eax 564 // nop 565 // leal 0(%esi,1),%esi 566 const uint8_t Inst[] = { 567 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax 568 0x90, // nop 569 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi 570 }; 571 memcpy(Loc - 2, Inst, sizeof(Inst)); 572 } 573 574 template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() { 575 CopyRel = R_X86_64_COPY; 576 GotRel = R_X86_64_GLOB_DAT; 577 PltRel = R_X86_64_JUMP_SLOT; 578 RelativeRel = R_X86_64_RELATIVE; 579 IRelativeRel = R_X86_64_IRELATIVE; 580 TlsGotRel = R_X86_64_TPOFF64; 581 TlsModuleIndexRel = R_X86_64_DTPMOD64; 582 TlsOffsetRel = R_X86_64_DTPOFF64; 583 GotEntrySize = 8; 584 GotPltEntrySize = 8; 585 PltEntrySize = 16; 586 PltHeaderSize = 16; 587 TlsGdRelaxSkip = 2; 588 // Align to the large page size (known as a superpage or huge page). 589 // FreeBSD automatically promotes large, superpage-aligned allocations. 590 DefaultImageBase = 0x200000; 591 } 592 593 template <class ELFT> 594 RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type, 595 const SymbolBody &S) const { 596 switch (Type) { 597 default: 598 return R_ABS; 599 case R_X86_64_TPOFF32: 600 return R_TLS; 601 case R_X86_64_TLSLD: 602 return R_TLSLD_PC; 603 case R_X86_64_TLSGD: 604 return R_TLSGD_PC; 605 case R_X86_64_SIZE32: 606 case R_X86_64_SIZE64: 607 return R_SIZE; 608 case R_X86_64_PLT32: 609 return R_PLT_PC; 610 case R_X86_64_PC32: 611 case R_X86_64_PC64: 612 return R_PC; 613 case R_X86_64_GOT32: 614 case R_X86_64_GOT64: 615 return R_GOT_FROM_END; 616 case R_X86_64_GOTPCREL: 617 case R_X86_64_GOTPCRELX: 618 case R_X86_64_REX_GOTPCRELX: 619 case R_X86_64_GOTTPOFF: 620 return R_GOT_PC; 621 case R_X86_64_NONE: 622 return R_HINT; 623 } 624 } 625 626 template <class ELFT> 627 void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const { 628 // The first entry holds the value of _DYNAMIC. It is not clear why that is 629 // required, but it is documented in the psabi and the glibc dynamic linker 630 // seems to use it (note that this is relevant for linking ld.so, not any 631 // other program). 632 write64le(Buf, In<ELFT>::Dynamic->getVA()); 633 } 634 635 template <class ELFT> 636 void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, 637 const SymbolBody &S) const { 638 // See comments in X86TargetInfo::writeGotPlt. 639 write32le(Buf, S.getPltVA<ELFT>() + 6); 640 } 641 642 template <class ELFT> 643 void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 644 const uint8_t PltData[] = { 645 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOT+8(%rip) 646 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOT+16(%rip) 647 0x0f, 0x1f, 0x40, 0x00 // nopl 0x0(rax) 648 }; 649 memcpy(Buf, PltData, sizeof(PltData)); 650 uint64_t Got = In<ELFT>::GotPlt->getVA(); 651 uint64_t Plt = In<ELFT>::Plt->getVA(); 652 write32le(Buf + 2, Got - Plt + 2); // GOT+8 653 write32le(Buf + 8, Got - Plt + 4); // GOT+16 654 } 655 656 template <class ELFT> 657 void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 658 uint64_t PltEntryAddr, int32_t Index, 659 unsigned RelOff) const { 660 const uint8_t Inst[] = { 661 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip) 662 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index> 663 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0] 664 }; 665 memcpy(Buf, Inst, sizeof(Inst)); 666 667 write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6); 668 write32le(Buf + 7, Index); 669 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 670 } 671 672 template <class ELFT> 673 bool X86_64TargetInfo<ELFT>::isPicRel(uint32_t Type) const { 674 return Type != R_X86_64_PC32 && Type != R_X86_64_32; 675 } 676 677 template <class ELFT> 678 bool X86_64TargetInfo<ELFT>::isTlsInitialExecRel(uint32_t Type) const { 679 return Type == R_X86_64_GOTTPOFF; 680 } 681 682 template <class ELFT> 683 bool X86_64TargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 684 return Type == R_X86_64_TLSGD; 685 } 686 687 template <class ELFT> 688 bool X86_64TargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 689 return Type == R_X86_64_DTPOFF32 || Type == R_X86_64_DTPOFF64 || 690 Type == R_X86_64_TLSLD; 691 } 692 693 template <class ELFT> 694 void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 695 uint64_t Val) const { 696 // Convert 697 // .byte 0x66 698 // leaq x@tlsgd(%rip), %rdi 699 // .word 0x6666 700 // rex64 701 // call __tls_get_addr@plt 702 // to 703 // mov %fs:0x0,%rax 704 // lea x@tpoff,%rax 705 const uint8_t Inst[] = { 706 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 707 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax 708 }; 709 memcpy(Loc - 4, Inst, sizeof(Inst)); 710 // The original code used a pc relative relocation and so we have to 711 // compensate for the -4 in had in the addend. 712 relocateOne(Loc + 8, R_X86_64_TPOFF32, Val + 4); 713 } 714 715 template <class ELFT> 716 void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 717 uint64_t Val) const { 718 // Convert 719 // .byte 0x66 720 // leaq x@tlsgd(%rip), %rdi 721 // .word 0x6666 722 // rex64 723 // call __tls_get_addr@plt 724 // to 725 // mov %fs:0x0,%rax 726 // addq x@tpoff,%rax 727 const uint8_t Inst[] = { 728 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 729 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax 730 }; 731 memcpy(Loc - 4, Inst, sizeof(Inst)); 732 // Both code sequences are PC relatives, but since we are moving the constant 733 // forward by 8 bytes we have to subtract the value by 8. 734 relocateOne(Loc + 8, R_X86_64_PC32, Val - 8); 735 } 736 737 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to 738 // R_X86_64_TPOFF32 so that it does not use GOT. 739 template <class ELFT> 740 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 741 uint64_t Val) const { 742 uint8_t *Inst = Loc - 3; 743 uint8_t Reg = Loc[-1] >> 3; 744 uint8_t *RegSlot = Loc - 1; 745 746 // Note that ADD with RSP or R12 is converted to ADD instead of LEA 747 // because LEA with these registers needs 4 bytes to encode and thus 748 // wouldn't fit the space. 749 750 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) { 751 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp" 752 memcpy(Inst, "\x48\x81\xc4", 3); 753 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) { 754 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12" 755 memcpy(Inst, "\x49\x81\xc4", 3); 756 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) { 757 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]" 758 memcpy(Inst, "\x4d\x8d", 2); 759 *RegSlot = 0x80 | (Reg << 3) | Reg; 760 } else if (memcmp(Inst, "\x48\x03", 2) == 0) { 761 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg" 762 memcpy(Inst, "\x48\x8d", 2); 763 *RegSlot = 0x80 | (Reg << 3) | Reg; 764 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) { 765 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]" 766 memcpy(Inst, "\x49\xc7", 2); 767 *RegSlot = 0xc0 | Reg; 768 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) { 769 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg" 770 memcpy(Inst, "\x48\xc7", 2); 771 *RegSlot = 0xc0 | Reg; 772 } else { 773 fatal(getErrorLocation(Loc - 3) + 774 "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only"); 775 } 776 777 // The original code used a PC relative relocation. 778 // Need to compensate for the -4 it had in the addend. 779 relocateOne(Loc, R_X86_64_TPOFF32, Val + 4); 780 } 781 782 template <class ELFT> 783 void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 784 uint64_t Val) const { 785 // Convert 786 // leaq bar@tlsld(%rip), %rdi 787 // callq __tls_get_addr@PLT 788 // leaq bar@dtpoff(%rax), %rcx 789 // to 790 // .word 0x6666 791 // .byte 0x66 792 // mov %fs:0,%rax 793 // leaq bar@tpoff(%rax), %rcx 794 if (Type == R_X86_64_DTPOFF64) { 795 write64le(Loc, Val); 796 return; 797 } 798 if (Type == R_X86_64_DTPOFF32) { 799 relocateOne(Loc, R_X86_64_TPOFF32, Val); 800 return; 801 } 802 803 const uint8_t Inst[] = { 804 0x66, 0x66, // .word 0x6666 805 0x66, // .byte 0x66 806 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax 807 }; 808 memcpy(Loc - 3, Inst, sizeof(Inst)); 809 } 810 811 template <class ELFT> 812 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 813 uint64_t Val) const { 814 switch (Type) { 815 case R_X86_64_32: 816 checkUInt<32>(Loc, Val, Type); 817 write32le(Loc, Val); 818 break; 819 case R_X86_64_32S: 820 case R_X86_64_TPOFF32: 821 case R_X86_64_GOT32: 822 case R_X86_64_GOTPCREL: 823 case R_X86_64_GOTPCRELX: 824 case R_X86_64_REX_GOTPCRELX: 825 case R_X86_64_PC32: 826 case R_X86_64_GOTTPOFF: 827 case R_X86_64_PLT32: 828 case R_X86_64_TLSGD: 829 case R_X86_64_TLSLD: 830 case R_X86_64_DTPOFF32: 831 case R_X86_64_SIZE32: 832 checkInt<32>(Loc, Val, Type); 833 write32le(Loc, Val); 834 break; 835 case R_X86_64_64: 836 case R_X86_64_DTPOFF64: 837 case R_X86_64_GLOB_DAT: 838 case R_X86_64_PC64: 839 case R_X86_64_SIZE64: 840 case R_X86_64_GOT64: 841 write64le(Loc, Val); 842 break; 843 default: 844 fatal(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 845 } 846 } 847 848 template <class ELFT> 849 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type, 850 const uint8_t *Data, 851 RelExpr RelExpr) const { 852 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX) 853 return RelExpr; 854 const uint8_t Op = Data[-2]; 855 const uint8_t ModRm = Data[-1]; 856 // FIXME: When PIC is disabled and foo is defined locally in the 857 // lower 32 bit address space, memory operand in mov can be converted into 858 // immediate operand. Otherwise, mov must be changed to lea. We support only 859 // latter relaxation at this moment. 860 if (Op == 0x8b) 861 return R_RELAX_GOT_PC; 862 // Relax call and jmp. 863 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25)) 864 return R_RELAX_GOT_PC; 865 866 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor. 867 // If PIC then no relaxation is available. 868 // We also don't relax test/binop instructions without REX byte, 869 // they are 32bit operations and not common to have. 870 assert(Type == R_X86_64_REX_GOTPCRELX); 871 return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC; 872 } 873 874 // A subset of relaxations can only be applied for no-PIC. This method 875 // handles such relaxations. Instructions encoding information was taken from: 876 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2" 877 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/ 878 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf) 879 template <class ELFT> 880 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val, 881 uint8_t Op, uint8_t ModRm) const { 882 const uint8_t Rex = Loc[-3]; 883 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg". 884 if (Op == 0x85) { 885 // See "TEST-Logical Compare" (4-428 Vol. 2B), 886 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension). 887 888 // ModR/M byte has form XX YYY ZZZ, where 889 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1). 890 // XX has different meanings: 891 // 00: The operand's memory address is in reg1. 892 // 01: The operand's memory address is reg1 + a byte-sized displacement. 893 // 10: The operand's memory address is reg1 + a word-sized displacement. 894 // 11: The operand is reg1 itself. 895 // If an instruction requires only one operand, the unused reg2 field 896 // holds extra opcode bits rather than a register code 897 // 0xC0 == 11 000 000 binary. 898 // 0x38 == 00 111 000 binary. 899 // We transfer reg2 to reg1 here as operand. 900 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3). 901 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte. 902 903 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32 904 // See "TEST-Logical Compare" (4-428 Vol. 2B). 905 Loc[-2] = 0xf7; 906 907 // Move R bit to the B bit in REX byte. 908 // REX byte is encoded as 0100WRXB, where 909 // 0100 is 4bit fixed pattern. 910 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the 911 // default operand size is used (which is 32-bit for most but not all 912 // instructions). 913 // REX.R This 1-bit value is an extension to the MODRM.reg field. 914 // REX.X This 1-bit value is an extension to the SIB.index field. 915 // REX.B This 1-bit value is an extension to the MODRM.rm field or the 916 // SIB.base field. 917 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A). 918 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 919 relocateOne(Loc, R_X86_64_PC32, Val); 920 return; 921 } 922 923 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub 924 // or xor operations. 925 926 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg". 927 // Logic is close to one for test instruction above, but we also 928 // write opcode extension here, see below for details. 929 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte. 930 931 // Primary opcode is 0x81, opcode extension is one of: 932 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB, 933 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP. 934 // This value was wrote to MODRM.reg in a line above. 935 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15), 936 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for 937 // descriptions about each operation. 938 Loc[-2] = 0x81; 939 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 940 relocateOne(Loc, R_X86_64_PC32, Val); 941 } 942 943 template <class ELFT> 944 void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const { 945 const uint8_t Op = Loc[-2]; 946 const uint8_t ModRm = Loc[-1]; 947 948 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg". 949 if (Op == 0x8b) { 950 Loc[-2] = 0x8d; 951 relocateOne(Loc, R_X86_64_PC32, Val); 952 return; 953 } 954 955 if (Op != 0xff) { 956 // We are relaxing a rip relative to an absolute, so compensate 957 // for the old -4 addend. 958 assert(!Config->Pic); 959 relaxGotNoPic(Loc, Val + 4, Op, ModRm); 960 return; 961 } 962 963 // Convert call/jmp instructions. 964 if (ModRm == 0x15) { 965 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo". 966 // Instead we convert to "addr32 call foo" where addr32 is an instruction 967 // prefix. That makes result expression to be a single instruction. 968 Loc[-2] = 0x67; // addr32 prefix 969 Loc[-1] = 0xe8; // call 970 relocateOne(Loc, R_X86_64_PC32, Val); 971 return; 972 } 973 974 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop". 975 // jmp doesn't return, so it is fine to use nop here, it is just a stub. 976 assert(ModRm == 0x25); 977 Loc[-2] = 0xe9; // jmp 978 Loc[3] = 0x90; // nop 979 relocateOne(Loc - 1, R_X86_64_PC32, Val + 1); 980 } 981 982 // Relocation masks following the #lo(value), #hi(value), #ha(value), 983 // #higher(value), #highera(value), #highest(value), and #highesta(value) 984 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 985 // document. 986 static uint16_t applyPPCLo(uint64_t V) { return V; } 987 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; } 988 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; } 989 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; } 990 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; } 991 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; } 992 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; } 993 994 PPCTargetInfo::PPCTargetInfo() {} 995 996 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 997 uint64_t Val) const { 998 switch (Type) { 999 case R_PPC_ADDR16_HA: 1000 write16be(Loc, applyPPCHa(Val)); 1001 break; 1002 case R_PPC_ADDR16_LO: 1003 write16be(Loc, applyPPCLo(Val)); 1004 break; 1005 case R_PPC_ADDR32: 1006 case R_PPC_REL32: 1007 write32be(Loc, Val); 1008 break; 1009 case R_PPC_REL24: 1010 or32be(Loc, Val & 0x3FFFFFC); 1011 break; 1012 default: 1013 fatal(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1014 } 1015 } 1016 1017 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1018 switch (Type) { 1019 case R_PPC_REL24: 1020 case R_PPC_REL32: 1021 return R_PC; 1022 default: 1023 return R_ABS; 1024 } 1025 } 1026 1027 PPC64TargetInfo::PPC64TargetInfo() { 1028 PltRel = GotRel = R_PPC64_GLOB_DAT; 1029 RelativeRel = R_PPC64_RELATIVE; 1030 GotEntrySize = 8; 1031 GotPltEntrySize = 8; 1032 PltEntrySize = 32; 1033 PltHeaderSize = 0; 1034 1035 // We need 64K pages (at least under glibc/Linux, the loader won't 1036 // set different permissions on a finer granularity than that). 1037 DefaultMaxPageSize = 65536; 1038 1039 // The PPC64 ELF ABI v1 spec, says: 1040 // 1041 // It is normally desirable to put segments with different characteristics 1042 // in separate 256 Mbyte portions of the address space, to give the 1043 // operating system full paging flexibility in the 64-bit address space. 1044 // 1045 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 1046 // use 0x10000000 as the starting address. 1047 DefaultImageBase = 0x10000000; 1048 } 1049 1050 static uint64_t PPC64TocOffset = 0x8000; 1051 1052 uint64_t getPPC64TocBase() { 1053 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 1054 // TOC starts where the first of these sections starts. We always create a 1055 // .got when we see a relocation that uses it, so for us the start is always 1056 // the .got. 1057 uint64_t TocVA = In<ELF64BE>::Got->getVA(); 1058 1059 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 1060 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 1061 // code (crt1.o) assumes that you can get from the TOC base to the 1062 // start of the .toc section with only a single (signed) 16-bit relocation. 1063 return TocVA + PPC64TocOffset; 1064 } 1065 1066 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1067 switch (Type) { 1068 default: 1069 return R_ABS; 1070 case R_PPC64_TOC16: 1071 case R_PPC64_TOC16_DS: 1072 case R_PPC64_TOC16_HA: 1073 case R_PPC64_TOC16_HI: 1074 case R_PPC64_TOC16_LO: 1075 case R_PPC64_TOC16_LO_DS: 1076 return R_GOTREL; 1077 case R_PPC64_TOC: 1078 return R_PPC_TOC; 1079 case R_PPC64_REL24: 1080 return R_PPC_PLT_OPD; 1081 } 1082 } 1083 1084 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1085 uint64_t PltEntryAddr, int32_t Index, 1086 unsigned RelOff) const { 1087 uint64_t Off = GotEntryAddr - getPPC64TocBase(); 1088 1089 // FIXME: What we should do, in theory, is get the offset of the function 1090 // descriptor in the .opd section, and use that as the offset from %r2 (the 1091 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will 1092 // be a pointer to the function descriptor in the .opd section. Using 1093 // this scheme is simpler, but requires an extra indirection per PLT dispatch. 1094 1095 write32be(Buf, 0xf8410028); // std %r2, 40(%r1) 1096 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha 1097 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11) 1098 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12) 1099 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11 1100 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12) 1101 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12) 1102 write32be(Buf + 28, 0x4e800420); // bctr 1103 } 1104 1105 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) { 1106 uint64_t V = Val - PPC64TocOffset; 1107 switch (Type) { 1108 case R_PPC64_TOC16: 1109 return {R_PPC64_ADDR16, V}; 1110 case R_PPC64_TOC16_DS: 1111 return {R_PPC64_ADDR16_DS, V}; 1112 case R_PPC64_TOC16_HA: 1113 return {R_PPC64_ADDR16_HA, V}; 1114 case R_PPC64_TOC16_HI: 1115 return {R_PPC64_ADDR16_HI, V}; 1116 case R_PPC64_TOC16_LO: 1117 return {R_PPC64_ADDR16_LO, V}; 1118 case R_PPC64_TOC16_LO_DS: 1119 return {R_PPC64_ADDR16_LO_DS, V}; 1120 default: 1121 return {Type, Val}; 1122 } 1123 } 1124 1125 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1126 uint64_t Val) const { 1127 // For a TOC-relative relocation, proceed in terms of the corresponding 1128 // ADDR16 relocation type. 1129 std::tie(Type, Val) = toAddr16Rel(Type, Val); 1130 1131 switch (Type) { 1132 case R_PPC64_ADDR14: { 1133 checkAlignment<4>(Loc, Val, Type); 1134 // Preserve the AA/LK bits in the branch instruction 1135 uint8_t AALK = Loc[3]; 1136 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 1137 break; 1138 } 1139 case R_PPC64_ADDR16: 1140 checkInt<16>(Loc, Val, Type); 1141 write16be(Loc, Val); 1142 break; 1143 case R_PPC64_ADDR16_DS: 1144 checkInt<16>(Loc, Val, Type); 1145 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3)); 1146 break; 1147 case R_PPC64_ADDR16_HA: 1148 case R_PPC64_REL16_HA: 1149 write16be(Loc, applyPPCHa(Val)); 1150 break; 1151 case R_PPC64_ADDR16_HI: 1152 case R_PPC64_REL16_HI: 1153 write16be(Loc, applyPPCHi(Val)); 1154 break; 1155 case R_PPC64_ADDR16_HIGHER: 1156 write16be(Loc, applyPPCHigher(Val)); 1157 break; 1158 case R_PPC64_ADDR16_HIGHERA: 1159 write16be(Loc, applyPPCHighera(Val)); 1160 break; 1161 case R_PPC64_ADDR16_HIGHEST: 1162 write16be(Loc, applyPPCHighest(Val)); 1163 break; 1164 case R_PPC64_ADDR16_HIGHESTA: 1165 write16be(Loc, applyPPCHighesta(Val)); 1166 break; 1167 case R_PPC64_ADDR16_LO: 1168 write16be(Loc, applyPPCLo(Val)); 1169 break; 1170 case R_PPC64_ADDR16_LO_DS: 1171 case R_PPC64_REL16_LO: 1172 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3)); 1173 break; 1174 case R_PPC64_ADDR32: 1175 case R_PPC64_REL32: 1176 checkInt<32>(Loc, Val, Type); 1177 write32be(Loc, Val); 1178 break; 1179 case R_PPC64_ADDR64: 1180 case R_PPC64_REL64: 1181 case R_PPC64_TOC: 1182 write64be(Loc, Val); 1183 break; 1184 case R_PPC64_REL24: { 1185 uint32_t Mask = 0x03FFFFFC; 1186 checkInt<24>(Loc, Val, Type); 1187 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask)); 1188 break; 1189 } 1190 default: 1191 fatal(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1192 } 1193 } 1194 1195 AArch64TargetInfo::AArch64TargetInfo() { 1196 CopyRel = R_AARCH64_COPY; 1197 RelativeRel = R_AARCH64_RELATIVE; 1198 IRelativeRel = R_AARCH64_IRELATIVE; 1199 GotRel = R_AARCH64_GLOB_DAT; 1200 PltRel = R_AARCH64_JUMP_SLOT; 1201 TlsDescRel = R_AARCH64_TLSDESC; 1202 TlsGotRel = R_AARCH64_TLS_TPREL64; 1203 GotEntrySize = 8; 1204 GotPltEntrySize = 8; 1205 PltEntrySize = 16; 1206 PltHeaderSize = 32; 1207 DefaultMaxPageSize = 65536; 1208 1209 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant 1210 // 1 of the tls structures and the tcb size is 16. 1211 TcbSize = 16; 1212 } 1213 1214 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type, 1215 const SymbolBody &S) const { 1216 switch (Type) { 1217 default: 1218 return R_ABS; 1219 case R_AARCH64_TLSDESC_ADR_PAGE21: 1220 return R_TLSDESC_PAGE; 1221 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1222 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1223 return R_TLSDESC; 1224 case R_AARCH64_TLSDESC_CALL: 1225 return R_TLSDESC_CALL; 1226 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1227 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1228 return R_TLS; 1229 case R_AARCH64_CALL26: 1230 case R_AARCH64_CONDBR19: 1231 case R_AARCH64_JUMP26: 1232 case R_AARCH64_TSTBR14: 1233 return R_PLT_PC; 1234 case R_AARCH64_PREL16: 1235 case R_AARCH64_PREL32: 1236 case R_AARCH64_PREL64: 1237 case R_AARCH64_ADR_PREL_LO21: 1238 return R_PC; 1239 case R_AARCH64_ADR_PREL_PG_HI21: 1240 return R_PAGE_PC; 1241 case R_AARCH64_LD64_GOT_LO12_NC: 1242 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1243 return R_GOT; 1244 case R_AARCH64_ADR_GOT_PAGE: 1245 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1246 return R_GOT_PAGE_PC; 1247 } 1248 } 1249 1250 RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 1251 RelExpr Expr) const { 1252 if (Expr == R_RELAX_TLS_GD_TO_IE) { 1253 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21) 1254 return R_RELAX_TLS_GD_TO_IE_PAGE_PC; 1255 return R_RELAX_TLS_GD_TO_IE_ABS; 1256 } 1257 return Expr; 1258 } 1259 1260 bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { 1261 switch (Type) { 1262 default: 1263 return false; 1264 case R_AARCH64_ADD_ABS_LO12_NC: 1265 case R_AARCH64_LD64_GOT_LO12_NC: 1266 case R_AARCH64_LDST128_ABS_LO12_NC: 1267 case R_AARCH64_LDST16_ABS_LO12_NC: 1268 case R_AARCH64_LDST32_ABS_LO12_NC: 1269 case R_AARCH64_LDST64_ABS_LO12_NC: 1270 case R_AARCH64_LDST8_ABS_LO12_NC: 1271 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1272 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1273 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1274 return true; 1275 } 1276 } 1277 1278 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1279 return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 || 1280 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; 1281 } 1282 1283 bool AArch64TargetInfo::isPicRel(uint32_t Type) const { 1284 return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64; 1285 } 1286 1287 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1288 write64le(Buf, In<ELF64LE>::Plt->getVA()); 1289 } 1290 1291 // Page(Expr) is the page address of the expression Expr, defined 1292 // as (Expr & ~0xFFF). (This applies even if the machine page size 1293 // supported by the platform has a different value.) 1294 uint64_t getAArch64Page(uint64_t Expr) { 1295 return Expr & (~static_cast<uint64_t>(0xFFF)); 1296 } 1297 1298 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const { 1299 const uint8_t PltData[] = { 1300 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 1301 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 1302 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 1303 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 1304 0x20, 0x02, 0x1f, 0xd6, // br x17 1305 0x1f, 0x20, 0x03, 0xd5, // nop 1306 0x1f, 0x20, 0x03, 0xd5, // nop 1307 0x1f, 0x20, 0x03, 0xd5 // nop 1308 }; 1309 memcpy(Buf, PltData, sizeof(PltData)); 1310 1311 uint64_t Got = In<ELF64LE>::GotPlt->getVA(); 1312 uint64_t Plt = In<ELF64LE>::Plt->getVA(); 1313 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 1314 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4)); 1315 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16); 1316 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16); 1317 } 1318 1319 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1320 uint64_t PltEntryAddr, int32_t Index, 1321 unsigned RelOff) const { 1322 const uint8_t Inst[] = { 1323 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 1324 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 1325 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n])) 1326 0x20, 0x02, 0x1f, 0xd6 // br x17 1327 }; 1328 memcpy(Buf, Inst, sizeof(Inst)); 1329 1330 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21, 1331 getAArch64Page(GotEntryAddr) - getAArch64Page(PltEntryAddr)); 1332 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotEntryAddr); 1333 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotEntryAddr); 1334 } 1335 1336 static void write32addr(uint8_t *L, uint64_t Imm) { 1337 uint32_t ImmLo = (Imm & 0x3) << 29; 1338 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3; 1339 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3); 1340 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi); 1341 } 1342 1343 // Return the bits [Start, End] from Val shifted Start bits. 1344 // For instance, getBits(0xF0, 4, 8) returns 0xF. 1345 static uint64_t getBits(uint64_t Val, int Start, int End) { 1346 uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1; 1347 return (Val >> Start) & Mask; 1348 } 1349 1350 // Update the immediate field in a AARCH64 ldr, str, and add instruction. 1351 static void or32imm(uint8_t *L, uint64_t Imm) { 1352 or32le(L, (Imm & 0xFFF) << 10); 1353 } 1354 1355 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1356 uint64_t Val) const { 1357 switch (Type) { 1358 case R_AARCH64_ABS16: 1359 case R_AARCH64_PREL16: 1360 checkIntUInt<16>(Loc, Val, Type); 1361 write16le(Loc, Val); 1362 break; 1363 case R_AARCH64_ABS32: 1364 case R_AARCH64_PREL32: 1365 checkIntUInt<32>(Loc, Val, Type); 1366 write32le(Loc, Val); 1367 break; 1368 case R_AARCH64_ABS64: 1369 case R_AARCH64_GLOB_DAT: 1370 case R_AARCH64_PREL64: 1371 write64le(Loc, Val); 1372 break; 1373 case R_AARCH64_ADD_ABS_LO12_NC: 1374 or32imm(Loc, Val); 1375 break; 1376 case R_AARCH64_ADR_GOT_PAGE: 1377 case R_AARCH64_ADR_PREL_PG_HI21: 1378 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1379 case R_AARCH64_TLSDESC_ADR_PAGE21: 1380 checkInt<33>(Loc, Val, Type); 1381 write32addr(Loc, Val >> 12); 1382 break; 1383 case R_AARCH64_ADR_PREL_LO21: 1384 checkInt<21>(Loc, Val, Type); 1385 write32addr(Loc, Val); 1386 break; 1387 case R_AARCH64_CALL26: 1388 case R_AARCH64_JUMP26: 1389 checkInt<28>(Loc, Val, Type); 1390 or32le(Loc, (Val & 0x0FFFFFFC) >> 2); 1391 break; 1392 case R_AARCH64_CONDBR19: 1393 checkInt<21>(Loc, Val, Type); 1394 or32le(Loc, (Val & 0x1FFFFC) << 3); 1395 break; 1396 case R_AARCH64_LD64_GOT_LO12_NC: 1397 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1398 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1399 checkAlignment<8>(Loc, Val, Type); 1400 or32le(Loc, (Val & 0xFF8) << 7); 1401 break; 1402 case R_AARCH64_LDST8_ABS_LO12_NC: 1403 or32imm(Loc, getBits(Val, 0, 11)); 1404 break; 1405 case R_AARCH64_LDST16_ABS_LO12_NC: 1406 or32imm(Loc, getBits(Val, 1, 11)); 1407 break; 1408 case R_AARCH64_LDST32_ABS_LO12_NC: 1409 or32imm(Loc, getBits(Val, 2, 11)); 1410 break; 1411 case R_AARCH64_LDST64_ABS_LO12_NC: 1412 or32imm(Loc, getBits(Val, 3, 11)); 1413 break; 1414 case R_AARCH64_LDST128_ABS_LO12_NC: 1415 or32imm(Loc, getBits(Val, 4, 11)); 1416 break; 1417 case R_AARCH64_MOVW_UABS_G0_NC: 1418 or32le(Loc, (Val & 0xFFFF) << 5); 1419 break; 1420 case R_AARCH64_MOVW_UABS_G1_NC: 1421 or32le(Loc, (Val & 0xFFFF0000) >> 11); 1422 break; 1423 case R_AARCH64_MOVW_UABS_G2_NC: 1424 or32le(Loc, (Val & 0xFFFF00000000) >> 27); 1425 break; 1426 case R_AARCH64_MOVW_UABS_G3: 1427 or32le(Loc, (Val & 0xFFFF000000000000) >> 43); 1428 break; 1429 case R_AARCH64_TSTBR14: 1430 checkInt<16>(Loc, Val, Type); 1431 or32le(Loc, (Val & 0xFFFC) << 3); 1432 break; 1433 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1434 checkInt<24>(Loc, Val, Type); 1435 or32imm(Loc, Val >> 12); 1436 break; 1437 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1438 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1439 or32imm(Loc, Val); 1440 break; 1441 default: 1442 fatal(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1443 } 1444 } 1445 1446 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 1447 uint64_t Val) const { 1448 // TLSDESC Global-Dynamic relocation are in the form: 1449 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1450 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1451 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1452 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1453 // blr x1 1454 // And it can optimized to: 1455 // movz x0, #0x0, lsl #16 1456 // movk x0, #0x10 1457 // nop 1458 // nop 1459 checkUInt<32>(Loc, Val, Type); 1460 1461 switch (Type) { 1462 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1463 case R_AARCH64_TLSDESC_CALL: 1464 write32le(Loc, 0xd503201f); // nop 1465 return; 1466 case R_AARCH64_TLSDESC_ADR_PAGE21: 1467 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz 1468 return; 1469 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1470 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk 1471 return; 1472 default: 1473 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1474 } 1475 } 1476 1477 void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 1478 uint64_t Val) const { 1479 // TLSDESC Global-Dynamic relocation are in the form: 1480 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1481 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1482 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1483 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1484 // blr x1 1485 // And it can optimized to: 1486 // adrp x0, :gottprel:v 1487 // ldr x0, [x0, :gottprel_lo12:v] 1488 // nop 1489 // nop 1490 1491 switch (Type) { 1492 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1493 case R_AARCH64_TLSDESC_CALL: 1494 write32le(Loc, 0xd503201f); // nop 1495 break; 1496 case R_AARCH64_TLSDESC_ADR_PAGE21: 1497 write32le(Loc, 0x90000000); // adrp 1498 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val); 1499 break; 1500 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1501 write32le(Loc, 0xf9400000); // ldr 1502 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val); 1503 break; 1504 default: 1505 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1506 } 1507 } 1508 1509 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 1510 uint64_t Val) const { 1511 checkUInt<32>(Loc, Val, Type); 1512 1513 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) { 1514 // Generate MOVZ. 1515 uint32_t RegNo = read32le(Loc) & 0x1f; 1516 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5)); 1517 return; 1518 } 1519 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) { 1520 // Generate MOVK. 1521 uint32_t RegNo = read32le(Loc) & 0x1f; 1522 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5)); 1523 return; 1524 } 1525 llvm_unreachable("invalid relocation for TLS IE to LE relaxation"); 1526 } 1527 1528 AMDGPUTargetInfo::AMDGPUTargetInfo() { 1529 RelativeRel = R_AMDGPU_REL64; 1530 GotRel = R_AMDGPU_ABS64; 1531 GotEntrySize = 8; 1532 } 1533 1534 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1535 uint64_t Val) const { 1536 switch (Type) { 1537 case R_AMDGPU_ABS32: 1538 case R_AMDGPU_GOTPCREL: 1539 case R_AMDGPU_GOTPCREL32_LO: 1540 case R_AMDGPU_REL32: 1541 case R_AMDGPU_REL32_LO: 1542 write32le(Loc, Val); 1543 break; 1544 case R_AMDGPU_ABS64: 1545 write64le(Loc, Val); 1546 break; 1547 case R_AMDGPU_GOTPCREL32_HI: 1548 case R_AMDGPU_REL32_HI: 1549 write32le(Loc, Val >> 32); 1550 break; 1551 default: 1552 fatal(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1553 } 1554 } 1555 1556 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1557 switch (Type) { 1558 case R_AMDGPU_ABS32: 1559 case R_AMDGPU_ABS64: 1560 return R_ABS; 1561 case R_AMDGPU_REL32: 1562 case R_AMDGPU_REL32_LO: 1563 case R_AMDGPU_REL32_HI: 1564 return R_PC; 1565 case R_AMDGPU_GOTPCREL: 1566 case R_AMDGPU_GOTPCREL32_LO: 1567 case R_AMDGPU_GOTPCREL32_HI: 1568 return R_GOT_PC; 1569 default: 1570 fatal("do not know how to handle relocation " + Twine(Type)); 1571 } 1572 } 1573 1574 ARMTargetInfo::ARMTargetInfo() { 1575 CopyRel = R_ARM_COPY; 1576 RelativeRel = R_ARM_RELATIVE; 1577 IRelativeRel = R_ARM_IRELATIVE; 1578 GotRel = R_ARM_GLOB_DAT; 1579 PltRel = R_ARM_JUMP_SLOT; 1580 TlsGotRel = R_ARM_TLS_TPOFF32; 1581 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32; 1582 TlsOffsetRel = R_ARM_TLS_DTPOFF32; 1583 GotEntrySize = 4; 1584 GotPltEntrySize = 4; 1585 PltEntrySize = 16; 1586 PltHeaderSize = 20; 1587 // ARM uses Variant 1 TLS 1588 TcbSize = 8; 1589 NeedsThunks = true; 1590 } 1591 1592 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1593 switch (Type) { 1594 default: 1595 return R_ABS; 1596 case R_ARM_THM_JUMP11: 1597 return R_PC; 1598 case R_ARM_CALL: 1599 case R_ARM_JUMP24: 1600 case R_ARM_PC24: 1601 case R_ARM_PLT32: 1602 case R_ARM_PREL31: 1603 case R_ARM_THM_JUMP19: 1604 case R_ARM_THM_JUMP24: 1605 case R_ARM_THM_CALL: 1606 return R_PLT_PC; 1607 case R_ARM_GOTOFF32: 1608 // (S + A) - GOT_ORG 1609 return R_GOTREL; 1610 case R_ARM_GOT_BREL: 1611 // GOT(S) + A - GOT_ORG 1612 return R_GOT_OFF; 1613 case R_ARM_GOT_PREL: 1614 case R_ARM_TLS_IE32: 1615 // GOT(S) + A - P 1616 return R_GOT_PC; 1617 case R_ARM_TARGET1: 1618 return Config->Target1Rel ? R_PC : R_ABS; 1619 case R_ARM_TARGET2: 1620 if (Config->Target2 == Target2Policy::Rel) 1621 return R_PC; 1622 if (Config->Target2 == Target2Policy::Abs) 1623 return R_ABS; 1624 return R_GOT_PC; 1625 case R_ARM_TLS_GD32: 1626 return R_TLSGD_PC; 1627 case R_ARM_TLS_LDM32: 1628 return R_TLSLD_PC; 1629 case R_ARM_BASE_PREL: 1630 // B(S) + A - P 1631 // FIXME: currently B(S) assumed to be .got, this may not hold for all 1632 // platforms. 1633 return R_GOTONLY_PC; 1634 case R_ARM_MOVW_PREL_NC: 1635 case R_ARM_MOVT_PREL: 1636 case R_ARM_REL32: 1637 case R_ARM_THM_MOVW_PREL_NC: 1638 case R_ARM_THM_MOVT_PREL: 1639 return R_PC; 1640 case R_ARM_NONE: 1641 return R_HINT; 1642 case R_ARM_TLS_LE32: 1643 return R_TLS; 1644 } 1645 } 1646 1647 bool ARMTargetInfo::isPicRel(uint32_t Type) const { 1648 return (Type == R_ARM_TARGET1 && !Config->Target1Rel) || 1649 (Type == R_ARM_ABS32); 1650 } 1651 1652 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const { 1653 if (Type == R_ARM_TARGET1 && !Config->Target1Rel) 1654 return R_ARM_ABS32; 1655 if (Type == R_ARM_ABS32) 1656 return Type; 1657 // Keep it going with a dummy value so that we can find more reloc errors. 1658 return R_ARM_ABS32; 1659 } 1660 1661 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1662 write32le(Buf, In<ELF32LE>::Plt->getVA()); 1663 } 1664 1665 void ARMTargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 1666 // An ARM entry is the address of the ifunc resolver function. 1667 write32le(Buf, S.getVA<ELF32LE>()); 1668 } 1669 1670 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const { 1671 const uint8_t PltData[] = { 1672 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]! 1673 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2 1674 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr 1675 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8] 1676 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8 1677 }; 1678 memcpy(Buf, PltData, sizeof(PltData)); 1679 uint64_t GotPlt = In<ELF32LE>::GotPlt->getVA(); 1680 uint64_t L1 = In<ELF32LE>::Plt->getVA() + 8; 1681 write32le(Buf + 16, GotPlt - L1 - 8); 1682 } 1683 1684 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1685 uint64_t PltEntryAddr, int32_t Index, 1686 unsigned RelOff) const { 1687 // FIXME: Using simple code sequence with simple relocations. 1688 // There is a more optimal sequence but it requires support for the group 1689 // relocations. See ELF for the ARM Architecture Appendix A.3 1690 const uint8_t PltData[] = { 1691 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2 1692 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc 1693 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip] 1694 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8 1695 }; 1696 memcpy(Buf, PltData, sizeof(PltData)); 1697 uint64_t L1 = PltEntryAddr + 4; 1698 write32le(Buf + 12, GotEntryAddr - L1 - 8); 1699 } 1700 1701 RelExpr ARMTargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType, 1702 const InputFile &File, 1703 const SymbolBody &S) const { 1704 // If S is an undefined weak symbol we don't need a Thunk 1705 if (S.isUndefined()) 1706 return Expr; 1707 // A state change from ARM to Thumb and vice versa must go through an 1708 // interworking thunk if the relocation type is not R_ARM_CALL or 1709 // R_ARM_THM_CALL. 1710 switch (RelocType) { 1711 case R_ARM_PC24: 1712 case R_ARM_PLT32: 1713 case R_ARM_JUMP24: 1714 // Source is ARM, all PLT entries are ARM so no interworking required. 1715 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb). 1716 if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1)) 1717 return R_THUNK_PC; 1718 break; 1719 case R_ARM_THM_JUMP19: 1720 case R_ARM_THM_JUMP24: 1721 // Source is Thumb, all PLT entries are ARM so interworking is required. 1722 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM). 1723 if (Expr == R_PLT_PC) 1724 return R_THUNK_PLT_PC; 1725 if ((S.getVA<ELF32LE>() & 1) == 0) 1726 return R_THUNK_PC; 1727 break; 1728 } 1729 return Expr; 1730 } 1731 1732 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1733 uint64_t Val) const { 1734 switch (Type) { 1735 case R_ARM_ABS32: 1736 case R_ARM_BASE_PREL: 1737 case R_ARM_GLOB_DAT: 1738 case R_ARM_GOTOFF32: 1739 case R_ARM_GOT_BREL: 1740 case R_ARM_GOT_PREL: 1741 case R_ARM_REL32: 1742 case R_ARM_RELATIVE: 1743 case R_ARM_TARGET1: 1744 case R_ARM_TARGET2: 1745 case R_ARM_TLS_GD32: 1746 case R_ARM_TLS_IE32: 1747 case R_ARM_TLS_LDM32: 1748 case R_ARM_TLS_LDO32: 1749 case R_ARM_TLS_LE32: 1750 case R_ARM_TLS_TPOFF32: 1751 write32le(Loc, Val); 1752 break; 1753 case R_ARM_TLS_DTPMOD32: 1754 write32le(Loc, 1); 1755 break; 1756 case R_ARM_PREL31: 1757 checkInt<31>(Loc, Val, Type); 1758 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000)); 1759 break; 1760 case R_ARM_CALL: 1761 // R_ARM_CALL is used for BL and BLX instructions, depending on the 1762 // value of bit 0 of Val, we must select a BL or BLX instruction 1763 if (Val & 1) { 1764 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX. 1765 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' 1766 checkInt<26>(Loc, Val, Type); 1767 write32le(Loc, 0xfa000000 | // opcode 1768 ((Val & 2) << 23) | // H 1769 ((Val >> 2) & 0x00ffffff)); // imm24 1770 break; 1771 } 1772 if ((read32le(Loc) & 0xfe000000) == 0xfa000000) 1773 // BLX (always unconditional) instruction to an ARM Target, select an 1774 // unconditional BL. 1775 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff)); 1776 // fall through as BL encoding is shared with B 1777 case R_ARM_JUMP24: 1778 case R_ARM_PC24: 1779 case R_ARM_PLT32: 1780 checkInt<26>(Loc, Val, Type); 1781 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff)); 1782 break; 1783 case R_ARM_THM_JUMP11: 1784 checkInt<12>(Loc, Val, Type); 1785 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff)); 1786 break; 1787 case R_ARM_THM_JUMP19: 1788 // Encoding T3: Val = S:J2:J1:imm6:imm11:0 1789 checkInt<21>(Loc, Val, Type); 1790 write16le(Loc, 1791 (read16le(Loc) & 0xfbc0) | // opcode cond 1792 ((Val >> 10) & 0x0400) | // S 1793 ((Val >> 12) & 0x003f)); // imm6 1794 write16le(Loc + 2, 1795 0x8000 | // opcode 1796 ((Val >> 8) & 0x0800) | // J2 1797 ((Val >> 5) & 0x2000) | // J1 1798 ((Val >> 1) & 0x07ff)); // imm11 1799 break; 1800 case R_ARM_THM_CALL: 1801 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the 1802 // value of bit 0 of Val, we must select a BL or BLX instruction 1803 if ((Val & 1) == 0) { 1804 // Ensure BLX destination is 4-byte aligned. As BLX instruction may 1805 // only be two byte aligned. This must be done before overflow check 1806 Val = alignTo(Val, 4); 1807 } 1808 // Bit 12 is 0 for BLX, 1 for BL 1809 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12); 1810 // Fall through as rest of encoding is the same as B.W 1811 case R_ARM_THM_JUMP24: 1812 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 1813 // FIXME: Use of I1 and I2 require v6T2ops 1814 checkInt<25>(Loc, Val, Type); 1815 write16le(Loc, 1816 0xf000 | // opcode 1817 ((Val >> 14) & 0x0400) | // S 1818 ((Val >> 12) & 0x03ff)); // imm10 1819 write16le(Loc + 2, 1820 (read16le(Loc + 2) & 0xd000) | // opcode 1821 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1 1822 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2 1823 ((Val >> 1) & 0x07ff)); // imm11 1824 break; 1825 case R_ARM_MOVW_ABS_NC: 1826 case R_ARM_MOVW_PREL_NC: 1827 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) | 1828 (Val & 0x0fff)); 1829 break; 1830 case R_ARM_MOVT_ABS: 1831 case R_ARM_MOVT_PREL: 1832 checkInt<32>(Loc, Val, Type); 1833 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | 1834 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff)); 1835 break; 1836 case R_ARM_THM_MOVT_ABS: 1837 case R_ARM_THM_MOVT_PREL: 1838 // Encoding T1: A = imm4:i:imm3:imm8 1839 checkInt<32>(Loc, Val, Type); 1840 write16le(Loc, 1841 0xf2c0 | // opcode 1842 ((Val >> 17) & 0x0400) | // i 1843 ((Val >> 28) & 0x000f)); // imm4 1844 write16le(Loc + 2, 1845 (read16le(Loc + 2) & 0x8f00) | // opcode 1846 ((Val >> 12) & 0x7000) | // imm3 1847 ((Val >> 16) & 0x00ff)); // imm8 1848 break; 1849 case R_ARM_THM_MOVW_ABS_NC: 1850 case R_ARM_THM_MOVW_PREL_NC: 1851 // Encoding T3: A = imm4:i:imm3:imm8 1852 write16le(Loc, 1853 0xf240 | // opcode 1854 ((Val >> 1) & 0x0400) | // i 1855 ((Val >> 12) & 0x000f)); // imm4 1856 write16le(Loc + 2, 1857 (read16le(Loc + 2) & 0x8f00) | // opcode 1858 ((Val << 4) & 0x7000) | // imm3 1859 (Val & 0x00ff)); // imm8 1860 break; 1861 default: 1862 fatal(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1863 } 1864 } 1865 1866 uint64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf, 1867 uint32_t Type) const { 1868 switch (Type) { 1869 default: 1870 return 0; 1871 case R_ARM_ABS32: 1872 case R_ARM_BASE_PREL: 1873 case R_ARM_GOTOFF32: 1874 case R_ARM_GOT_BREL: 1875 case R_ARM_GOT_PREL: 1876 case R_ARM_REL32: 1877 case R_ARM_TARGET1: 1878 case R_ARM_TARGET2: 1879 case R_ARM_TLS_GD32: 1880 case R_ARM_TLS_LDM32: 1881 case R_ARM_TLS_LDO32: 1882 case R_ARM_TLS_IE32: 1883 case R_ARM_TLS_LE32: 1884 return SignExtend64<32>(read32le(Buf)); 1885 case R_ARM_PREL31: 1886 return SignExtend64<31>(read32le(Buf)); 1887 case R_ARM_CALL: 1888 case R_ARM_JUMP24: 1889 case R_ARM_PC24: 1890 case R_ARM_PLT32: 1891 return SignExtend64<26>(read32le(Buf) << 2); 1892 case R_ARM_THM_JUMP11: 1893 return SignExtend64<12>(read16le(Buf) << 1); 1894 case R_ARM_THM_JUMP19: { 1895 // Encoding T3: A = S:J2:J1:imm10:imm6:0 1896 uint16_t Hi = read16le(Buf); 1897 uint16_t Lo = read16le(Buf + 2); 1898 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S 1899 ((Lo & 0x0800) << 8) | // J2 1900 ((Lo & 0x2000) << 5) | // J1 1901 ((Hi & 0x003f) << 12) | // imm6 1902 ((Lo & 0x07ff) << 1)); // imm11:0 1903 } 1904 case R_ARM_THM_CALL: 1905 case R_ARM_THM_JUMP24: { 1906 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 1907 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) 1908 // FIXME: I1 and I2 require v6T2ops 1909 uint16_t Hi = read16le(Buf); 1910 uint16_t Lo = read16le(Buf + 2); 1911 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S 1912 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1 1913 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2 1914 ((Hi & 0x003ff) << 12) | // imm0 1915 ((Lo & 0x007ff) << 1)); // imm11:0 1916 } 1917 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and 1918 // MOVT is in the range -32768 <= A < 32768 1919 case R_ARM_MOVW_ABS_NC: 1920 case R_ARM_MOVT_ABS: 1921 case R_ARM_MOVW_PREL_NC: 1922 case R_ARM_MOVT_PREL: { 1923 uint64_t Val = read32le(Buf) & 0x000f0fff; 1924 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff)); 1925 } 1926 case R_ARM_THM_MOVW_ABS_NC: 1927 case R_ARM_THM_MOVT_ABS: 1928 case R_ARM_THM_MOVW_PREL_NC: 1929 case R_ARM_THM_MOVT_PREL: { 1930 // Encoding T3: A = imm4:i:imm3:imm8 1931 uint16_t Hi = read16le(Buf); 1932 uint16_t Lo = read16le(Buf + 2); 1933 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4 1934 ((Hi & 0x0400) << 1) | // i 1935 ((Lo & 0x7000) >> 4) | // imm3 1936 (Lo & 0x00ff)); // imm8 1937 } 1938 } 1939 } 1940 1941 bool ARMTargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 1942 return Type == R_ARM_TLS_LDO32 || Type == R_ARM_TLS_LDM32; 1943 } 1944 1945 bool ARMTargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 1946 return Type == R_ARM_TLS_GD32; 1947 } 1948 1949 bool ARMTargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1950 return Type == R_ARM_TLS_IE32; 1951 } 1952 1953 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() { 1954 GotPltHeaderEntriesNum = 2; 1955 DefaultMaxPageSize = 65536; 1956 GotEntrySize = sizeof(typename ELFT::uint); 1957 GotPltEntrySize = sizeof(typename ELFT::uint); 1958 PltEntrySize = 16; 1959 PltHeaderSize = 32; 1960 CopyRel = R_MIPS_COPY; 1961 PltRel = R_MIPS_JUMP_SLOT; 1962 NeedsThunks = true; 1963 if (ELFT::Is64Bits) { 1964 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 1965 TlsGotRel = R_MIPS_TLS_TPREL64; 1966 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 1967 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 1968 } else { 1969 RelativeRel = R_MIPS_REL32; 1970 TlsGotRel = R_MIPS_TLS_TPREL32; 1971 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 1972 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 1973 } 1974 } 1975 1976 template <class ELFT> 1977 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type, 1978 const SymbolBody &S) const { 1979 // See comment in the calculateMipsRelChain. 1980 if (ELFT::Is64Bits || Config->MipsN32Abi) 1981 Type &= 0xff; 1982 switch (Type) { 1983 default: 1984 return R_ABS; 1985 case R_MIPS_JALR: 1986 return R_HINT; 1987 case R_MIPS_GPREL16: 1988 case R_MIPS_GPREL32: 1989 return R_MIPS_GOTREL; 1990 case R_MIPS_26: 1991 return R_PLT; 1992 case R_MIPS_HI16: 1993 case R_MIPS_LO16: 1994 case R_MIPS_GOT_OFST: 1995 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 1996 // offset between start of function and 'gp' value which by default 1997 // equal to the start of .got section. In that case we consider these 1998 // relocations as relative. 1999 if (&S == ElfSym<ELFT>::MipsGpDisp) 2000 return R_PC; 2001 return R_ABS; 2002 case R_MIPS_PC32: 2003 case R_MIPS_PC16: 2004 case R_MIPS_PC19_S2: 2005 case R_MIPS_PC21_S2: 2006 case R_MIPS_PC26_S2: 2007 case R_MIPS_PCHI16: 2008 case R_MIPS_PCLO16: 2009 return R_PC; 2010 case R_MIPS_GOT16: 2011 if (S.isLocal()) 2012 return R_MIPS_GOT_LOCAL_PAGE; 2013 // fallthrough 2014 case R_MIPS_CALL16: 2015 case R_MIPS_GOT_DISP: 2016 case R_MIPS_TLS_GOTTPREL: 2017 return R_MIPS_GOT_OFF; 2018 case R_MIPS_CALL_HI16: 2019 case R_MIPS_CALL_LO16: 2020 case R_MIPS_GOT_HI16: 2021 case R_MIPS_GOT_LO16: 2022 return R_MIPS_GOT_OFF32; 2023 case R_MIPS_GOT_PAGE: 2024 return R_MIPS_GOT_LOCAL_PAGE; 2025 case R_MIPS_TLS_GD: 2026 return R_MIPS_TLSGD; 2027 case R_MIPS_TLS_LDM: 2028 return R_MIPS_TLSLD; 2029 } 2030 } 2031 2032 template <class ELFT> bool MipsTargetInfo<ELFT>::isPicRel(uint32_t Type) const { 2033 return Type == R_MIPS_32 || Type == R_MIPS_64; 2034 } 2035 2036 template <class ELFT> 2037 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const { 2038 return RelativeRel; 2039 } 2040 2041 template <class ELFT> 2042 bool MipsTargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 2043 return Type == R_MIPS_TLS_LDM; 2044 } 2045 2046 template <class ELFT> 2047 bool MipsTargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 2048 return Type == R_MIPS_TLS_GD; 2049 } 2050 2051 template <class ELFT> 2052 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 2053 write32<ELFT::TargetEndianness>(Buf, In<ELFT>::Plt->getVA()); 2054 } 2055 2056 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2057 static int64_t getPcRelocAddend(const uint8_t *Loc) { 2058 uint32_t Instr = read32<E>(Loc); 2059 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2060 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT); 2061 } 2062 2063 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2064 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) { 2065 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2066 uint32_t Instr = read32<E>(Loc); 2067 if (SHIFT > 0) 2068 checkAlignment<(1 << SHIFT)>(Loc, V, Type); 2069 checkInt<BSIZE + SHIFT>(Loc, V, Type); 2070 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask)); 2071 } 2072 2073 template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) { 2074 uint32_t Instr = read32<E>(Loc); 2075 uint16_t Res = ((V + 0x8000) >> 16) & 0xffff; 2076 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2077 } 2078 2079 template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) { 2080 uint32_t Instr = read32<E>(Loc); 2081 uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff; 2082 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2083 } 2084 2085 template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) { 2086 uint32_t Instr = read32<E>(Loc); 2087 uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff; 2088 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2089 } 2090 2091 template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) { 2092 uint32_t Instr = read32<E>(Loc); 2093 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff)); 2094 } 2095 2096 template <class ELFT> static bool isMipsR6() { 2097 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf); 2098 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH; 2099 return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6; 2100 } 2101 2102 template <class ELFT> 2103 void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 2104 const endianness E = ELFT::TargetEndianness; 2105 if (Config->MipsN32Abi) { 2106 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 2107 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 2108 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 2109 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 2110 } else { 2111 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 2112 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 2113 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 2114 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 2115 } 2116 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 2117 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 2118 write32<E>(Buf + 24, 0x0320f809); // jalr $25 2119 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 2120 uint64_t Got = In<ELFT>::GotPlt->getVA(); 2121 writeMipsHi16<E>(Buf, Got); 2122 writeMipsLo16<E>(Buf + 4, Got); 2123 writeMipsLo16<E>(Buf + 8, Got); 2124 } 2125 2126 template <class ELFT> 2127 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 2128 uint64_t PltEntryAddr, int32_t Index, 2129 unsigned RelOff) const { 2130 const endianness E = ELFT::TargetEndianness; 2131 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 2132 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 2133 // jr $25 2134 write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008); 2135 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 2136 writeMipsHi16<E>(Buf, GotEntryAddr); 2137 writeMipsLo16<E>(Buf + 4, GotEntryAddr); 2138 writeMipsLo16<E>(Buf + 12, GotEntryAddr); 2139 } 2140 2141 template <class ELFT> 2142 RelExpr MipsTargetInfo<ELFT>::getThunkExpr(RelExpr Expr, uint32_t Type, 2143 const InputFile &File, 2144 const SymbolBody &S) const { 2145 // Any MIPS PIC code function is invoked with its address in register $t9. 2146 // So if we have a branch instruction from non-PIC code to the PIC one 2147 // we cannot make the jump directly and need to create a small stubs 2148 // to save the target function address. 2149 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 2150 if (Type != R_MIPS_26) 2151 return Expr; 2152 auto *F = dyn_cast<ELFFileBase<ELFT>>(&File); 2153 if (!F) 2154 return Expr; 2155 // If current file has PIC code, LA25 stub is not required. 2156 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 2157 return Expr; 2158 auto *D = dyn_cast<DefinedRegular<ELFT>>(&S); 2159 // LA25 is required if target file has PIC code 2160 // or target symbol is a PIC symbol. 2161 return D && D->isMipsPIC() ? R_THUNK_ABS : Expr; 2162 } 2163 2164 template <class ELFT> 2165 uint64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf, 2166 uint32_t Type) const { 2167 const endianness E = ELFT::TargetEndianness; 2168 switch (Type) { 2169 default: 2170 return 0; 2171 case R_MIPS_32: 2172 case R_MIPS_GPREL32: 2173 case R_MIPS_TLS_DTPREL32: 2174 case R_MIPS_TLS_TPREL32: 2175 return read32<E>(Buf); 2176 case R_MIPS_26: 2177 // FIXME (simon): If the relocation target symbol is not a PLT entry 2178 // we should use another expression for calculation: 2179 // ((A << 2) | (P & 0xf0000000)) >> 2 2180 return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2); 2181 case R_MIPS_GPREL16: 2182 case R_MIPS_LO16: 2183 case R_MIPS_PCLO16: 2184 case R_MIPS_TLS_DTPREL_HI16: 2185 case R_MIPS_TLS_DTPREL_LO16: 2186 case R_MIPS_TLS_TPREL_HI16: 2187 case R_MIPS_TLS_TPREL_LO16: 2188 return SignExtend64<16>(read32<E>(Buf)); 2189 case R_MIPS_PC16: 2190 return getPcRelocAddend<E, 16, 2>(Buf); 2191 case R_MIPS_PC19_S2: 2192 return getPcRelocAddend<E, 19, 2>(Buf); 2193 case R_MIPS_PC21_S2: 2194 return getPcRelocAddend<E, 21, 2>(Buf); 2195 case R_MIPS_PC26_S2: 2196 return getPcRelocAddend<E, 26, 2>(Buf); 2197 case R_MIPS_PC32: 2198 return getPcRelocAddend<E, 32, 0>(Buf); 2199 } 2200 } 2201 2202 static std::pair<uint32_t, uint64_t> 2203 calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) { 2204 // MIPS N64 ABI packs multiple relocations into the single relocation 2205 // record. In general, all up to three relocations can have arbitrary 2206 // types. In fact, Clang and GCC uses only a few combinations. For now, 2207 // we support two of them. That is allow to pass at least all LLVM 2208 // test suite cases. 2209 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 2210 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 2211 // The first relocation is a 'real' relocation which is calculated 2212 // using the corresponding symbol's value. The second and the third 2213 // relocations used to modify result of the first one: extend it to 2214 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 2215 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 2216 uint32_t Type2 = (Type >> 8) & 0xff; 2217 uint32_t Type3 = (Type >> 16) & 0xff; 2218 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 2219 return std::make_pair(Type, Val); 2220 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 2221 return std::make_pair(Type2, Val); 2222 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 2223 return std::make_pair(Type3, -Val); 2224 error(getErrorLocation(Loc) + "unsupported relocations combination " + 2225 Twine(Type)); 2226 return std::make_pair(Type & 0xff, Val); 2227 } 2228 2229 template <class ELFT> 2230 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 2231 uint64_t Val) const { 2232 const endianness E = ELFT::TargetEndianness; 2233 // Thread pointer and DRP offsets from the start of TLS data area. 2234 // https://www.linux-mips.org/wiki/NPTL 2235 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 2236 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64) 2237 Val -= 0x8000; 2238 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 2239 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64) 2240 Val -= 0x7000; 2241 if (ELFT::Is64Bits || Config->MipsN32Abi) 2242 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 2243 switch (Type) { 2244 case R_MIPS_32: 2245 case R_MIPS_GPREL32: 2246 case R_MIPS_TLS_DTPREL32: 2247 case R_MIPS_TLS_TPREL32: 2248 write32<E>(Loc, Val); 2249 break; 2250 case R_MIPS_64: 2251 case R_MIPS_TLS_DTPREL64: 2252 case R_MIPS_TLS_TPREL64: 2253 write64<E>(Loc, Val); 2254 break; 2255 case R_MIPS_26: 2256 write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff)); 2257 break; 2258 case R_MIPS_GOT_DISP: 2259 case R_MIPS_GOT_PAGE: 2260 case R_MIPS_GOT16: 2261 case R_MIPS_GPREL16: 2262 case R_MIPS_TLS_GD: 2263 case R_MIPS_TLS_LDM: 2264 checkInt<16>(Loc, Val, Type); 2265 // fallthrough 2266 case R_MIPS_CALL16: 2267 case R_MIPS_CALL_LO16: 2268 case R_MIPS_GOT_LO16: 2269 case R_MIPS_GOT_OFST: 2270 case R_MIPS_LO16: 2271 case R_MIPS_PCLO16: 2272 case R_MIPS_TLS_DTPREL_LO16: 2273 case R_MIPS_TLS_GOTTPREL: 2274 case R_MIPS_TLS_TPREL_LO16: 2275 writeMipsLo16<E>(Loc, Val); 2276 break; 2277 case R_MIPS_CALL_HI16: 2278 case R_MIPS_GOT_HI16: 2279 case R_MIPS_HI16: 2280 case R_MIPS_PCHI16: 2281 case R_MIPS_TLS_DTPREL_HI16: 2282 case R_MIPS_TLS_TPREL_HI16: 2283 writeMipsHi16<E>(Loc, Val); 2284 break; 2285 case R_MIPS_HIGHER: 2286 writeMipsHigher<E>(Loc, Val); 2287 break; 2288 case R_MIPS_HIGHEST: 2289 writeMipsHighest<E>(Loc, Val); 2290 break; 2291 case R_MIPS_JALR: 2292 // Ignore this optimization relocation for now 2293 break; 2294 case R_MIPS_PC16: 2295 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val); 2296 break; 2297 case R_MIPS_PC19_S2: 2298 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val); 2299 break; 2300 case R_MIPS_PC21_S2: 2301 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val); 2302 break; 2303 case R_MIPS_PC26_S2: 2304 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val); 2305 break; 2306 case R_MIPS_PC32: 2307 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val); 2308 break; 2309 default: 2310 fatal(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 2311 } 2312 } 2313 2314 template <class ELFT> 2315 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const { 2316 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST; 2317 } 2318 } 2319 } 2320