1 //===- Target.cpp ---------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Machine-specific things, such as applying relocations, creation of 11 // GOT or PLT entries, etc., are handled in this file. 12 // 13 // Refer the ELF spec for the single letter varaibles, S, A or P, used 14 // in this file. 15 // 16 //===----------------------------------------------------------------------===// 17 18 #include "Target.h" 19 #include "Error.h" 20 #include "InputFiles.h" 21 #include "OutputSections.h" 22 #include "Symbols.h" 23 24 #include "llvm/ADT/ArrayRef.h" 25 #include "llvm/Object/ELF.h" 26 #include "llvm/Support/Endian.h" 27 #include "llvm/Support/ELF.h" 28 29 using namespace llvm; 30 using namespace llvm::object; 31 using namespace llvm::support::endian; 32 using namespace llvm::ELF; 33 34 namespace lld { 35 namespace elf { 36 37 TargetInfo *Target; 38 39 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); } 40 41 template <unsigned N> static void checkInt(int64_t V, uint32_t Type) { 42 if (isInt<N>(V)) 43 return; 44 StringRef S = getELFRelocationTypeName(Config->EMachine, Type); 45 error("relocation " + S + " out of range"); 46 } 47 48 template <unsigned N> static void checkUInt(uint64_t V, uint32_t Type) { 49 if (isUInt<N>(V)) 50 return; 51 StringRef S = getELFRelocationTypeName(Config->EMachine, Type); 52 error("relocation " + S + " out of range"); 53 } 54 55 template <unsigned N> static void checkIntUInt(uint64_t V, uint32_t Type) { 56 if (isInt<N>(V) || isUInt<N>(V)) 57 return; 58 StringRef S = getELFRelocationTypeName(Config->EMachine, Type); 59 error("relocation " + S + " out of range"); 60 } 61 62 template <unsigned N> static void checkAlignment(uint64_t V, uint32_t Type) { 63 if ((V & (N - 1)) == 0) 64 return; 65 StringRef S = getELFRelocationTypeName(Config->EMachine, Type); 66 error("improper alignment for relocation " + S); 67 } 68 69 namespace { 70 class X86TargetInfo final : public TargetInfo { 71 public: 72 X86TargetInfo(); 73 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 74 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 75 void writeGotPltHeader(uint8_t *Buf) const override; 76 uint32_t getDynRel(uint32_t Type) const override; 77 uint32_t getTlsGotRel(uint32_t Type) const override; 78 bool pointsToLocalDynamicGotEntry(uint32_t Type) const override; 79 bool isTlsLocalDynamicRel(uint32_t Type) const override; 80 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 81 bool isTlsInitialExecRel(uint32_t Type) const override; 82 void writeGotPlt(uint8_t *Buf, uint64_t Plt) const override; 83 void writePltZero(uint8_t *Buf) const override; 84 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 85 int32_t Index, unsigned RelOff) const override; 86 bool isRelRelative(uint32_t Type) const override; 87 bool needsCopyRelImpl(uint32_t Type) const override; 88 bool needsDynRelative(uint32_t Type) const override; 89 bool needsGot(uint32_t Type, const SymbolBody &S) const override; 90 bool needsPltImpl(uint32_t Type) const override; 91 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 92 93 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 94 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 95 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 96 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 97 98 bool isGotRelative(uint32_t Type) const override; 99 bool refersToGotEntry(uint32_t Type) const override; 100 }; 101 102 class X86_64TargetInfo final : public TargetInfo { 103 public: 104 X86_64TargetInfo(); 105 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 106 uint32_t getDynRel(uint32_t Type) const override; 107 uint32_t getTlsGotRel(uint32_t Type) const override; 108 bool pointsToLocalDynamicGotEntry(uint32_t Type) const override; 109 bool isTlsLocalDynamicRel(uint32_t Type) const override; 110 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 111 bool isTlsInitialExecRel(uint32_t Type) const override; 112 void writeGotPltHeader(uint8_t *Buf) const override; 113 void writeGotPlt(uint8_t *Buf, uint64_t Plt) const override; 114 void writePltZero(uint8_t *Buf) const override; 115 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 116 int32_t Index, unsigned RelOff) const override; 117 bool needsCopyRelImpl(uint32_t Type) const override; 118 bool needsGot(uint32_t Type, const SymbolBody &S) const override; 119 bool refersToGotEntry(uint32_t Type) const override; 120 bool needsPltImpl(uint32_t Type) const override; 121 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 122 bool isRelRelative(uint32_t Type) const override; 123 124 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 125 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 126 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 127 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 128 }; 129 130 class PPCTargetInfo final : public TargetInfo { 131 public: 132 PPCTargetInfo(); 133 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 134 bool isRelRelative(uint32_t Type) const override; 135 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 136 }; 137 138 class PPC64TargetInfo final : public TargetInfo { 139 public: 140 PPC64TargetInfo(); 141 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 142 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 143 int32_t Index, unsigned RelOff) const override; 144 bool needsGot(uint32_t Type, const SymbolBody &S) const override; 145 bool needsPltImpl(uint32_t Type) const override; 146 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 147 bool isRelRelative(uint32_t Type) const override; 148 }; 149 150 class AArch64TargetInfo final : public TargetInfo { 151 public: 152 AArch64TargetInfo(); 153 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 154 uint32_t getDynRel(uint32_t Type) const override; 155 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 156 bool isTlsInitialExecRel(uint32_t Type) const override; 157 void writeGotPlt(uint8_t *Buf, uint64_t Plt) const override; 158 void writePltZero(uint8_t *Buf) const override; 159 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 160 int32_t Index, unsigned RelOff) const override; 161 uint32_t getTlsGotRel(uint32_t Type) const override; 162 bool isRelRelative(uint32_t Type) const override; 163 bool needsCopyRelImpl(uint32_t Type) const override; 164 bool needsGot(uint32_t Type, const SymbolBody &S) const override; 165 bool refersToGotEntry(uint32_t Type) const override; 166 bool needsPltImpl(uint32_t Type) const override; 167 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 168 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 169 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 170 171 private: 172 static const uint64_t TcbSize = 16; 173 }; 174 175 class AMDGPUTargetInfo final : public TargetInfo { 176 public: 177 AMDGPUTargetInfo() {} 178 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 179 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 180 }; 181 182 template <class ELFT> class MipsTargetInfo final : public TargetInfo { 183 public: 184 MipsTargetInfo(); 185 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 186 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 187 uint32_t getDynRel(uint32_t Type) const override; 188 void writeGotPlt(uint8_t *Buf, uint64_t Plt) const override; 189 void writePltZero(uint8_t *Buf) const override; 190 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 191 int32_t Index, unsigned RelOff) const override; 192 void writeGotHeader(uint8_t *Buf) const override; 193 void writeThunk(uint8_t *Buf, uint64_t S) const override; 194 bool needsCopyRelImpl(uint32_t Type) const override; 195 bool needsGot(uint32_t Type, const SymbolBody &S) const override; 196 bool needsPltImpl(uint32_t Type) const override; 197 bool needsThunk(uint32_t Type, const InputFile &File, 198 const SymbolBody &S) const override; 199 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 200 bool isHintRel(uint32_t Type) const override; 201 bool isRelRelative(uint32_t Type) const override; 202 bool refersToGotEntry(uint32_t Type) const override; 203 }; 204 } // anonymous namespace 205 206 TargetInfo *createTarget() { 207 switch (Config->EMachine) { 208 case EM_386: 209 return new X86TargetInfo(); 210 case EM_AARCH64: 211 return new AArch64TargetInfo(); 212 case EM_AMDGPU: 213 return new AMDGPUTargetInfo(); 214 case EM_MIPS: 215 switch (Config->EKind) { 216 case ELF32LEKind: 217 return new MipsTargetInfo<ELF32LE>(); 218 case ELF32BEKind: 219 return new MipsTargetInfo<ELF32BE>(); 220 default: 221 fatal("unsupported MIPS target"); 222 } 223 case EM_PPC: 224 return new PPCTargetInfo(); 225 case EM_PPC64: 226 return new PPC64TargetInfo(); 227 case EM_X86_64: 228 return new X86_64TargetInfo(); 229 } 230 fatal("unknown target machine"); 231 } 232 233 TargetInfo::~TargetInfo() {} 234 235 uint64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, 236 uint32_t Type) const { 237 return 0; 238 } 239 240 bool TargetInfo::canRelaxTls(uint32_t Type, const SymbolBody *S) const { 241 if (Config->Shared || (S && !S->isTls())) 242 return false; 243 244 // We know we are producing an executable. 245 246 // Global-Dynamic relocs can be relaxed to Initial-Exec or Local-Exec 247 // depending on the symbol being locally defined or not. 248 if (isTlsGlobalDynamicRel(Type)) 249 return true; 250 251 // Local-Dynamic relocs can be relaxed to Local-Exec. 252 if (isTlsLocalDynamicRel(Type)) 253 return true; 254 255 // Initial-Exec relocs can be relaxed to Local-Exec if the symbol is locally 256 // defined. 257 if (isTlsInitialExecRel(Type)) 258 return !S->isPreemptible(); 259 260 return false; 261 } 262 263 uint64_t TargetInfo::getVAStart() const { return Config->Pic ? 0 : VAStart; } 264 265 bool TargetInfo::needsCopyRelImpl(uint32_t Type) const { return false; } 266 267 template <typename ELFT> static bool mayNeedCopy(const SymbolBody &S) { 268 if (Config->Shared) 269 return false; 270 auto *SS = dyn_cast<SharedSymbol<ELFT>>(&S); 271 if (!SS) 272 return false; 273 return SS->isObject(); 274 } 275 276 template <class ELFT> 277 bool TargetInfo::needsCopyRel(uint32_t Type, const SymbolBody &S) const { 278 return mayNeedCopy<ELFT>(S) && needsCopyRelImpl(Type); 279 } 280 281 bool TargetInfo::isGotRelative(uint32_t Type) const { return false; } 282 bool TargetInfo::isHintRel(uint32_t Type) const { return false; } 283 bool TargetInfo::isRelRelative(uint32_t Type) const { return true; } 284 285 bool TargetInfo::needsGot(uint32_t Type, const SymbolBody &S) const { 286 return false; 287 } 288 289 bool TargetInfo::needsPltImpl(uint32_t Type) const { return false; } 290 291 bool TargetInfo::refersToGotEntry(uint32_t Type) const { return false; } 292 293 TargetInfo::PltNeed TargetInfo::needsPlt(uint32_t Type, 294 const SymbolBody &S) const { 295 if (S.isGnuIFunc()) 296 return Plt_Explicit; 297 if (S.isPreemptible() && needsPltImpl(Type)) 298 return Plt_Explicit; 299 300 // This handles a non PIC program call to function in a shared library. 301 // In an ideal world, we could just report an error saying the relocation 302 // can overflow at runtime. 303 // In the real world with glibc, crt1.o has a R_X86_64_PC32 pointing to 304 // libc.so. 305 // 306 // The general idea on how to handle such cases is to create a PLT entry 307 // and use that as the function value. 308 // 309 // For the static linking part, we just return true and everything else 310 // will use the the PLT entry as the address. 311 // 312 // The remaining problem is making sure pointer equality still works. We 313 // need the help of the dynamic linker for that. We let it know that we have 314 // a direct reference to a so symbol by creating an undefined symbol with a 315 // non zero st_value. Seeing that, the dynamic linker resolves the symbol to 316 // the value of the symbol we created. This is true even for got entries, so 317 // pointer equality is maintained. To avoid an infinite loop, the only entry 318 // that points to the real function is a dedicated got entry used by the 319 // plt. That is identified by special relocation types (R_X86_64_JUMP_SLOT, 320 // R_386_JMP_SLOT, etc). 321 if (S.isShared()) 322 if (!Config->Pic && S.isFunc() && !refersToGotEntry(Type)) 323 return Plt_Implicit; 324 325 return Plt_No; 326 } 327 328 bool TargetInfo::needsThunk(uint32_t Type, const InputFile &File, 329 const SymbolBody &S) const { 330 return false; 331 } 332 333 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; } 334 335 bool TargetInfo::pointsToLocalDynamicGotEntry(uint32_t Type) const { 336 return false; 337 } 338 339 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; } 340 341 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 342 return false; 343 } 344 345 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 346 uint64_t Val) const { 347 llvm_unreachable("Should not have claimed to be relaxable"); 348 } 349 350 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 351 uint64_t Val) const { 352 llvm_unreachable("Should not have claimed to be relaxable"); 353 } 354 355 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 356 uint64_t Val) const { 357 llvm_unreachable("Should not have claimed to be relaxable"); 358 } 359 360 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 361 uint64_t Val) const { 362 llvm_unreachable("Should not have claimed to be relaxable"); 363 } 364 365 X86TargetInfo::X86TargetInfo() { 366 CopyRel = R_386_COPY; 367 GotRel = R_386_GLOB_DAT; 368 PltRel = R_386_JUMP_SLOT; 369 IRelativeRel = R_386_IRELATIVE; 370 RelativeRel = R_386_RELATIVE; 371 TlsGotRel = R_386_TLS_TPOFF; 372 TlsModuleIndexRel = R_386_TLS_DTPMOD32; 373 TlsOffsetRel = R_386_TLS_DTPOFF32; 374 UseLazyBinding = true; 375 PltEntrySize = 16; 376 PltZeroSize = 16; 377 TlsGdToLeSkip = 2; 378 } 379 380 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 381 switch (Type) { 382 default: 383 return R_ABS; 384 case R_386_PLT32: 385 case R_386_PC32: 386 case R_386_GOTPC: 387 return R_PC; 388 } 389 } 390 391 bool X86TargetInfo::isRelRelative(uint32_t Type) const { 392 switch (Type) { 393 default: 394 return false; 395 case R_386_PC32: 396 case R_386_PLT32: 397 case R_386_TLS_LDO_32: 398 return true; 399 } 400 } 401 402 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const { 403 write32le(Buf, Out<ELF32LE>::Dynamic->getVA()); 404 } 405 406 void X86TargetInfo::writeGotPlt(uint8_t *Buf, uint64_t Plt) const { 407 // Entries in .got.plt initially points back to the corresponding 408 // PLT entries with a fixed offset to skip the first instruction. 409 write32le(Buf, Plt + 6); 410 } 411 412 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const { 413 if (Type == R_386_TLS_LE) 414 return R_386_TLS_TPOFF; 415 if (Type == R_386_TLS_LE_32) 416 return R_386_TLS_TPOFF32; 417 return Type; 418 } 419 420 uint32_t X86TargetInfo::getTlsGotRel(uint32_t Type) const { 421 if (Type == R_386_TLS_IE) 422 return Type; 423 return R_386_GOT32; 424 } 425 426 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 427 return Type == R_386_TLS_GD; 428 } 429 430 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 431 return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM; 432 } 433 434 bool X86TargetInfo::pointsToLocalDynamicGotEntry(uint32_t Type) const { 435 return Type == R_386_TLS_LDM; 436 } 437 438 bool X86TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 439 return Type == R_386_TLS_IE || Type == R_386_TLS_GOTIE; 440 } 441 442 void X86TargetInfo::writePltZero(uint8_t *Buf) const { 443 // Executable files and shared object files have 444 // separate procedure linkage tables. 445 if (Config->Pic) { 446 const uint8_t V[] = { 447 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl 4(%ebx) 448 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *8(%ebx) 449 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 450 }; 451 memcpy(Buf, V, sizeof(V)); 452 return; 453 } 454 455 const uint8_t PltData[] = { 456 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOT+4) 457 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOT+8) 458 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 459 }; 460 memcpy(Buf, PltData, sizeof(PltData)); 461 uint32_t Got = Out<ELF32LE>::GotPlt->getVA(); 462 write32le(Buf + 2, Got + 4); 463 write32le(Buf + 8, Got + 8); 464 } 465 466 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 467 uint64_t PltEntryAddr, int32_t Index, 468 unsigned RelOff) const { 469 const uint8_t Inst[] = { 470 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx) 471 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset 472 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC 473 }; 474 memcpy(Buf, Inst, sizeof(Inst)); 475 476 // jmp *foo@GOT(%ebx) or jmp *foo_in_GOT 477 Buf[1] = Config->Pic ? 0xa3 : 0x25; 478 uint32_t Got = UseLazyBinding ? Out<ELF32LE>::GotPlt->getVA() 479 : Out<ELF32LE>::Got->getVA(); 480 write32le(Buf + 2, Config->Shared ? GotEntryAddr - Got : GotEntryAddr); 481 write32le(Buf + 7, RelOff); 482 write32le(Buf + 12, -Index * PltEntrySize - PltZeroSize - 16); 483 } 484 485 bool X86TargetInfo::needsCopyRelImpl(uint32_t Type) const { 486 return Type == R_386_32 || Type == R_386_16 || Type == R_386_8; 487 } 488 489 bool X86TargetInfo::needsGot(uint32_t Type, const SymbolBody &S) const { 490 if (S.isTls() && Type == R_386_TLS_GD) 491 return Target->canRelaxTls(Type, &S) && S.isPreemptible(); 492 if (Type == R_386_TLS_GOTIE || Type == R_386_TLS_IE) 493 return !canRelaxTls(Type, &S); 494 return Type == R_386_GOT32 || needsPlt(Type, S); 495 } 496 497 bool X86TargetInfo::needsPltImpl(uint32_t Type) const { 498 return Type == R_386_PLT32; 499 } 500 501 bool X86TargetInfo::isGotRelative(uint32_t Type) const { 502 // This relocation does not require got entry, 503 // but it is relative to got and needs it to be created. 504 // Here we request for that. 505 return Type == R_386_GOTOFF; 506 } 507 508 bool X86TargetInfo::refersToGotEntry(uint32_t Type) const { 509 return Type == R_386_GOT32; 510 } 511 512 uint64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf, 513 uint32_t Type) const { 514 switch (Type) { 515 default: 516 return 0; 517 case R_386_32: 518 case R_386_GOT32: 519 case R_386_GOTOFF: 520 case R_386_GOTPC: 521 case R_386_PC32: 522 case R_386_PLT32: 523 return read32le(Buf); 524 } 525 } 526 527 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 528 uint64_t Val) const { 529 switch (Type) { 530 case R_386_32: 531 write32le(Loc, Val); 532 break; 533 case R_386_GOTOFF: 534 write32le(Loc, Val - Out<ELF32LE>::Got->getVA()); 535 break; 536 case R_386_GOTPC: 537 write32le(Loc, Val + Out<ELF32LE>::Got->getVA()); 538 break; 539 case R_386_PC32: 540 case R_386_PLT32: 541 write32le(Loc, Val); 542 break; 543 case R_386_GOT32: 544 case R_386_TLS_GD: 545 case R_386_TLS_LDM: { 546 uint64_t V = Val - Out<ELF32LE>::Got->getVA() - 547 Out<ELF32LE>::Got->getNumEntries() * 4; 548 checkInt<32>(V, Type); 549 write32le(Loc, V); 550 break; 551 } 552 case R_386_TLS_IE: 553 case R_386_TLS_LDO_32: 554 write32le(Loc, Val); 555 break; 556 case R_386_TLS_LE: 557 write32le(Loc, Val - Out<ELF32LE>::TlsPhdr->p_memsz); 558 break; 559 case R_386_TLS_LE_32: 560 write32le(Loc, Out<ELF32LE>::TlsPhdr->p_memsz - Val); 561 break; 562 default: 563 fatal("unrecognized reloc " + Twine(Type)); 564 } 565 } 566 567 bool X86TargetInfo::needsDynRelative(uint32_t Type) const { 568 return Config->Shared && Type == R_386_TLS_IE; 569 } 570 571 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 572 uint64_t Val) const { 573 // GD can be optimized to LE: 574 // leal x@tlsgd(, %ebx, 1), 575 // call __tls_get_addr@plt 576 // Can be converted to: 577 // movl %gs:0,%eax 578 // addl $x@ntpoff,%eax 579 // But gold emits subl $foo@tpoff,%eax instead of addl. 580 // These instructions are completely equal in behavior. 581 // This method generates subl to be consistent with gold. 582 const uint8_t Inst[] = { 583 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 584 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax 585 }; 586 memcpy(Loc - 3, Inst, sizeof(Inst)); 587 relocateOne(Loc + 5, R_386_32, Out<ELF32LE>::TlsPhdr->p_memsz - Val); 588 } 589 590 // "Ulrich Drepper, ELF Handling For Thread-Local Storage" (5.1 591 // IA-32 Linker Optimizations, http://www.akkadia.org/drepper/tls.pdf) shows 592 // how GD can be optimized to IE: 593 // leal x@tlsgd(, %ebx, 1), 594 // call __tls_get_addr@plt 595 // Is converted to: 596 // movl %gs:0, %eax 597 // addl x@gotntpoff(%ebx), %eax 598 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 599 uint64_t Val) const { 600 const uint8_t Inst[] = { 601 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 602 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax 603 }; 604 memcpy(Loc - 3, Inst, sizeof(Inst)); 605 relocateOne(Loc + 5, R_386_32, Val - Out<ELF32LE>::Got->getVA() - 606 Out<ELF32LE>::Got->getNumEntries() * 4); 607 } 608 609 // In some conditions, relocations can be optimized to avoid using GOT. 610 // This function does that for Initial Exec to Local Exec case. 611 // Read "ELF Handling For Thread-Local Storage, 5.1 612 // IA-32 Linker Optimizations" (http://www.akkadia.org/drepper/tls.pdf) 613 // by Ulrich Drepper for details. 614 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 615 uint64_t Val) const { 616 // Ulrich's document section 6.2 says that @gotntpoff can 617 // be used with MOVL or ADDL instructions. 618 // @indntpoff is similar to @gotntpoff, but for use in 619 // position dependent code. 620 uint8_t *Inst = Loc - 2; 621 uint8_t *Op = Loc - 1; 622 uint8_t Reg = (Loc[-1] >> 3) & 7; 623 bool IsMov = *Inst == 0x8b; 624 if (Type == R_386_TLS_IE) { 625 // For R_386_TLS_IE relocation we perform the next transformations: 626 // MOVL foo@INDNTPOFF,%EAX is transformed to MOVL $foo,%EAX 627 // MOVL foo@INDNTPOFF,%REG is transformed to MOVL $foo,%REG 628 // ADDL foo@INDNTPOFF,%REG is transformed to ADDL $foo,%REG 629 // First one is special because when EAX is used the sequence is 5 bytes 630 // long, otherwise it is 6 bytes. 631 if (*Op == 0xa1) { 632 *Op = 0xb8; 633 } else { 634 *Inst = IsMov ? 0xc7 : 0x81; 635 *Op = 0xc0 | ((*Op >> 3) & 7); 636 } 637 } else { 638 // R_386_TLS_GOTIE relocation can be optimized to 639 // R_386_TLS_LE so that it does not use GOT. 640 // "MOVL foo@GOTTPOFF(%RIP), %REG" is transformed to "MOVL $foo, %REG". 641 // "ADDL foo@GOTNTPOFF(%RIP), %REG" is transformed to "LEAL foo(%REG), %REG" 642 // Note: gold converts to ADDL instead of LEAL. 643 *Inst = IsMov ? 0xc7 : 0x8d; 644 if (IsMov) 645 *Op = 0xc0 | ((*Op >> 3) & 7); 646 else 647 *Op = 0x80 | Reg | (Reg << 3); 648 } 649 relocateOne(Loc, R_386_TLS_LE, Val); 650 } 651 652 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 653 uint64_t Val) const { 654 if (Type == R_386_TLS_LDO_32) { 655 relocateOne(Loc, R_386_TLS_LE, Val); 656 return; 657 } 658 659 // LD can be optimized to LE: 660 // leal foo(%reg),%eax 661 // call ___tls_get_addr 662 // Is converted to: 663 // movl %gs:0,%eax 664 // nop 665 // leal 0(%esi,1),%esi 666 const uint8_t Inst[] = { 667 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax 668 0x90, // nop 669 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi 670 }; 671 memcpy(Loc - 2, Inst, sizeof(Inst)); 672 } 673 674 X86_64TargetInfo::X86_64TargetInfo() { 675 CopyRel = R_X86_64_COPY; 676 GotRel = R_X86_64_GLOB_DAT; 677 PltRel = R_X86_64_JUMP_SLOT; 678 RelativeRel = R_X86_64_RELATIVE; 679 IRelativeRel = R_X86_64_IRELATIVE; 680 TlsGotRel = R_X86_64_TPOFF64; 681 TlsModuleIndexRel = R_X86_64_DTPMOD64; 682 TlsOffsetRel = R_X86_64_DTPOFF64; 683 UseLazyBinding = true; 684 PltEntrySize = 16; 685 PltZeroSize = 16; 686 TlsGdToLeSkip = 2; 687 } 688 689 RelExpr X86_64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 690 switch (Type) { 691 default: 692 return R_ABS; 693 case R_X86_64_SIZE32: 694 case R_X86_64_SIZE64: 695 return R_SIZE; 696 case R_X86_64_GOTPCREL: 697 case R_X86_64_PLT32: 698 case R_X86_64_PC32: 699 case R_X86_64_TLSLD: 700 case R_X86_64_GOTTPOFF: 701 case R_X86_64_TLSGD: 702 return R_PC; 703 } 704 } 705 706 void X86_64TargetInfo::writeGotPltHeader(uint8_t *Buf) const { 707 write64le(Buf, Out<ELF64LE>::Dynamic->getVA()); 708 } 709 710 void X86_64TargetInfo::writeGotPlt(uint8_t *Buf, uint64_t Plt) const { 711 // See comments in X86TargetInfo::writeGotPlt. 712 write32le(Buf, Plt + 6); 713 } 714 715 void X86_64TargetInfo::writePltZero(uint8_t *Buf) const { 716 const uint8_t PltData[] = { 717 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOT+8(%rip) 718 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOT+16(%rip) 719 0x0f, 0x1f, 0x40, 0x00 // nopl 0x0(rax) 720 }; 721 memcpy(Buf, PltData, sizeof(PltData)); 722 uint64_t Got = Out<ELF64LE>::GotPlt->getVA(); 723 uint64_t Plt = Out<ELF64LE>::Plt->getVA(); 724 write32le(Buf + 2, Got - Plt + 2); // GOT+8 725 write32le(Buf + 8, Got - Plt + 4); // GOT+16 726 } 727 728 void X86_64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 729 uint64_t PltEntryAddr, int32_t Index, 730 unsigned RelOff) const { 731 const uint8_t Inst[] = { 732 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip) 733 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index> 734 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0] 735 }; 736 memcpy(Buf, Inst, sizeof(Inst)); 737 738 write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6); 739 write32le(Buf + 7, Index); 740 write32le(Buf + 12, -Index * PltEntrySize - PltZeroSize - 16); 741 } 742 743 bool X86_64TargetInfo::needsCopyRelImpl(uint32_t Type) const { 744 return Type == R_X86_64_32S || Type == R_X86_64_32 || Type == R_X86_64_PC32 || 745 Type == R_X86_64_64; 746 } 747 748 bool X86_64TargetInfo::refersToGotEntry(uint32_t Type) const { 749 return Type == R_X86_64_GOTPCREL || Type == R_X86_64_GOTPCRELX || 750 Type == R_X86_64_REX_GOTPCRELX; 751 } 752 753 bool X86_64TargetInfo::needsGot(uint32_t Type, const SymbolBody &S) const { 754 if (Type == R_X86_64_TLSGD) 755 return Target->canRelaxTls(Type, &S) && S.isPreemptible(); 756 if (Type == R_X86_64_GOTTPOFF) 757 return !canRelaxTls(Type, &S); 758 return refersToGotEntry(Type) || needsPlt(Type, S); 759 } 760 761 uint32_t X86_64TargetInfo::getDynRel(uint32_t Type) const { 762 if (Type == R_X86_64_PC32 || Type == R_X86_64_32) 763 if (Config->Shared) 764 error(getELFRelocationTypeName(EM_X86_64, Type) + 765 " cannot be a dynamic relocation"); 766 return Type; 767 } 768 769 uint32_t X86_64TargetInfo::getTlsGotRel(uint32_t Type) const { 770 // No other types of TLS relocations requiring GOT should 771 // reach here. 772 assert(Type == R_X86_64_GOTTPOFF); 773 return R_X86_64_PC32; 774 } 775 776 bool X86_64TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 777 return Type == R_X86_64_GOTTPOFF; 778 } 779 780 bool X86_64TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 781 return Type == R_X86_64_TLSGD; 782 } 783 784 bool X86_64TargetInfo::pointsToLocalDynamicGotEntry(uint32_t Type) const { 785 return Type == R_X86_64_TLSLD; 786 } 787 788 bool X86_64TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 789 return Type == R_X86_64_DTPOFF32 || Type == R_X86_64_DTPOFF64 || 790 Type == R_X86_64_TLSLD; 791 } 792 793 bool X86_64TargetInfo::needsPltImpl(uint32_t Type) const { 794 return Type == R_X86_64_PLT32; 795 } 796 797 bool X86_64TargetInfo::isRelRelative(uint32_t Type) const { 798 switch (Type) { 799 default: 800 return false; 801 case R_X86_64_DTPOFF32: 802 case R_X86_64_DTPOFF64: 803 case R_X86_64_GOTTPOFF: 804 case R_X86_64_PC8: 805 case R_X86_64_PC16: 806 case R_X86_64_PC32: 807 case R_X86_64_PC64: 808 case R_X86_64_PLT32: 809 case R_X86_64_TPOFF32: 810 return true; 811 } 812 } 813 814 // "Ulrich Drepper, ELF Handling For Thread-Local Storage" (5.5 815 // x86-x64 linker optimizations, http://www.akkadia.org/drepper/tls.pdf) shows 816 // how GD can be optimized to LE: 817 // .byte 0x66 818 // leaq x@tlsgd(%rip), %rdi 819 // .word 0x6666 820 // rex64 821 // call __tls_get_addr@plt 822 // Is converted to: 823 // mov %fs:0x0,%rax 824 // lea x@tpoff,%rax 825 void X86_64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 826 uint64_t Val) const { 827 const uint8_t Inst[] = { 828 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 829 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax 830 }; 831 memcpy(Loc - 4, Inst, sizeof(Inst)); 832 relocateOne(Loc + 8, R_X86_64_TPOFF32, Val + 4); 833 } 834 835 // "Ulrich Drepper, ELF Handling For Thread-Local Storage" (5.5 836 // x86-x64 linker optimizations, http://www.akkadia.org/drepper/tls.pdf) shows 837 // how GD can be optimized to IE: 838 // .byte 0x66 839 // leaq x@tlsgd(%rip), %rdi 840 // .word 0x6666 841 // rex64 842 // call __tls_get_addr@plt 843 // Is converted to: 844 // mov %fs:0x0,%rax 845 // addq x@tpoff,%rax 846 void X86_64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 847 uint64_t Val) const { 848 const uint8_t Inst[] = { 849 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 850 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax 851 }; 852 memcpy(Loc - 4, Inst, sizeof(Inst)); 853 relocateOne(Loc + 8, R_X86_64_PC32, Val - 8); 854 } 855 856 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to 857 // R_X86_64_TPOFF32 so that it does not use GOT. 858 // This function does that. Read "ELF Handling For Thread-Local Storage, 859 // 5.5 x86-x64 linker optimizations" (http://www.akkadia.org/drepper/tls.pdf) 860 // by Ulrich Drepper for details. 861 void X86_64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 862 uint64_t Val) const { 863 // Ulrich's document section 6.5 says that @gottpoff(%rip) must be 864 // used in MOVQ or ADDQ instructions only. 865 // "MOVQ foo@GOTTPOFF(%RIP), %REG" is transformed to "MOVQ $foo, %REG". 866 // "ADDQ foo@GOTTPOFF(%RIP), %REG" is transformed to "LEAQ foo(%REG), %REG" 867 // (if the register is not RSP/R12) or "ADDQ $foo, %RSP". 868 // Opcodes info can be found at http://ref.x86asm.net/coder64.html#x48. 869 uint8_t *Prefix = Loc - 3; 870 uint8_t *Inst = Loc - 2; 871 uint8_t *RegSlot = Loc - 1; 872 uint8_t Reg = Loc[-1] >> 3; 873 bool IsMov = *Inst == 0x8b; 874 bool RspAdd = !IsMov && Reg == 4; 875 // r12 and rsp registers requires special handling. 876 // Problem is that for other registers, for example leaq 0xXXXXXXXX(%r11),%r11 877 // result out is 7 bytes: 4d 8d 9b XX XX XX XX, 878 // but leaq 0xXXXXXXXX(%r12),%r12 is 8 bytes: 4d 8d a4 24 XX XX XX XX. 879 // The same true for rsp. So we convert to addq for them, saving 1 byte that 880 // we dont have. 881 if (RspAdd) 882 *Inst = 0x81; 883 else 884 *Inst = IsMov ? 0xc7 : 0x8d; 885 if (*Prefix == 0x4c) 886 *Prefix = (IsMov || RspAdd) ? 0x49 : 0x4d; 887 *RegSlot = (IsMov || RspAdd) ? (0xc0 | Reg) : (0x80 | Reg | (Reg << 3)); 888 relocateOne(Loc, R_X86_64_TPOFF32, Val + 4); 889 } 890 891 // "Ulrich Drepper, ELF Handling For Thread-Local Storage" (5.5 892 // x86-x64 linker optimizations, http://www.akkadia.org/drepper/tls.pdf) shows 893 // how LD can be optimized to LE: 894 // leaq bar@tlsld(%rip), %rdi 895 // callq __tls_get_addr@PLT 896 // leaq bar@dtpoff(%rax), %rcx 897 // Is converted to: 898 // .word 0x6666 899 // .byte 0x66 900 // mov %fs:0,%rax 901 // leaq bar@tpoff(%rax), %rcx 902 void X86_64TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 903 uint64_t Val) const { 904 if (Type == R_X86_64_DTPOFF64) { 905 write64le(Loc, Val - Out<ELF64LE>::TlsPhdr->p_memsz); 906 return; 907 } 908 if (Type == R_X86_64_DTPOFF32) { 909 relocateOne(Loc, R_X86_64_TPOFF32, Val); 910 return; 911 } 912 913 const uint8_t Inst[] = { 914 0x66, 0x66, //.word 0x6666 915 0x66, //.byte 0x66 916 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax 917 }; 918 memcpy(Loc - 3, Inst, sizeof(Inst)); 919 } 920 921 void X86_64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 922 uint64_t Val) const { 923 switch (Type) { 924 case R_X86_64_32: 925 checkUInt<32>(Val, Type); 926 write32le(Loc, Val); 927 break; 928 case R_X86_64_32S: 929 checkInt<32>(Val, Type); 930 write32le(Loc, Val); 931 break; 932 case R_X86_64_64: 933 case R_X86_64_DTPOFF64: 934 write64le(Loc, Val); 935 break; 936 case R_X86_64_DTPOFF32: 937 write32le(Loc, Val); 938 break; 939 case R_X86_64_GOTPCREL: 940 case R_X86_64_GOTPCRELX: 941 case R_X86_64_REX_GOTPCRELX: 942 case R_X86_64_PC32: 943 case R_X86_64_PLT32: 944 case R_X86_64_TLSGD: 945 case R_X86_64_TLSLD: 946 write32le(Loc, Val); 947 break; 948 case R_X86_64_SIZE32: 949 write32le(Loc, Val); 950 break; 951 case R_X86_64_SIZE64: 952 write64le(Loc, Val); 953 break; 954 case R_X86_64_TPOFF32: { 955 Val -= Out<ELF64LE>::TlsPhdr->p_memsz; 956 checkInt<32>(Val, Type); 957 write32le(Loc, Val); 958 break; 959 } 960 default: 961 fatal("unrecognized reloc " + Twine(Type)); 962 } 963 } 964 965 // Relocation masks following the #lo(value), #hi(value), #ha(value), 966 // #higher(value), #highera(value), #highest(value), and #highesta(value) 967 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 968 // document. 969 static uint16_t applyPPCLo(uint64_t V) { return V; } 970 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; } 971 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; } 972 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; } 973 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; } 974 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; } 975 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; } 976 977 PPCTargetInfo::PPCTargetInfo() {} 978 bool PPCTargetInfo::isRelRelative(uint32_t Type) const { return false; } 979 980 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 981 uint64_t Val) const { 982 switch (Type) { 983 case R_PPC_ADDR16_HA: 984 write16be(Loc, applyPPCHa(Val)); 985 break; 986 case R_PPC_ADDR16_LO: 987 write16be(Loc, applyPPCLo(Val)); 988 break; 989 default: 990 fatal("unrecognized reloc " + Twine(Type)); 991 } 992 } 993 994 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 995 return R_ABS; 996 } 997 998 PPC64TargetInfo::PPC64TargetInfo() { 999 GotRel = R_PPC64_GLOB_DAT; 1000 RelativeRel = R_PPC64_RELATIVE; 1001 PltEntrySize = 32; 1002 1003 // We need 64K pages (at least under glibc/Linux, the loader won't 1004 // set different permissions on a finer granularity than that). 1005 PageSize = 65536; 1006 1007 // The PPC64 ELF ABI v1 spec, says: 1008 // 1009 // It is normally desirable to put segments with different characteristics 1010 // in separate 256 Mbyte portions of the address space, to give the 1011 // operating system full paging flexibility in the 64-bit address space. 1012 // 1013 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 1014 // use 0x10000000 as the starting address. 1015 VAStart = 0x10000000; 1016 } 1017 1018 uint64_t getPPC64TocBase() { 1019 // The TOC consists of sections .got, .toc, .tocbss, .plt in that 1020 // order. The TOC starts where the first of these sections starts. 1021 1022 // FIXME: This obviously does not do the right thing when there is no .got 1023 // section, but there is a .toc or .tocbss section. 1024 uint64_t TocVA = Out<ELF64BE>::Got->getVA(); 1025 if (!TocVA) 1026 TocVA = Out<ELF64BE>::Plt->getVA(); 1027 1028 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 1029 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 1030 // code (crt1.o) assumes that you can get from the TOC base to the 1031 // start of the .toc section with only a single (signed) 16-bit relocation. 1032 return TocVA + 0x8000; 1033 } 1034 1035 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1036 switch (Type) { 1037 default: 1038 return R_ABS; 1039 case R_PPC64_REL24: 1040 return R_PPC_OPD; 1041 } 1042 } 1043 1044 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1045 uint64_t PltEntryAddr, int32_t Index, 1046 unsigned RelOff) const { 1047 uint64_t Off = GotEntryAddr - getPPC64TocBase(); 1048 1049 // FIXME: What we should do, in theory, is get the offset of the function 1050 // descriptor in the .opd section, and use that as the offset from %r2 (the 1051 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will 1052 // be a pointer to the function descriptor in the .opd section. Using 1053 // this scheme is simpler, but requires an extra indirection per PLT dispatch. 1054 1055 write32be(Buf, 0xf8410028); // std %r2, 40(%r1) 1056 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha 1057 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11) 1058 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12) 1059 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11 1060 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12) 1061 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12) 1062 write32be(Buf + 28, 0x4e800420); // bctr 1063 } 1064 1065 bool PPC64TargetInfo::needsGot(uint32_t Type, const SymbolBody &S) const { 1066 if (needsPlt(Type, S)) 1067 return true; 1068 1069 switch (Type) { 1070 default: return false; 1071 case R_PPC64_GOT16: 1072 case R_PPC64_GOT16_DS: 1073 case R_PPC64_GOT16_HA: 1074 case R_PPC64_GOT16_HI: 1075 case R_PPC64_GOT16_LO: 1076 case R_PPC64_GOT16_LO_DS: 1077 return true; 1078 } 1079 } 1080 1081 bool PPC64TargetInfo::needsPltImpl(uint32_t Type) const { 1082 // These are function calls that need to be redirected through a PLT stub. 1083 return Type == R_PPC64_REL24; 1084 } 1085 1086 bool PPC64TargetInfo::isRelRelative(uint32_t Type) const { 1087 switch (Type) { 1088 default: 1089 return true; 1090 case R_PPC64_ADDR64: 1091 case R_PPC64_TOC: 1092 return false; 1093 } 1094 } 1095 1096 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1097 uint64_t Val) const { 1098 uint64_t TB = getPPC64TocBase(); 1099 1100 // For a TOC-relative relocation, adjust the addend and proceed in terms of 1101 // the corresponding ADDR16 relocation type. 1102 switch (Type) { 1103 case R_PPC64_TOC16: Type = R_PPC64_ADDR16; Val -= TB; break; 1104 case R_PPC64_TOC16_DS: Type = R_PPC64_ADDR16_DS; Val -= TB; break; 1105 case R_PPC64_TOC16_HA: Type = R_PPC64_ADDR16_HA; Val -= TB; break; 1106 case R_PPC64_TOC16_HI: Type = R_PPC64_ADDR16_HI; Val -= TB; break; 1107 case R_PPC64_TOC16_LO: Type = R_PPC64_ADDR16_LO; Val -= TB; break; 1108 case R_PPC64_TOC16_LO_DS: Type = R_PPC64_ADDR16_LO_DS; Val -= TB; break; 1109 default: break; 1110 } 1111 1112 switch (Type) { 1113 case R_PPC64_ADDR14: { 1114 checkAlignment<4>(Val, Type); 1115 // Preserve the AA/LK bits in the branch instruction 1116 uint8_t AALK = Loc[3]; 1117 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 1118 break; 1119 } 1120 case R_PPC64_ADDR16: 1121 checkInt<16>(Val, Type); 1122 write16be(Loc, Val); 1123 break; 1124 case R_PPC64_ADDR16_DS: 1125 checkInt<16>(Val, Type); 1126 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3)); 1127 break; 1128 case R_PPC64_ADDR16_HA: 1129 write16be(Loc, applyPPCHa(Val)); 1130 break; 1131 case R_PPC64_ADDR16_HI: 1132 write16be(Loc, applyPPCHi(Val)); 1133 break; 1134 case R_PPC64_ADDR16_HIGHER: 1135 write16be(Loc, applyPPCHigher(Val)); 1136 break; 1137 case R_PPC64_ADDR16_HIGHERA: 1138 write16be(Loc, applyPPCHighera(Val)); 1139 break; 1140 case R_PPC64_ADDR16_HIGHEST: 1141 write16be(Loc, applyPPCHighest(Val)); 1142 break; 1143 case R_PPC64_ADDR16_HIGHESTA: 1144 write16be(Loc, applyPPCHighesta(Val)); 1145 break; 1146 case R_PPC64_ADDR16_LO: 1147 write16be(Loc, applyPPCLo(Val)); 1148 break; 1149 case R_PPC64_ADDR16_LO_DS: 1150 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3)); 1151 break; 1152 case R_PPC64_ADDR32: 1153 checkInt<32>(Val, Type); 1154 write32be(Loc, Val); 1155 break; 1156 case R_PPC64_ADDR64: 1157 write64be(Loc, Val); 1158 break; 1159 case R_PPC64_REL16_HA: 1160 write16be(Loc, applyPPCHa(Val)); 1161 break; 1162 case R_PPC64_REL16_HI: 1163 write16be(Loc, applyPPCHi(Val)); 1164 break; 1165 case R_PPC64_REL16_LO: 1166 write16be(Loc, applyPPCLo(Val)); 1167 break; 1168 case R_PPC64_REL24: { 1169 uint32_t Mask = 0x03FFFFFC; 1170 checkInt<24>(Val, Type); 1171 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask)); 1172 break; 1173 } 1174 case R_PPC64_REL32: 1175 checkInt<32>(Val, Type); 1176 write32be(Loc, Val); 1177 break; 1178 case R_PPC64_REL64: 1179 write64be(Loc, Val); 1180 break; 1181 case R_PPC64_TOC: 1182 write64be(Loc, Val); 1183 break; 1184 default: 1185 fatal("unrecognized reloc " + Twine(Type)); 1186 } 1187 } 1188 1189 AArch64TargetInfo::AArch64TargetInfo() { 1190 CopyRel = R_AARCH64_COPY; 1191 RelativeRel = R_AARCH64_RELATIVE; 1192 IRelativeRel = R_AARCH64_IRELATIVE; 1193 GotRel = R_AARCH64_GLOB_DAT; 1194 PltRel = R_AARCH64_JUMP_SLOT; 1195 TlsGotRel = R_AARCH64_TLS_TPREL64; 1196 TlsModuleIndexRel = R_AARCH64_TLS_DTPMOD64; 1197 TlsOffsetRel = R_AARCH64_TLS_DTPREL64; 1198 UseLazyBinding = true; 1199 PltEntrySize = 16; 1200 PltZeroSize = 32; 1201 } 1202 1203 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type, 1204 const SymbolBody &S) const { 1205 switch (Type) { 1206 default: 1207 return R_ABS; 1208 case R_AARCH64_JUMP26: 1209 case R_AARCH64_CALL26: 1210 case R_AARCH64_PREL16: 1211 case R_AARCH64_PREL32: 1212 case R_AARCH64_PREL64: 1213 case R_AARCH64_CONDBR19: 1214 case R_AARCH64_ADR_PREL_LO21: 1215 case R_AARCH64_TSTBR14: 1216 return R_PC; 1217 case R_AARCH64_ADR_GOT_PAGE: 1218 case R_AARCH64_ADR_PREL_PG_HI21: 1219 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1220 return R_PAGE_PC; 1221 } 1222 } 1223 1224 bool AArch64TargetInfo::isRelRelative(uint32_t Type) const { 1225 switch (Type) { 1226 default: 1227 return false; 1228 case R_AARCH64_ADD_ABS_LO12_NC: 1229 case R_AARCH64_ADR_GOT_PAGE: 1230 case R_AARCH64_ADR_PREL_LO21: 1231 case R_AARCH64_ADR_PREL_PG_HI21: 1232 case R_AARCH64_CALL26: 1233 case R_AARCH64_CONDBR19: 1234 case R_AARCH64_JUMP26: 1235 case R_AARCH64_LDST8_ABS_LO12_NC: 1236 case R_AARCH64_LDST16_ABS_LO12_NC: 1237 case R_AARCH64_LDST32_ABS_LO12_NC: 1238 case R_AARCH64_LDST64_ABS_LO12_NC: 1239 case R_AARCH64_LDST128_ABS_LO12_NC: 1240 case R_AARCH64_PREL32: 1241 case R_AARCH64_PREL64: 1242 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1243 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1244 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1245 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1246 case R_AARCH64_TSTBR14: 1247 return true; 1248 } 1249 } 1250 1251 bool AArch64TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 1252 return Type == R_AARCH64_TLSDESC_ADR_PAGE21 || 1253 Type == R_AARCH64_TLSDESC_LD64_LO12_NC || 1254 Type == R_AARCH64_TLSDESC_ADD_LO12_NC || 1255 Type == R_AARCH64_TLSDESC_CALL; 1256 } 1257 1258 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1259 return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 || 1260 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; 1261 } 1262 1263 uint32_t AArch64TargetInfo::getDynRel(uint32_t Type) const { 1264 if (Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64) 1265 return Type; 1266 StringRef S = getELFRelocationTypeName(EM_AARCH64, Type); 1267 error("relocation " + S + " cannot be used when making a shared object; " 1268 "recompile with -fPIC."); 1269 // Keep it going with a dummy value so that we can find more reloc errors. 1270 return R_AARCH64_ABS32; 1271 } 1272 1273 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, uint64_t Plt) const { 1274 write64le(Buf, Out<ELF64LE>::Plt->getVA()); 1275 } 1276 1277 static uint64_t getAArch64Page(uint64_t Expr) { 1278 return Expr & (~static_cast<uint64_t>(0xFFF)); 1279 } 1280 1281 void AArch64TargetInfo::writePltZero(uint8_t *Buf) const { 1282 const uint8_t PltData[] = { 1283 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 1284 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 1285 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 1286 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 1287 0x20, 0x02, 0x1f, 0xd6, // br x17 1288 0x1f, 0x20, 0x03, 0xd5, // nop 1289 0x1f, 0x20, 0x03, 0xd5, // nop 1290 0x1f, 0x20, 0x03, 0xd5 // nop 1291 }; 1292 memcpy(Buf, PltData, sizeof(PltData)); 1293 1294 uint64_t Got = Out<ELF64LE>::GotPlt->getVA(); 1295 uint64_t Plt = Out<ELF64LE>::Plt->getVA(); 1296 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 1297 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4)); 1298 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16); 1299 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16); 1300 } 1301 1302 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1303 uint64_t PltEntryAddr, int32_t Index, 1304 unsigned RelOff) const { 1305 const uint8_t Inst[] = { 1306 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 1307 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 1308 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n])) 1309 0x20, 0x02, 0x1f, 0xd6 // br x17 1310 }; 1311 memcpy(Buf, Inst, sizeof(Inst)); 1312 1313 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21, 1314 getAArch64Page(GotEntryAddr) - getAArch64Page(PltEntryAddr)); 1315 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotEntryAddr); 1316 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotEntryAddr); 1317 } 1318 1319 uint32_t AArch64TargetInfo::getTlsGotRel(uint32_t Type) const { 1320 assert(Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 || 1321 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC); 1322 return Type; 1323 } 1324 1325 bool AArch64TargetInfo::needsCopyRelImpl(uint32_t Type) const { 1326 switch (Type) { 1327 default: 1328 return false; 1329 case R_AARCH64_ABS16: 1330 case R_AARCH64_ABS32: 1331 case R_AARCH64_ABS64: 1332 case R_AARCH64_ADD_ABS_LO12_NC: 1333 case R_AARCH64_ADR_PREL_LO21: 1334 case R_AARCH64_ADR_PREL_PG_HI21: 1335 case R_AARCH64_LDST8_ABS_LO12_NC: 1336 case R_AARCH64_LDST16_ABS_LO12_NC: 1337 case R_AARCH64_LDST32_ABS_LO12_NC: 1338 case R_AARCH64_LDST64_ABS_LO12_NC: 1339 case R_AARCH64_LDST128_ABS_LO12_NC: 1340 return true; 1341 } 1342 } 1343 1344 bool AArch64TargetInfo::needsGot(uint32_t Type, const SymbolBody &S) const { 1345 switch (Type) { 1346 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1347 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1348 return !canRelaxTls(Type, &S); 1349 case R_AARCH64_ADR_GOT_PAGE: 1350 case R_AARCH64_LD64_GOT_LO12_NC: 1351 return true; 1352 default: 1353 return needsPlt(Type, S); 1354 } 1355 } 1356 1357 bool AArch64TargetInfo::refersToGotEntry(uint32_t Type) const { 1358 return Type == R_AARCH64_ADR_GOT_PAGE || Type == R_AARCH64_LD64_GOT_LO12_NC; 1359 } 1360 1361 bool AArch64TargetInfo::needsPltImpl(uint32_t Type) const { 1362 switch (Type) { 1363 default: 1364 return false; 1365 case R_AARCH64_CALL26: 1366 case R_AARCH64_CONDBR19: 1367 case R_AARCH64_JUMP26: 1368 case R_AARCH64_TSTBR14: 1369 return true; 1370 } 1371 } 1372 1373 static void updateAArch64Addr(uint8_t *L, uint64_t Imm) { 1374 uint32_t ImmLo = (Imm & 0x3) << 29; 1375 uint32_t ImmHi = ((Imm & 0x1FFFFC) >> 2) << 5; 1376 uint64_t Mask = (0x3 << 29) | (0x7FFFF << 5); 1377 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi); 1378 } 1379 1380 static inline void updateAArch64Add(uint8_t *L, uint64_t Imm) { 1381 or32le(L, (Imm & 0xFFF) << 10); 1382 } 1383 1384 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1385 uint64_t Val) const { 1386 switch (Type) { 1387 case R_AARCH64_ABS16: 1388 checkIntUInt<16>(Val, Type); 1389 write16le(Loc, Val); 1390 break; 1391 case R_AARCH64_ABS32: 1392 checkIntUInt<32>(Val, Type); 1393 write32le(Loc, Val); 1394 break; 1395 case R_AARCH64_ABS64: 1396 write64le(Loc, Val); 1397 break; 1398 case R_AARCH64_ADD_ABS_LO12_NC: 1399 // This relocation stores 12 bits and there's no instruction 1400 // to do it. Instead, we do a 32 bits store of the value 1401 // of r_addend bitwise-or'ed Loc. This assumes that the addend 1402 // bits in Loc are zero. 1403 or32le(Loc, (Val & 0xFFF) << 10); 1404 break; 1405 case R_AARCH64_ADR_GOT_PAGE: { 1406 uint64_t X = Val; 1407 checkInt<33>(X, Type); 1408 updateAArch64Addr(Loc, (X >> 12) & 0x1FFFFF); // X[32:12] 1409 break; 1410 } 1411 case R_AARCH64_ADR_PREL_LO21: { 1412 uint64_t X = Val; 1413 checkInt<21>(X, Type); 1414 updateAArch64Addr(Loc, X & 0x1FFFFF); 1415 break; 1416 } 1417 case R_AARCH64_ADR_PREL_PG_HI21: 1418 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: { 1419 uint64_t X = Val; 1420 checkInt<33>(X, Type); 1421 updateAArch64Addr(Loc, (X >> 12) & 0x1FFFFF); // X[32:12] 1422 break; 1423 } 1424 case R_AARCH64_CALL26: 1425 case R_AARCH64_JUMP26: { 1426 uint64_t X = Val; 1427 checkInt<28>(X, Type); 1428 or32le(Loc, (X & 0x0FFFFFFC) >> 2); 1429 break; 1430 } 1431 case R_AARCH64_CONDBR19: { 1432 uint64_t X = Val; 1433 checkInt<21>(X, Type); 1434 or32le(Loc, (X & 0x1FFFFC) << 3); 1435 break; 1436 } 1437 case R_AARCH64_LD64_GOT_LO12_NC: 1438 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1439 checkAlignment<8>(Val, Type); 1440 or32le(Loc, (Val & 0xFF8) << 7); 1441 break; 1442 case R_AARCH64_LDST128_ABS_LO12_NC: 1443 or32le(Loc, (Val & 0x0FF8) << 6); 1444 break; 1445 case R_AARCH64_LDST16_ABS_LO12_NC: 1446 or32le(Loc, (Val & 0x0FFC) << 9); 1447 break; 1448 case R_AARCH64_LDST8_ABS_LO12_NC: 1449 or32le(Loc, (Val & 0xFFF) << 10); 1450 break; 1451 case R_AARCH64_LDST32_ABS_LO12_NC: 1452 or32le(Loc, (Val & 0xFFC) << 8); 1453 break; 1454 case R_AARCH64_LDST64_ABS_LO12_NC: 1455 or32le(Loc, (Val & 0xFF8) << 7); 1456 break; 1457 case R_AARCH64_PREL16: 1458 checkIntUInt<16>(Val, Type); 1459 write16le(Loc, Val); 1460 break; 1461 case R_AARCH64_PREL32: 1462 checkIntUInt<32>(Val, Type); 1463 write32le(Loc, Val); 1464 break; 1465 case R_AARCH64_PREL64: 1466 write64le(Loc, Val); 1467 break; 1468 case R_AARCH64_TSTBR14: { 1469 uint64_t X = Val; 1470 checkInt<16>(X, Type); 1471 or32le(Loc, (X & 0xFFFC) << 3); 1472 break; 1473 } 1474 case R_AARCH64_TLSLE_ADD_TPREL_HI12: { 1475 uint64_t V = llvm::alignTo(TcbSize, Out<ELF64LE>::TlsPhdr->p_align) + Val; 1476 checkInt<24>(V, Type); 1477 updateAArch64Add(Loc, (V & 0xFFF000) >> 12); 1478 break; 1479 } 1480 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: { 1481 uint64_t V = llvm::alignTo(TcbSize, Out<ELF64LE>::TlsPhdr->p_align) + Val; 1482 updateAArch64Add(Loc, V & 0xFFF); 1483 break; 1484 } 1485 default: 1486 fatal("unrecognized reloc " + Twine(Type)); 1487 } 1488 } 1489 1490 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 1491 uint64_t Val) const { 1492 // TLSDESC Global-Dynamic relocation are in the form: 1493 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1494 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1495 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1496 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1497 // And it can optimized to: 1498 // movz x0, #0x0, lsl #16 1499 // movk x0, #0x10 1500 // nop 1501 // nop 1502 uint64_t TPOff = llvm::alignTo(TcbSize, Out<ELF64LE>::TlsPhdr->p_align); 1503 uint64_t X = Val + TPOff; 1504 checkUInt<32>(X, Type); 1505 1506 uint32_t NewInst; 1507 switch (Type) { 1508 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1509 case R_AARCH64_TLSDESC_CALL: 1510 // nop 1511 NewInst = 0xd503201f; 1512 break; 1513 case R_AARCH64_TLSDESC_ADR_PAGE21: 1514 // movz 1515 NewInst = 0xd2a00000 | (((X >> 16) & 0xffff) << 5); 1516 break; 1517 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1518 // movk 1519 NewInst = 0xf2800000 | ((X & 0xffff) << 5); 1520 break; 1521 default: 1522 llvm_unreachable("unsupported Relocation for TLS GD to LE relax"); 1523 } 1524 write32le(Loc, NewInst); 1525 } 1526 1527 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 1528 uint64_t Val) const { 1529 uint64_t TPOff = llvm::alignTo(TcbSize, Out<ELF64LE>::TlsPhdr->p_align); 1530 uint64_t X = Val + TPOff; 1531 checkUInt<32>(X, Type); 1532 1533 uint32_t Inst = read32le(Loc); 1534 uint32_t NewInst; 1535 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) { 1536 // Generate movz. 1537 unsigned RegNo = (Inst & 0x1f); 1538 NewInst = (0xd2a00000 | RegNo) | (((X >> 16) & 0xffff) << 5); 1539 } else if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) { 1540 // Generate movk 1541 unsigned RegNo = (Inst & 0x1f); 1542 NewInst = (0xf2800000 | RegNo) | ((X & 0xffff) << 5); 1543 } else { 1544 llvm_unreachable("invalid Relocation for TLS IE to LE Relax"); 1545 } 1546 write32le(Loc, NewInst); 1547 } 1548 1549 // Implementing relocations for AMDGPU is low priority since most 1550 // programs don't use relocations now. Thus, this function is not 1551 // actually called (relocateOne is called for each relocation). 1552 // That's why the AMDGPU port works without implementing this function. 1553 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1554 uint64_t Val) const { 1555 llvm_unreachable("not implemented"); 1556 } 1557 1558 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1559 llvm_unreachable("not implemented"); 1560 } 1561 1562 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() { 1563 GotHeaderEntriesNum = 2; 1564 GotPltHeaderEntriesNum = 2; 1565 PageSize = 65536; 1566 PltEntrySize = 16; 1567 PltZeroSize = 32; 1568 ThunkSize = 16; 1569 UseLazyBinding = true; 1570 CopyRel = R_MIPS_COPY; 1571 PltRel = R_MIPS_JUMP_SLOT; 1572 RelativeRel = R_MIPS_REL32; 1573 } 1574 1575 template <class ELFT> 1576 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type, 1577 const SymbolBody &S) const { 1578 switch (Type) { 1579 default: 1580 return R_ABS; 1581 case R_MIPS_HI16: 1582 case R_MIPS_LO16: 1583 // MIPS _gp_disp designates offset between start of function and 'gp' 1584 // pointer into GOT. __gnu_local_gp is equal to the current value of 1585 // the 'gp'. Therefore any relocations against them do not require 1586 // dynamic relocation. 1587 if (&S == ElfSym<ELFT>::MipsGpDisp) 1588 return R_PC; 1589 return R_ABS; 1590 case R_MIPS_PC32: 1591 case R_MIPS_PC16: 1592 case R_MIPS_PC19_S2: 1593 case R_MIPS_PC21_S2: 1594 case R_MIPS_PC26_S2: 1595 case R_MIPS_PCHI16: 1596 case R_MIPS_PCLO16: 1597 return R_PC; 1598 } 1599 } 1600 1601 template <class ELFT> 1602 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const { 1603 if (Type == R_MIPS_32 || Type == R_MIPS_64) 1604 return R_MIPS_REL32; 1605 StringRef S = getELFRelocationTypeName(EM_MIPS, Type); 1606 error("relocation " + S + " cannot be used when making a shared object; " 1607 "recompile with -fPIC."); 1608 // Keep it going with a dummy value so that we can find more reloc errors. 1609 return R_MIPS_32; 1610 } 1611 1612 template <class ELFT> 1613 void MipsTargetInfo<ELFT>::writeGotHeader(uint8_t *Buf) const { 1614 typedef typename ELFT::Off Elf_Off; 1615 typedef typename ELFT::uint uintX_t; 1616 1617 // Set the MSB of the second GOT slot. This is not required by any 1618 // MIPS ABI documentation, though. 1619 // 1620 // There is a comment in glibc saying that "The MSB of got[1] of a 1621 // gnu object is set to identify gnu objects," and in GNU gold it 1622 // says "the second entry will be used by some runtime loaders". 1623 // But how this field is being used is unclear. 1624 // 1625 // We are not really willing to mimic other linkers behaviors 1626 // without understanding why they do that, but because all files 1627 // generated by GNU tools have this special GOT value, and because 1628 // we've been doing this for years, it is probably a safe bet to 1629 // keep doing this for now. We really need to revisit this to see 1630 // if we had to do this. 1631 auto *P = reinterpret_cast<Elf_Off *>(Buf); 1632 P[1] = uintX_t(1) << (ELFT::Is64Bits ? 63 : 31); 1633 } 1634 1635 template <class ELFT> 1636 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, uint64_t Plt) const { 1637 write32<ELFT::TargetEndianness>(Buf, Out<ELFT>::Plt->getVA()); 1638 } 1639 1640 static uint16_t mipsHigh(uint64_t V) { return (V + 0x8000) >> 16; } 1641 1642 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 1643 static int64_t getPcRelocAddend(const uint8_t *Loc) { 1644 uint32_t Instr = read32<E>(Loc); 1645 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 1646 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT); 1647 } 1648 1649 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 1650 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) { 1651 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 1652 uint32_t Instr = read32<E>(Loc); 1653 if (SHIFT > 0) 1654 checkAlignment<(1 << SHIFT)>(V, Type); 1655 checkInt<BSIZE + SHIFT>(V, Type); 1656 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask)); 1657 } 1658 1659 template <endianness E> 1660 static void writeMipsHi16(uint8_t *Loc, uint64_t V) { 1661 uint32_t Instr = read32<E>(Loc); 1662 write32<E>(Loc, (Instr & 0xffff0000) | mipsHigh(V)); 1663 } 1664 1665 template <endianness E> 1666 static void writeMipsLo16(uint8_t *Loc, uint64_t V) { 1667 uint32_t Instr = read32<E>(Loc); 1668 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff)); 1669 } 1670 1671 template <endianness E> static int16_t readSignedLo16(const uint8_t *Loc) { 1672 return SignExtend32<16>(read32<E>(Loc) & 0xffff); 1673 } 1674 1675 template <class ELFT> 1676 void MipsTargetInfo<ELFT>::writePltZero(uint8_t *Buf) const { 1677 const endianness E = ELFT::TargetEndianness; 1678 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 1679 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 1680 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 1681 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 1682 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 1683 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 1684 write32<E>(Buf + 24, 0x0320f809); // jalr $25 1685 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 1686 uint64_t Got = Out<ELFT>::GotPlt->getVA(); 1687 writeMipsHi16<E>(Buf, Got); 1688 writeMipsLo16<E>(Buf + 4, Got); 1689 writeMipsLo16<E>(Buf + 8, Got); 1690 } 1691 1692 template <class ELFT> 1693 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1694 uint64_t PltEntryAddr, int32_t Index, 1695 unsigned RelOff) const { 1696 const endianness E = ELFT::TargetEndianness; 1697 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 1698 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 1699 write32<E>(Buf + 8, 0x03200008); // jr $25 1700 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 1701 writeMipsHi16<E>(Buf, GotEntryAddr); 1702 writeMipsLo16<E>(Buf + 4, GotEntryAddr); 1703 writeMipsLo16<E>(Buf + 12, GotEntryAddr); 1704 } 1705 1706 template <class ELFT> 1707 void MipsTargetInfo<ELFT>::writeThunk(uint8_t *Buf, uint64_t S) const { 1708 // Write MIPS LA25 thunk code to call PIC function from the non-PIC one. 1709 // See MipsTargetInfo::writeThunk for details. 1710 const endianness E = ELFT::TargetEndianness; 1711 write32<E>(Buf, 0x3c190000); // lui $25, %hi(func) 1712 write32<E>(Buf + 4, 0x08000000); // j func 1713 write32<E>(Buf + 8, 0x27390000); // addiu $25, $25, %lo(func) 1714 write32<E>(Buf + 12, 0x00000000); // nop 1715 writeMipsHi16<E>(Buf, S); 1716 write32<E>(Buf + 4, 0x08000000 | (S >> 2)); 1717 writeMipsLo16<E>(Buf + 8, S); 1718 } 1719 1720 template <class ELFT> 1721 bool MipsTargetInfo<ELFT>::needsCopyRelImpl(uint32_t Type) const { 1722 return !isRelRelative(Type) || Type == R_MIPS_LO16; 1723 } 1724 1725 template <class ELFT> 1726 bool MipsTargetInfo<ELFT>::needsGot(uint32_t Type, const SymbolBody &S) const { 1727 return needsPlt(Type, S) || refersToGotEntry(Type); 1728 } 1729 1730 template <class ELFT> 1731 bool MipsTargetInfo<ELFT>::refersToGotEntry(uint32_t Type) const { 1732 return Type == R_MIPS_GOT16 || Type == R_MIPS_CALL16; 1733 } 1734 1735 template <class ELFT> 1736 bool MipsTargetInfo<ELFT>::needsPltImpl(uint32_t Type) const { 1737 return Type == R_MIPS_26; 1738 } 1739 1740 template <class ELFT> 1741 bool MipsTargetInfo<ELFT>::needsThunk(uint32_t Type, const InputFile &File, 1742 const SymbolBody &S) const { 1743 // Any MIPS PIC code function is invoked with its address in register $t9. 1744 // So if we have a branch instruction from non-PIC code to the PIC one 1745 // we cannot make the jump directly and need to create a small stubs 1746 // to save the target function address. 1747 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 1748 if (Type != R_MIPS_26) 1749 return false; 1750 auto *F = dyn_cast<ELFFileBase<ELFT>>(&File); 1751 if (!F) 1752 return false; 1753 // If current file has PIC code, LA25 stub is not required. 1754 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 1755 return false; 1756 auto *D = dyn_cast<DefinedRegular<ELFT>>(&S); 1757 if (!D || !D->Section) 1758 return false; 1759 // LA25 is required if target file has PIC code 1760 // or target symbol is a PIC symbol. 1761 return (D->Section->getFile()->getObj().getHeader()->e_flags & EF_MIPS_PIC) || 1762 (D->StOther & STO_MIPS_MIPS16) == STO_MIPS_PIC; 1763 } 1764 1765 template <class ELFT> 1766 uint64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf, 1767 uint32_t Type) const { 1768 const endianness E = ELFT::TargetEndianness; 1769 switch (Type) { 1770 default: 1771 return 0; 1772 case R_MIPS_32: 1773 case R_MIPS_GPREL32: 1774 return read32<E>(Buf); 1775 case R_MIPS_26: 1776 // FIXME (simon): If the relocation target symbol is not a PLT entry 1777 // we should use another expression for calculation: 1778 // ((A << 2) | (P & 0xf0000000)) >> 2 1779 return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2); 1780 case R_MIPS_GPREL16: 1781 case R_MIPS_LO16: 1782 case R_MIPS_PCLO16: 1783 case R_MIPS_TLS_DTPREL_HI16: 1784 case R_MIPS_TLS_DTPREL_LO16: 1785 case R_MIPS_TLS_TPREL_HI16: 1786 case R_MIPS_TLS_TPREL_LO16: 1787 return readSignedLo16<E>(Buf); 1788 case R_MIPS_PC16: 1789 return getPcRelocAddend<E, 16, 2>(Buf); 1790 case R_MIPS_PC19_S2: 1791 return getPcRelocAddend<E, 19, 2>(Buf); 1792 case R_MIPS_PC21_S2: 1793 return getPcRelocAddend<E, 21, 2>(Buf); 1794 case R_MIPS_PC26_S2: 1795 return getPcRelocAddend<E, 26, 2>(Buf); 1796 case R_MIPS_PC32: 1797 return getPcRelocAddend<E, 32, 0>(Buf); 1798 } 1799 } 1800 1801 template <class ELFT> 1802 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 1803 uint64_t Val) const { 1804 const endianness E = ELFT::TargetEndianness; 1805 // Thread pointer and DRP offsets from the start of TLS data area. 1806 // https://www.linux-mips.org/wiki/NPTL 1807 const uint32_t TPOffset = 0x7000; 1808 const uint32_t DTPOffset = 0x8000; 1809 switch (Type) { 1810 case R_MIPS_32: 1811 write32<E>(Loc, Val); 1812 break; 1813 case R_MIPS_26: { 1814 uint32_t Instr = read32<E>(Loc); 1815 write32<E>(Loc, (Instr & ~0x3ffffff) | (Val >> 2)); 1816 break; 1817 } 1818 case R_MIPS_CALL16: 1819 case R_MIPS_GOT16: { 1820 int64_t V = Val - getMipsGpAddr<ELFT>(); 1821 if (Type == R_MIPS_GOT16) 1822 checkInt<16>(V, Type); 1823 writeMipsLo16<E>(Loc, V); 1824 break; 1825 } 1826 case R_MIPS_GPREL16: { 1827 int64_t V = Val - getMipsGpAddr<ELFT>(); 1828 checkInt<16>(V, Type); 1829 writeMipsLo16<E>(Loc, V); 1830 break; 1831 } 1832 case R_MIPS_GPREL32: 1833 write32<E>(Loc, Val - getMipsGpAddr<ELFT>()); 1834 break; 1835 case R_MIPS_HI16: 1836 writeMipsHi16<E>(Loc, Val); 1837 break; 1838 case R_MIPS_JALR: 1839 // Ignore this optimization relocation for now 1840 break; 1841 case R_MIPS_LO16: 1842 writeMipsLo16<E>(Loc, Val); 1843 break; 1844 case R_MIPS_PC16: 1845 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val); 1846 break; 1847 case R_MIPS_PC19_S2: 1848 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val); 1849 break; 1850 case R_MIPS_PC21_S2: 1851 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val); 1852 break; 1853 case R_MIPS_PC26_S2: 1854 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val); 1855 break; 1856 case R_MIPS_PC32: 1857 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val); 1858 break; 1859 case R_MIPS_PCHI16: 1860 writeMipsHi16<E>(Loc, Val); 1861 break; 1862 case R_MIPS_PCLO16: 1863 writeMipsLo16<E>(Loc, Val); 1864 break; 1865 case R_MIPS_TLS_DTPREL_HI16: 1866 writeMipsHi16<E>(Loc, Val - DTPOffset); 1867 break; 1868 case R_MIPS_TLS_DTPREL_LO16: 1869 writeMipsLo16<E>(Loc, Val - DTPOffset); 1870 break; 1871 case R_MIPS_TLS_TPREL_HI16: 1872 writeMipsHi16<E>(Loc, Val - TPOffset); 1873 break; 1874 case R_MIPS_TLS_TPREL_LO16: 1875 writeMipsLo16<E>(Loc, Val - TPOffset); 1876 break; 1877 default: 1878 fatal("unrecognized reloc " + Twine(Type)); 1879 } 1880 } 1881 1882 template <class ELFT> 1883 bool MipsTargetInfo<ELFT>::isHintRel(uint32_t Type) const { 1884 return Type == R_MIPS_JALR; 1885 } 1886 1887 template <class ELFT> 1888 bool MipsTargetInfo<ELFT>::isRelRelative(uint32_t Type) const { 1889 switch (Type) { 1890 default: 1891 return true; 1892 case R_MIPS_26: 1893 case R_MIPS_32: 1894 case R_MIPS_64: 1895 case R_MIPS_HI16: 1896 case R_MIPS_TLS_DTPREL_HI16: 1897 case R_MIPS_TLS_DTPREL_LO16: 1898 case R_MIPS_TLS_TPREL_HI16: 1899 case R_MIPS_TLS_TPREL_LO16: 1900 return false; 1901 } 1902 } 1903 1904 // _gp is a MIPS-specific ABI-defined symbol which points to 1905 // a location that is relative to GOT. This function returns 1906 // the value for the symbol. 1907 template <class ELFT> typename ELFT::uint getMipsGpAddr() { 1908 return Out<ELFT>::Got->getVA() + MipsGPOffset; 1909 } 1910 1911 template uint32_t getMipsGpAddr<ELF32LE>(); 1912 template uint32_t getMipsGpAddr<ELF32BE>(); 1913 template uint64_t getMipsGpAddr<ELF64LE>(); 1914 template uint64_t getMipsGpAddr<ELF64BE>(); 1915 1916 template bool TargetInfo::needsCopyRel<ELF32LE>(uint32_t, 1917 const SymbolBody &) const; 1918 template bool TargetInfo::needsCopyRel<ELF32BE>(uint32_t, 1919 const SymbolBody &) const; 1920 template bool TargetInfo::needsCopyRel<ELF64LE>(uint32_t, 1921 const SymbolBody &) const; 1922 template bool TargetInfo::needsCopyRel<ELF64BE>(uint32_t, 1923 const SymbolBody &) const; 1924 } 1925 } 1926