1 //===- Target.cpp ---------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Machine-specific things, such as applying relocations, creation of 11 // GOT or PLT entries, etc., are handled in this file. 12 // 13 // Refer the ELF spec for the single letter variables, S, A or P, used 14 // in this file. 15 // 16 // Some functions defined in this file has "relaxTls" as part of their names. 17 // They do peephole optimization for TLS variables by rewriting instructions. 18 // They are not part of the ABI but optional optimization, so you can skip 19 // them if you are not interested in how TLS variables are optimized. 20 // See the following paper for the details. 21 // 22 // Ulrich Drepper, ELF Handling For Thread-Local Storage 23 // http://www.akkadia.org/drepper/tls.pdf 24 // 25 //===----------------------------------------------------------------------===// 26 27 #include "Target.h" 28 #include "Error.h" 29 #include "InputFiles.h" 30 #include "Memory.h" 31 #include "OutputSections.h" 32 #include "SymbolTable.h" 33 #include "Symbols.h" 34 #include "SyntheticSections.h" 35 #include "Thunks.h" 36 #include "Writer.h" 37 #include "llvm/ADT/ArrayRef.h" 38 #include "llvm/Object/ELF.h" 39 #include "llvm/Support/ELF.h" 40 #include "llvm/Support/Endian.h" 41 42 using namespace llvm; 43 using namespace llvm::object; 44 using namespace llvm::support::endian; 45 using namespace llvm::ELF; 46 47 std::string lld::toString(uint32_t Type) { 48 StringRef S = getELFRelocationTypeName(elf::Config->EMachine, Type); 49 if (S == "Unknown") 50 return ("Unknown (" + Twine(Type) + ")").str(); 51 return S; 52 } 53 54 namespace lld { 55 namespace elf { 56 57 TargetInfo *Target; 58 59 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); } 60 static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); } 61 62 template <class ELFT> static std::string getErrorLoc(uint8_t *Loc) { 63 for (InputSectionData *D : Symtab<ELFT>::X->Sections) { 64 auto *IS = dyn_cast_or_null<InputSection<ELFT>>(D); 65 if (!IS || !IS->OutSec) 66 continue; 67 68 uint8_t *ISLoc = cast<OutputSection<ELFT>>(IS->OutSec)->Loc + IS->OutSecOff; 69 if (ISLoc <= Loc && Loc < ISLoc + IS->getSize()) 70 return IS->getLocation(Loc - ISLoc) + ": "; 71 } 72 return ""; 73 } 74 75 static std::string getErrorLocation(uint8_t *Loc) { 76 switch (Config->EKind) { 77 case ELF32LEKind: 78 return getErrorLoc<ELF32LE>(Loc); 79 case ELF32BEKind: 80 return getErrorLoc<ELF32BE>(Loc); 81 case ELF64LEKind: 82 return getErrorLoc<ELF64LE>(Loc); 83 case ELF64BEKind: 84 return getErrorLoc<ELF64BE>(Loc); 85 default: 86 llvm_unreachable("unknown ELF type"); 87 } 88 } 89 90 template <unsigned N> 91 static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) { 92 if (!isInt<N>(V)) 93 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 94 " out of range"); 95 } 96 97 template <unsigned N> 98 static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 99 if (!isUInt<N>(V)) 100 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 101 " out of range"); 102 } 103 104 template <unsigned N> 105 static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) { 106 if (!isInt<N>(V) && !isUInt<N>(V)) 107 error(getErrorLocation(Loc) + "relocation " + toString(Type) + 108 " out of range"); 109 } 110 111 template <unsigned N> 112 static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) { 113 if ((V & (N - 1)) != 0) 114 error(getErrorLocation(Loc) + "improper alignment for relocation " + 115 toString(Type)); 116 } 117 118 namespace { 119 class X86TargetInfo final : public TargetInfo { 120 public: 121 X86TargetInfo(); 122 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 123 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 124 void writeGotPltHeader(uint8_t *Buf) const override; 125 uint32_t getDynRel(uint32_t Type) const override; 126 bool isTlsLocalDynamicRel(uint32_t Type) const override; 127 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 128 bool isTlsInitialExecRel(uint32_t Type) const override; 129 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 130 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 131 void writePltHeader(uint8_t *Buf) const override; 132 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 133 int32_t Index, unsigned RelOff) const override; 134 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 135 136 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 137 RelExpr Expr) const override; 138 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 139 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 140 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 141 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 142 }; 143 144 template <class ELFT> class X86_64TargetInfo final : public TargetInfo { 145 public: 146 X86_64TargetInfo(); 147 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 148 bool isPicRel(uint32_t Type) const override; 149 bool isTlsLocalDynamicRel(uint32_t Type) const override; 150 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 151 bool isTlsInitialExecRel(uint32_t Type) const override; 152 void writeGotPltHeader(uint8_t *Buf) const override; 153 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 154 void writePltHeader(uint8_t *Buf) const override; 155 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 156 int32_t Index, unsigned RelOff) const override; 157 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 158 159 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 160 RelExpr Expr) const override; 161 void relaxGot(uint8_t *Loc, uint64_t Val) const override; 162 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 163 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 164 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 165 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 166 167 private: 168 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op, 169 uint8_t ModRm) const; 170 }; 171 172 class PPCTargetInfo final : public TargetInfo { 173 public: 174 PPCTargetInfo(); 175 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 176 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 177 }; 178 179 class PPC64TargetInfo final : public TargetInfo { 180 public: 181 PPC64TargetInfo(); 182 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 183 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 184 int32_t Index, unsigned RelOff) const override; 185 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 186 }; 187 188 class AArch64TargetInfo final : public TargetInfo { 189 public: 190 AArch64TargetInfo(); 191 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 192 bool isPicRel(uint32_t Type) const override; 193 bool isTlsInitialExecRel(uint32_t Type) const override; 194 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 195 void writePltHeader(uint8_t *Buf) const override; 196 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 197 int32_t Index, unsigned RelOff) const override; 198 bool usesOnlyLowPageBits(uint32_t Type) const override; 199 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 200 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 201 RelExpr Expr) const override; 202 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 203 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 204 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 205 }; 206 207 class AMDGPUTargetInfo final : public TargetInfo { 208 public: 209 AMDGPUTargetInfo(); 210 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 211 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 212 }; 213 214 class ARMTargetInfo final : public TargetInfo { 215 public: 216 ARMTargetInfo(); 217 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 218 bool isPicRel(uint32_t Type) const override; 219 uint32_t getDynRel(uint32_t Type) const override; 220 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 221 bool isTlsLocalDynamicRel(uint32_t Type) const override; 222 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 223 bool isTlsInitialExecRel(uint32_t Type) const override; 224 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 225 void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override; 226 void writePltHeader(uint8_t *Buf) const override; 227 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 228 int32_t Index, unsigned RelOff) const override; 229 void addPltSymbols(InputSectionData *IS, uint64_t Off) const override; 230 void addPltHeaderSymbols(InputSectionData *ISD) const override; 231 bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File, 232 const SymbolBody &S) const override; 233 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 234 }; 235 236 template <class ELFT> class MipsTargetInfo final : public TargetInfo { 237 public: 238 MipsTargetInfo(); 239 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 240 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 241 bool isPicRel(uint32_t Type) const override; 242 uint32_t getDynRel(uint32_t Type) const override; 243 bool isTlsLocalDynamicRel(uint32_t Type) const override; 244 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 245 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 246 void writePltHeader(uint8_t *Buf) const override; 247 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 248 int32_t Index, unsigned RelOff) const override; 249 bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File, 250 const SymbolBody &S) const override; 251 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 252 bool usesOnlyLowPageBits(uint32_t Type) const override; 253 }; 254 } // anonymous namespace 255 256 TargetInfo *createTarget() { 257 switch (Config->EMachine) { 258 case EM_386: 259 case EM_IAMCU: 260 return make<X86TargetInfo>(); 261 case EM_AARCH64: 262 return make<AArch64TargetInfo>(); 263 case EM_AMDGPU: 264 return make<AMDGPUTargetInfo>(); 265 case EM_ARM: 266 return make<ARMTargetInfo>(); 267 case EM_MIPS: 268 switch (Config->EKind) { 269 case ELF32LEKind: 270 return make<MipsTargetInfo<ELF32LE>>(); 271 case ELF32BEKind: 272 return make<MipsTargetInfo<ELF32BE>>(); 273 case ELF64LEKind: 274 return make<MipsTargetInfo<ELF64LE>>(); 275 case ELF64BEKind: 276 return make<MipsTargetInfo<ELF64BE>>(); 277 default: 278 fatal("unsupported MIPS target"); 279 } 280 case EM_PPC: 281 return make<PPCTargetInfo>(); 282 case EM_PPC64: 283 return make<PPC64TargetInfo>(); 284 case EM_X86_64: 285 if (Config->EKind == ELF32LEKind) 286 return make<X86_64TargetInfo<ELF32LE>>(); 287 return make<X86_64TargetInfo<ELF64LE>>(); 288 } 289 fatal("unknown target machine"); 290 } 291 292 TargetInfo::~TargetInfo() {} 293 294 uint64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, 295 uint32_t Type) const { 296 return 0; 297 } 298 299 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; } 300 301 bool TargetInfo::needsThunk(RelExpr Expr, uint32_t RelocType, 302 const InputFile *File, const SymbolBody &S) const { 303 return false; 304 } 305 306 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; } 307 308 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; } 309 310 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { return false; } 311 312 void TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 313 writeGotPlt(Buf, S); 314 } 315 316 RelExpr TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 317 RelExpr Expr) const { 318 return Expr; 319 } 320 321 void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const { 322 llvm_unreachable("Should not have claimed to be relaxable"); 323 } 324 325 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 326 uint64_t Val) const { 327 llvm_unreachable("Should not have claimed to be relaxable"); 328 } 329 330 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 331 uint64_t Val) const { 332 llvm_unreachable("Should not have claimed to be relaxable"); 333 } 334 335 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 336 uint64_t Val) const { 337 llvm_unreachable("Should not have claimed to be relaxable"); 338 } 339 340 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 341 uint64_t Val) const { 342 llvm_unreachable("Should not have claimed to be relaxable"); 343 } 344 345 X86TargetInfo::X86TargetInfo() { 346 CopyRel = R_386_COPY; 347 GotRel = R_386_GLOB_DAT; 348 PltRel = R_386_JUMP_SLOT; 349 IRelativeRel = R_386_IRELATIVE; 350 RelativeRel = R_386_RELATIVE; 351 TlsGotRel = R_386_TLS_TPOFF; 352 TlsModuleIndexRel = R_386_TLS_DTPMOD32; 353 TlsOffsetRel = R_386_TLS_DTPOFF32; 354 GotEntrySize = 4; 355 GotPltEntrySize = 4; 356 PltEntrySize = 16; 357 PltHeaderSize = 16; 358 TlsGdRelaxSkip = 2; 359 } 360 361 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 362 switch (Type) { 363 case R_386_8: 364 case R_386_16: 365 case R_386_32: 366 case R_386_TLS_LDO_32: 367 return R_ABS; 368 case R_386_TLS_GD: 369 return R_TLSGD; 370 case R_386_TLS_LDM: 371 return R_TLSLD; 372 case R_386_PLT32: 373 return R_PLT_PC; 374 case R_386_PC8: 375 case R_386_PC16: 376 case R_386_PC32: 377 return R_PC; 378 case R_386_GOTPC: 379 return R_GOTONLY_PC_FROM_END; 380 case R_386_TLS_IE: 381 return R_GOT; 382 case R_386_GOT32: 383 case R_386_GOT32X: 384 case R_386_TLS_GOTIE: 385 return R_GOT_FROM_END; 386 case R_386_GOTOFF: 387 return R_GOTREL_FROM_END; 388 case R_386_TLS_LE: 389 return R_TLS; 390 case R_386_TLS_LE_32: 391 return R_NEG_TLS; 392 case R_386_NONE: 393 return R_HINT; 394 default: 395 error(toString(S.File) + ": unknown relocation type: " + toString(Type)); 396 return R_HINT; 397 } 398 } 399 400 RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 401 RelExpr Expr) const { 402 switch (Expr) { 403 default: 404 return Expr; 405 case R_RELAX_TLS_GD_TO_IE: 406 return R_RELAX_TLS_GD_TO_IE_END; 407 case R_RELAX_TLS_GD_TO_LE: 408 return R_RELAX_TLS_GD_TO_LE_NEG; 409 } 410 } 411 412 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const { 413 write32le(Buf, In<ELF32LE>::Dynamic->getVA()); 414 } 415 416 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const { 417 // Entries in .got.plt initially points back to the corresponding 418 // PLT entries with a fixed offset to skip the first instruction. 419 write32le(Buf, S.getPltVA<ELF32LE>() + 6); 420 } 421 422 void X86TargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 423 // An x86 entry is the address of the ifunc resolver function. 424 write32le(Buf, S.getVA<ELF32LE>()); 425 } 426 427 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const { 428 if (Type == R_386_TLS_LE) 429 return R_386_TLS_TPOFF; 430 if (Type == R_386_TLS_LE_32) 431 return R_386_TLS_TPOFF32; 432 return Type; 433 } 434 435 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 436 return Type == R_386_TLS_GD; 437 } 438 439 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 440 return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM; 441 } 442 443 bool X86TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 444 return Type == R_386_TLS_IE || Type == R_386_TLS_GOTIE; 445 } 446 447 void X86TargetInfo::writePltHeader(uint8_t *Buf) const { 448 // Executable files and shared object files have 449 // separate procedure linkage tables. 450 if (Config->Pic) { 451 const uint8_t V[] = { 452 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl 4(%ebx) 453 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *8(%ebx) 454 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 455 }; 456 memcpy(Buf, V, sizeof(V)); 457 return; 458 } 459 460 const uint8_t PltData[] = { 461 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOT+4) 462 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOT+8) 463 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 464 }; 465 memcpy(Buf, PltData, sizeof(PltData)); 466 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 467 write32le(Buf + 2, Got + 4); 468 write32le(Buf + 8, Got + 8); 469 } 470 471 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 472 uint64_t PltEntryAddr, int32_t Index, 473 unsigned RelOff) const { 474 const uint8_t Inst[] = { 475 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx) 476 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset 477 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC 478 }; 479 memcpy(Buf, Inst, sizeof(Inst)); 480 481 // jmp *foo@GOT(%ebx) or jmp *foo_in_GOT 482 Buf[1] = Config->Pic ? 0xa3 : 0x25; 483 uint32_t Got = In<ELF32LE>::GotPlt->getVA(); 484 write32le(Buf + 2, Config->Shared ? GotEntryAddr - Got : GotEntryAddr); 485 write32le(Buf + 7, RelOff); 486 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 487 } 488 489 uint64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf, 490 uint32_t Type) const { 491 switch (Type) { 492 default: 493 return 0; 494 case R_386_8: 495 case R_386_PC8: 496 return *Buf; 497 case R_386_16: 498 case R_386_PC16: 499 return read16le(Buf); 500 case R_386_32: 501 case R_386_GOT32: 502 case R_386_GOT32X: 503 case R_386_GOTOFF: 504 case R_386_GOTPC: 505 case R_386_PC32: 506 case R_386_PLT32: 507 case R_386_TLS_LE: 508 return read32le(Buf); 509 } 510 } 511 512 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 513 uint64_t Val) const { 514 // R_386_{PC,}{8,16} are not part of the i386 psABI, but they are 515 // being used for some 16-bit programs such as boot loaders, so 516 // we want to support them. 517 switch (Type) { 518 case R_386_8: 519 case R_386_PC8: 520 checkInt<8>(Loc, Val, Type); 521 *Loc = Val; 522 break; 523 case R_386_16: 524 case R_386_PC16: 525 checkInt<16>(Loc, Val, Type); 526 write16le(Loc, Val); 527 break; 528 default: 529 checkInt<32>(Loc, Val, Type); 530 write32le(Loc, Val); 531 } 532 } 533 534 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 535 uint64_t Val) const { 536 // Convert 537 // leal x@tlsgd(, %ebx, 1), 538 // call __tls_get_addr@plt 539 // to 540 // movl %gs:0,%eax 541 // subl $x@ntpoff,%eax 542 const uint8_t Inst[] = { 543 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 544 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax 545 }; 546 memcpy(Loc - 3, Inst, sizeof(Inst)); 547 relocateOne(Loc + 5, R_386_32, Val); 548 } 549 550 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 551 uint64_t Val) const { 552 // Convert 553 // leal x@tlsgd(, %ebx, 1), 554 // call __tls_get_addr@plt 555 // to 556 // movl %gs:0, %eax 557 // addl x@gotntpoff(%ebx), %eax 558 const uint8_t Inst[] = { 559 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 560 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax 561 }; 562 memcpy(Loc - 3, Inst, sizeof(Inst)); 563 relocateOne(Loc + 5, R_386_32, Val); 564 } 565 566 // In some conditions, relocations can be optimized to avoid using GOT. 567 // This function does that for Initial Exec to Local Exec case. 568 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 569 uint64_t Val) const { 570 // Ulrich's document section 6.2 says that @gotntpoff can 571 // be used with MOVL or ADDL instructions. 572 // @indntpoff is similar to @gotntpoff, but for use in 573 // position dependent code. 574 uint8_t Reg = (Loc[-1] >> 3) & 7; 575 576 if (Type == R_386_TLS_IE) { 577 if (Loc[-1] == 0xa1) { 578 // "movl foo@indntpoff,%eax" -> "movl $foo,%eax" 579 // This case is different from the generic case below because 580 // this is a 5 byte instruction while below is 6 bytes. 581 Loc[-1] = 0xb8; 582 } else if (Loc[-2] == 0x8b) { 583 // "movl foo@indntpoff,%reg" -> "movl $foo,%reg" 584 Loc[-2] = 0xc7; 585 Loc[-1] = 0xc0 | Reg; 586 } else { 587 // "addl foo@indntpoff,%reg" -> "addl $foo,%reg" 588 Loc[-2] = 0x81; 589 Loc[-1] = 0xc0 | Reg; 590 } 591 } else { 592 assert(Type == R_386_TLS_GOTIE); 593 if (Loc[-2] == 0x8b) { 594 // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg" 595 Loc[-2] = 0xc7; 596 Loc[-1] = 0xc0 | Reg; 597 } else { 598 // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg" 599 Loc[-2] = 0x8d; 600 Loc[-1] = 0x80 | (Reg << 3) | Reg; 601 } 602 } 603 relocateOne(Loc, R_386_TLS_LE, Val); 604 } 605 606 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 607 uint64_t Val) const { 608 if (Type == R_386_TLS_LDO_32) { 609 relocateOne(Loc, R_386_TLS_LE, Val); 610 return; 611 } 612 613 // Convert 614 // leal foo(%reg),%eax 615 // call ___tls_get_addr 616 // to 617 // movl %gs:0,%eax 618 // nop 619 // leal 0(%esi,1),%esi 620 const uint8_t Inst[] = { 621 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax 622 0x90, // nop 623 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi 624 }; 625 memcpy(Loc - 2, Inst, sizeof(Inst)); 626 } 627 628 template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() { 629 CopyRel = R_X86_64_COPY; 630 GotRel = R_X86_64_GLOB_DAT; 631 PltRel = R_X86_64_JUMP_SLOT; 632 RelativeRel = R_X86_64_RELATIVE; 633 IRelativeRel = R_X86_64_IRELATIVE; 634 TlsGotRel = R_X86_64_TPOFF64; 635 TlsModuleIndexRel = R_X86_64_DTPMOD64; 636 TlsOffsetRel = R_X86_64_DTPOFF64; 637 GotEntrySize = 8; 638 GotPltEntrySize = 8; 639 PltEntrySize = 16; 640 PltHeaderSize = 16; 641 TlsGdRelaxSkip = 2; 642 // Align to the large page size (known as a superpage or huge page). 643 // FreeBSD automatically promotes large, superpage-aligned allocations. 644 DefaultImageBase = 0x200000; 645 } 646 647 template <class ELFT> 648 RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type, 649 const SymbolBody &S) const { 650 switch (Type) { 651 case R_X86_64_8: 652 case R_X86_64_32: 653 case R_X86_64_32S: 654 case R_X86_64_64: 655 case R_X86_64_DTPOFF32: 656 case R_X86_64_DTPOFF64: 657 return R_ABS; 658 case R_X86_64_TPOFF32: 659 return R_TLS; 660 case R_X86_64_TLSLD: 661 return R_TLSLD_PC; 662 case R_X86_64_TLSGD: 663 return R_TLSGD_PC; 664 case R_X86_64_SIZE32: 665 case R_X86_64_SIZE64: 666 return R_SIZE; 667 case R_X86_64_PLT32: 668 return R_PLT_PC; 669 case R_X86_64_PC32: 670 case R_X86_64_PC64: 671 return R_PC; 672 case R_X86_64_GOT32: 673 case R_X86_64_GOT64: 674 return R_GOT_FROM_END; 675 case R_X86_64_GOTPCREL: 676 case R_X86_64_GOTPCRELX: 677 case R_X86_64_REX_GOTPCRELX: 678 case R_X86_64_GOTTPOFF: 679 return R_GOT_PC; 680 case R_X86_64_NONE: 681 return R_HINT; 682 default: 683 error(toString(S.File) + ": unknown relocation type: " + toString(Type)); 684 return R_HINT; 685 } 686 } 687 688 template <class ELFT> 689 void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const { 690 // The first entry holds the value of _DYNAMIC. It is not clear why that is 691 // required, but it is documented in the psabi and the glibc dynamic linker 692 // seems to use it (note that this is relevant for linking ld.so, not any 693 // other program). 694 write64le(Buf, In<ELFT>::Dynamic->getVA()); 695 } 696 697 template <class ELFT> 698 void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, 699 const SymbolBody &S) const { 700 // See comments in X86TargetInfo::writeGotPlt. 701 write32le(Buf, S.getPltVA<ELFT>() + 6); 702 } 703 704 template <class ELFT> 705 void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 706 const uint8_t PltData[] = { 707 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOT+8(%rip) 708 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOT+16(%rip) 709 0x0f, 0x1f, 0x40, 0x00 // nopl 0x0(rax) 710 }; 711 memcpy(Buf, PltData, sizeof(PltData)); 712 uint64_t Got = In<ELFT>::GotPlt->getVA(); 713 uint64_t Plt = In<ELFT>::Plt->getVA(); 714 write32le(Buf + 2, Got - Plt + 2); // GOT+8 715 write32le(Buf + 8, Got - Plt + 4); // GOT+16 716 } 717 718 template <class ELFT> 719 void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 720 uint64_t PltEntryAddr, int32_t Index, 721 unsigned RelOff) const { 722 const uint8_t Inst[] = { 723 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip) 724 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index> 725 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0] 726 }; 727 memcpy(Buf, Inst, sizeof(Inst)); 728 729 write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6); 730 write32le(Buf + 7, Index); 731 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 732 } 733 734 template <class ELFT> 735 bool X86_64TargetInfo<ELFT>::isPicRel(uint32_t Type) const { 736 return Type != R_X86_64_PC32 && Type != R_X86_64_32; 737 } 738 739 template <class ELFT> 740 bool X86_64TargetInfo<ELFT>::isTlsInitialExecRel(uint32_t Type) const { 741 return Type == R_X86_64_GOTTPOFF; 742 } 743 744 template <class ELFT> 745 bool X86_64TargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 746 return Type == R_X86_64_TLSGD; 747 } 748 749 template <class ELFT> 750 bool X86_64TargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 751 return Type == R_X86_64_DTPOFF32 || Type == R_X86_64_DTPOFF64 || 752 Type == R_X86_64_TLSLD; 753 } 754 755 template <class ELFT> 756 void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 757 uint64_t Val) const { 758 // Convert 759 // .byte 0x66 760 // leaq x@tlsgd(%rip), %rdi 761 // .word 0x6666 762 // rex64 763 // call __tls_get_addr@plt 764 // to 765 // mov %fs:0x0,%rax 766 // lea x@tpoff,%rax 767 const uint8_t Inst[] = { 768 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 769 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax 770 }; 771 memcpy(Loc - 4, Inst, sizeof(Inst)); 772 // The original code used a pc relative relocation and so we have to 773 // compensate for the -4 in had in the addend. 774 relocateOne(Loc + 8, R_X86_64_TPOFF32, Val + 4); 775 } 776 777 template <class ELFT> 778 void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 779 uint64_t Val) const { 780 // Convert 781 // .byte 0x66 782 // leaq x@tlsgd(%rip), %rdi 783 // .word 0x6666 784 // rex64 785 // call __tls_get_addr@plt 786 // to 787 // mov %fs:0x0,%rax 788 // addq x@tpoff,%rax 789 const uint8_t Inst[] = { 790 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 791 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax 792 }; 793 memcpy(Loc - 4, Inst, sizeof(Inst)); 794 // Both code sequences are PC relatives, but since we are moving the constant 795 // forward by 8 bytes we have to subtract the value by 8. 796 relocateOne(Loc + 8, R_X86_64_PC32, Val - 8); 797 } 798 799 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to 800 // R_X86_64_TPOFF32 so that it does not use GOT. 801 template <class ELFT> 802 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 803 uint64_t Val) const { 804 uint8_t *Inst = Loc - 3; 805 uint8_t Reg = Loc[-1] >> 3; 806 uint8_t *RegSlot = Loc - 1; 807 808 // Note that ADD with RSP or R12 is converted to ADD instead of LEA 809 // because LEA with these registers needs 4 bytes to encode and thus 810 // wouldn't fit the space. 811 812 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) { 813 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp" 814 memcpy(Inst, "\x48\x81\xc4", 3); 815 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) { 816 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12" 817 memcpy(Inst, "\x49\x81\xc4", 3); 818 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) { 819 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]" 820 memcpy(Inst, "\x4d\x8d", 2); 821 *RegSlot = 0x80 | (Reg << 3) | Reg; 822 } else if (memcmp(Inst, "\x48\x03", 2) == 0) { 823 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg" 824 memcpy(Inst, "\x48\x8d", 2); 825 *RegSlot = 0x80 | (Reg << 3) | Reg; 826 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) { 827 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]" 828 memcpy(Inst, "\x49\xc7", 2); 829 *RegSlot = 0xc0 | Reg; 830 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) { 831 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg" 832 memcpy(Inst, "\x48\xc7", 2); 833 *RegSlot = 0xc0 | Reg; 834 } else { 835 error(getErrorLocation(Loc - 3) + 836 "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only"); 837 } 838 839 // The original code used a PC relative relocation. 840 // Need to compensate for the -4 it had in the addend. 841 relocateOne(Loc, R_X86_64_TPOFF32, Val + 4); 842 } 843 844 template <class ELFT> 845 void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 846 uint64_t Val) const { 847 // Convert 848 // leaq bar@tlsld(%rip), %rdi 849 // callq __tls_get_addr@PLT 850 // leaq bar@dtpoff(%rax), %rcx 851 // to 852 // .word 0x6666 853 // .byte 0x66 854 // mov %fs:0,%rax 855 // leaq bar@tpoff(%rax), %rcx 856 if (Type == R_X86_64_DTPOFF64) { 857 write64le(Loc, Val); 858 return; 859 } 860 if (Type == R_X86_64_DTPOFF32) { 861 relocateOne(Loc, R_X86_64_TPOFF32, Val); 862 return; 863 } 864 865 const uint8_t Inst[] = { 866 0x66, 0x66, // .word 0x6666 867 0x66, // .byte 0x66 868 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax 869 }; 870 memcpy(Loc - 3, Inst, sizeof(Inst)); 871 } 872 873 template <class ELFT> 874 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 875 uint64_t Val) const { 876 switch (Type) { 877 case R_X86_64_8: 878 checkUInt<8>(Loc, Val, Type); 879 *Loc = Val; 880 break; 881 case R_X86_64_32: 882 checkUInt<32>(Loc, Val, Type); 883 write32le(Loc, Val); 884 break; 885 case R_X86_64_32S: 886 case R_X86_64_TPOFF32: 887 case R_X86_64_GOT32: 888 case R_X86_64_GOTPCREL: 889 case R_X86_64_GOTPCRELX: 890 case R_X86_64_REX_GOTPCRELX: 891 case R_X86_64_PC32: 892 case R_X86_64_GOTTPOFF: 893 case R_X86_64_PLT32: 894 case R_X86_64_TLSGD: 895 case R_X86_64_TLSLD: 896 case R_X86_64_DTPOFF32: 897 case R_X86_64_SIZE32: 898 checkInt<32>(Loc, Val, Type); 899 write32le(Loc, Val); 900 break; 901 case R_X86_64_64: 902 case R_X86_64_DTPOFF64: 903 case R_X86_64_GLOB_DAT: 904 case R_X86_64_PC64: 905 case R_X86_64_SIZE64: 906 case R_X86_64_GOT64: 907 write64le(Loc, Val); 908 break; 909 default: 910 llvm_unreachable("unexpected relocation"); 911 } 912 } 913 914 template <class ELFT> 915 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type, 916 const uint8_t *Data, 917 RelExpr RelExpr) const { 918 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX) 919 return RelExpr; 920 const uint8_t Op = Data[-2]; 921 const uint8_t ModRm = Data[-1]; 922 // FIXME: When PIC is disabled and foo is defined locally in the 923 // lower 32 bit address space, memory operand in mov can be converted into 924 // immediate operand. Otherwise, mov must be changed to lea. We support only 925 // latter relaxation at this moment. 926 if (Op == 0x8b) 927 return R_RELAX_GOT_PC; 928 // Relax call and jmp. 929 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25)) 930 return R_RELAX_GOT_PC; 931 932 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor. 933 // If PIC then no relaxation is available. 934 // We also don't relax test/binop instructions without REX byte, 935 // they are 32bit operations and not common to have. 936 assert(Type == R_X86_64_REX_GOTPCRELX); 937 return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC; 938 } 939 940 // A subset of relaxations can only be applied for no-PIC. This method 941 // handles such relaxations. Instructions encoding information was taken from: 942 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2" 943 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/ 944 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf) 945 template <class ELFT> 946 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val, 947 uint8_t Op, uint8_t ModRm) const { 948 const uint8_t Rex = Loc[-3]; 949 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg". 950 if (Op == 0x85) { 951 // See "TEST-Logical Compare" (4-428 Vol. 2B), 952 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension). 953 954 // ModR/M byte has form XX YYY ZZZ, where 955 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1). 956 // XX has different meanings: 957 // 00: The operand's memory address is in reg1. 958 // 01: The operand's memory address is reg1 + a byte-sized displacement. 959 // 10: The operand's memory address is reg1 + a word-sized displacement. 960 // 11: The operand is reg1 itself. 961 // If an instruction requires only one operand, the unused reg2 field 962 // holds extra opcode bits rather than a register code 963 // 0xC0 == 11 000 000 binary. 964 // 0x38 == 00 111 000 binary. 965 // We transfer reg2 to reg1 here as operand. 966 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3). 967 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte. 968 969 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32 970 // See "TEST-Logical Compare" (4-428 Vol. 2B). 971 Loc[-2] = 0xf7; 972 973 // Move R bit to the B bit in REX byte. 974 // REX byte is encoded as 0100WRXB, where 975 // 0100 is 4bit fixed pattern. 976 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the 977 // default operand size is used (which is 32-bit for most but not all 978 // instructions). 979 // REX.R This 1-bit value is an extension to the MODRM.reg field. 980 // REX.X This 1-bit value is an extension to the SIB.index field. 981 // REX.B This 1-bit value is an extension to the MODRM.rm field or the 982 // SIB.base field. 983 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A). 984 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 985 relocateOne(Loc, R_X86_64_PC32, Val); 986 return; 987 } 988 989 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub 990 // or xor operations. 991 992 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg". 993 // Logic is close to one for test instruction above, but we also 994 // write opcode extension here, see below for details. 995 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte. 996 997 // Primary opcode is 0x81, opcode extension is one of: 998 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB, 999 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP. 1000 // This value was wrote to MODRM.reg in a line above. 1001 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15), 1002 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for 1003 // descriptions about each operation. 1004 Loc[-2] = 0x81; 1005 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 1006 relocateOne(Loc, R_X86_64_PC32, Val); 1007 } 1008 1009 template <class ELFT> 1010 void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const { 1011 const uint8_t Op = Loc[-2]; 1012 const uint8_t ModRm = Loc[-1]; 1013 1014 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg". 1015 if (Op == 0x8b) { 1016 Loc[-2] = 0x8d; 1017 relocateOne(Loc, R_X86_64_PC32, Val); 1018 return; 1019 } 1020 1021 if (Op != 0xff) { 1022 // We are relaxing a rip relative to an absolute, so compensate 1023 // for the old -4 addend. 1024 assert(!Config->Pic); 1025 relaxGotNoPic(Loc, Val + 4, Op, ModRm); 1026 return; 1027 } 1028 1029 // Convert call/jmp instructions. 1030 if (ModRm == 0x15) { 1031 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo". 1032 // Instead we convert to "addr32 call foo" where addr32 is an instruction 1033 // prefix. That makes result expression to be a single instruction. 1034 Loc[-2] = 0x67; // addr32 prefix 1035 Loc[-1] = 0xe8; // call 1036 relocateOne(Loc, R_X86_64_PC32, Val); 1037 return; 1038 } 1039 1040 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop". 1041 // jmp doesn't return, so it is fine to use nop here, it is just a stub. 1042 assert(ModRm == 0x25); 1043 Loc[-2] = 0xe9; // jmp 1044 Loc[3] = 0x90; // nop 1045 relocateOne(Loc - 1, R_X86_64_PC32, Val + 1); 1046 } 1047 1048 // Relocation masks following the #lo(value), #hi(value), #ha(value), 1049 // #higher(value), #highera(value), #highest(value), and #highesta(value) 1050 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 1051 // document. 1052 static uint16_t applyPPCLo(uint64_t V) { return V; } 1053 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; } 1054 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; } 1055 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; } 1056 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; } 1057 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; } 1058 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; } 1059 1060 PPCTargetInfo::PPCTargetInfo() {} 1061 1062 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1063 uint64_t Val) const { 1064 switch (Type) { 1065 case R_PPC_ADDR16_HA: 1066 write16be(Loc, applyPPCHa(Val)); 1067 break; 1068 case R_PPC_ADDR16_LO: 1069 write16be(Loc, applyPPCLo(Val)); 1070 break; 1071 case R_PPC_ADDR32: 1072 case R_PPC_REL32: 1073 write32be(Loc, Val); 1074 break; 1075 case R_PPC_REL24: 1076 or32be(Loc, Val & 0x3FFFFFC); 1077 break; 1078 default: 1079 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1080 } 1081 } 1082 1083 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1084 switch (Type) { 1085 case R_PPC_REL24: 1086 case R_PPC_REL32: 1087 return R_PC; 1088 default: 1089 return R_ABS; 1090 } 1091 } 1092 1093 PPC64TargetInfo::PPC64TargetInfo() { 1094 PltRel = GotRel = R_PPC64_GLOB_DAT; 1095 RelativeRel = R_PPC64_RELATIVE; 1096 GotEntrySize = 8; 1097 GotPltEntrySize = 8; 1098 PltEntrySize = 32; 1099 PltHeaderSize = 0; 1100 1101 // We need 64K pages (at least under glibc/Linux, the loader won't 1102 // set different permissions on a finer granularity than that). 1103 DefaultMaxPageSize = 65536; 1104 1105 // The PPC64 ELF ABI v1 spec, says: 1106 // 1107 // It is normally desirable to put segments with different characteristics 1108 // in separate 256 Mbyte portions of the address space, to give the 1109 // operating system full paging flexibility in the 64-bit address space. 1110 // 1111 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 1112 // use 0x10000000 as the starting address. 1113 DefaultImageBase = 0x10000000; 1114 } 1115 1116 static uint64_t PPC64TocOffset = 0x8000; 1117 1118 uint64_t getPPC64TocBase() { 1119 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 1120 // TOC starts where the first of these sections starts. We always create a 1121 // .got when we see a relocation that uses it, so for us the start is always 1122 // the .got. 1123 uint64_t TocVA = In<ELF64BE>::Got->getVA(); 1124 1125 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 1126 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 1127 // code (crt1.o) assumes that you can get from the TOC base to the 1128 // start of the .toc section with only a single (signed) 16-bit relocation. 1129 return TocVA + PPC64TocOffset; 1130 } 1131 1132 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1133 switch (Type) { 1134 default: 1135 return R_ABS; 1136 case R_PPC64_TOC16: 1137 case R_PPC64_TOC16_DS: 1138 case R_PPC64_TOC16_HA: 1139 case R_PPC64_TOC16_HI: 1140 case R_PPC64_TOC16_LO: 1141 case R_PPC64_TOC16_LO_DS: 1142 return R_GOTREL; 1143 case R_PPC64_TOC: 1144 return R_PPC_TOC; 1145 case R_PPC64_REL24: 1146 return R_PPC_PLT_OPD; 1147 } 1148 } 1149 1150 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1151 uint64_t PltEntryAddr, int32_t Index, 1152 unsigned RelOff) const { 1153 uint64_t Off = GotEntryAddr - getPPC64TocBase(); 1154 1155 // FIXME: What we should do, in theory, is get the offset of the function 1156 // descriptor in the .opd section, and use that as the offset from %r2 (the 1157 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will 1158 // be a pointer to the function descriptor in the .opd section. Using 1159 // this scheme is simpler, but requires an extra indirection per PLT dispatch. 1160 1161 write32be(Buf, 0xf8410028); // std %r2, 40(%r1) 1162 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha 1163 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11) 1164 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12) 1165 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11 1166 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12) 1167 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12) 1168 write32be(Buf + 28, 0x4e800420); // bctr 1169 } 1170 1171 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) { 1172 uint64_t V = Val - PPC64TocOffset; 1173 switch (Type) { 1174 case R_PPC64_TOC16: 1175 return {R_PPC64_ADDR16, V}; 1176 case R_PPC64_TOC16_DS: 1177 return {R_PPC64_ADDR16_DS, V}; 1178 case R_PPC64_TOC16_HA: 1179 return {R_PPC64_ADDR16_HA, V}; 1180 case R_PPC64_TOC16_HI: 1181 return {R_PPC64_ADDR16_HI, V}; 1182 case R_PPC64_TOC16_LO: 1183 return {R_PPC64_ADDR16_LO, V}; 1184 case R_PPC64_TOC16_LO_DS: 1185 return {R_PPC64_ADDR16_LO_DS, V}; 1186 default: 1187 return {Type, Val}; 1188 } 1189 } 1190 1191 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1192 uint64_t Val) const { 1193 // For a TOC-relative relocation, proceed in terms of the corresponding 1194 // ADDR16 relocation type. 1195 std::tie(Type, Val) = toAddr16Rel(Type, Val); 1196 1197 switch (Type) { 1198 case R_PPC64_ADDR14: { 1199 checkAlignment<4>(Loc, Val, Type); 1200 // Preserve the AA/LK bits in the branch instruction 1201 uint8_t AALK = Loc[3]; 1202 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 1203 break; 1204 } 1205 case R_PPC64_ADDR16: 1206 checkInt<16>(Loc, Val, Type); 1207 write16be(Loc, Val); 1208 break; 1209 case R_PPC64_ADDR16_DS: 1210 checkInt<16>(Loc, Val, Type); 1211 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3)); 1212 break; 1213 case R_PPC64_ADDR16_HA: 1214 case R_PPC64_REL16_HA: 1215 write16be(Loc, applyPPCHa(Val)); 1216 break; 1217 case R_PPC64_ADDR16_HI: 1218 case R_PPC64_REL16_HI: 1219 write16be(Loc, applyPPCHi(Val)); 1220 break; 1221 case R_PPC64_ADDR16_HIGHER: 1222 write16be(Loc, applyPPCHigher(Val)); 1223 break; 1224 case R_PPC64_ADDR16_HIGHERA: 1225 write16be(Loc, applyPPCHighera(Val)); 1226 break; 1227 case R_PPC64_ADDR16_HIGHEST: 1228 write16be(Loc, applyPPCHighest(Val)); 1229 break; 1230 case R_PPC64_ADDR16_HIGHESTA: 1231 write16be(Loc, applyPPCHighesta(Val)); 1232 break; 1233 case R_PPC64_ADDR16_LO: 1234 write16be(Loc, applyPPCLo(Val)); 1235 break; 1236 case R_PPC64_ADDR16_LO_DS: 1237 case R_PPC64_REL16_LO: 1238 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3)); 1239 break; 1240 case R_PPC64_ADDR32: 1241 case R_PPC64_REL32: 1242 checkInt<32>(Loc, Val, Type); 1243 write32be(Loc, Val); 1244 break; 1245 case R_PPC64_ADDR64: 1246 case R_PPC64_REL64: 1247 case R_PPC64_TOC: 1248 write64be(Loc, Val); 1249 break; 1250 case R_PPC64_REL24: { 1251 uint32_t Mask = 0x03FFFFFC; 1252 checkInt<24>(Loc, Val, Type); 1253 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask)); 1254 break; 1255 } 1256 default: 1257 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1258 } 1259 } 1260 1261 AArch64TargetInfo::AArch64TargetInfo() { 1262 CopyRel = R_AARCH64_COPY; 1263 RelativeRel = R_AARCH64_RELATIVE; 1264 IRelativeRel = R_AARCH64_IRELATIVE; 1265 GotRel = R_AARCH64_GLOB_DAT; 1266 PltRel = R_AARCH64_JUMP_SLOT; 1267 TlsDescRel = R_AARCH64_TLSDESC; 1268 TlsGotRel = R_AARCH64_TLS_TPREL64; 1269 GotEntrySize = 8; 1270 GotPltEntrySize = 8; 1271 PltEntrySize = 16; 1272 PltHeaderSize = 32; 1273 DefaultMaxPageSize = 65536; 1274 1275 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant 1276 // 1 of the tls structures and the tcb size is 16. 1277 TcbSize = 16; 1278 } 1279 1280 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type, 1281 const SymbolBody &S) const { 1282 switch (Type) { 1283 default: 1284 return R_ABS; 1285 case R_AARCH64_TLSDESC_ADR_PAGE21: 1286 return R_TLSDESC_PAGE; 1287 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1288 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1289 return R_TLSDESC; 1290 case R_AARCH64_TLSDESC_CALL: 1291 return R_TLSDESC_CALL; 1292 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1293 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1294 return R_TLS; 1295 case R_AARCH64_CALL26: 1296 case R_AARCH64_CONDBR19: 1297 case R_AARCH64_JUMP26: 1298 case R_AARCH64_TSTBR14: 1299 return R_PLT_PC; 1300 case R_AARCH64_PREL16: 1301 case R_AARCH64_PREL32: 1302 case R_AARCH64_PREL64: 1303 case R_AARCH64_ADR_PREL_LO21: 1304 return R_PC; 1305 case R_AARCH64_ADR_PREL_PG_HI21: 1306 return R_PAGE_PC; 1307 case R_AARCH64_LD64_GOT_LO12_NC: 1308 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1309 return R_GOT; 1310 case R_AARCH64_ADR_GOT_PAGE: 1311 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1312 return R_GOT_PAGE_PC; 1313 } 1314 } 1315 1316 RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 1317 RelExpr Expr) const { 1318 if (Expr == R_RELAX_TLS_GD_TO_IE) { 1319 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21) 1320 return R_RELAX_TLS_GD_TO_IE_PAGE_PC; 1321 return R_RELAX_TLS_GD_TO_IE_ABS; 1322 } 1323 return Expr; 1324 } 1325 1326 bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { 1327 switch (Type) { 1328 default: 1329 return false; 1330 case R_AARCH64_ADD_ABS_LO12_NC: 1331 case R_AARCH64_LD64_GOT_LO12_NC: 1332 case R_AARCH64_LDST128_ABS_LO12_NC: 1333 case R_AARCH64_LDST16_ABS_LO12_NC: 1334 case R_AARCH64_LDST32_ABS_LO12_NC: 1335 case R_AARCH64_LDST64_ABS_LO12_NC: 1336 case R_AARCH64_LDST8_ABS_LO12_NC: 1337 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1338 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1339 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1340 return true; 1341 } 1342 } 1343 1344 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1345 return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 || 1346 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; 1347 } 1348 1349 bool AArch64TargetInfo::isPicRel(uint32_t Type) const { 1350 return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64; 1351 } 1352 1353 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1354 write64le(Buf, In<ELF64LE>::Plt->getVA()); 1355 } 1356 1357 // Page(Expr) is the page address of the expression Expr, defined 1358 // as (Expr & ~0xFFF). (This applies even if the machine page size 1359 // supported by the platform has a different value.) 1360 uint64_t getAArch64Page(uint64_t Expr) { 1361 return Expr & (~static_cast<uint64_t>(0xFFF)); 1362 } 1363 1364 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const { 1365 const uint8_t PltData[] = { 1366 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 1367 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 1368 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 1369 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 1370 0x20, 0x02, 0x1f, 0xd6, // br x17 1371 0x1f, 0x20, 0x03, 0xd5, // nop 1372 0x1f, 0x20, 0x03, 0xd5, // nop 1373 0x1f, 0x20, 0x03, 0xd5 // nop 1374 }; 1375 memcpy(Buf, PltData, sizeof(PltData)); 1376 1377 uint64_t Got = In<ELF64LE>::GotPlt->getVA(); 1378 uint64_t Plt = In<ELF64LE>::Plt->getVA(); 1379 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 1380 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4)); 1381 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16); 1382 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16); 1383 } 1384 1385 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1386 uint64_t PltEntryAddr, int32_t Index, 1387 unsigned RelOff) const { 1388 const uint8_t Inst[] = { 1389 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 1390 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 1391 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n])) 1392 0x20, 0x02, 0x1f, 0xd6 // br x17 1393 }; 1394 memcpy(Buf, Inst, sizeof(Inst)); 1395 1396 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21, 1397 getAArch64Page(GotEntryAddr) - getAArch64Page(PltEntryAddr)); 1398 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotEntryAddr); 1399 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotEntryAddr); 1400 } 1401 1402 static void write32AArch64Addr(uint8_t *L, uint64_t Imm) { 1403 uint32_t ImmLo = (Imm & 0x3) << 29; 1404 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3; 1405 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3); 1406 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi); 1407 } 1408 1409 // Return the bits [Start, End] from Val shifted Start bits. 1410 // For instance, getBits(0xF0, 4, 8) returns 0xF. 1411 static uint64_t getBits(uint64_t Val, int Start, int End) { 1412 uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1; 1413 return (Val >> Start) & Mask; 1414 } 1415 1416 // Update the immediate field in a AARCH64 ldr, str, and add instruction. 1417 static void or32AArch64Imm(uint8_t *L, uint64_t Imm) { 1418 or32le(L, (Imm & 0xFFF) << 10); 1419 } 1420 1421 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1422 uint64_t Val) const { 1423 switch (Type) { 1424 case R_AARCH64_ABS16: 1425 case R_AARCH64_PREL16: 1426 checkIntUInt<16>(Loc, Val, Type); 1427 write16le(Loc, Val); 1428 break; 1429 case R_AARCH64_ABS32: 1430 case R_AARCH64_PREL32: 1431 checkIntUInt<32>(Loc, Val, Type); 1432 write32le(Loc, Val); 1433 break; 1434 case R_AARCH64_ABS64: 1435 case R_AARCH64_GLOB_DAT: 1436 case R_AARCH64_PREL64: 1437 write64le(Loc, Val); 1438 break; 1439 case R_AARCH64_ADD_ABS_LO12_NC: 1440 or32AArch64Imm(Loc, Val); 1441 break; 1442 case R_AARCH64_ADR_GOT_PAGE: 1443 case R_AARCH64_ADR_PREL_PG_HI21: 1444 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1445 case R_AARCH64_TLSDESC_ADR_PAGE21: 1446 checkInt<33>(Loc, Val, Type); 1447 write32AArch64Addr(Loc, Val >> 12); 1448 break; 1449 case R_AARCH64_ADR_PREL_LO21: 1450 checkInt<21>(Loc, Val, Type); 1451 write32AArch64Addr(Loc, Val); 1452 break; 1453 case R_AARCH64_CALL26: 1454 case R_AARCH64_JUMP26: 1455 checkInt<28>(Loc, Val, Type); 1456 or32le(Loc, (Val & 0x0FFFFFFC) >> 2); 1457 break; 1458 case R_AARCH64_CONDBR19: 1459 checkInt<21>(Loc, Val, Type); 1460 or32le(Loc, (Val & 0x1FFFFC) << 3); 1461 break; 1462 case R_AARCH64_LD64_GOT_LO12_NC: 1463 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1464 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1465 checkAlignment<8>(Loc, Val, Type); 1466 or32le(Loc, (Val & 0xFF8) << 7); 1467 break; 1468 case R_AARCH64_LDST8_ABS_LO12_NC: 1469 or32AArch64Imm(Loc, getBits(Val, 0, 11)); 1470 break; 1471 case R_AARCH64_LDST16_ABS_LO12_NC: 1472 or32AArch64Imm(Loc, getBits(Val, 1, 11)); 1473 break; 1474 case R_AARCH64_LDST32_ABS_LO12_NC: 1475 or32AArch64Imm(Loc, getBits(Val, 2, 11)); 1476 break; 1477 case R_AARCH64_LDST64_ABS_LO12_NC: 1478 or32AArch64Imm(Loc, getBits(Val, 3, 11)); 1479 break; 1480 case R_AARCH64_LDST128_ABS_LO12_NC: 1481 or32AArch64Imm(Loc, getBits(Val, 4, 11)); 1482 break; 1483 case R_AARCH64_MOVW_UABS_G0_NC: 1484 or32le(Loc, (Val & 0xFFFF) << 5); 1485 break; 1486 case R_AARCH64_MOVW_UABS_G1_NC: 1487 or32le(Loc, (Val & 0xFFFF0000) >> 11); 1488 break; 1489 case R_AARCH64_MOVW_UABS_G2_NC: 1490 or32le(Loc, (Val & 0xFFFF00000000) >> 27); 1491 break; 1492 case R_AARCH64_MOVW_UABS_G3: 1493 or32le(Loc, (Val & 0xFFFF000000000000) >> 43); 1494 break; 1495 case R_AARCH64_TSTBR14: 1496 checkInt<16>(Loc, Val, Type); 1497 or32le(Loc, (Val & 0xFFFC) << 3); 1498 break; 1499 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1500 checkInt<24>(Loc, Val, Type); 1501 or32AArch64Imm(Loc, Val >> 12); 1502 break; 1503 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1504 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1505 or32AArch64Imm(Loc, Val); 1506 break; 1507 default: 1508 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1509 } 1510 } 1511 1512 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 1513 uint64_t Val) const { 1514 // TLSDESC Global-Dynamic relocation are in the form: 1515 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1516 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1517 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1518 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1519 // blr x1 1520 // And it can optimized to: 1521 // movz x0, #0x0, lsl #16 1522 // movk x0, #0x10 1523 // nop 1524 // nop 1525 checkUInt<32>(Loc, Val, Type); 1526 1527 switch (Type) { 1528 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1529 case R_AARCH64_TLSDESC_CALL: 1530 write32le(Loc, 0xd503201f); // nop 1531 return; 1532 case R_AARCH64_TLSDESC_ADR_PAGE21: 1533 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz 1534 return; 1535 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1536 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk 1537 return; 1538 default: 1539 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1540 } 1541 } 1542 1543 void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 1544 uint64_t Val) const { 1545 // TLSDESC Global-Dynamic relocation are in the form: 1546 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1547 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1548 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1549 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1550 // blr x1 1551 // And it can optimized to: 1552 // adrp x0, :gottprel:v 1553 // ldr x0, [x0, :gottprel_lo12:v] 1554 // nop 1555 // nop 1556 1557 switch (Type) { 1558 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1559 case R_AARCH64_TLSDESC_CALL: 1560 write32le(Loc, 0xd503201f); // nop 1561 break; 1562 case R_AARCH64_TLSDESC_ADR_PAGE21: 1563 write32le(Loc, 0x90000000); // adrp 1564 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val); 1565 break; 1566 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1567 write32le(Loc, 0xf9400000); // ldr 1568 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val); 1569 break; 1570 default: 1571 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1572 } 1573 } 1574 1575 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 1576 uint64_t Val) const { 1577 checkUInt<32>(Loc, Val, Type); 1578 1579 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) { 1580 // Generate MOVZ. 1581 uint32_t RegNo = read32le(Loc) & 0x1f; 1582 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5)); 1583 return; 1584 } 1585 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) { 1586 // Generate MOVK. 1587 uint32_t RegNo = read32le(Loc) & 0x1f; 1588 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5)); 1589 return; 1590 } 1591 llvm_unreachable("invalid relocation for TLS IE to LE relaxation"); 1592 } 1593 1594 AMDGPUTargetInfo::AMDGPUTargetInfo() { 1595 RelativeRel = R_AMDGPU_REL64; 1596 GotRel = R_AMDGPU_ABS64; 1597 GotEntrySize = 8; 1598 } 1599 1600 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1601 uint64_t Val) const { 1602 switch (Type) { 1603 case R_AMDGPU_ABS32: 1604 case R_AMDGPU_GOTPCREL: 1605 case R_AMDGPU_GOTPCREL32_LO: 1606 case R_AMDGPU_REL32: 1607 case R_AMDGPU_REL32_LO: 1608 write32le(Loc, Val); 1609 break; 1610 case R_AMDGPU_ABS64: 1611 write64le(Loc, Val); 1612 break; 1613 case R_AMDGPU_GOTPCREL32_HI: 1614 case R_AMDGPU_REL32_HI: 1615 write32le(Loc, Val >> 32); 1616 break; 1617 default: 1618 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1619 } 1620 } 1621 1622 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1623 switch (Type) { 1624 case R_AMDGPU_ABS32: 1625 case R_AMDGPU_ABS64: 1626 return R_ABS; 1627 case R_AMDGPU_REL32: 1628 case R_AMDGPU_REL32_LO: 1629 case R_AMDGPU_REL32_HI: 1630 return R_PC; 1631 case R_AMDGPU_GOTPCREL: 1632 case R_AMDGPU_GOTPCREL32_LO: 1633 case R_AMDGPU_GOTPCREL32_HI: 1634 return R_GOT_PC; 1635 default: 1636 error(toString(S.File) + ": unknown relocation type: " + toString(Type)); 1637 return R_HINT; 1638 } 1639 } 1640 1641 ARMTargetInfo::ARMTargetInfo() { 1642 CopyRel = R_ARM_COPY; 1643 RelativeRel = R_ARM_RELATIVE; 1644 IRelativeRel = R_ARM_IRELATIVE; 1645 GotRel = R_ARM_GLOB_DAT; 1646 PltRel = R_ARM_JUMP_SLOT; 1647 TlsGotRel = R_ARM_TLS_TPOFF32; 1648 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32; 1649 TlsOffsetRel = R_ARM_TLS_DTPOFF32; 1650 GotEntrySize = 4; 1651 GotPltEntrySize = 4; 1652 PltEntrySize = 16; 1653 PltHeaderSize = 20; 1654 // ARM uses Variant 1 TLS 1655 TcbSize = 8; 1656 NeedsThunks = true; 1657 } 1658 1659 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1660 switch (Type) { 1661 default: 1662 return R_ABS; 1663 case R_ARM_THM_JUMP11: 1664 return R_PC; 1665 case R_ARM_CALL: 1666 case R_ARM_JUMP24: 1667 case R_ARM_PC24: 1668 case R_ARM_PLT32: 1669 case R_ARM_PREL31: 1670 case R_ARM_THM_JUMP19: 1671 case R_ARM_THM_JUMP24: 1672 case R_ARM_THM_CALL: 1673 return R_PLT_PC; 1674 case R_ARM_GOTOFF32: 1675 // (S + A) - GOT_ORG 1676 return R_GOTREL; 1677 case R_ARM_GOT_BREL: 1678 // GOT(S) + A - GOT_ORG 1679 return R_GOT_OFF; 1680 case R_ARM_GOT_PREL: 1681 case R_ARM_TLS_IE32: 1682 // GOT(S) + A - P 1683 return R_GOT_PC; 1684 case R_ARM_TARGET1: 1685 return Config->Target1Rel ? R_PC : R_ABS; 1686 case R_ARM_TARGET2: 1687 if (Config->Target2 == Target2Policy::Rel) 1688 return R_PC; 1689 if (Config->Target2 == Target2Policy::Abs) 1690 return R_ABS; 1691 return R_GOT_PC; 1692 case R_ARM_TLS_GD32: 1693 return R_TLSGD_PC; 1694 case R_ARM_TLS_LDM32: 1695 return R_TLSLD_PC; 1696 case R_ARM_BASE_PREL: 1697 // B(S) + A - P 1698 // FIXME: currently B(S) assumed to be .got, this may not hold for all 1699 // platforms. 1700 return R_GOTONLY_PC; 1701 case R_ARM_MOVW_PREL_NC: 1702 case R_ARM_MOVT_PREL: 1703 case R_ARM_REL32: 1704 case R_ARM_THM_MOVW_PREL_NC: 1705 case R_ARM_THM_MOVT_PREL: 1706 return R_PC; 1707 case R_ARM_NONE: 1708 return R_HINT; 1709 case R_ARM_TLS_LE32: 1710 return R_TLS; 1711 } 1712 } 1713 1714 bool ARMTargetInfo::isPicRel(uint32_t Type) const { 1715 return (Type == R_ARM_TARGET1 && !Config->Target1Rel) || 1716 (Type == R_ARM_ABS32); 1717 } 1718 1719 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const { 1720 if (Type == R_ARM_TARGET1 && !Config->Target1Rel) 1721 return R_ARM_ABS32; 1722 if (Type == R_ARM_ABS32) 1723 return Type; 1724 // Keep it going with a dummy value so that we can find more reloc errors. 1725 return R_ARM_ABS32; 1726 } 1727 1728 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1729 write32le(Buf, In<ELF32LE>::Plt->getVA()); 1730 } 1731 1732 void ARMTargetInfo::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const { 1733 // An ARM entry is the address of the ifunc resolver function. 1734 write32le(Buf, S.getVA<ELF32LE>()); 1735 } 1736 1737 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const { 1738 const uint8_t PltData[] = { 1739 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]! 1740 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2 1741 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr 1742 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8] 1743 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8 1744 }; 1745 memcpy(Buf, PltData, sizeof(PltData)); 1746 uint64_t GotPlt = In<ELF32LE>::GotPlt->getVA(); 1747 uint64_t L1 = In<ELF32LE>::Plt->getVA() + 8; 1748 write32le(Buf + 16, GotPlt - L1 - 8); 1749 } 1750 1751 void ARMTargetInfo::addPltHeaderSymbols(InputSectionData *ISD) const { 1752 auto *IS = cast<InputSection<ELF32LE>>(ISD); 1753 addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS); 1754 addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS); 1755 } 1756 1757 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1758 uint64_t PltEntryAddr, int32_t Index, 1759 unsigned RelOff) const { 1760 // FIXME: Using simple code sequence with simple relocations. 1761 // There is a more optimal sequence but it requires support for the group 1762 // relocations. See ELF for the ARM Architecture Appendix A.3 1763 const uint8_t PltData[] = { 1764 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2 1765 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc 1766 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip] 1767 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8 1768 }; 1769 memcpy(Buf, PltData, sizeof(PltData)); 1770 uint64_t L1 = PltEntryAddr + 4; 1771 write32le(Buf + 12, GotEntryAddr - L1 - 8); 1772 } 1773 1774 void ARMTargetInfo::addPltSymbols(InputSectionData *ISD, uint64_t Off) const { 1775 auto *IS = cast<InputSection<ELF32LE>>(ISD); 1776 addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS); 1777 addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS); 1778 } 1779 1780 bool ARMTargetInfo::needsThunk(RelExpr Expr, uint32_t RelocType, 1781 const InputFile *File, 1782 const SymbolBody &S) const { 1783 // If S is an undefined weak symbol in an executable we don't need a Thunk. 1784 // In a DSO calls to undefined symbols, including weak ones get PLT entries 1785 // which may need a thunk. 1786 if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak() && 1787 !Config->Shared) 1788 return false; 1789 // A state change from ARM to Thumb and vice versa must go through an 1790 // interworking thunk if the relocation type is not R_ARM_CALL or 1791 // R_ARM_THM_CALL. 1792 switch (RelocType) { 1793 case R_ARM_PC24: 1794 case R_ARM_PLT32: 1795 case R_ARM_JUMP24: 1796 // Source is ARM, all PLT entries are ARM so no interworking required. 1797 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb). 1798 if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1)) 1799 return true; 1800 break; 1801 case R_ARM_THM_JUMP19: 1802 case R_ARM_THM_JUMP24: 1803 // Source is Thumb, all PLT entries are ARM so interworking is required. 1804 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM). 1805 if (Expr == R_PLT_PC || ((S.getVA<ELF32LE>() & 1) == 0)) 1806 return true; 1807 break; 1808 } 1809 return false; 1810 } 1811 1812 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1813 uint64_t Val) const { 1814 switch (Type) { 1815 case R_ARM_ABS32: 1816 case R_ARM_BASE_PREL: 1817 case R_ARM_GLOB_DAT: 1818 case R_ARM_GOTOFF32: 1819 case R_ARM_GOT_BREL: 1820 case R_ARM_GOT_PREL: 1821 case R_ARM_REL32: 1822 case R_ARM_RELATIVE: 1823 case R_ARM_TARGET1: 1824 case R_ARM_TARGET2: 1825 case R_ARM_TLS_GD32: 1826 case R_ARM_TLS_IE32: 1827 case R_ARM_TLS_LDM32: 1828 case R_ARM_TLS_LDO32: 1829 case R_ARM_TLS_LE32: 1830 case R_ARM_TLS_TPOFF32: 1831 write32le(Loc, Val); 1832 break; 1833 case R_ARM_TLS_DTPMOD32: 1834 write32le(Loc, 1); 1835 break; 1836 case R_ARM_PREL31: 1837 checkInt<31>(Loc, Val, Type); 1838 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000)); 1839 break; 1840 case R_ARM_CALL: 1841 // R_ARM_CALL is used for BL and BLX instructions, depending on the 1842 // value of bit 0 of Val, we must select a BL or BLX instruction 1843 if (Val & 1) { 1844 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX. 1845 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' 1846 checkInt<26>(Loc, Val, Type); 1847 write32le(Loc, 0xfa000000 | // opcode 1848 ((Val & 2) << 23) | // H 1849 ((Val >> 2) & 0x00ffffff)); // imm24 1850 break; 1851 } 1852 if ((read32le(Loc) & 0xfe000000) == 0xfa000000) 1853 // BLX (always unconditional) instruction to an ARM Target, select an 1854 // unconditional BL. 1855 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff)); 1856 // fall through as BL encoding is shared with B 1857 case R_ARM_JUMP24: 1858 case R_ARM_PC24: 1859 case R_ARM_PLT32: 1860 checkInt<26>(Loc, Val, Type); 1861 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff)); 1862 break; 1863 case R_ARM_THM_JUMP11: 1864 checkInt<12>(Loc, Val, Type); 1865 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff)); 1866 break; 1867 case R_ARM_THM_JUMP19: 1868 // Encoding T3: Val = S:J2:J1:imm6:imm11:0 1869 checkInt<21>(Loc, Val, Type); 1870 write16le(Loc, 1871 (read16le(Loc) & 0xfbc0) | // opcode cond 1872 ((Val >> 10) & 0x0400) | // S 1873 ((Val >> 12) & 0x003f)); // imm6 1874 write16le(Loc + 2, 1875 0x8000 | // opcode 1876 ((Val >> 8) & 0x0800) | // J2 1877 ((Val >> 5) & 0x2000) | // J1 1878 ((Val >> 1) & 0x07ff)); // imm11 1879 break; 1880 case R_ARM_THM_CALL: 1881 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the 1882 // value of bit 0 of Val, we must select a BL or BLX instruction 1883 if ((Val & 1) == 0) { 1884 // Ensure BLX destination is 4-byte aligned. As BLX instruction may 1885 // only be two byte aligned. This must be done before overflow check 1886 Val = alignTo(Val, 4); 1887 } 1888 // Bit 12 is 0 for BLX, 1 for BL 1889 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12); 1890 // Fall through as rest of encoding is the same as B.W 1891 case R_ARM_THM_JUMP24: 1892 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 1893 // FIXME: Use of I1 and I2 require v6T2ops 1894 checkInt<25>(Loc, Val, Type); 1895 write16le(Loc, 1896 0xf000 | // opcode 1897 ((Val >> 14) & 0x0400) | // S 1898 ((Val >> 12) & 0x03ff)); // imm10 1899 write16le(Loc + 2, 1900 (read16le(Loc + 2) & 0xd000) | // opcode 1901 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1 1902 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2 1903 ((Val >> 1) & 0x07ff)); // imm11 1904 break; 1905 case R_ARM_MOVW_ABS_NC: 1906 case R_ARM_MOVW_PREL_NC: 1907 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) | 1908 (Val & 0x0fff)); 1909 break; 1910 case R_ARM_MOVT_ABS: 1911 case R_ARM_MOVT_PREL: 1912 checkInt<32>(Loc, Val, Type); 1913 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | 1914 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff)); 1915 break; 1916 case R_ARM_THM_MOVT_ABS: 1917 case R_ARM_THM_MOVT_PREL: 1918 // Encoding T1: A = imm4:i:imm3:imm8 1919 checkInt<32>(Loc, Val, Type); 1920 write16le(Loc, 1921 0xf2c0 | // opcode 1922 ((Val >> 17) & 0x0400) | // i 1923 ((Val >> 28) & 0x000f)); // imm4 1924 write16le(Loc + 2, 1925 (read16le(Loc + 2) & 0x8f00) | // opcode 1926 ((Val >> 12) & 0x7000) | // imm3 1927 ((Val >> 16) & 0x00ff)); // imm8 1928 break; 1929 case R_ARM_THM_MOVW_ABS_NC: 1930 case R_ARM_THM_MOVW_PREL_NC: 1931 // Encoding T3: A = imm4:i:imm3:imm8 1932 write16le(Loc, 1933 0xf240 | // opcode 1934 ((Val >> 1) & 0x0400) | // i 1935 ((Val >> 12) & 0x000f)); // imm4 1936 write16le(Loc + 2, 1937 (read16le(Loc + 2) & 0x8f00) | // opcode 1938 ((Val << 4) & 0x7000) | // imm3 1939 (Val & 0x00ff)); // imm8 1940 break; 1941 default: 1942 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 1943 } 1944 } 1945 1946 uint64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf, 1947 uint32_t Type) const { 1948 switch (Type) { 1949 default: 1950 return 0; 1951 case R_ARM_ABS32: 1952 case R_ARM_BASE_PREL: 1953 case R_ARM_GOTOFF32: 1954 case R_ARM_GOT_BREL: 1955 case R_ARM_GOT_PREL: 1956 case R_ARM_REL32: 1957 case R_ARM_TARGET1: 1958 case R_ARM_TARGET2: 1959 case R_ARM_TLS_GD32: 1960 case R_ARM_TLS_LDM32: 1961 case R_ARM_TLS_LDO32: 1962 case R_ARM_TLS_IE32: 1963 case R_ARM_TLS_LE32: 1964 return SignExtend64<32>(read32le(Buf)); 1965 case R_ARM_PREL31: 1966 return SignExtend64<31>(read32le(Buf)); 1967 case R_ARM_CALL: 1968 case R_ARM_JUMP24: 1969 case R_ARM_PC24: 1970 case R_ARM_PLT32: 1971 return SignExtend64<26>(read32le(Buf) << 2); 1972 case R_ARM_THM_JUMP11: 1973 return SignExtend64<12>(read16le(Buf) << 1); 1974 case R_ARM_THM_JUMP19: { 1975 // Encoding T3: A = S:J2:J1:imm10:imm6:0 1976 uint16_t Hi = read16le(Buf); 1977 uint16_t Lo = read16le(Buf + 2); 1978 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S 1979 ((Lo & 0x0800) << 8) | // J2 1980 ((Lo & 0x2000) << 5) | // J1 1981 ((Hi & 0x003f) << 12) | // imm6 1982 ((Lo & 0x07ff) << 1)); // imm11:0 1983 } 1984 case R_ARM_THM_CALL: 1985 case R_ARM_THM_JUMP24: { 1986 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 1987 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) 1988 // FIXME: I1 and I2 require v6T2ops 1989 uint16_t Hi = read16le(Buf); 1990 uint16_t Lo = read16le(Buf + 2); 1991 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S 1992 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1 1993 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2 1994 ((Hi & 0x003ff) << 12) | // imm0 1995 ((Lo & 0x007ff) << 1)); // imm11:0 1996 } 1997 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and 1998 // MOVT is in the range -32768 <= A < 32768 1999 case R_ARM_MOVW_ABS_NC: 2000 case R_ARM_MOVT_ABS: 2001 case R_ARM_MOVW_PREL_NC: 2002 case R_ARM_MOVT_PREL: { 2003 uint64_t Val = read32le(Buf) & 0x000f0fff; 2004 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff)); 2005 } 2006 case R_ARM_THM_MOVW_ABS_NC: 2007 case R_ARM_THM_MOVT_ABS: 2008 case R_ARM_THM_MOVW_PREL_NC: 2009 case R_ARM_THM_MOVT_PREL: { 2010 // Encoding T3: A = imm4:i:imm3:imm8 2011 uint16_t Hi = read16le(Buf); 2012 uint16_t Lo = read16le(Buf + 2); 2013 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4 2014 ((Hi & 0x0400) << 1) | // i 2015 ((Lo & 0x7000) >> 4) | // imm3 2016 (Lo & 0x00ff)); // imm8 2017 } 2018 } 2019 } 2020 2021 bool ARMTargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 2022 return Type == R_ARM_TLS_LDO32 || Type == R_ARM_TLS_LDM32; 2023 } 2024 2025 bool ARMTargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 2026 return Type == R_ARM_TLS_GD32; 2027 } 2028 2029 bool ARMTargetInfo::isTlsInitialExecRel(uint32_t Type) const { 2030 return Type == R_ARM_TLS_IE32; 2031 } 2032 2033 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() { 2034 GotPltHeaderEntriesNum = 2; 2035 DefaultMaxPageSize = 65536; 2036 GotEntrySize = sizeof(typename ELFT::uint); 2037 GotPltEntrySize = sizeof(typename ELFT::uint); 2038 PltEntrySize = 16; 2039 PltHeaderSize = 32; 2040 CopyRel = R_MIPS_COPY; 2041 PltRel = R_MIPS_JUMP_SLOT; 2042 NeedsThunks = true; 2043 if (ELFT::Is64Bits) { 2044 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 2045 TlsGotRel = R_MIPS_TLS_TPREL64; 2046 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 2047 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 2048 } else { 2049 RelativeRel = R_MIPS_REL32; 2050 TlsGotRel = R_MIPS_TLS_TPREL32; 2051 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 2052 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 2053 } 2054 } 2055 2056 template <class ELFT> 2057 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type, 2058 const SymbolBody &S) const { 2059 // See comment in the calculateMipsRelChain. 2060 if (ELFT::Is64Bits || Config->MipsN32Abi) 2061 Type &= 0xff; 2062 switch (Type) { 2063 default: 2064 return R_ABS; 2065 case R_MIPS_JALR: 2066 return R_HINT; 2067 case R_MIPS_GPREL16: 2068 case R_MIPS_GPREL32: 2069 return R_MIPS_GOTREL; 2070 case R_MIPS_26: 2071 return R_PLT; 2072 case R_MIPS_HI16: 2073 case R_MIPS_LO16: 2074 case R_MIPS_GOT_OFST: 2075 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 2076 // offset between start of function and 'gp' value which by default 2077 // equal to the start of .got section. In that case we consider these 2078 // relocations as relative. 2079 if (&S == ElfSym<ELFT>::MipsGpDisp) 2080 return R_PC; 2081 return R_ABS; 2082 case R_MIPS_PC32: 2083 case R_MIPS_PC16: 2084 case R_MIPS_PC19_S2: 2085 case R_MIPS_PC21_S2: 2086 case R_MIPS_PC26_S2: 2087 case R_MIPS_PCHI16: 2088 case R_MIPS_PCLO16: 2089 return R_PC; 2090 case R_MIPS_GOT16: 2091 if (S.isLocal()) 2092 return R_MIPS_GOT_LOCAL_PAGE; 2093 // fallthrough 2094 case R_MIPS_CALL16: 2095 case R_MIPS_GOT_DISP: 2096 case R_MIPS_TLS_GOTTPREL: 2097 return R_MIPS_GOT_OFF; 2098 case R_MIPS_CALL_HI16: 2099 case R_MIPS_CALL_LO16: 2100 case R_MIPS_GOT_HI16: 2101 case R_MIPS_GOT_LO16: 2102 return R_MIPS_GOT_OFF32; 2103 case R_MIPS_GOT_PAGE: 2104 return R_MIPS_GOT_LOCAL_PAGE; 2105 case R_MIPS_TLS_GD: 2106 return R_MIPS_TLSGD; 2107 case R_MIPS_TLS_LDM: 2108 return R_MIPS_TLSLD; 2109 } 2110 } 2111 2112 template <class ELFT> bool MipsTargetInfo<ELFT>::isPicRel(uint32_t Type) const { 2113 return Type == R_MIPS_32 || Type == R_MIPS_64; 2114 } 2115 2116 template <class ELFT> 2117 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const { 2118 return RelativeRel; 2119 } 2120 2121 template <class ELFT> 2122 bool MipsTargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 2123 return Type == R_MIPS_TLS_LDM; 2124 } 2125 2126 template <class ELFT> 2127 bool MipsTargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 2128 return Type == R_MIPS_TLS_GD; 2129 } 2130 2131 template <class ELFT> 2132 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 2133 write32<ELFT::TargetEndianness>(Buf, In<ELFT>::Plt->getVA()); 2134 } 2135 2136 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2137 static int64_t getPcRelocAddend(const uint8_t *Loc) { 2138 uint32_t Instr = read32<E>(Loc); 2139 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2140 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT); 2141 } 2142 2143 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 2144 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) { 2145 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 2146 uint32_t Instr = read32<E>(Loc); 2147 if (SHIFT > 0) 2148 checkAlignment<(1 << SHIFT)>(Loc, V, Type); 2149 checkInt<BSIZE + SHIFT>(Loc, V, Type); 2150 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask)); 2151 } 2152 2153 template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) { 2154 uint32_t Instr = read32<E>(Loc); 2155 uint16_t Res = ((V + 0x8000) >> 16) & 0xffff; 2156 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2157 } 2158 2159 template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) { 2160 uint32_t Instr = read32<E>(Loc); 2161 uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff; 2162 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2163 } 2164 2165 template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) { 2166 uint32_t Instr = read32<E>(Loc); 2167 uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff; 2168 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2169 } 2170 2171 template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) { 2172 uint32_t Instr = read32<E>(Loc); 2173 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff)); 2174 } 2175 2176 template <class ELFT> static bool isMipsR6() { 2177 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf); 2178 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH; 2179 return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6; 2180 } 2181 2182 template <class ELFT> 2183 void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 2184 const endianness E = ELFT::TargetEndianness; 2185 if (Config->MipsN32Abi) { 2186 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 2187 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 2188 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 2189 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 2190 } else { 2191 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 2192 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 2193 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 2194 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 2195 } 2196 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 2197 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 2198 write32<E>(Buf + 24, 0x0320f809); // jalr $25 2199 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 2200 uint64_t Got = In<ELFT>::GotPlt->getVA(); 2201 writeMipsHi16<E>(Buf, Got); 2202 writeMipsLo16<E>(Buf + 4, Got); 2203 writeMipsLo16<E>(Buf + 8, Got); 2204 } 2205 2206 template <class ELFT> 2207 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 2208 uint64_t PltEntryAddr, int32_t Index, 2209 unsigned RelOff) const { 2210 const endianness E = ELFT::TargetEndianness; 2211 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 2212 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 2213 // jr $25 2214 write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008); 2215 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 2216 writeMipsHi16<E>(Buf, GotEntryAddr); 2217 writeMipsLo16<E>(Buf + 4, GotEntryAddr); 2218 writeMipsLo16<E>(Buf + 12, GotEntryAddr); 2219 } 2220 2221 template <class ELFT> 2222 bool MipsTargetInfo<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, 2223 const InputFile *File, 2224 const SymbolBody &S) const { 2225 // Any MIPS PIC code function is invoked with its address in register $t9. 2226 // So if we have a branch instruction from non-PIC code to the PIC one 2227 // we cannot make the jump directly and need to create a small stubs 2228 // to save the target function address. 2229 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 2230 if (Type != R_MIPS_26) 2231 return false; 2232 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 2233 if (!F) 2234 return false; 2235 // If current file has PIC code, LA25 stub is not required. 2236 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 2237 return false; 2238 auto *D = dyn_cast<DefinedRegular<ELFT>>(&S); 2239 // LA25 is required if target file has PIC code 2240 // or target symbol is a PIC symbol. 2241 return D && D->isMipsPIC(); 2242 } 2243 2244 template <class ELFT> 2245 uint64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf, 2246 uint32_t Type) const { 2247 const endianness E = ELFT::TargetEndianness; 2248 switch (Type) { 2249 default: 2250 return 0; 2251 case R_MIPS_32: 2252 case R_MIPS_GPREL32: 2253 case R_MIPS_TLS_DTPREL32: 2254 case R_MIPS_TLS_TPREL32: 2255 return read32<E>(Buf); 2256 case R_MIPS_26: 2257 // FIXME (simon): If the relocation target symbol is not a PLT entry 2258 // we should use another expression for calculation: 2259 // ((A << 2) | (P & 0xf0000000)) >> 2 2260 return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2); 2261 case R_MIPS_GPREL16: 2262 case R_MIPS_LO16: 2263 case R_MIPS_PCLO16: 2264 case R_MIPS_TLS_DTPREL_HI16: 2265 case R_MIPS_TLS_DTPREL_LO16: 2266 case R_MIPS_TLS_TPREL_HI16: 2267 case R_MIPS_TLS_TPREL_LO16: 2268 return SignExtend64<16>(read32<E>(Buf)); 2269 case R_MIPS_PC16: 2270 return getPcRelocAddend<E, 16, 2>(Buf); 2271 case R_MIPS_PC19_S2: 2272 return getPcRelocAddend<E, 19, 2>(Buf); 2273 case R_MIPS_PC21_S2: 2274 return getPcRelocAddend<E, 21, 2>(Buf); 2275 case R_MIPS_PC26_S2: 2276 return getPcRelocAddend<E, 26, 2>(Buf); 2277 case R_MIPS_PC32: 2278 return getPcRelocAddend<E, 32, 0>(Buf); 2279 } 2280 } 2281 2282 static std::pair<uint32_t, uint64_t> 2283 calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) { 2284 // MIPS N64 ABI packs multiple relocations into the single relocation 2285 // record. In general, all up to three relocations can have arbitrary 2286 // types. In fact, Clang and GCC uses only a few combinations. For now, 2287 // we support two of them. That is allow to pass at least all LLVM 2288 // test suite cases. 2289 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 2290 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 2291 // The first relocation is a 'real' relocation which is calculated 2292 // using the corresponding symbol's value. The second and the third 2293 // relocations used to modify result of the first one: extend it to 2294 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 2295 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 2296 uint32_t Type2 = (Type >> 8) & 0xff; 2297 uint32_t Type3 = (Type >> 16) & 0xff; 2298 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 2299 return std::make_pair(Type, Val); 2300 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 2301 return std::make_pair(Type2, Val); 2302 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 2303 return std::make_pair(Type3, -Val); 2304 error(getErrorLocation(Loc) + "unsupported relocations combination " + 2305 Twine(Type)); 2306 return std::make_pair(Type & 0xff, Val); 2307 } 2308 2309 template <class ELFT> 2310 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 2311 uint64_t Val) const { 2312 const endianness E = ELFT::TargetEndianness; 2313 // Thread pointer and DRP offsets from the start of TLS data area. 2314 // https://www.linux-mips.org/wiki/NPTL 2315 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 2316 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64) 2317 Val -= 0x8000; 2318 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 2319 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64) 2320 Val -= 0x7000; 2321 if (ELFT::Is64Bits || Config->MipsN32Abi) 2322 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 2323 switch (Type) { 2324 case R_MIPS_32: 2325 case R_MIPS_GPREL32: 2326 case R_MIPS_TLS_DTPREL32: 2327 case R_MIPS_TLS_TPREL32: 2328 write32<E>(Loc, Val); 2329 break; 2330 case R_MIPS_64: 2331 case R_MIPS_TLS_DTPREL64: 2332 case R_MIPS_TLS_TPREL64: 2333 write64<E>(Loc, Val); 2334 break; 2335 case R_MIPS_26: 2336 write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff)); 2337 break; 2338 case R_MIPS_GOT_DISP: 2339 case R_MIPS_GOT_PAGE: 2340 case R_MIPS_GOT16: 2341 case R_MIPS_GPREL16: 2342 case R_MIPS_TLS_GD: 2343 case R_MIPS_TLS_LDM: 2344 checkInt<16>(Loc, Val, Type); 2345 // fallthrough 2346 case R_MIPS_CALL16: 2347 case R_MIPS_CALL_LO16: 2348 case R_MIPS_GOT_LO16: 2349 case R_MIPS_GOT_OFST: 2350 case R_MIPS_LO16: 2351 case R_MIPS_PCLO16: 2352 case R_MIPS_TLS_DTPREL_LO16: 2353 case R_MIPS_TLS_GOTTPREL: 2354 case R_MIPS_TLS_TPREL_LO16: 2355 writeMipsLo16<E>(Loc, Val); 2356 break; 2357 case R_MIPS_CALL_HI16: 2358 case R_MIPS_GOT_HI16: 2359 case R_MIPS_HI16: 2360 case R_MIPS_PCHI16: 2361 case R_MIPS_TLS_DTPREL_HI16: 2362 case R_MIPS_TLS_TPREL_HI16: 2363 writeMipsHi16<E>(Loc, Val); 2364 break; 2365 case R_MIPS_HIGHER: 2366 writeMipsHigher<E>(Loc, Val); 2367 break; 2368 case R_MIPS_HIGHEST: 2369 writeMipsHighest<E>(Loc, Val); 2370 break; 2371 case R_MIPS_JALR: 2372 // Ignore this optimization relocation for now 2373 break; 2374 case R_MIPS_PC16: 2375 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val); 2376 break; 2377 case R_MIPS_PC19_S2: 2378 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val); 2379 break; 2380 case R_MIPS_PC21_S2: 2381 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val); 2382 break; 2383 case R_MIPS_PC26_S2: 2384 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val); 2385 break; 2386 case R_MIPS_PC32: 2387 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val); 2388 break; 2389 default: 2390 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 2391 } 2392 } 2393 2394 template <class ELFT> 2395 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const { 2396 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST; 2397 } 2398 } 2399 } 2400