1 //===- Target.cpp ---------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Machine-specific things, such as applying relocations, creation of 11 // GOT or PLT entries, etc., are handled in this file. 12 // 13 // Refer the ELF spec for the single letter variables, S, A or P, used 14 // in this file. 15 // 16 // Some functions defined in this file has "relaxTls" as part of their names. 17 // They do peephole optimization for TLS variables by rewriting instructions. 18 // They are not part of the ABI but optional optimization, so you can skip 19 // them if you are not interested in how TLS variables are optimized. 20 // See the following paper for the details. 21 // 22 // Ulrich Drepper, ELF Handling For Thread-Local Storage 23 // http://www.akkadia.org/drepper/tls.pdf 24 // 25 //===----------------------------------------------------------------------===// 26 27 #include "Target.h" 28 #include "Error.h" 29 #include "InputFiles.h" 30 #include "OutputSections.h" 31 #include "Symbols.h" 32 #include "Thunks.h" 33 34 #include "llvm/ADT/ArrayRef.h" 35 #include "llvm/Object/ELF.h" 36 #include "llvm/Support/Endian.h" 37 #include "llvm/Support/ELF.h" 38 39 using namespace llvm; 40 using namespace llvm::object; 41 using namespace llvm::support::endian; 42 using namespace llvm::ELF; 43 44 namespace lld { 45 namespace elf { 46 47 TargetInfo *Target; 48 49 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); } 50 51 StringRef getRelName(uint32_t Type) { 52 return getELFRelocationTypeName(Config->EMachine, Type); 53 } 54 55 template <unsigned N> static void checkInt(int64_t V, uint32_t Type) { 56 if (!isInt<N>(V)) 57 error("relocation " + getRelName(Type) + " out of range"); 58 } 59 60 template <unsigned N> static void checkUInt(uint64_t V, uint32_t Type) { 61 if (!isUInt<N>(V)) 62 error("relocation " + getRelName(Type) + " out of range"); 63 } 64 65 template <unsigned N> static void checkIntUInt(uint64_t V, uint32_t Type) { 66 if (!isInt<N>(V) && !isUInt<N>(V)) 67 error("relocation " + getRelName(Type) + " out of range"); 68 } 69 70 template <unsigned N> static void checkAlignment(uint64_t V, uint32_t Type) { 71 if ((V & (N - 1)) != 0) 72 error("improper alignment for relocation " + getRelName(Type)); 73 } 74 75 static void errorDynRel(uint32_t Type) { 76 error("relocation " + getRelName(Type) + 77 " cannot be used against shared object; recompile with -fPIC."); 78 } 79 80 namespace { 81 class X86TargetInfo final : public TargetInfo { 82 public: 83 X86TargetInfo(); 84 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 85 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 86 void writeGotPltHeader(uint8_t *Buf) const override; 87 uint32_t getDynRel(uint32_t Type) const override; 88 bool isTlsLocalDynamicRel(uint32_t Type) const override; 89 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 90 bool isTlsInitialExecRel(uint32_t Type) const override; 91 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 92 void writePltHeader(uint8_t *Buf) const override; 93 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 94 int32_t Index, unsigned RelOff) const override; 95 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 96 97 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 98 RelExpr Expr) const override; 99 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 100 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 101 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 102 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 103 }; 104 105 template <class ELFT> class X86_64TargetInfo final : public TargetInfo { 106 public: 107 X86_64TargetInfo(); 108 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 109 uint32_t getDynRel(uint32_t Type) const override; 110 bool isTlsLocalDynamicRel(uint32_t Type) const override; 111 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 112 bool isTlsInitialExecRel(uint32_t Type) const override; 113 void writeGotPltHeader(uint8_t *Buf) const override; 114 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 115 void writePltHeader(uint8_t *Buf) const override; 116 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 117 int32_t Index, unsigned RelOff) const override; 118 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 119 120 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 121 RelExpr Expr) const override; 122 void relaxGot(uint8_t *Loc, uint64_t Val) const override; 123 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 124 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 125 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 126 void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 127 128 private: 129 void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op, 130 uint8_t ModRm) const; 131 }; 132 133 class PPCTargetInfo final : public TargetInfo { 134 public: 135 PPCTargetInfo(); 136 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 137 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 138 }; 139 140 class PPC64TargetInfo final : public TargetInfo { 141 public: 142 PPC64TargetInfo(); 143 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 144 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 145 int32_t Index, unsigned RelOff) const override; 146 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 147 }; 148 149 class AArch64TargetInfo final : public TargetInfo { 150 public: 151 AArch64TargetInfo(); 152 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 153 uint32_t getDynRel(uint32_t Type) const override; 154 bool isTlsInitialExecRel(uint32_t Type) const override; 155 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 156 void writePltHeader(uint8_t *Buf) const override; 157 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 158 int32_t Index, unsigned RelOff) const override; 159 bool usesOnlyLowPageBits(uint32_t Type) const override; 160 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 161 RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 162 RelExpr Expr) const override; 163 void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 164 void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 165 void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 166 }; 167 168 class AMDGPUTargetInfo final : public TargetInfo { 169 public: 170 AMDGPUTargetInfo(); 171 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 172 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 173 }; 174 175 class ARMTargetInfo final : public TargetInfo { 176 public: 177 ARMTargetInfo(); 178 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 179 uint32_t getDynRel(uint32_t Type) const override; 180 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 181 bool isTlsLocalDynamicRel(uint32_t Type) const override; 182 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 183 bool isTlsInitialExecRel(uint32_t Type) const override; 184 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 185 void writePltHeader(uint8_t *Buf) const override; 186 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 187 int32_t Index, unsigned RelOff) const override; 188 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File, 189 const SymbolBody &S) const override; 190 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 191 }; 192 193 template <class ELFT> class MipsTargetInfo final : public TargetInfo { 194 public: 195 MipsTargetInfo(); 196 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override; 197 uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 198 uint32_t getDynRel(uint32_t Type) const override; 199 bool isTlsLocalDynamicRel(uint32_t Type) const override; 200 bool isTlsGlobalDynamicRel(uint32_t Type) const override; 201 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 202 void writePltHeader(uint8_t *Buf) const override; 203 void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr, 204 int32_t Index, unsigned RelOff) const override; 205 RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File, 206 const SymbolBody &S) const override; 207 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 208 bool usesOnlyLowPageBits(uint32_t Type) const override; 209 }; 210 } // anonymous namespace 211 212 TargetInfo *createTarget() { 213 switch (Config->EMachine) { 214 case EM_386: 215 case EM_IAMCU: 216 return new X86TargetInfo(); 217 case EM_AARCH64: 218 return new AArch64TargetInfo(); 219 case EM_AMDGPU: 220 return new AMDGPUTargetInfo(); 221 case EM_ARM: 222 return new ARMTargetInfo(); 223 case EM_MIPS: 224 switch (Config->EKind) { 225 case ELF32LEKind: 226 return new MipsTargetInfo<ELF32LE>(); 227 case ELF32BEKind: 228 return new MipsTargetInfo<ELF32BE>(); 229 case ELF64LEKind: 230 return new MipsTargetInfo<ELF64LE>(); 231 case ELF64BEKind: 232 return new MipsTargetInfo<ELF64BE>(); 233 default: 234 fatal("unsupported MIPS target"); 235 } 236 case EM_PPC: 237 return new PPCTargetInfo(); 238 case EM_PPC64: 239 return new PPC64TargetInfo(); 240 case EM_X86_64: 241 if (Config->EKind == ELF32LEKind) 242 return new X86_64TargetInfo<ELF32LE>(); 243 return new X86_64TargetInfo<ELF64LE>(); 244 } 245 fatal("unknown target machine"); 246 } 247 248 TargetInfo::~TargetInfo() {} 249 250 uint64_t TargetInfo::getImplicitAddend(const uint8_t *Buf, 251 uint32_t Type) const { 252 return 0; 253 } 254 255 bool TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { return false; } 256 257 RelExpr TargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType, 258 const InputFile &File, 259 const SymbolBody &S) const { 260 return Expr; 261 } 262 263 bool TargetInfo::isTlsInitialExecRel(uint32_t Type) const { return false; } 264 265 bool TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { return false; } 266 267 bool TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { return false; } 268 269 RelExpr TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 270 RelExpr Expr) const { 271 return Expr; 272 } 273 274 void TargetInfo::relaxGot(uint8_t *Loc, uint64_t Val) const { 275 llvm_unreachable("Should not have claimed to be relaxable"); 276 } 277 278 void TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 279 uint64_t Val) const { 280 llvm_unreachable("Should not have claimed to be relaxable"); 281 } 282 283 void TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 284 uint64_t Val) const { 285 llvm_unreachable("Should not have claimed to be relaxable"); 286 } 287 288 void TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 289 uint64_t Val) const { 290 llvm_unreachable("Should not have claimed to be relaxable"); 291 } 292 293 void TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 294 uint64_t Val) const { 295 llvm_unreachable("Should not have claimed to be relaxable"); 296 } 297 298 X86TargetInfo::X86TargetInfo() { 299 CopyRel = R_386_COPY; 300 GotRel = R_386_GLOB_DAT; 301 PltRel = R_386_JUMP_SLOT; 302 IRelativeRel = R_386_IRELATIVE; 303 RelativeRel = R_386_RELATIVE; 304 TlsGotRel = R_386_TLS_TPOFF; 305 TlsModuleIndexRel = R_386_TLS_DTPMOD32; 306 TlsOffsetRel = R_386_TLS_DTPOFF32; 307 GotEntrySize = 4; 308 GotPltEntrySize = 4; 309 PltEntrySize = 16; 310 PltHeaderSize = 16; 311 TlsGdRelaxSkip = 2; 312 } 313 314 RelExpr X86TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 315 switch (Type) { 316 default: 317 return R_ABS; 318 case R_386_TLS_GD: 319 return R_TLSGD; 320 case R_386_TLS_LDM: 321 return R_TLSLD; 322 case R_386_PLT32: 323 return R_PLT_PC; 324 case R_386_PC32: 325 return R_PC; 326 case R_386_GOTPC: 327 return R_GOTONLY_PC_FROM_END; 328 case R_386_TLS_IE: 329 return R_GOT; 330 case R_386_GOT32: 331 case R_386_GOT32X: 332 case R_386_TLS_GOTIE: 333 return R_GOT_FROM_END; 334 case R_386_GOTOFF: 335 return R_GOTREL_FROM_END; 336 case R_386_TLS_LE: 337 return R_TLS; 338 case R_386_TLS_LE_32: 339 return R_NEG_TLS; 340 } 341 } 342 343 RelExpr X86TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 344 RelExpr Expr) const { 345 switch (Expr) { 346 default: 347 return Expr; 348 case R_RELAX_TLS_GD_TO_IE: 349 return R_RELAX_TLS_GD_TO_IE_END; 350 case R_RELAX_TLS_GD_TO_LE: 351 return R_RELAX_TLS_GD_TO_LE_NEG; 352 } 353 } 354 355 void X86TargetInfo::writeGotPltHeader(uint8_t *Buf) const { 356 write32le(Buf, Out<ELF32LE>::Dynamic->getVA()); 357 } 358 359 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const { 360 // Entries in .got.plt initially points back to the corresponding 361 // PLT entries with a fixed offset to skip the first instruction. 362 write32le(Buf, S.getPltVA<ELF32LE>() + 6); 363 } 364 365 uint32_t X86TargetInfo::getDynRel(uint32_t Type) const { 366 if (Type == R_386_TLS_LE) 367 return R_386_TLS_TPOFF; 368 if (Type == R_386_TLS_LE_32) 369 return R_386_TLS_TPOFF32; 370 return Type; 371 } 372 373 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 374 return Type == R_386_TLS_GD; 375 } 376 377 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 378 return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM; 379 } 380 381 bool X86TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 382 return Type == R_386_TLS_IE || Type == R_386_TLS_GOTIE; 383 } 384 385 void X86TargetInfo::writePltHeader(uint8_t *Buf) const { 386 // Executable files and shared object files have 387 // separate procedure linkage tables. 388 if (Config->Pic) { 389 const uint8_t V[] = { 390 0xff, 0xb3, 0x04, 0x00, 0x00, 0x00, // pushl 4(%ebx) 391 0xff, 0xa3, 0x08, 0x00, 0x00, 0x00, // jmp *8(%ebx) 392 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 393 }; 394 memcpy(Buf, V, sizeof(V)); 395 return; 396 } 397 398 const uint8_t PltData[] = { 399 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushl (GOT+4) 400 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *(GOT+8) 401 0x90, 0x90, 0x90, 0x90 // nop; nop; nop; nop 402 }; 403 memcpy(Buf, PltData, sizeof(PltData)); 404 uint32_t Got = Out<ELF32LE>::GotPlt->getVA(); 405 write32le(Buf + 2, Got + 4); 406 write32le(Buf + 8, Got + 8); 407 } 408 409 void X86TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 410 uint64_t PltEntryAddr, int32_t Index, 411 unsigned RelOff) const { 412 const uint8_t Inst[] = { 413 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, // jmp *foo_in_GOT|*foo@GOT(%ebx) 414 0x68, 0x00, 0x00, 0x00, 0x00, // pushl $reloc_offset 415 0xe9, 0x00, 0x00, 0x00, 0x00 // jmp .PLT0@PC 416 }; 417 memcpy(Buf, Inst, sizeof(Inst)); 418 419 // jmp *foo@GOT(%ebx) or jmp *foo_in_GOT 420 Buf[1] = Config->Pic ? 0xa3 : 0x25; 421 uint32_t Got = Out<ELF32LE>::GotPlt->getVA(); 422 write32le(Buf + 2, Config->Shared ? GotEntryAddr - Got : GotEntryAddr); 423 write32le(Buf + 7, RelOff); 424 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 425 } 426 427 uint64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf, 428 uint32_t Type) const { 429 switch (Type) { 430 default: 431 return 0; 432 case R_386_32: 433 case R_386_GOT32: 434 case R_386_GOT32X: 435 case R_386_GOTOFF: 436 case R_386_GOTPC: 437 case R_386_PC32: 438 case R_386_PLT32: 439 case R_386_TLS_LE: 440 return read32le(Buf); 441 } 442 } 443 444 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 445 uint64_t Val) const { 446 checkInt<32>(Val, Type); 447 write32le(Loc, Val); 448 } 449 450 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 451 uint64_t Val) const { 452 // Convert 453 // leal x@tlsgd(, %ebx, 1), 454 // call __tls_get_addr@plt 455 // to 456 // movl %gs:0,%eax 457 // subl $x@ntpoff,%eax 458 const uint8_t Inst[] = { 459 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 460 0x81, 0xe8, 0x00, 0x00, 0x00, 0x00 // subl 0(%ebx), %eax 461 }; 462 memcpy(Loc - 3, Inst, sizeof(Inst)); 463 relocateOne(Loc + 5, R_386_32, Val); 464 } 465 466 void X86TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 467 uint64_t Val) const { 468 // Convert 469 // leal x@tlsgd(, %ebx, 1), 470 // call __tls_get_addr@plt 471 // to 472 // movl %gs:0, %eax 473 // addl x@gotntpoff(%ebx), %eax 474 const uint8_t Inst[] = { 475 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0, %eax 476 0x03, 0x83, 0x00, 0x00, 0x00, 0x00 // addl 0(%ebx), %eax 477 }; 478 memcpy(Loc - 3, Inst, sizeof(Inst)); 479 relocateOne(Loc + 5, R_386_32, Val); 480 } 481 482 // In some conditions, relocations can be optimized to avoid using GOT. 483 // This function does that for Initial Exec to Local Exec case. 484 void X86TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 485 uint64_t Val) const { 486 // Ulrich's document section 6.2 says that @gotntpoff can 487 // be used with MOVL or ADDL instructions. 488 // @indntpoff is similar to @gotntpoff, but for use in 489 // position dependent code. 490 uint8_t Reg = (Loc[-1] >> 3) & 7; 491 492 if (Type == R_386_TLS_IE) { 493 if (Loc[-1] == 0xa1) { 494 // "movl foo@indntpoff,%eax" -> "movl $foo,%eax" 495 // This case is different from the generic case below because 496 // this is a 5 byte instruction while below is 6 bytes. 497 Loc[-1] = 0xb8; 498 } else if (Loc[-2] == 0x8b) { 499 // "movl foo@indntpoff,%reg" -> "movl $foo,%reg" 500 Loc[-2] = 0xc7; 501 Loc[-1] = 0xc0 | Reg; 502 } else { 503 // "addl foo@indntpoff,%reg" -> "addl $foo,%reg" 504 Loc[-2] = 0x81; 505 Loc[-1] = 0xc0 | Reg; 506 } 507 } else { 508 assert(Type == R_386_TLS_GOTIE); 509 if (Loc[-2] == 0x8b) { 510 // "movl foo@gottpoff(%rip),%reg" -> "movl $foo,%reg" 511 Loc[-2] = 0xc7; 512 Loc[-1] = 0xc0 | Reg; 513 } else { 514 // "addl foo@gotntpoff(%rip),%reg" -> "leal foo(%reg),%reg" 515 Loc[-2] = 0x8d; 516 Loc[-1] = 0x80 | (Reg << 3) | Reg; 517 } 518 } 519 relocateOne(Loc, R_386_TLS_LE, Val); 520 } 521 522 void X86TargetInfo::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 523 uint64_t Val) const { 524 if (Type == R_386_TLS_LDO_32) { 525 relocateOne(Loc, R_386_TLS_LE, Val); 526 return; 527 } 528 529 // Convert 530 // leal foo(%reg),%eax 531 // call ___tls_get_addr 532 // to 533 // movl %gs:0,%eax 534 // nop 535 // leal 0(%esi,1),%esi 536 const uint8_t Inst[] = { 537 0x65, 0xa1, 0x00, 0x00, 0x00, 0x00, // movl %gs:0,%eax 538 0x90, // nop 539 0x8d, 0x74, 0x26, 0x00 // leal 0(%esi,1),%esi 540 }; 541 memcpy(Loc - 2, Inst, sizeof(Inst)); 542 } 543 544 template <class ELFT> X86_64TargetInfo<ELFT>::X86_64TargetInfo() { 545 CopyRel = R_X86_64_COPY; 546 GotRel = R_X86_64_GLOB_DAT; 547 PltRel = R_X86_64_JUMP_SLOT; 548 RelativeRel = R_X86_64_RELATIVE; 549 IRelativeRel = R_X86_64_IRELATIVE; 550 TlsGotRel = R_X86_64_TPOFF64; 551 TlsModuleIndexRel = R_X86_64_DTPMOD64; 552 TlsOffsetRel = R_X86_64_DTPOFF64; 553 GotEntrySize = 8; 554 GotPltEntrySize = 8; 555 PltEntrySize = 16; 556 PltHeaderSize = 16; 557 TlsGdRelaxSkip = 2; 558 } 559 560 template <class ELFT> 561 RelExpr X86_64TargetInfo<ELFT>::getRelExpr(uint32_t Type, 562 const SymbolBody &S) const { 563 switch (Type) { 564 default: 565 return R_ABS; 566 case R_X86_64_TPOFF32: 567 return R_TLS; 568 case R_X86_64_TLSLD: 569 return R_TLSLD_PC; 570 case R_X86_64_TLSGD: 571 return R_TLSGD_PC; 572 case R_X86_64_SIZE32: 573 case R_X86_64_SIZE64: 574 return R_SIZE; 575 case R_X86_64_PLT32: 576 return R_PLT_PC; 577 case R_X86_64_PC32: 578 case R_X86_64_PC64: 579 return R_PC; 580 case R_X86_64_GOT32: 581 return R_GOT_FROM_END; 582 case R_X86_64_GOTPCREL: 583 case R_X86_64_GOTPCRELX: 584 case R_X86_64_REX_GOTPCRELX: 585 case R_X86_64_GOTTPOFF: 586 return R_GOT_PC; 587 } 588 } 589 590 template <class ELFT> 591 void X86_64TargetInfo<ELFT>::writeGotPltHeader(uint8_t *Buf) const { 592 // The first entry holds the value of _DYNAMIC. It is not clear why that is 593 // required, but it is documented in the psabi and the glibc dynamic linker 594 // seems to use it (note that this is relevant for linking ld.so, not any 595 // other program). 596 write64le(Buf, Out<ELFT>::Dynamic->getVA()); 597 } 598 599 template <class ELFT> 600 void X86_64TargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, 601 const SymbolBody &S) const { 602 // See comments in X86TargetInfo::writeGotPlt. 603 write32le(Buf, S.getPltVA<ELFT>() + 6); 604 } 605 606 template <class ELFT> 607 void X86_64TargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 608 const uint8_t PltData[] = { 609 0xff, 0x35, 0x00, 0x00, 0x00, 0x00, // pushq GOT+8(%rip) 610 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmp *GOT+16(%rip) 611 0x0f, 0x1f, 0x40, 0x00 // nopl 0x0(rax) 612 }; 613 memcpy(Buf, PltData, sizeof(PltData)); 614 uint64_t Got = Out<ELFT>::GotPlt->getVA(); 615 uint64_t Plt = Out<ELFT>::Plt->getVA(); 616 write32le(Buf + 2, Got - Plt + 2); // GOT+8 617 write32le(Buf + 8, Got - Plt + 4); // GOT+16 618 } 619 620 template <class ELFT> 621 void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 622 uint64_t PltEntryAddr, int32_t Index, 623 unsigned RelOff) const { 624 const uint8_t Inst[] = { 625 0xff, 0x25, 0x00, 0x00, 0x00, 0x00, // jmpq *got(%rip) 626 0x68, 0x00, 0x00, 0x00, 0x00, // pushq <relocation index> 627 0xe9, 0x00, 0x00, 0x00, 0x00 // jmpq plt[0] 628 }; 629 memcpy(Buf, Inst, sizeof(Inst)); 630 631 write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6); 632 write32le(Buf + 7, Index); 633 write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16); 634 } 635 636 template <class ELFT> 637 uint32_t X86_64TargetInfo<ELFT>::getDynRel(uint32_t Type) const { 638 if (Type == R_X86_64_PC32 || Type == R_X86_64_32) 639 errorDynRel(Type); 640 return Type; 641 } 642 643 template <class ELFT> 644 bool X86_64TargetInfo<ELFT>::isTlsInitialExecRel(uint32_t Type) const { 645 return Type == R_X86_64_GOTTPOFF; 646 } 647 648 template <class ELFT> 649 bool X86_64TargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 650 return Type == R_X86_64_TLSGD; 651 } 652 653 template <class ELFT> 654 bool X86_64TargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 655 return Type == R_X86_64_DTPOFF32 || Type == R_X86_64_DTPOFF64 || 656 Type == R_X86_64_TLSLD; 657 } 658 659 template <class ELFT> 660 void X86_64TargetInfo<ELFT>::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 661 uint64_t Val) const { 662 // Convert 663 // .byte 0x66 664 // leaq x@tlsgd(%rip), %rdi 665 // .word 0x6666 666 // rex64 667 // call __tls_get_addr@plt 668 // to 669 // mov %fs:0x0,%rax 670 // lea x@tpoff,%rax 671 const uint8_t Inst[] = { 672 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 673 0x48, 0x8d, 0x80, 0x00, 0x00, 0x00, 0x00 // lea x@tpoff,%rax 674 }; 675 memcpy(Loc - 4, Inst, sizeof(Inst)); 676 // The original code used a pc relative relocation and so we have to 677 // compensate for the -4 in had in the addend. 678 relocateOne(Loc + 8, R_X86_64_TPOFF32, Val + 4); 679 } 680 681 template <class ELFT> 682 void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 683 uint64_t Val) const { 684 // Convert 685 // .byte 0x66 686 // leaq x@tlsgd(%rip), %rdi 687 // .word 0x6666 688 // rex64 689 // call __tls_get_addr@plt 690 // to 691 // mov %fs:0x0,%rax 692 // addq x@tpoff,%rax 693 const uint8_t Inst[] = { 694 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax 695 0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00 // addq x@tpoff,%rax 696 }; 697 memcpy(Loc - 4, Inst, sizeof(Inst)); 698 // Both code sequences are PC relatives, but since we are moving the constant 699 // forward by 8 bytes we have to subtract the value by 8. 700 relocateOne(Loc + 8, R_X86_64_PC32, Val - 8); 701 } 702 703 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to 704 // R_X86_64_TPOFF32 so that it does not use GOT. 705 template <class ELFT> 706 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 707 uint64_t Val) const { 708 uint8_t *Inst = Loc - 3; 709 uint8_t Reg = Loc[-1] >> 3; 710 uint8_t *RegSlot = Loc - 1; 711 712 // Note that ADD with RSP or R12 is converted to ADD instead of LEA 713 // because LEA with these registers needs 4 bytes to encode and thus 714 // wouldn't fit the space. 715 716 if (memcmp(Inst, "\x48\x03\x25", 3) == 0) { 717 // "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp" 718 memcpy(Inst, "\x48\x81\xc4", 3); 719 } else if (memcmp(Inst, "\x4c\x03\x25", 3) == 0) { 720 // "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12" 721 memcpy(Inst, "\x49\x81\xc4", 3); 722 } else if (memcmp(Inst, "\x4c\x03", 2) == 0) { 723 // "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]" 724 memcpy(Inst, "\x4d\x8d", 2); 725 *RegSlot = 0x80 | (Reg << 3) | Reg; 726 } else if (memcmp(Inst, "\x48\x03", 2) == 0) { 727 // "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg" 728 memcpy(Inst, "\x48\x8d", 2); 729 *RegSlot = 0x80 | (Reg << 3) | Reg; 730 } else if (memcmp(Inst, "\x4c\x8b", 2) == 0) { 731 // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]" 732 memcpy(Inst, "\x49\xc7", 2); 733 *RegSlot = 0xc0 | Reg; 734 } else if (memcmp(Inst, "\x48\x8b", 2) == 0) { 735 // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg" 736 memcpy(Inst, "\x48\xc7", 2); 737 *RegSlot = 0xc0 | Reg; 738 } else { 739 fatal("R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only"); 740 } 741 742 // The original code used a PC relative relocation. 743 // Need to compensate for the -4 it had in the addend. 744 relocateOne(Loc, R_X86_64_TPOFF32, Val + 4); 745 } 746 747 template <class ELFT> 748 void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, 749 uint64_t Val) const { 750 // Convert 751 // leaq bar@tlsld(%rip), %rdi 752 // callq __tls_get_addr@PLT 753 // leaq bar@dtpoff(%rax), %rcx 754 // to 755 // .word 0x6666 756 // .byte 0x66 757 // mov %fs:0,%rax 758 // leaq bar@tpoff(%rax), %rcx 759 if (Type == R_X86_64_DTPOFF64) { 760 write64le(Loc, Val); 761 return; 762 } 763 if (Type == R_X86_64_DTPOFF32) { 764 relocateOne(Loc, R_X86_64_TPOFF32, Val); 765 return; 766 } 767 768 const uint8_t Inst[] = { 769 0x66, 0x66, // .word 0x6666 770 0x66, // .byte 0x66 771 0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00 // mov %fs:0,%rax 772 }; 773 memcpy(Loc - 3, Inst, sizeof(Inst)); 774 } 775 776 template <class ELFT> 777 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 778 uint64_t Val) const { 779 switch (Type) { 780 case R_X86_64_32: 781 checkUInt<32>(Val, Type); 782 write32le(Loc, Val); 783 break; 784 case R_X86_64_32S: 785 case R_X86_64_TPOFF32: 786 case R_X86_64_GOT32: 787 case R_X86_64_GOTPCREL: 788 case R_X86_64_GOTPCRELX: 789 case R_X86_64_REX_GOTPCRELX: 790 case R_X86_64_PC32: 791 case R_X86_64_GOTTPOFF: 792 case R_X86_64_PLT32: 793 case R_X86_64_TLSGD: 794 case R_X86_64_TLSLD: 795 case R_X86_64_DTPOFF32: 796 case R_X86_64_SIZE32: 797 checkInt<32>(Val, Type); 798 write32le(Loc, Val); 799 break; 800 case R_X86_64_64: 801 case R_X86_64_DTPOFF64: 802 case R_X86_64_SIZE64: 803 case R_X86_64_PC64: 804 write64le(Loc, Val); 805 break; 806 default: 807 fatal("unrecognized reloc " + Twine(Type)); 808 } 809 } 810 811 template <class ELFT> 812 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type, 813 const uint8_t *Data, 814 RelExpr RelExpr) const { 815 if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX) 816 return RelExpr; 817 const uint8_t Op = Data[-2]; 818 const uint8_t ModRm = Data[-1]; 819 // FIXME: When PIC is disabled and foo is defined locally in the 820 // lower 32 bit address space, memory operand in mov can be converted into 821 // immediate operand. Otherwise, mov must be changed to lea. We support only 822 // latter relaxation at this moment. 823 if (Op == 0x8b) 824 return R_RELAX_GOT_PC; 825 // Relax call and jmp. 826 if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25)) 827 return R_RELAX_GOT_PC; 828 829 // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor. 830 // If PIC then no relaxation is available. 831 // We also don't relax test/binop instructions without REX byte, 832 // they are 32bit operations and not common to have. 833 assert(Type == R_X86_64_REX_GOTPCRELX); 834 return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC; 835 } 836 837 // A subset of relaxations can only be applied for no-PIC. This method 838 // handles such relaxations. Instructions encoding information was taken from: 839 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2" 840 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/ 841 // 64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf) 842 template <class ELFT> 843 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val, 844 uint8_t Op, uint8_t ModRm) const { 845 const uint8_t Rex = Loc[-3]; 846 // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg". 847 if (Op == 0x85) { 848 // See "TEST-Logical Compare" (4-428 Vol. 2B), 849 // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension). 850 851 // ModR/M byte has form XX YYY ZZZ, where 852 // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1). 853 // XX has different meanings: 854 // 00: The operand's memory address is in reg1. 855 // 01: The operand's memory address is reg1 + a byte-sized displacement. 856 // 10: The operand's memory address is reg1 + a word-sized displacement. 857 // 11: The operand is reg1 itself. 858 // If an instruction requires only one operand, the unused reg2 field 859 // holds extra opcode bits rather than a register code 860 // 0xC0 == 11 000 000 binary. 861 // 0x38 == 00 111 000 binary. 862 // We transfer reg2 to reg1 here as operand. 863 // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3). 864 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte. 865 866 // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32 867 // See "TEST-Logical Compare" (4-428 Vol. 2B). 868 Loc[-2] = 0xf7; 869 870 // Move R bit to the B bit in REX byte. 871 // REX byte is encoded as 0100WRXB, where 872 // 0100 is 4bit fixed pattern. 873 // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the 874 // default operand size is used (which is 32-bit for most but not all 875 // instructions). 876 // REX.R This 1-bit value is an extension to the MODRM.reg field. 877 // REX.X This 1-bit value is an extension to the SIB.index field. 878 // REX.B This 1-bit value is an extension to the MODRM.rm field or the 879 // SIB.base field. 880 // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A). 881 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 882 relocateOne(Loc, R_X86_64_PC32, Val); 883 return; 884 } 885 886 // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub 887 // or xor operations. 888 889 // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg". 890 // Logic is close to one for test instruction above, but we also 891 // write opcode extension here, see below for details. 892 Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte. 893 894 // Primary opcode is 0x81, opcode extension is one of: 895 // 000b = ADD, 001b is OR, 010b is ADC, 011b is SBB, 896 // 100b is AND, 101b is SUB, 110b is XOR, 111b is CMP. 897 // This value was wrote to MODRM.reg in a line above. 898 // See "3.2 INSTRUCTIONS (A-M)" (Vol. 2A 3-15), 899 // "INSTRUCTION SET REFERENCE, N-Z" (Vol. 2B 4-1) for 900 // descriptions about each operation. 901 Loc[-2] = 0x81; 902 Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2; 903 relocateOne(Loc, R_X86_64_PC32, Val); 904 } 905 906 template <class ELFT> 907 void X86_64TargetInfo<ELFT>::relaxGot(uint8_t *Loc, uint64_t Val) const { 908 const uint8_t Op = Loc[-2]; 909 const uint8_t ModRm = Loc[-1]; 910 911 // Convert "mov foo@GOTPCREL(%rip),%reg" to "lea foo(%rip),%reg". 912 if (Op == 0x8b) { 913 Loc[-2] = 0x8d; 914 relocateOne(Loc, R_X86_64_PC32, Val); 915 return; 916 } 917 918 if (Op != 0xff) { 919 // We are relaxing a rip relative to an absolute, so compensate 920 // for the old -4 addend. 921 assert(!Config->Pic); 922 relaxGotNoPic(Loc, Val + 4, Op, ModRm); 923 return; 924 } 925 926 // Convert call/jmp instructions. 927 if (ModRm == 0x15) { 928 // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo". 929 // Instead we convert to "addr32 call foo" where addr32 is an instruction 930 // prefix. That makes result expression to be a single instruction. 931 Loc[-2] = 0x67; // addr32 prefix 932 Loc[-1] = 0xe8; // call 933 relocateOne(Loc, R_X86_64_PC32, Val); 934 return; 935 } 936 937 // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop". 938 // jmp doesn't return, so it is fine to use nop here, it is just a stub. 939 assert(ModRm == 0x25); 940 Loc[-2] = 0xe9; // jmp 941 Loc[3] = 0x90; // nop 942 relocateOne(Loc - 1, R_X86_64_PC32, Val + 1); 943 } 944 945 // Relocation masks following the #lo(value), #hi(value), #ha(value), 946 // #higher(value), #highera(value), #highest(value), and #highesta(value) 947 // macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi 948 // document. 949 static uint16_t applyPPCLo(uint64_t V) { return V; } 950 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; } 951 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; } 952 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; } 953 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; } 954 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; } 955 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; } 956 957 PPCTargetInfo::PPCTargetInfo() {} 958 959 void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 960 uint64_t Val) const { 961 switch (Type) { 962 case R_PPC_ADDR16_HA: 963 write16be(Loc, applyPPCHa(Val)); 964 break; 965 case R_PPC_ADDR16_LO: 966 write16be(Loc, applyPPCLo(Val)); 967 break; 968 default: 969 fatal("unrecognized reloc " + Twine(Type)); 970 } 971 } 972 973 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 974 return R_ABS; 975 } 976 977 PPC64TargetInfo::PPC64TargetInfo() { 978 PltRel = GotRel = R_PPC64_GLOB_DAT; 979 RelativeRel = R_PPC64_RELATIVE; 980 GotEntrySize = 8; 981 GotPltEntrySize = 8; 982 PltEntrySize = 32; 983 PltHeaderSize = 0; 984 985 // We need 64K pages (at least under glibc/Linux, the loader won't 986 // set different permissions on a finer granularity than that). 987 MaxPageSize = 65536; 988 989 // The PPC64 ELF ABI v1 spec, says: 990 // 991 // It is normally desirable to put segments with different characteristics 992 // in separate 256 Mbyte portions of the address space, to give the 993 // operating system full paging flexibility in the 64-bit address space. 994 // 995 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers 996 // use 0x10000000 as the starting address. 997 DefaultImageBase = 0x10000000; 998 } 999 1000 static uint64_t PPC64TocOffset = 0x8000; 1001 1002 uint64_t getPPC64TocBase() { 1003 // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The 1004 // TOC starts where the first of these sections starts. We always create a 1005 // .got when we see a relocation that uses it, so for us the start is always 1006 // the .got. 1007 uint64_t TocVA = Out<ELF64BE>::Got->getVA(); 1008 1009 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000 1010 // thus permitting a full 64 Kbytes segment. Note that the glibc startup 1011 // code (crt1.o) assumes that you can get from the TOC base to the 1012 // start of the .toc section with only a single (signed) 16-bit relocation. 1013 return TocVA + PPC64TocOffset; 1014 } 1015 1016 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1017 switch (Type) { 1018 default: 1019 return R_ABS; 1020 case R_PPC64_TOC16: 1021 case R_PPC64_TOC16_DS: 1022 case R_PPC64_TOC16_HA: 1023 case R_PPC64_TOC16_HI: 1024 case R_PPC64_TOC16_LO: 1025 case R_PPC64_TOC16_LO_DS: 1026 return R_GOTREL; 1027 case R_PPC64_TOC: 1028 return R_PPC_TOC; 1029 case R_PPC64_REL24: 1030 return R_PPC_PLT_OPD; 1031 } 1032 } 1033 1034 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1035 uint64_t PltEntryAddr, int32_t Index, 1036 unsigned RelOff) const { 1037 uint64_t Off = GotEntryAddr - getPPC64TocBase(); 1038 1039 // FIXME: What we should do, in theory, is get the offset of the function 1040 // descriptor in the .opd section, and use that as the offset from %r2 (the 1041 // TOC-base pointer). Instead, we have the GOT-entry offset, and that will 1042 // be a pointer to the function descriptor in the .opd section. Using 1043 // this scheme is simpler, but requires an extra indirection per PLT dispatch. 1044 1045 write32be(Buf, 0xf8410028); // std %r2, 40(%r1) 1046 write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha 1047 write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11) 1048 write32be(Buf + 12, 0xe96c0000); // ld %r11,0(%r12) 1049 write32be(Buf + 16, 0x7d6903a6); // mtctr %r11 1050 write32be(Buf + 20, 0xe84c0008); // ld %r2,8(%r12) 1051 write32be(Buf + 24, 0xe96c0010); // ld %r11,16(%r12) 1052 write32be(Buf + 28, 0x4e800420); // bctr 1053 } 1054 1055 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) { 1056 uint64_t V = Val - PPC64TocOffset; 1057 switch (Type) { 1058 case R_PPC64_TOC16: 1059 return {R_PPC64_ADDR16, V}; 1060 case R_PPC64_TOC16_DS: 1061 return {R_PPC64_ADDR16_DS, V}; 1062 case R_PPC64_TOC16_HA: 1063 return {R_PPC64_ADDR16_HA, V}; 1064 case R_PPC64_TOC16_HI: 1065 return {R_PPC64_ADDR16_HI, V}; 1066 case R_PPC64_TOC16_LO: 1067 return {R_PPC64_ADDR16_LO, V}; 1068 case R_PPC64_TOC16_LO_DS: 1069 return {R_PPC64_ADDR16_LO_DS, V}; 1070 default: 1071 return {Type, Val}; 1072 } 1073 } 1074 1075 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1076 uint64_t Val) const { 1077 // For a TOC-relative relocation, proceed in terms of the corresponding 1078 // ADDR16 relocation type. 1079 std::tie(Type, Val) = toAddr16Rel(Type, Val); 1080 1081 switch (Type) { 1082 case R_PPC64_ADDR14: { 1083 checkAlignment<4>(Val, Type); 1084 // Preserve the AA/LK bits in the branch instruction 1085 uint8_t AALK = Loc[3]; 1086 write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc)); 1087 break; 1088 } 1089 case R_PPC64_ADDR16: 1090 checkInt<16>(Val, Type); 1091 write16be(Loc, Val); 1092 break; 1093 case R_PPC64_ADDR16_DS: 1094 checkInt<16>(Val, Type); 1095 write16be(Loc, (read16be(Loc) & 3) | (Val & ~3)); 1096 break; 1097 case R_PPC64_ADDR16_HA: 1098 case R_PPC64_REL16_HA: 1099 write16be(Loc, applyPPCHa(Val)); 1100 break; 1101 case R_PPC64_ADDR16_HI: 1102 case R_PPC64_REL16_HI: 1103 write16be(Loc, applyPPCHi(Val)); 1104 break; 1105 case R_PPC64_ADDR16_HIGHER: 1106 write16be(Loc, applyPPCHigher(Val)); 1107 break; 1108 case R_PPC64_ADDR16_HIGHERA: 1109 write16be(Loc, applyPPCHighera(Val)); 1110 break; 1111 case R_PPC64_ADDR16_HIGHEST: 1112 write16be(Loc, applyPPCHighest(Val)); 1113 break; 1114 case R_PPC64_ADDR16_HIGHESTA: 1115 write16be(Loc, applyPPCHighesta(Val)); 1116 break; 1117 case R_PPC64_ADDR16_LO: 1118 write16be(Loc, applyPPCLo(Val)); 1119 break; 1120 case R_PPC64_ADDR16_LO_DS: 1121 case R_PPC64_REL16_LO: 1122 write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3)); 1123 break; 1124 case R_PPC64_ADDR32: 1125 case R_PPC64_REL32: 1126 checkInt<32>(Val, Type); 1127 write32be(Loc, Val); 1128 break; 1129 case R_PPC64_ADDR64: 1130 case R_PPC64_REL64: 1131 case R_PPC64_TOC: 1132 write64be(Loc, Val); 1133 break; 1134 case R_PPC64_REL24: { 1135 uint32_t Mask = 0x03FFFFFC; 1136 checkInt<24>(Val, Type); 1137 write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask)); 1138 break; 1139 } 1140 default: 1141 fatal("unrecognized reloc " + Twine(Type)); 1142 } 1143 } 1144 1145 AArch64TargetInfo::AArch64TargetInfo() { 1146 CopyRel = R_AARCH64_COPY; 1147 RelativeRel = R_AARCH64_RELATIVE; 1148 IRelativeRel = R_AARCH64_IRELATIVE; 1149 GotRel = R_AARCH64_GLOB_DAT; 1150 PltRel = R_AARCH64_JUMP_SLOT; 1151 TlsDescRel = R_AARCH64_TLSDESC; 1152 TlsGotRel = R_AARCH64_TLS_TPREL64; 1153 GotEntrySize = 8; 1154 GotPltEntrySize = 8; 1155 PltEntrySize = 16; 1156 PltHeaderSize = 32; 1157 MaxPageSize = 65536; 1158 1159 // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant 1160 // 1 of the tls structures and the tcb size is 16. 1161 TcbSize = 16; 1162 } 1163 1164 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type, 1165 const SymbolBody &S) const { 1166 switch (Type) { 1167 default: 1168 return R_ABS; 1169 case R_AARCH64_TLSDESC_ADR_PAGE21: 1170 return R_TLSDESC_PAGE; 1171 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1172 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1173 return R_TLSDESC; 1174 case R_AARCH64_TLSDESC_CALL: 1175 return R_TLSDESC_CALL; 1176 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1177 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1178 return R_TLS; 1179 case R_AARCH64_CALL26: 1180 case R_AARCH64_CONDBR19: 1181 case R_AARCH64_JUMP26: 1182 case R_AARCH64_TSTBR14: 1183 return R_PLT_PC; 1184 case R_AARCH64_PREL16: 1185 case R_AARCH64_PREL32: 1186 case R_AARCH64_PREL64: 1187 case R_AARCH64_ADR_PREL_LO21: 1188 return R_PC; 1189 case R_AARCH64_ADR_PREL_PG_HI21: 1190 return R_PAGE_PC; 1191 case R_AARCH64_LD64_GOT_LO12_NC: 1192 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1193 return R_GOT; 1194 case R_AARCH64_ADR_GOT_PAGE: 1195 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1196 return R_GOT_PAGE_PC; 1197 } 1198 } 1199 1200 RelExpr AArch64TargetInfo::adjustRelaxExpr(uint32_t Type, const uint8_t *Data, 1201 RelExpr Expr) const { 1202 if (Expr == R_RELAX_TLS_GD_TO_IE) { 1203 if (Type == R_AARCH64_TLSDESC_ADR_PAGE21) 1204 return R_RELAX_TLS_GD_TO_IE_PAGE_PC; 1205 return R_RELAX_TLS_GD_TO_IE_ABS; 1206 } 1207 return Expr; 1208 } 1209 1210 bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const { 1211 switch (Type) { 1212 default: 1213 return false; 1214 case R_AARCH64_ADD_ABS_LO12_NC: 1215 case R_AARCH64_LD64_GOT_LO12_NC: 1216 case R_AARCH64_LDST128_ABS_LO12_NC: 1217 case R_AARCH64_LDST16_ABS_LO12_NC: 1218 case R_AARCH64_LDST32_ABS_LO12_NC: 1219 case R_AARCH64_LDST64_ABS_LO12_NC: 1220 case R_AARCH64_LDST8_ABS_LO12_NC: 1221 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1222 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1223 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1224 return true; 1225 } 1226 } 1227 1228 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1229 return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 || 1230 Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; 1231 } 1232 1233 uint32_t AArch64TargetInfo::getDynRel(uint32_t Type) const { 1234 if (Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64) 1235 return Type; 1236 // Keep it going with a dummy value so that we can find more reloc errors. 1237 errorDynRel(Type); 1238 return R_AARCH64_ABS32; 1239 } 1240 1241 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1242 write64le(Buf, Out<ELF64LE>::Plt->getVA()); 1243 } 1244 1245 static uint64_t getAArch64Page(uint64_t Expr) { 1246 return Expr & (~static_cast<uint64_t>(0xFFF)); 1247 } 1248 1249 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const { 1250 const uint8_t PltData[] = { 1251 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 1252 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 1253 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 1254 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 1255 0x20, 0x02, 0x1f, 0xd6, // br x17 1256 0x1f, 0x20, 0x03, 0xd5, // nop 1257 0x1f, 0x20, 0x03, 0xd5, // nop 1258 0x1f, 0x20, 0x03, 0xd5 // nop 1259 }; 1260 memcpy(Buf, PltData, sizeof(PltData)); 1261 1262 uint64_t Got = Out<ELF64LE>::GotPlt->getVA(); 1263 uint64_t Plt = Out<ELF64LE>::Plt->getVA(); 1264 relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 1265 getAArch64Page(Got + 16) - getAArch64Page(Plt + 4)); 1266 relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16); 1267 relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16); 1268 } 1269 1270 void AArch64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1271 uint64_t PltEntryAddr, int32_t Index, 1272 unsigned RelOff) const { 1273 const uint8_t Inst[] = { 1274 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 1275 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 1276 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n])) 1277 0x20, 0x02, 0x1f, 0xd6 // br x17 1278 }; 1279 memcpy(Buf, Inst, sizeof(Inst)); 1280 1281 relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21, 1282 getAArch64Page(GotEntryAddr) - getAArch64Page(PltEntryAddr)); 1283 relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotEntryAddr); 1284 relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotEntryAddr); 1285 } 1286 1287 static void updateAArch64Addr(uint8_t *L, uint64_t Imm) { 1288 uint32_t ImmLo = (Imm & 0x3) << 29; 1289 uint32_t ImmHi = (Imm & 0x1FFFFC) << 3; 1290 uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3); 1291 write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi); 1292 } 1293 1294 static inline void updateAArch64Add(uint8_t *L, uint64_t Imm) { 1295 or32le(L, (Imm & 0xFFF) << 10); 1296 } 1297 1298 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1299 uint64_t Val) const { 1300 switch (Type) { 1301 case R_AARCH64_ABS16: 1302 case R_AARCH64_PREL16: 1303 checkIntUInt<16>(Val, Type); 1304 write16le(Loc, Val); 1305 break; 1306 case R_AARCH64_ABS32: 1307 case R_AARCH64_PREL32: 1308 checkIntUInt<32>(Val, Type); 1309 write32le(Loc, Val); 1310 break; 1311 case R_AARCH64_ABS64: 1312 case R_AARCH64_PREL64: 1313 write64le(Loc, Val); 1314 break; 1315 case R_AARCH64_ADD_ABS_LO12_NC: 1316 // This relocation stores 12 bits and there's no instruction 1317 // to do it. Instead, we do a 32 bits store of the value 1318 // of r_addend bitwise-or'ed Loc. This assumes that the addend 1319 // bits in Loc are zero. 1320 or32le(Loc, (Val & 0xFFF) << 10); 1321 break; 1322 case R_AARCH64_ADR_GOT_PAGE: 1323 case R_AARCH64_ADR_PREL_PG_HI21: 1324 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 1325 case R_AARCH64_TLSDESC_ADR_PAGE21: 1326 checkInt<33>(Val, Type); 1327 updateAArch64Addr(Loc, Val >> 12); 1328 break; 1329 case R_AARCH64_ADR_PREL_LO21: 1330 checkInt<21>(Val, Type); 1331 updateAArch64Addr(Loc, Val); 1332 break; 1333 case R_AARCH64_CALL26: 1334 case R_AARCH64_JUMP26: 1335 checkInt<28>(Val, Type); 1336 or32le(Loc, (Val & 0x0FFFFFFC) >> 2); 1337 break; 1338 case R_AARCH64_CONDBR19: 1339 checkInt<21>(Val, Type); 1340 or32le(Loc, (Val & 0x1FFFFC) << 3); 1341 break; 1342 case R_AARCH64_LD64_GOT_LO12_NC: 1343 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 1344 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1345 checkAlignment<8>(Val, Type); 1346 or32le(Loc, (Val & 0xFF8) << 7); 1347 break; 1348 case R_AARCH64_LDST128_ABS_LO12_NC: 1349 or32le(Loc, (Val & 0x0FF8) << 6); 1350 break; 1351 case R_AARCH64_LDST16_ABS_LO12_NC: 1352 or32le(Loc, (Val & 0x0FFC) << 9); 1353 break; 1354 case R_AARCH64_LDST8_ABS_LO12_NC: 1355 or32le(Loc, (Val & 0xFFF) << 10); 1356 break; 1357 case R_AARCH64_LDST32_ABS_LO12_NC: 1358 or32le(Loc, (Val & 0xFFC) << 8); 1359 break; 1360 case R_AARCH64_LDST64_ABS_LO12_NC: 1361 or32le(Loc, (Val & 0xFF8) << 7); 1362 break; 1363 case R_AARCH64_MOVW_UABS_G0_NC: 1364 or32le(Loc, (Val & 0xFFFF) << 5); 1365 break; 1366 case R_AARCH64_MOVW_UABS_G1_NC: 1367 or32le(Loc, (Val & 0xFFFF0000) >> 11); 1368 break; 1369 case R_AARCH64_MOVW_UABS_G2_NC: 1370 or32le(Loc, (Val & 0xFFFF00000000) >> 27); 1371 break; 1372 case R_AARCH64_MOVW_UABS_G3: 1373 or32le(Loc, (Val & 0xFFFF000000000000) >> 43); 1374 break; 1375 case R_AARCH64_TSTBR14: 1376 checkInt<16>(Val, Type); 1377 or32le(Loc, (Val & 0xFFFC) << 3); 1378 break; 1379 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 1380 checkInt<24>(Val, Type); 1381 updateAArch64Add(Loc, Val >> 12); 1382 break; 1383 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 1384 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1385 updateAArch64Add(Loc, Val); 1386 break; 1387 default: 1388 fatal("unrecognized reloc " + Twine(Type)); 1389 } 1390 } 1391 1392 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, 1393 uint64_t Val) const { 1394 // TLSDESC Global-Dynamic relocation are in the form: 1395 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1396 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1397 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1398 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1399 // blr x1 1400 // And it can optimized to: 1401 // movz x0, #0x0, lsl #16 1402 // movk x0, #0x10 1403 // nop 1404 // nop 1405 checkUInt<32>(Val, Type); 1406 1407 switch (Type) { 1408 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1409 case R_AARCH64_TLSDESC_CALL: 1410 write32le(Loc, 0xd503201f); // nop 1411 return; 1412 case R_AARCH64_TLSDESC_ADR_PAGE21: 1413 write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz 1414 return; 1415 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1416 write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk 1417 return; 1418 default: 1419 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1420 } 1421 } 1422 1423 void AArch64TargetInfo::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, 1424 uint64_t Val) const { 1425 // TLSDESC Global-Dynamic relocation are in the form: 1426 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 1427 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12_NC] 1428 // add x0, x0, :tlsdesc_los:v [_AARCH64_TLSDESC_ADD_LO12_NC] 1429 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 1430 // blr x1 1431 // And it can optimized to: 1432 // adrp x0, :gottprel:v 1433 // ldr x0, [x0, :gottprel_lo12:v] 1434 // nop 1435 // nop 1436 1437 switch (Type) { 1438 case R_AARCH64_TLSDESC_ADD_LO12_NC: 1439 case R_AARCH64_TLSDESC_CALL: 1440 write32le(Loc, 0xd503201f); // nop 1441 break; 1442 case R_AARCH64_TLSDESC_ADR_PAGE21: 1443 write32le(Loc, 0x90000000); // adrp 1444 relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val); 1445 break; 1446 case R_AARCH64_TLSDESC_LD64_LO12_NC: 1447 write32le(Loc, 0xf9400000); // ldr 1448 relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val); 1449 break; 1450 default: 1451 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 1452 } 1453 } 1454 1455 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, 1456 uint64_t Val) const { 1457 checkUInt<32>(Val, Type); 1458 1459 if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) { 1460 // Generate MOVZ. 1461 uint32_t RegNo = read32le(Loc) & 0x1f; 1462 write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5)); 1463 return; 1464 } 1465 if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) { 1466 // Generate MOVK. 1467 uint32_t RegNo = read32le(Loc) & 0x1f; 1468 write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5)); 1469 return; 1470 } 1471 llvm_unreachable("invalid relocation for TLS IE to LE relaxation"); 1472 } 1473 1474 AMDGPUTargetInfo::AMDGPUTargetInfo() { 1475 RelativeRel = R_AMDGPU_REL64; 1476 GotRel = R_AMDGPU_ABS64; 1477 GotEntrySize = 8; 1478 } 1479 1480 void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1481 uint64_t Val) const { 1482 switch (Type) { 1483 case R_AMDGPU_ABS32: 1484 case R_AMDGPU_GOTPCREL: 1485 case R_AMDGPU_GOTPCREL32_LO: 1486 case R_AMDGPU_REL32: 1487 case R_AMDGPU_REL32_LO: 1488 write32le(Loc, Val); 1489 break; 1490 case R_AMDGPU_ABS64: 1491 write64le(Loc, Val); 1492 break; 1493 case R_AMDGPU_GOTPCREL32_HI: 1494 case R_AMDGPU_REL32_HI: 1495 write32le(Loc, Val >> 32); 1496 break; 1497 default: 1498 fatal("unrecognized reloc " + Twine(Type)); 1499 } 1500 } 1501 1502 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1503 switch (Type) { 1504 case R_AMDGPU_ABS32: 1505 case R_AMDGPU_ABS64: 1506 return R_ABS; 1507 case R_AMDGPU_REL32: 1508 case R_AMDGPU_REL32_LO: 1509 case R_AMDGPU_REL32_HI: 1510 return R_PC; 1511 case R_AMDGPU_GOTPCREL: 1512 case R_AMDGPU_GOTPCREL32_LO: 1513 case R_AMDGPU_GOTPCREL32_HI: 1514 return R_GOT_PC; 1515 default: 1516 fatal("do not know how to handle relocation " + Twine(Type)); 1517 } 1518 } 1519 1520 ARMTargetInfo::ARMTargetInfo() { 1521 CopyRel = R_ARM_COPY; 1522 RelativeRel = R_ARM_RELATIVE; 1523 IRelativeRel = R_ARM_IRELATIVE; 1524 GotRel = R_ARM_GLOB_DAT; 1525 PltRel = R_ARM_JUMP_SLOT; 1526 TlsGotRel = R_ARM_TLS_TPOFF32; 1527 TlsModuleIndexRel = R_ARM_TLS_DTPMOD32; 1528 TlsOffsetRel = R_ARM_TLS_DTPOFF32; 1529 GotEntrySize = 4; 1530 GotPltEntrySize = 4; 1531 PltEntrySize = 16; 1532 PltHeaderSize = 20; 1533 // ARM uses Variant 1 TLS 1534 TcbSize = 8; 1535 NeedsThunks = true; 1536 } 1537 1538 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const { 1539 switch (Type) { 1540 default: 1541 return R_ABS; 1542 case R_ARM_THM_JUMP11: 1543 return R_PC; 1544 case R_ARM_CALL: 1545 case R_ARM_JUMP24: 1546 case R_ARM_PC24: 1547 case R_ARM_PLT32: 1548 case R_ARM_PREL31: 1549 case R_ARM_THM_JUMP19: 1550 case R_ARM_THM_JUMP24: 1551 case R_ARM_THM_CALL: 1552 return R_PLT_PC; 1553 case R_ARM_GOTOFF32: 1554 // (S + A) - GOT_ORG 1555 return R_GOTREL; 1556 case R_ARM_GOT_BREL: 1557 // GOT(S) + A - GOT_ORG 1558 return R_GOT_OFF; 1559 case R_ARM_GOT_PREL: 1560 case R_ARM_TLS_IE32: 1561 // GOT(S) + A - P 1562 return R_GOT_PC; 1563 case R_ARM_TARGET1: 1564 return Config->Target1Rel ? R_PC : R_ABS; 1565 case R_ARM_TARGET2: 1566 if (Config->Target2 == Target2Policy::Rel) 1567 return R_PC; 1568 if (Config->Target2 == Target2Policy::Abs) 1569 return R_ABS; 1570 return R_GOT_PC; 1571 case R_ARM_TLS_GD32: 1572 return R_TLSGD_PC; 1573 case R_ARM_TLS_LDM32: 1574 return R_TLSLD_PC; 1575 case R_ARM_BASE_PREL: 1576 // B(S) + A - P 1577 // FIXME: currently B(S) assumed to be .got, this may not hold for all 1578 // platforms. 1579 return R_GOTONLY_PC; 1580 case R_ARM_MOVW_PREL_NC: 1581 case R_ARM_MOVT_PREL: 1582 case R_ARM_REL32: 1583 case R_ARM_THM_MOVW_PREL_NC: 1584 case R_ARM_THM_MOVT_PREL: 1585 return R_PC; 1586 case R_ARM_NONE: 1587 return R_HINT; 1588 case R_ARM_TLS_LE32: 1589 return R_TLS; 1590 } 1591 } 1592 1593 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const { 1594 if (Type == R_ARM_TARGET1 && !Config->Target1Rel) 1595 return R_ARM_ABS32; 1596 if (Type == R_ARM_ABS32) 1597 return Type; 1598 // Keep it going with a dummy value so that we can find more reloc errors. 1599 errorDynRel(Type); 1600 return R_ARM_ABS32; 1601 } 1602 1603 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1604 write32le(Buf, Out<ELF32LE>::Plt->getVA()); 1605 } 1606 1607 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const { 1608 const uint8_t PltData[] = { 1609 0x04, 0xe0, 0x2d, 0xe5, // str lr, [sp,#-4]! 1610 0x04, 0xe0, 0x9f, 0xe5, // ldr lr, L2 1611 0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr 1612 0x08, 0xf0, 0xbe, 0xe5, // ldr pc, [lr, #8] 1613 0x00, 0x00, 0x00, 0x00, // L2: .word &(.got.plt) - L1 - 8 1614 }; 1615 memcpy(Buf, PltData, sizeof(PltData)); 1616 uint64_t GotPlt = Out<ELF32LE>::GotPlt->getVA(); 1617 uint64_t L1 = Out<ELF32LE>::Plt->getVA() + 8; 1618 write32le(Buf + 16, GotPlt - L1 - 8); 1619 } 1620 1621 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 1622 uint64_t PltEntryAddr, int32_t Index, 1623 unsigned RelOff) const { 1624 // FIXME: Using simple code sequence with simple relocations. 1625 // There is a more optimal sequence but it requires support for the group 1626 // relocations. See ELF for the ARM Architecture Appendix A.3 1627 const uint8_t PltData[] = { 1628 0x04, 0xc0, 0x9f, 0xe5, // ldr ip, L2 1629 0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc 1630 0x00, 0xf0, 0x9c, 0xe5, // ldr pc, [ip] 1631 0x00, 0x00, 0x00, 0x00, // L2: .word Offset(&(.plt.got) - L1 - 8 1632 }; 1633 memcpy(Buf, PltData, sizeof(PltData)); 1634 uint64_t L1 = PltEntryAddr + 4; 1635 write32le(Buf + 12, GotEntryAddr - L1 - 8); 1636 } 1637 1638 RelExpr ARMTargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType, 1639 const InputFile &File, 1640 const SymbolBody &S) const { 1641 // A state change from ARM to Thumb and vice versa must go through an 1642 // interworking thunk if the relocation type is not R_ARM_CALL or 1643 // R_ARM_THM_CALL. 1644 switch (RelocType) { 1645 case R_ARM_PC24: 1646 case R_ARM_PLT32: 1647 case R_ARM_JUMP24: 1648 // Source is ARM, all PLT entries are ARM so no interworking required. 1649 // Otherwise we need to interwork if Symbol has bit 0 set (Thumb). 1650 if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1)) 1651 return R_THUNK_PC; 1652 break; 1653 case R_ARM_THM_JUMP19: 1654 case R_ARM_THM_JUMP24: 1655 // Source is Thumb, all PLT entries are ARM so interworking is required. 1656 // Otherwise we need to interwork if Symbol has bit 0 clear (ARM). 1657 if (Expr == R_PLT_PC) 1658 return R_THUNK_PLT_PC; 1659 if ((S.getVA<ELF32LE>() & 1) == 0) 1660 return R_THUNK_PC; 1661 break; 1662 } 1663 return Expr; 1664 } 1665 1666 void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type, 1667 uint64_t Val) const { 1668 switch (Type) { 1669 case R_ARM_ABS32: 1670 case R_ARM_BASE_PREL: 1671 case R_ARM_GOTOFF32: 1672 case R_ARM_GOT_BREL: 1673 case R_ARM_GOT_PREL: 1674 case R_ARM_REL32: 1675 case R_ARM_TARGET1: 1676 case R_ARM_TARGET2: 1677 case R_ARM_TLS_GD32: 1678 case R_ARM_TLS_IE32: 1679 case R_ARM_TLS_LDM32: 1680 case R_ARM_TLS_LDO32: 1681 case R_ARM_TLS_LE32: 1682 write32le(Loc, Val); 1683 break; 1684 case R_ARM_PREL31: 1685 checkInt<31>(Val, Type); 1686 write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000)); 1687 break; 1688 case R_ARM_CALL: 1689 // R_ARM_CALL is used for BL and BLX instructions, depending on the 1690 // value of bit 0 of Val, we must select a BL or BLX instruction 1691 if (Val & 1) { 1692 // If bit 0 of Val is 1 the target is Thumb, we must select a BLX. 1693 // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1' 1694 checkInt<26>(Val, Type); 1695 write32le(Loc, 0xfa000000 | // opcode 1696 ((Val & 2) << 23) | // H 1697 ((Val >> 2) & 0x00ffffff)); // imm24 1698 break; 1699 } 1700 if ((read32le(Loc) & 0xfe000000) == 0xfa000000) 1701 // BLX (always unconditional) instruction to an ARM Target, select an 1702 // unconditional BL. 1703 write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff)); 1704 // fall through as BL encoding is shared with B 1705 case R_ARM_JUMP24: 1706 case R_ARM_PC24: 1707 case R_ARM_PLT32: 1708 checkInt<26>(Val, Type); 1709 write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff)); 1710 break; 1711 case R_ARM_THM_JUMP11: 1712 checkInt<12>(Val, Type); 1713 write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff)); 1714 break; 1715 case R_ARM_THM_JUMP19: 1716 // Encoding T3: Val = S:J2:J1:imm6:imm11:0 1717 checkInt<21>(Val, Type); 1718 write16le(Loc, 1719 (read16le(Loc) & 0xfbc0) | // opcode cond 1720 ((Val >> 10) & 0x0400) | // S 1721 ((Val >> 12) & 0x003f)); // imm6 1722 write16le(Loc + 2, 1723 0x8000 | // opcode 1724 ((Val >> 8) & 0x0800) | // J2 1725 ((Val >> 5) & 0x2000) | // J1 1726 ((Val >> 1) & 0x07ff)); // imm11 1727 break; 1728 case R_ARM_THM_CALL: 1729 // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the 1730 // value of bit 0 of Val, we must select a BL or BLX instruction 1731 if ((Val & 1) == 0) { 1732 // Ensure BLX destination is 4-byte aligned. As BLX instruction may 1733 // only be two byte aligned. This must be done before overflow check 1734 Val = alignTo(Val, 4); 1735 } 1736 // Bit 12 is 0 for BLX, 1 for BL 1737 write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12); 1738 // Fall through as rest of encoding is the same as B.W 1739 case R_ARM_THM_JUMP24: 1740 // Encoding B T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0 1741 // FIXME: Use of I1 and I2 require v6T2ops 1742 checkInt<25>(Val, Type); 1743 write16le(Loc, 1744 0xf000 | // opcode 1745 ((Val >> 14) & 0x0400) | // S 1746 ((Val >> 12) & 0x03ff)); // imm10 1747 write16le(Loc + 2, 1748 (read16le(Loc + 2) & 0xd000) | // opcode 1749 (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1 1750 (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2 1751 ((Val >> 1) & 0x07ff)); // imm11 1752 break; 1753 case R_ARM_MOVW_ABS_NC: 1754 case R_ARM_MOVW_PREL_NC: 1755 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) | 1756 (Val & 0x0fff)); 1757 break; 1758 case R_ARM_MOVT_ABS: 1759 case R_ARM_MOVT_PREL: 1760 checkInt<32>(Val, Type); 1761 write32le(Loc, (read32le(Loc) & ~0x000f0fff) | 1762 (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff)); 1763 break; 1764 case R_ARM_THM_MOVT_ABS: 1765 case R_ARM_THM_MOVT_PREL: 1766 // Encoding T1: A = imm4:i:imm3:imm8 1767 checkInt<32>(Val, Type); 1768 write16le(Loc, 1769 0xf2c0 | // opcode 1770 ((Val >> 17) & 0x0400) | // i 1771 ((Val >> 28) & 0x000f)); // imm4 1772 write16le(Loc + 2, 1773 (read16le(Loc + 2) & 0x8f00) | // opcode 1774 ((Val >> 12) & 0x7000) | // imm3 1775 ((Val >> 16) & 0x00ff)); // imm8 1776 break; 1777 case R_ARM_THM_MOVW_ABS_NC: 1778 case R_ARM_THM_MOVW_PREL_NC: 1779 // Encoding T3: A = imm4:i:imm3:imm8 1780 write16le(Loc, 1781 0xf240 | // opcode 1782 ((Val >> 1) & 0x0400) | // i 1783 ((Val >> 12) & 0x000f)); // imm4 1784 write16le(Loc + 2, 1785 (read16le(Loc + 2) & 0x8f00) | // opcode 1786 ((Val << 4) & 0x7000) | // imm3 1787 (Val & 0x00ff)); // imm8 1788 break; 1789 default: 1790 fatal("unrecognized reloc " + Twine(Type)); 1791 } 1792 } 1793 1794 uint64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf, 1795 uint32_t Type) const { 1796 switch (Type) { 1797 default: 1798 return 0; 1799 case R_ARM_ABS32: 1800 case R_ARM_BASE_PREL: 1801 case R_ARM_GOTOFF32: 1802 case R_ARM_GOT_BREL: 1803 case R_ARM_GOT_PREL: 1804 case R_ARM_REL32: 1805 case R_ARM_TARGET1: 1806 case R_ARM_TARGET2: 1807 case R_ARM_TLS_GD32: 1808 case R_ARM_TLS_LDM32: 1809 case R_ARM_TLS_LDO32: 1810 case R_ARM_TLS_IE32: 1811 case R_ARM_TLS_LE32: 1812 return SignExtend64<32>(read32le(Buf)); 1813 case R_ARM_PREL31: 1814 return SignExtend64<31>(read32le(Buf)); 1815 case R_ARM_CALL: 1816 case R_ARM_JUMP24: 1817 case R_ARM_PC24: 1818 case R_ARM_PLT32: 1819 return SignExtend64<26>(read32le(Buf) << 2); 1820 case R_ARM_THM_JUMP11: 1821 return SignExtend64<12>(read16le(Buf) << 1); 1822 case R_ARM_THM_JUMP19: { 1823 // Encoding T3: A = S:J2:J1:imm10:imm6:0 1824 uint16_t Hi = read16le(Buf); 1825 uint16_t Lo = read16le(Buf + 2); 1826 return SignExtend64<20>(((Hi & 0x0400) << 10) | // S 1827 ((Lo & 0x0800) << 8) | // J2 1828 ((Lo & 0x2000) << 5) | // J1 1829 ((Hi & 0x003f) << 12) | // imm6 1830 ((Lo & 0x07ff) << 1)); // imm11:0 1831 } 1832 case R_ARM_THM_CALL: 1833 case R_ARM_THM_JUMP24: { 1834 // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0 1835 // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S) 1836 // FIXME: I1 and I2 require v6T2ops 1837 uint16_t Hi = read16le(Buf); 1838 uint16_t Lo = read16le(Buf + 2); 1839 return SignExtend64<24>(((Hi & 0x0400) << 14) | // S 1840 (~((Lo ^ (Hi << 3)) << 10) & 0x00800000) | // I1 1841 (~((Lo ^ (Hi << 1)) << 11) & 0x00400000) | // I2 1842 ((Hi & 0x003ff) << 12) | // imm0 1843 ((Lo & 0x007ff) << 1)); // imm11:0 1844 } 1845 // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and 1846 // MOVT is in the range -32768 <= A < 32768 1847 case R_ARM_MOVW_ABS_NC: 1848 case R_ARM_MOVT_ABS: 1849 case R_ARM_MOVW_PREL_NC: 1850 case R_ARM_MOVT_PREL: { 1851 uint64_t Val = read32le(Buf) & 0x000f0fff; 1852 return SignExtend64<16>(((Val & 0x000f0000) >> 4) | (Val & 0x00fff)); 1853 } 1854 case R_ARM_THM_MOVW_ABS_NC: 1855 case R_ARM_THM_MOVT_ABS: 1856 case R_ARM_THM_MOVW_PREL_NC: 1857 case R_ARM_THM_MOVT_PREL: { 1858 // Encoding T3: A = imm4:i:imm3:imm8 1859 uint16_t Hi = read16le(Buf); 1860 uint16_t Lo = read16le(Buf + 2); 1861 return SignExtend64<16>(((Hi & 0x000f) << 12) | // imm4 1862 ((Hi & 0x0400) << 1) | // i 1863 ((Lo & 0x7000) >> 4) | // imm3 1864 (Lo & 0x00ff)); // imm8 1865 } 1866 } 1867 } 1868 1869 bool ARMTargetInfo::isTlsLocalDynamicRel(uint32_t Type) const { 1870 return Type == R_ARM_TLS_LDO32 || Type == R_ARM_TLS_LDM32; 1871 } 1872 1873 bool ARMTargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const { 1874 return Type == R_ARM_TLS_GD32; 1875 } 1876 1877 bool ARMTargetInfo::isTlsInitialExecRel(uint32_t Type) const { 1878 return Type == R_ARM_TLS_IE32; 1879 } 1880 1881 template <class ELFT> MipsTargetInfo<ELFT>::MipsTargetInfo() { 1882 GotPltHeaderEntriesNum = 2; 1883 MaxPageSize = 65536; 1884 GotEntrySize = sizeof(typename ELFT::uint); 1885 GotPltEntrySize = sizeof(typename ELFT::uint); 1886 PltEntrySize = 16; 1887 PltHeaderSize = 32; 1888 CopyRel = R_MIPS_COPY; 1889 PltRel = R_MIPS_JUMP_SLOT; 1890 NeedsThunks = true; 1891 if (ELFT::Is64Bits) { 1892 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 1893 TlsGotRel = R_MIPS_TLS_TPREL64; 1894 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 1895 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 1896 } else { 1897 RelativeRel = R_MIPS_REL32; 1898 TlsGotRel = R_MIPS_TLS_TPREL32; 1899 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 1900 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 1901 } 1902 } 1903 1904 template <class ELFT> 1905 RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type, 1906 const SymbolBody &S) const { 1907 if (ELFT::Is64Bits) 1908 // See comment in the calculateMips64RelChain. 1909 Type &= 0xff; 1910 switch (Type) { 1911 default: 1912 return R_ABS; 1913 case R_MIPS_JALR: 1914 return R_HINT; 1915 case R_MIPS_GPREL16: 1916 case R_MIPS_GPREL32: 1917 return R_GOTREL; 1918 case R_MIPS_26: 1919 return R_PLT; 1920 case R_MIPS_HI16: 1921 case R_MIPS_LO16: 1922 case R_MIPS_GOT_OFST: 1923 // MIPS _gp_disp designates offset between start of function and 'gp' 1924 // pointer into GOT. __gnu_local_gp is equal to the current value of 1925 // the 'gp'. Therefore any relocations against them do not require 1926 // dynamic relocation. 1927 if (&S == ElfSym<ELFT>::MipsGpDisp) 1928 return R_PC; 1929 return R_ABS; 1930 case R_MIPS_PC32: 1931 case R_MIPS_PC16: 1932 case R_MIPS_PC19_S2: 1933 case R_MIPS_PC21_S2: 1934 case R_MIPS_PC26_S2: 1935 case R_MIPS_PCHI16: 1936 case R_MIPS_PCLO16: 1937 return R_PC; 1938 case R_MIPS_GOT16: 1939 if (S.isLocal()) 1940 return R_MIPS_GOT_LOCAL_PAGE; 1941 // fallthrough 1942 case R_MIPS_CALL16: 1943 case R_MIPS_GOT_DISP: 1944 case R_MIPS_TLS_GOTTPREL: 1945 return R_MIPS_GOT_OFF; 1946 case R_MIPS_CALL_HI16: 1947 case R_MIPS_CALL_LO16: 1948 case R_MIPS_GOT_HI16: 1949 case R_MIPS_GOT_LO16: 1950 return R_MIPS_GOT_OFF32; 1951 case R_MIPS_GOT_PAGE: 1952 return R_MIPS_GOT_LOCAL_PAGE; 1953 case R_MIPS_TLS_GD: 1954 return R_MIPS_TLSGD; 1955 case R_MIPS_TLS_LDM: 1956 return R_MIPS_TLSLD; 1957 } 1958 } 1959 1960 template <class ELFT> 1961 uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const { 1962 if (Type == R_MIPS_32 || Type == R_MIPS_64) 1963 return RelativeRel; 1964 // Keep it going with a dummy value so that we can find more reloc errors. 1965 errorDynRel(Type); 1966 return R_MIPS_32; 1967 } 1968 1969 template <class ELFT> 1970 bool MipsTargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const { 1971 return Type == R_MIPS_TLS_LDM; 1972 } 1973 1974 template <class ELFT> 1975 bool MipsTargetInfo<ELFT>::isTlsGlobalDynamicRel(uint32_t Type) const { 1976 return Type == R_MIPS_TLS_GD; 1977 } 1978 1979 template <class ELFT> 1980 void MipsTargetInfo<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 1981 write32<ELFT::TargetEndianness>(Buf, Out<ELFT>::Plt->getVA()); 1982 } 1983 1984 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 1985 static int64_t getPcRelocAddend(const uint8_t *Loc) { 1986 uint32_t Instr = read32<E>(Loc); 1987 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 1988 return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT); 1989 } 1990 1991 template <endianness E, uint8_t BSIZE, uint8_t SHIFT> 1992 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) { 1993 uint32_t Mask = 0xffffffff >> (32 - BSIZE); 1994 uint32_t Instr = read32<E>(Loc); 1995 if (SHIFT > 0) 1996 checkAlignment<(1 << SHIFT)>(V, Type); 1997 checkInt<BSIZE + SHIFT>(V, Type); 1998 write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask)); 1999 } 2000 2001 template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) { 2002 uint32_t Instr = read32<E>(Loc); 2003 uint16_t Res = ((V + 0x8000) >> 16) & 0xffff; 2004 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2005 } 2006 2007 template <endianness E> static void writeMipsHigher(uint8_t *Loc, uint64_t V) { 2008 uint32_t Instr = read32<E>(Loc); 2009 uint16_t Res = ((V + 0x80008000) >> 32) & 0xffff; 2010 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2011 } 2012 2013 template <endianness E> static void writeMipsHighest(uint8_t *Loc, uint64_t V) { 2014 uint32_t Instr = read32<E>(Loc); 2015 uint16_t Res = ((V + 0x800080008000) >> 48) & 0xffff; 2016 write32<E>(Loc, (Instr & 0xffff0000) | Res); 2017 } 2018 2019 template <endianness E> static void writeMipsLo16(uint8_t *Loc, uint64_t V) { 2020 uint32_t Instr = read32<E>(Loc); 2021 write32<E>(Loc, (Instr & 0xffff0000) | (V & 0xffff)); 2022 } 2023 2024 template <class ELFT> static bool isMipsR6() { 2025 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf); 2026 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH; 2027 return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6; 2028 } 2029 2030 template <class ELFT> 2031 void MipsTargetInfo<ELFT>::writePltHeader(uint8_t *Buf) const { 2032 const endianness E = ELFT::TargetEndianness; 2033 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 2034 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 2035 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 2036 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 2037 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 2038 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 2039 write32<E>(Buf + 24, 0x0320f809); // jalr $25 2040 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 2041 uint64_t Got = Out<ELFT>::GotPlt->getVA(); 2042 writeMipsHi16<E>(Buf, Got); 2043 writeMipsLo16<E>(Buf + 4, Got); 2044 writeMipsLo16<E>(Buf + 8, Got); 2045 } 2046 2047 template <class ELFT> 2048 void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr, 2049 uint64_t PltEntryAddr, int32_t Index, 2050 unsigned RelOff) const { 2051 const endianness E = ELFT::TargetEndianness; 2052 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 2053 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 2054 // jr $25 2055 write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008); 2056 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 2057 writeMipsHi16<E>(Buf, GotEntryAddr); 2058 writeMipsLo16<E>(Buf + 4, GotEntryAddr); 2059 writeMipsLo16<E>(Buf + 12, GotEntryAddr); 2060 } 2061 2062 template <class ELFT> 2063 RelExpr MipsTargetInfo<ELFT>::getThunkExpr(RelExpr Expr, uint32_t Type, 2064 const InputFile &File, 2065 const SymbolBody &S) const { 2066 // Any MIPS PIC code function is invoked with its address in register $t9. 2067 // So if we have a branch instruction from non-PIC code to the PIC one 2068 // we cannot make the jump directly and need to create a small stubs 2069 // to save the target function address. 2070 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 2071 if (Type != R_MIPS_26) 2072 return Expr; 2073 auto *F = dyn_cast<ELFFileBase<ELFT>>(&File); 2074 if (!F) 2075 return Expr; 2076 // If current file has PIC code, LA25 stub is not required. 2077 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 2078 return Expr; 2079 auto *D = dyn_cast<DefinedRegular<ELFT>>(&S); 2080 // LA25 is required if target file has PIC code 2081 // or target symbol is a PIC symbol. 2082 return D && D->isMipsPIC() ? R_THUNK_ABS : Expr; 2083 } 2084 2085 template <class ELFT> 2086 uint64_t MipsTargetInfo<ELFT>::getImplicitAddend(const uint8_t *Buf, 2087 uint32_t Type) const { 2088 const endianness E = ELFT::TargetEndianness; 2089 switch (Type) { 2090 default: 2091 return 0; 2092 case R_MIPS_32: 2093 case R_MIPS_GPREL32: 2094 case R_MIPS_TLS_DTPREL32: 2095 case R_MIPS_TLS_TPREL32: 2096 return read32<E>(Buf); 2097 case R_MIPS_26: 2098 // FIXME (simon): If the relocation target symbol is not a PLT entry 2099 // we should use another expression for calculation: 2100 // ((A << 2) | (P & 0xf0000000)) >> 2 2101 return SignExtend64<28>((read32<E>(Buf) & 0x3ffffff) << 2); 2102 case R_MIPS_GPREL16: 2103 case R_MIPS_LO16: 2104 case R_MIPS_PCLO16: 2105 case R_MIPS_TLS_DTPREL_HI16: 2106 case R_MIPS_TLS_DTPREL_LO16: 2107 case R_MIPS_TLS_TPREL_HI16: 2108 case R_MIPS_TLS_TPREL_LO16: 2109 return SignExtend64<16>(read32<E>(Buf)); 2110 case R_MIPS_PC16: 2111 return getPcRelocAddend<E, 16, 2>(Buf); 2112 case R_MIPS_PC19_S2: 2113 return getPcRelocAddend<E, 19, 2>(Buf); 2114 case R_MIPS_PC21_S2: 2115 return getPcRelocAddend<E, 21, 2>(Buf); 2116 case R_MIPS_PC26_S2: 2117 return getPcRelocAddend<E, 26, 2>(Buf); 2118 case R_MIPS_PC32: 2119 return getPcRelocAddend<E, 32, 0>(Buf); 2120 } 2121 } 2122 2123 static std::pair<uint32_t, uint64_t> calculateMips64RelChain(uint32_t Type, 2124 uint64_t Val) { 2125 // MIPS N64 ABI packs multiple relocations into the single relocation 2126 // record. In general, all up to three relocations can have arbitrary 2127 // types. In fact, Clang and GCC uses only a few combinations. For now, 2128 // we support two of them. That is allow to pass at least all LLVM 2129 // test suite cases. 2130 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 2131 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 2132 // The first relocation is a 'real' relocation which is calculated 2133 // using the corresponding symbol's value. The second and the third 2134 // relocations used to modify result of the first one: extend it to 2135 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 2136 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 2137 uint32_t Type2 = (Type >> 8) & 0xff; 2138 uint32_t Type3 = (Type >> 16) & 0xff; 2139 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 2140 return std::make_pair(Type, Val); 2141 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 2142 return std::make_pair(Type2, Val); 2143 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 2144 return std::make_pair(Type3, -Val); 2145 error("unsupported relocations combination " + Twine(Type)); 2146 return std::make_pair(Type & 0xff, Val); 2147 } 2148 2149 template <class ELFT> 2150 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, 2151 uint64_t Val) const { 2152 const endianness E = ELFT::TargetEndianness; 2153 // Thread pointer and DRP offsets from the start of TLS data area. 2154 // https://www.linux-mips.org/wiki/NPTL 2155 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 2156 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64) 2157 Val -= 0x8000; 2158 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 2159 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64) 2160 Val -= 0x7000; 2161 if (ELFT::Is64Bits) 2162 std::tie(Type, Val) = calculateMips64RelChain(Type, Val); 2163 switch (Type) { 2164 case R_MIPS_32: 2165 case R_MIPS_GPREL32: 2166 case R_MIPS_TLS_DTPREL32: 2167 case R_MIPS_TLS_TPREL32: 2168 write32<E>(Loc, Val); 2169 break; 2170 case R_MIPS_64: 2171 case R_MIPS_TLS_DTPREL64: 2172 case R_MIPS_TLS_TPREL64: 2173 write64<E>(Loc, Val); 2174 break; 2175 case R_MIPS_26: 2176 write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff)); 2177 break; 2178 case R_MIPS_GOT_DISP: 2179 case R_MIPS_GOT_PAGE: 2180 case R_MIPS_GOT16: 2181 case R_MIPS_GPREL16: 2182 case R_MIPS_TLS_GD: 2183 case R_MIPS_TLS_LDM: 2184 checkInt<16>(Val, Type); 2185 // fallthrough 2186 case R_MIPS_CALL16: 2187 case R_MIPS_CALL_LO16: 2188 case R_MIPS_GOT_LO16: 2189 case R_MIPS_GOT_OFST: 2190 case R_MIPS_LO16: 2191 case R_MIPS_PCLO16: 2192 case R_MIPS_TLS_DTPREL_LO16: 2193 case R_MIPS_TLS_GOTTPREL: 2194 case R_MIPS_TLS_TPREL_LO16: 2195 writeMipsLo16<E>(Loc, Val); 2196 break; 2197 case R_MIPS_CALL_HI16: 2198 case R_MIPS_GOT_HI16: 2199 case R_MIPS_HI16: 2200 case R_MIPS_PCHI16: 2201 case R_MIPS_TLS_DTPREL_HI16: 2202 case R_MIPS_TLS_TPREL_HI16: 2203 writeMipsHi16<E>(Loc, Val); 2204 break; 2205 case R_MIPS_HIGHER: 2206 writeMipsHigher<E>(Loc, Val); 2207 break; 2208 case R_MIPS_HIGHEST: 2209 writeMipsHighest<E>(Loc, Val); 2210 break; 2211 case R_MIPS_JALR: 2212 // Ignore this optimization relocation for now 2213 break; 2214 case R_MIPS_PC16: 2215 applyMipsPcReloc<E, 16, 2>(Loc, Type, Val); 2216 break; 2217 case R_MIPS_PC19_S2: 2218 applyMipsPcReloc<E, 19, 2>(Loc, Type, Val); 2219 break; 2220 case R_MIPS_PC21_S2: 2221 applyMipsPcReloc<E, 21, 2>(Loc, Type, Val); 2222 break; 2223 case R_MIPS_PC26_S2: 2224 applyMipsPcReloc<E, 26, 2>(Loc, Type, Val); 2225 break; 2226 case R_MIPS_PC32: 2227 applyMipsPcReloc<E, 32, 0>(Loc, Type, Val); 2228 break; 2229 default: 2230 fatal("unrecognized reloc " + Twine(Type)); 2231 } 2232 } 2233 2234 template <class ELFT> 2235 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const { 2236 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST; 2237 } 2238 } 2239 } 2240