1 //===- RISCV.cpp ----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 14 using namespace llvm; 15 using namespace llvm::object; 16 using namespace llvm::support::endian; 17 using namespace llvm::ELF; 18 19 namespace lld { 20 namespace elf { 21 22 namespace { 23 24 class RISCV final : public TargetInfo { 25 public: 26 RISCV(); 27 uint32_t calcEFlags() const override; 28 void writeGotHeader(uint8_t *buf) const override; 29 void writeGotPlt(uint8_t *buf, const Symbol &s) const override; 30 void writePltHeader(uint8_t *buf) const override; 31 void writePlt(uint8_t *buf, const Symbol &sym, 32 uint64_t pltEntryAddr) const override; 33 RelType getDynRel(RelType type) const override; 34 RelExpr getRelExpr(RelType type, const Symbol &s, 35 const uint8_t *loc) const override; 36 void relocate(uint8_t *loc, const Relocation &rel, 37 uint64_t val) const override; 38 }; 39 40 } // end anonymous namespace 41 42 const uint64_t dtpOffset = 0x800; 43 44 enum Op { 45 ADDI = 0x13, 46 AUIPC = 0x17, 47 JALR = 0x67, 48 LD = 0x3003, 49 LW = 0x2003, 50 SRLI = 0x5013, 51 SUB = 0x40000033, 52 }; 53 54 enum Reg { 55 X_RA = 1, 56 X_T0 = 5, 57 X_T1 = 6, 58 X_T2 = 7, 59 X_T3 = 28, 60 }; 61 62 static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; } 63 static uint32_t lo12(uint32_t val) { return val & 4095; } 64 65 static uint32_t itype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t imm) { 66 return op | (rd << 7) | (rs1 << 15) | (imm << 20); 67 } 68 static uint32_t rtype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t rs2) { 69 return op | (rd << 7) | (rs1 << 15) | (rs2 << 20); 70 } 71 static uint32_t utype(uint32_t op, uint32_t rd, uint32_t imm) { 72 return op | (rd << 7) | (imm << 12); 73 } 74 75 RISCV::RISCV() { 76 copyRel = R_RISCV_COPY; 77 noneRel = R_RISCV_NONE; 78 pltRel = R_RISCV_JUMP_SLOT; 79 relativeRel = R_RISCV_RELATIVE; 80 iRelativeRel = R_RISCV_IRELATIVE; 81 if (config->is64) { 82 symbolicRel = R_RISCV_64; 83 tlsModuleIndexRel = R_RISCV_TLS_DTPMOD64; 84 tlsOffsetRel = R_RISCV_TLS_DTPREL64; 85 tlsGotRel = R_RISCV_TLS_TPREL64; 86 } else { 87 symbolicRel = R_RISCV_32; 88 tlsModuleIndexRel = R_RISCV_TLS_DTPMOD32; 89 tlsOffsetRel = R_RISCV_TLS_DTPREL32; 90 tlsGotRel = R_RISCV_TLS_TPREL32; 91 } 92 gotRel = symbolicRel; 93 94 // .got[0] = _DYNAMIC 95 gotBaseSymInGotPlt = false; 96 gotHeaderEntriesNum = 1; 97 98 // .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map 99 gotPltHeaderEntriesNum = 2; 100 101 pltHeaderSize = 32; 102 pltEntrySize = 16; 103 ipltEntrySize = 16; 104 } 105 106 static uint32_t getEFlags(InputFile *f) { 107 if (config->is64) 108 return cast<ObjFile<ELF64LE>>(f)->getObj().getHeader()->e_flags; 109 return cast<ObjFile<ELF32LE>>(f)->getObj().getHeader()->e_flags; 110 } 111 112 uint32_t RISCV::calcEFlags() const { 113 // If there are only binary input files (from -b binary), use a 114 // value of 0 for the ELF header flags. 115 if (objectFiles.empty()) 116 return 0; 117 118 uint32_t target = getEFlags(objectFiles.front()); 119 120 for (InputFile *f : objectFiles) { 121 uint32_t eflags = getEFlags(f); 122 if (eflags & EF_RISCV_RVC) 123 target |= EF_RISCV_RVC; 124 125 if ((eflags & EF_RISCV_FLOAT_ABI) != (target & EF_RISCV_FLOAT_ABI)) 126 error(toString(f) + 127 ": cannot link object files with different floating-point ABI"); 128 129 if ((eflags & EF_RISCV_RVE) != (target & EF_RISCV_RVE)) 130 error(toString(f) + 131 ": cannot link object files with different EF_RISCV_RVE"); 132 } 133 134 return target; 135 } 136 137 void RISCV::writeGotHeader(uint8_t *buf) const { 138 if (config->is64) 139 write64le(buf, mainPart->dynamic->getVA()); 140 else 141 write32le(buf, mainPart->dynamic->getVA()); 142 } 143 144 void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const { 145 if (config->is64) 146 write64le(buf, in.plt->getVA()); 147 else 148 write32le(buf, in.plt->getVA()); 149 } 150 151 void RISCV::writePltHeader(uint8_t *buf) const { 152 // 1: auipc t2, %pcrel_hi(.got.plt) 153 // sub t1, t1, t3 154 // l[wd] t3, %pcrel_lo(1b)(t2); t3 = _dl_runtime_resolve 155 // addi t1, t1, -pltHeaderSize-12; t1 = &.plt[i] - &.plt[0] 156 // addi t0, t2, %pcrel_lo(1b) 157 // srli t1, t1, (rv64?1:2); t1 = &.got.plt[i] - &.got.plt[0] 158 // l[wd] t0, Wordsize(t0); t0 = link_map 159 // jr t3 160 uint32_t offset = in.gotPlt->getVA() - in.plt->getVA(); 161 uint32_t load = config->is64 ? LD : LW; 162 write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset))); 163 write32le(buf + 4, rtype(SUB, X_T1, X_T1, X_T3)); 164 write32le(buf + 8, itype(load, X_T3, X_T2, lo12(offset))); 165 write32le(buf + 12, itype(ADDI, X_T1, X_T1, -target->pltHeaderSize - 12)); 166 write32le(buf + 16, itype(ADDI, X_T0, X_T2, lo12(offset))); 167 write32le(buf + 20, itype(SRLI, X_T1, X_T1, config->is64 ? 1 : 2)); 168 write32le(buf + 24, itype(load, X_T0, X_T0, config->wordsize)); 169 write32le(buf + 28, itype(JALR, 0, X_T3, 0)); 170 } 171 172 void RISCV::writePlt(uint8_t *buf, const Symbol &sym, 173 uint64_t pltEntryAddr) const { 174 // 1: auipc t3, %pcrel_hi([email protected]) 175 // l[wd] t3, %pcrel_lo(1b)(t3) 176 // jalr t1, t3 177 // nop 178 uint32_t offset = sym.getGotPltVA() - pltEntryAddr; 179 write32le(buf + 0, utype(AUIPC, X_T3, hi20(offset))); 180 write32le(buf + 4, itype(config->is64 ? LD : LW, X_T3, X_T3, lo12(offset))); 181 write32le(buf + 8, itype(JALR, X_T1, X_T3, 0)); 182 write32le(buf + 12, itype(ADDI, 0, 0, 0)); 183 } 184 185 RelType RISCV::getDynRel(RelType type) const { 186 return type == target->symbolicRel ? type 187 : static_cast<RelType>(R_RISCV_NONE); 188 } 189 190 RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s, 191 const uint8_t *loc) const { 192 switch (type) { 193 case R_RISCV_NONE: 194 return R_NONE; 195 case R_RISCV_32: 196 case R_RISCV_64: 197 case R_RISCV_HI20: 198 case R_RISCV_LO12_I: 199 case R_RISCV_LO12_S: 200 case R_RISCV_RVC_LUI: 201 return R_ABS; 202 case R_RISCV_ADD8: 203 case R_RISCV_ADD16: 204 case R_RISCV_ADD32: 205 case R_RISCV_ADD64: 206 case R_RISCV_SET6: 207 case R_RISCV_SET8: 208 case R_RISCV_SET16: 209 case R_RISCV_SET32: 210 case R_RISCV_SUB6: 211 case R_RISCV_SUB8: 212 case R_RISCV_SUB16: 213 case R_RISCV_SUB32: 214 case R_RISCV_SUB64: 215 return R_RISCV_ADD; 216 case R_RISCV_JAL: 217 case R_RISCV_BRANCH: 218 case R_RISCV_PCREL_HI20: 219 case R_RISCV_RVC_BRANCH: 220 case R_RISCV_RVC_JUMP: 221 case R_RISCV_32_PCREL: 222 return R_PC; 223 case R_RISCV_CALL: 224 case R_RISCV_CALL_PLT: 225 return R_PLT_PC; 226 case R_RISCV_GOT_HI20: 227 return R_GOT_PC; 228 case R_RISCV_PCREL_LO12_I: 229 case R_RISCV_PCREL_LO12_S: 230 return R_RISCV_PC_INDIRECT; 231 case R_RISCV_TLS_GD_HI20: 232 return R_TLSGD_PC; 233 case R_RISCV_TLS_GOT_HI20: 234 config->hasStaticTlsModel = true; 235 return R_GOT_PC; 236 case R_RISCV_TPREL_HI20: 237 case R_RISCV_TPREL_LO12_I: 238 case R_RISCV_TPREL_LO12_S: 239 return R_TLS; 240 case R_RISCV_RELAX: 241 case R_RISCV_TPREL_ADD: 242 return R_NONE; 243 case R_RISCV_ALIGN: 244 // Not just a hint; always padded to the worst-case number of NOPs, so may 245 // not currently be aligned, and without linker relaxation support we can't 246 // delete NOPs to realign. 247 errorOrWarn(getErrorLocation(loc) + "relocation R_RISCV_ALIGN requires " 248 "unimplemented linker relaxation; recompile with -mno-relax"); 249 return R_NONE; 250 default: 251 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 252 ") against symbol " + toString(s)); 253 return R_NONE; 254 } 255 } 256 257 // Extract bits V[Begin:End], where range is inclusive, and Begin must be < 63. 258 static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) { 259 return (v & ((1ULL << (begin + 1)) - 1)) >> end; 260 } 261 262 void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { 263 const unsigned bits = config->wordsize * 8; 264 265 switch (rel.type) { 266 case R_RISCV_32: 267 write32le(loc, val); 268 return; 269 case R_RISCV_64: 270 write64le(loc, val); 271 return; 272 273 case R_RISCV_RVC_BRANCH: { 274 checkInt(loc, static_cast<int64_t>(val) >> 1, 8, rel); 275 checkAlignment(loc, val, 2, rel); 276 uint16_t insn = read16le(loc) & 0xE383; 277 uint16_t imm8 = extractBits(val, 8, 8) << 12; 278 uint16_t imm4_3 = extractBits(val, 4, 3) << 10; 279 uint16_t imm7_6 = extractBits(val, 7, 6) << 5; 280 uint16_t imm2_1 = extractBits(val, 2, 1) << 3; 281 uint16_t imm5 = extractBits(val, 5, 5) << 2; 282 insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5; 283 284 write16le(loc, insn); 285 return; 286 } 287 288 case R_RISCV_RVC_JUMP: { 289 checkInt(loc, static_cast<int64_t>(val) >> 1, 11, rel); 290 checkAlignment(loc, val, 2, rel); 291 uint16_t insn = read16le(loc) & 0xE003; 292 uint16_t imm11 = extractBits(val, 11, 11) << 12; 293 uint16_t imm4 = extractBits(val, 4, 4) << 11; 294 uint16_t imm9_8 = extractBits(val, 9, 8) << 9; 295 uint16_t imm10 = extractBits(val, 10, 10) << 8; 296 uint16_t imm6 = extractBits(val, 6, 6) << 7; 297 uint16_t imm7 = extractBits(val, 7, 7) << 6; 298 uint16_t imm3_1 = extractBits(val, 3, 1) << 3; 299 uint16_t imm5 = extractBits(val, 5, 5) << 2; 300 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; 301 302 write16le(loc, insn); 303 return; 304 } 305 306 case R_RISCV_RVC_LUI: { 307 int64_t imm = SignExtend64(val + 0x800, bits) >> 12; 308 checkInt(loc, imm, 6, rel); 309 if (imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0` 310 write16le(loc, (read16le(loc) & 0x0F83) | 0x4000); 311 } else { 312 uint16_t imm17 = extractBits(val + 0x800, 17, 17) << 12; 313 uint16_t imm16_12 = extractBits(val + 0x800, 16, 12) << 2; 314 write16le(loc, (read16le(loc) & 0xEF83) | imm17 | imm16_12); 315 } 316 return; 317 } 318 319 case R_RISCV_JAL: { 320 checkInt(loc, static_cast<int64_t>(val) >> 1, 20, rel); 321 checkAlignment(loc, val, 2, rel); 322 323 uint32_t insn = read32le(loc) & 0xFFF; 324 uint32_t imm20 = extractBits(val, 20, 20) << 31; 325 uint32_t imm10_1 = extractBits(val, 10, 1) << 21; 326 uint32_t imm11 = extractBits(val, 11, 11) << 20; 327 uint32_t imm19_12 = extractBits(val, 19, 12) << 12; 328 insn |= imm20 | imm10_1 | imm11 | imm19_12; 329 330 write32le(loc, insn); 331 return; 332 } 333 334 case R_RISCV_BRANCH: { 335 checkInt(loc, static_cast<int64_t>(val) >> 1, 12, rel); 336 checkAlignment(loc, val, 2, rel); 337 338 uint32_t insn = read32le(loc) & 0x1FFF07F; 339 uint32_t imm12 = extractBits(val, 12, 12) << 31; 340 uint32_t imm10_5 = extractBits(val, 10, 5) << 25; 341 uint32_t imm4_1 = extractBits(val, 4, 1) << 8; 342 uint32_t imm11 = extractBits(val, 11, 11) << 7; 343 insn |= imm12 | imm10_5 | imm4_1 | imm11; 344 345 write32le(loc, insn); 346 return; 347 } 348 349 // auipc + jalr pair 350 case R_RISCV_CALL: 351 case R_RISCV_CALL_PLT: { 352 int64_t hi = SignExtend64(val + 0x800, bits) >> 12; 353 checkInt(loc, hi, 20, rel); 354 if (isInt<20>(hi)) { 355 relocateNoSym(loc, R_RISCV_PCREL_HI20, val); 356 relocateNoSym(loc + 4, R_RISCV_PCREL_LO12_I, val); 357 } 358 return; 359 } 360 361 case R_RISCV_GOT_HI20: 362 case R_RISCV_PCREL_HI20: 363 case R_RISCV_TLS_GD_HI20: 364 case R_RISCV_TLS_GOT_HI20: 365 case R_RISCV_TPREL_HI20: 366 case R_RISCV_HI20: { 367 uint64_t hi = val + 0x800; 368 checkInt(loc, SignExtend64(hi, bits) >> 12, 20, rel); 369 write32le(loc, (read32le(loc) & 0xFFF) | (hi & 0xFFFFF000)); 370 return; 371 } 372 373 case R_RISCV_PCREL_LO12_I: 374 case R_RISCV_TPREL_LO12_I: 375 case R_RISCV_LO12_I: { 376 uint64_t hi = (val + 0x800) >> 12; 377 uint64_t lo = val - (hi << 12); 378 write32le(loc, (read32le(loc) & 0xFFFFF) | ((lo & 0xFFF) << 20)); 379 return; 380 } 381 382 case R_RISCV_PCREL_LO12_S: 383 case R_RISCV_TPREL_LO12_S: 384 case R_RISCV_LO12_S: { 385 uint64_t hi = (val + 0x800) >> 12; 386 uint64_t lo = val - (hi << 12); 387 uint32_t imm11_5 = extractBits(lo, 11, 5) << 25; 388 uint32_t imm4_0 = extractBits(lo, 4, 0) << 7; 389 write32le(loc, (read32le(loc) & 0x1FFF07F) | imm11_5 | imm4_0); 390 return; 391 } 392 393 case R_RISCV_ADD8: 394 *loc += val; 395 return; 396 case R_RISCV_ADD16: 397 write16le(loc, read16le(loc) + val); 398 return; 399 case R_RISCV_ADD32: 400 write32le(loc, read32le(loc) + val); 401 return; 402 case R_RISCV_ADD64: 403 write64le(loc, read64le(loc) + val); 404 return; 405 case R_RISCV_SUB6: 406 *loc = (*loc & 0xc0) | (((*loc & 0x3f) - val) & 0x3f); 407 return; 408 case R_RISCV_SUB8: 409 *loc -= val; 410 return; 411 case R_RISCV_SUB16: 412 write16le(loc, read16le(loc) - val); 413 return; 414 case R_RISCV_SUB32: 415 write32le(loc, read32le(loc) - val); 416 return; 417 case R_RISCV_SUB64: 418 write64le(loc, read64le(loc) - val); 419 return; 420 case R_RISCV_SET6: 421 *loc = (*loc & 0xc0) | (val & 0x3f); 422 return; 423 case R_RISCV_SET8: 424 *loc = val; 425 return; 426 case R_RISCV_SET16: 427 write16le(loc, val); 428 return; 429 case R_RISCV_SET32: 430 case R_RISCV_32_PCREL: 431 write32le(loc, val); 432 return; 433 434 case R_RISCV_TLS_DTPREL32: 435 write32le(loc, val - dtpOffset); 436 break; 437 case R_RISCV_TLS_DTPREL64: 438 write64le(loc, val - dtpOffset); 439 break; 440 441 case R_RISCV_RELAX: 442 return; // Ignored (for now) 443 444 default: 445 llvm_unreachable("unknown relocation"); 446 } 447 } 448 449 TargetInfo *getRISCVTargetInfo() { 450 static RISCV target; 451 return ⌖ 452 } 453 454 } // namespace elf 455 } // namespace lld 456