1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Error.h" 11 #include "InputFiles.h" 12 #include "OutputSections.h" 13 #include "Symbols.h" 14 #include "SyntheticSections.h" 15 #include "Target.h" 16 #include "Thunks.h" 17 #include "llvm/Object/ELF.h" 18 #include "llvm/Support/Endian.h" 19 20 using namespace llvm; 21 using namespace llvm::object; 22 using namespace llvm::support::endian; 23 using namespace llvm::ELF; 24 using namespace lld; 25 using namespace lld::elf; 26 27 namespace { 28 template <class ELFT> class MIPS final : public TargetInfo { 29 public: 30 MIPS(); 31 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, const InputFile &File, 32 const uint8_t *Loc) const override; 33 int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 34 bool isPicRel(uint32_t Type) const override; 35 uint32_t getDynRel(uint32_t Type) const override; 36 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 37 void writePltHeader(uint8_t *Buf) const override; 38 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 39 int32_t Index, unsigned RelOff) const override; 40 bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File, 41 const SymbolBody &S) const override; 42 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 43 bool usesOnlyLowPageBits(uint32_t Type) const override; 44 }; 45 } // namespace 46 47 template <class ELFT> MIPS<ELFT>::MIPS() { 48 GotPltHeaderEntriesNum = 2; 49 DefaultMaxPageSize = 65536; 50 GotEntrySize = sizeof(typename ELFT::uint); 51 GotPltEntrySize = sizeof(typename ELFT::uint); 52 PltEntrySize = 16; 53 PltHeaderSize = 32; 54 CopyRel = R_MIPS_COPY; 55 PltRel = R_MIPS_JUMP_SLOT; 56 NeedsThunks = true; 57 TrapInstr = 0xefefefef; 58 59 if (ELFT::Is64Bits) { 60 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 61 TlsGotRel = R_MIPS_TLS_TPREL64; 62 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 63 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 64 } else { 65 RelativeRel = R_MIPS_REL32; 66 TlsGotRel = R_MIPS_TLS_TPREL32; 67 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 68 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 69 } 70 } 71 72 template <class ELFT> 73 RelExpr MIPS<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S, 74 const InputFile &File, 75 const uint8_t *Loc) const { 76 // See comment in the calculateMipsRelChain. 77 if (ELFT::Is64Bits || Config->MipsN32Abi) 78 Type &= 0xff; 79 switch (Type) { 80 case R_MIPS_JALR: 81 case R_MICROMIPS_JALR: 82 return R_HINT; 83 case R_MIPS_GPREL16: 84 case R_MIPS_GPREL32: 85 case R_MICROMIPS_GPREL16: 86 case R_MICROMIPS_GPREL7_S2: 87 return R_MIPS_GOTREL; 88 case R_MIPS_26: 89 case R_MICROMIPS_26_S1: 90 return R_PLT; 91 case R_MICROMIPS_PC26_S1: 92 return R_PLT_PC; 93 case R_MIPS_HI16: 94 case R_MIPS_LO16: 95 case R_MIPS_HIGHER: 96 case R_MIPS_HIGHEST: 97 case R_MICROMIPS_HI16: 98 case R_MICROMIPS_LO16: 99 case R_MICROMIPS_HIGHER: 100 case R_MICROMIPS_HIGHEST: 101 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 102 // offset between start of function and 'gp' value which by default 103 // equal to the start of .got section. In that case we consider these 104 // relocations as relative. 105 if (&S == ElfSym::MipsGpDisp) 106 return R_MIPS_GOT_GP_PC; 107 if (&S == ElfSym::MipsLocalGp) 108 return R_MIPS_GOT_GP; 109 LLVM_FALLTHROUGH; 110 case R_MIPS_32: 111 case R_MIPS_64: 112 case R_MIPS_GOT_OFST: 113 case R_MIPS_SUB: 114 case R_MIPS_TLS_DTPREL_HI16: 115 case R_MIPS_TLS_DTPREL_LO16: 116 case R_MIPS_TLS_DTPREL32: 117 case R_MIPS_TLS_DTPREL64: 118 case R_MIPS_TLS_TPREL_HI16: 119 case R_MIPS_TLS_TPREL_LO16: 120 case R_MIPS_TLS_TPREL32: 121 case R_MIPS_TLS_TPREL64: 122 case R_MICROMIPS_GOT_OFST: 123 case R_MICROMIPS_SUB: 124 case R_MICROMIPS_TLS_DTPREL_HI16: 125 case R_MICROMIPS_TLS_DTPREL_LO16: 126 case R_MICROMIPS_TLS_TPREL_HI16: 127 case R_MICROMIPS_TLS_TPREL_LO16: 128 return R_ABS; 129 case R_MIPS_PC32: 130 case R_MIPS_PC16: 131 case R_MIPS_PC19_S2: 132 case R_MIPS_PC21_S2: 133 case R_MIPS_PC26_S2: 134 case R_MIPS_PCHI16: 135 case R_MIPS_PCLO16: 136 case R_MICROMIPS_PC7_S1: 137 case R_MICROMIPS_PC10_S1: 138 case R_MICROMIPS_PC16_S1: 139 case R_MICROMIPS_PC18_S3: 140 case R_MICROMIPS_PC19_S2: 141 case R_MICROMIPS_PC23_S2: 142 case R_MICROMIPS_PC21_S1: 143 return R_PC; 144 case R_MIPS_GOT16: 145 case R_MICROMIPS_GOT16: 146 if (S.isLocal()) 147 return R_MIPS_GOT_LOCAL_PAGE; 148 LLVM_FALLTHROUGH; 149 case R_MIPS_CALL16: 150 case R_MIPS_GOT_DISP: 151 case R_MIPS_TLS_GOTTPREL: 152 case R_MICROMIPS_CALL16: 153 case R_MICROMIPS_GOT_DISP: 154 case R_MICROMIPS_TLS_GOTTPREL: 155 return R_MIPS_GOT_OFF; 156 case R_MIPS_CALL_HI16: 157 case R_MIPS_CALL_LO16: 158 case R_MIPS_GOT_HI16: 159 case R_MIPS_GOT_LO16: 160 case R_MICROMIPS_CALL_HI16: 161 case R_MICROMIPS_CALL_LO16: 162 case R_MICROMIPS_GOT_HI16: 163 case R_MICROMIPS_GOT_LO16: 164 return R_MIPS_GOT_OFF32; 165 case R_MIPS_GOT_PAGE: 166 case R_MICROMIPS_GOT_PAGE: 167 return R_MIPS_GOT_LOCAL_PAGE; 168 case R_MIPS_TLS_GD: 169 case R_MICROMIPS_TLS_GD: 170 return R_MIPS_TLSGD; 171 case R_MIPS_TLS_LDM: 172 case R_MICROMIPS_TLS_LDM: 173 return R_MIPS_TLSLD; 174 case R_MIPS_NONE: 175 return R_NONE; 176 default: 177 error("do not know how to handle relocation '" + toString(Type) + "' (" + 178 Twine(Type) + ")"); 179 return R_HINT; 180 } 181 } 182 183 template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const { 184 return Type == R_MIPS_32 || Type == R_MIPS_64; 185 } 186 187 template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const { 188 return RelativeRel; 189 } 190 191 template <class ELFT> 192 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 193 write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA()); 194 } 195 196 template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) { 197 // The major opcode of a microMIPS instruction needs to appear 198 // in the first 16-bit word (lowest address) for efficient hardware 199 // decode so that it knows if the instruction is 16-bit or 32-bit 200 // as early as possible. To do so, little-endian binaries keep 16-bit 201 // words in a big-endian order. That is why we have to swap these 202 // words to get a correct value. 203 uint32_t V = read32<E>(Loc); 204 if (E == support::little) 205 return (V << 16) | (V >> 16); 206 return V; 207 } 208 209 template <endianness E> 210 static void writeRelocation(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 211 uint8_t Shift) { 212 uint32_t Instr = read32<E>(Loc); 213 uint32_t Mask = 0xffffffff >> (32 - BitsSize); 214 uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 215 write32<E>(Loc, Data); 216 } 217 218 template <endianness E> 219 static void writeMicroRelocation32(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 220 uint8_t Shift) { 221 // See comments in readShuffle for purpose of this code. 222 uint16_t *Words = (uint16_t *)Loc; 223 if (E == support::little) 224 std::swap(Words[0], Words[1]); 225 226 writeRelocation<E>(Loc, V, BitsSize, Shift); 227 228 if (E == support::little) 229 std::swap(Words[0], Words[1]); 230 } 231 232 template <endianness E> 233 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 234 uint8_t Shift) { 235 uint16_t Instr = read16<E>(Loc); 236 uint16_t Mask = 0xffff >> (16 - BitsSize); 237 uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 238 write16<E>(Loc, Data); 239 } 240 241 static bool isMicroMips() { return Config->MipsEFlags & EF_MIPS_MICROMIPS; } 242 243 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const { 244 const endianness E = ELFT::TargetEndianness; 245 if (isMicroMips()) { 246 uint64_t GotPlt = In<ELFT>::GotPlt->getVA(); 247 uint64_t Plt = In<ELFT>::Plt->getVA(); 248 // Overwrite trap instructions written by Writer::writeTrapInstr. 249 memset(Buf, 0, PltHeaderSize); 250 251 write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 252 write16<E>(Buf + 4, 0xff23); // lw $25, 0($3) 253 write16<E>(Buf + 8, 0x0535); // subu16 $2, $2, $3 254 write16<E>(Buf + 10, 0x2525); // srl16 $2, $2, 2 255 write16<E>(Buf + 12, 0x3302); // addiu $24, $2, -2 256 write16<E>(Buf + 14, 0xfffe); 257 write16<E>(Buf + 16, 0x0dff); // move $15, $31 258 if (isMipsR6()) { 259 write16<E>(Buf + 18, 0x0f83); // move $28, $3 260 write16<E>(Buf + 20, 0x472b); // jalrc $25 261 write16<E>(Buf + 22, 0x0c00); // nop 262 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt); 263 } else { 264 write16<E>(Buf + 18, 0x45f9); // jalrc $25 265 write16<E>(Buf + 20, 0x0f83); // move $28, $3 266 write16<E>(Buf + 22, 0x0c00); // nop 267 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt); 268 } 269 return; 270 } 271 272 if (Config->MipsN32Abi) { 273 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 274 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 275 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 276 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 277 } else { 278 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 279 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 280 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 281 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 282 } 283 284 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 285 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 286 write32<E>(Buf + 24, 0x0320f809); // jalr $25 287 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 288 289 uint64_t GotPlt = InX::GotPlt->getVA(); 290 writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16); 291 writeRelocation<E>(Buf + 4, GotPlt, 16, 0); 292 writeRelocation<E>(Buf + 8, GotPlt, 16, 0); 293 } 294 295 template <class ELFT> 296 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 297 uint64_t PltEntryAddr, int32_t Index, 298 unsigned RelOff) const { 299 const endianness E = ELFT::TargetEndianness; 300 if (isMicroMips()) { 301 // Overwrite trap instructions written by Writer::writeTrapInstr. 302 memset(Buf, 0, PltEntrySize); 303 304 if (isMipsR6()) { 305 write16<E>(Buf, 0x7840); // addiupc $2, (GOTPLT) - . 306 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 307 write16<E>(Buf + 8, 0x0f02); // move $24, $2 308 write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25 309 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr); 310 } else { 311 write16<E>(Buf, 0x7900); // addiupc $2, (GOTPLT) - . 312 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 313 write16<E>(Buf + 8, 0x4599); // jrc $25 / jr16 $25 314 write16<E>(Buf + 10, 0x0f02); // move $24, $2 315 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr); 316 } 317 return; 318 } 319 320 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 321 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 322 write32<E>(Buf + 8, isMipsR6() ? 0x03200009 : 0x03200008); // jr $25 323 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 324 writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16); 325 writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0); 326 writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0); 327 } 328 329 template <class ELFT> 330 bool MIPS<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, const InputFile *File, 331 const SymbolBody &S) const { 332 // Any MIPS PIC code function is invoked with its address in register $t9. 333 // So if we have a branch instruction from non-PIC code to the PIC one 334 // we cannot make the jump directly and need to create a small stubs 335 // to save the target function address. 336 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 337 if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 && 338 Type != R_MICROMIPS_PC26_S1) 339 return false; 340 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 341 if (!F) 342 return false; 343 // If current file has PIC code, LA25 stub is not required. 344 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 345 return false; 346 auto *D = dyn_cast<DefinedRegular>(&S); 347 // LA25 is required if target file has PIC code 348 // or target symbol is a PIC symbol. 349 return D && D->isMipsPIC<ELFT>(); 350 } 351 352 template <class ELFT> 353 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const { 354 const endianness E = ELFT::TargetEndianness; 355 switch (Type) { 356 default: 357 return 0; 358 case R_MIPS_32: 359 case R_MIPS_GPREL32: 360 case R_MIPS_TLS_DTPREL32: 361 case R_MIPS_TLS_TPREL32: 362 return SignExtend64<32>(read32<E>(Buf)); 363 case R_MIPS_26: 364 // FIXME (simon): If the relocation target symbol is not a PLT entry 365 // we should use another expression for calculation: 366 // ((A << 2) | (P & 0xf0000000)) >> 2 367 return SignExtend64<28>(read32<E>(Buf) << 2); 368 case R_MIPS_GOT16: 369 case R_MIPS_HI16: 370 case R_MIPS_PCHI16: 371 return SignExtend64<16>(read32<E>(Buf)) << 16; 372 case R_MIPS_GPREL16: 373 case R_MIPS_LO16: 374 case R_MIPS_PCLO16: 375 case R_MIPS_TLS_DTPREL_HI16: 376 case R_MIPS_TLS_DTPREL_LO16: 377 case R_MIPS_TLS_TPREL_HI16: 378 case R_MIPS_TLS_TPREL_LO16: 379 return SignExtend64<16>(read32<E>(Buf)); 380 case R_MICROMIPS_GOT16: 381 case R_MICROMIPS_HI16: 382 return SignExtend64<16>(readShuffle<E>(Buf)) << 16; 383 case R_MICROMIPS_GPREL16: 384 case R_MICROMIPS_LO16: 385 case R_MICROMIPS_TLS_DTPREL_HI16: 386 case R_MICROMIPS_TLS_DTPREL_LO16: 387 case R_MICROMIPS_TLS_TPREL_HI16: 388 case R_MICROMIPS_TLS_TPREL_LO16: 389 return SignExtend64<16>(readShuffle<E>(Buf)); 390 case R_MICROMIPS_GPREL7_S2: 391 return SignExtend64<9>(readShuffle<E>(Buf) << 2); 392 case R_MIPS_PC16: 393 return SignExtend64<18>(read32<E>(Buf) << 2); 394 case R_MIPS_PC19_S2: 395 return SignExtend64<21>(read32<E>(Buf) << 2); 396 case R_MIPS_PC21_S2: 397 return SignExtend64<23>(read32<E>(Buf) << 2); 398 case R_MIPS_PC26_S2: 399 return SignExtend64<28>(read32<E>(Buf) << 2); 400 case R_MIPS_PC32: 401 return SignExtend64<32>(read32<E>(Buf)); 402 case R_MICROMIPS_26_S1: 403 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 404 case R_MICROMIPS_PC7_S1: 405 return SignExtend64<8>(read16<E>(Buf) << 1); 406 case R_MICROMIPS_PC10_S1: 407 return SignExtend64<11>(read16<E>(Buf) << 1); 408 case R_MICROMIPS_PC16_S1: 409 return SignExtend64<17>(readShuffle<E>(Buf) << 1); 410 case R_MICROMIPS_PC18_S3: 411 return SignExtend64<21>(readShuffle<E>(Buf) << 3); 412 case R_MICROMIPS_PC19_S2: 413 return SignExtend64<21>(readShuffle<E>(Buf) << 2); 414 case R_MICROMIPS_PC21_S1: 415 return SignExtend64<22>(readShuffle<E>(Buf) << 1); 416 case R_MICROMIPS_PC23_S2: 417 return SignExtend64<25>(readShuffle<E>(Buf) << 2); 418 case R_MICROMIPS_PC26_S1: 419 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 420 } 421 } 422 423 static std::pair<uint32_t, uint64_t> 424 calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) { 425 // MIPS N64 ABI packs multiple relocations into the single relocation 426 // record. In general, all up to three relocations can have arbitrary 427 // types. In fact, Clang and GCC uses only a few combinations. For now, 428 // we support two of them. That is allow to pass at least all LLVM 429 // test suite cases. 430 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 431 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 432 // The first relocation is a 'real' relocation which is calculated 433 // using the corresponding symbol's value. The second and the third 434 // relocations used to modify result of the first one: extend it to 435 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 436 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 437 uint32_t Type2 = (Type >> 8) & 0xff; 438 uint32_t Type3 = (Type >> 16) & 0xff; 439 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 440 return std::make_pair(Type, Val); 441 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 442 return std::make_pair(Type2, Val); 443 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 444 return std::make_pair(Type3, -Val); 445 if (Type2 == R_MICROMIPS_SUB && 446 (Type3 == R_MICROMIPS_HI16 || Type3 == R_MICROMIPS_LO16)) 447 return std::make_pair(Type3, -Val); 448 error(getErrorLocation(Loc) + "unsupported relocations combination " + 449 Twine(Type)); 450 return std::make_pair(Type & 0xff, Val); 451 } 452 453 template <class ELFT> 454 void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const { 455 const endianness E = ELFT::TargetEndianness; 456 // Thread pointer and DRP offsets from the start of TLS data area. 457 // https://www.linux-mips.org/wiki/NPTL 458 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 459 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 || 460 Type == R_MICROMIPS_TLS_DTPREL_HI16 || 461 Type == R_MICROMIPS_TLS_DTPREL_LO16) 462 Val -= 0x8000; 463 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 464 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 || 465 Type == R_MICROMIPS_TLS_TPREL_HI16 || 466 Type == R_MICROMIPS_TLS_TPREL_LO16) 467 Val -= 0x7000; 468 if (ELFT::Is64Bits || Config->MipsN32Abi) 469 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 470 switch (Type) { 471 case R_MIPS_32: 472 case R_MIPS_GPREL32: 473 case R_MIPS_TLS_DTPREL32: 474 case R_MIPS_TLS_TPREL32: 475 write32<E>(Loc, Val); 476 break; 477 case R_MIPS_64: 478 case R_MIPS_TLS_DTPREL64: 479 case R_MIPS_TLS_TPREL64: 480 write64<E>(Loc, Val); 481 break; 482 case R_MIPS_26: 483 writeRelocation<E>(Loc, Val, 26, 2); 484 break; 485 case R_MIPS_GOT16: 486 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 487 // is updated addend (not a GOT index). In that case write high 16 bits 488 // to store a correct addend value. 489 if (Config->Relocatable) { 490 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 491 } else { 492 checkInt<16>(Loc, Val, Type); 493 writeRelocation<E>(Loc, Val, 16, 0); 494 } 495 break; 496 case R_MICROMIPS_GOT16: 497 if (Config->Relocatable) { 498 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 499 } else { 500 checkInt<16>(Loc, Val, Type); 501 writeMicroRelocation32<E>(Loc, Val, 16, 0); 502 } 503 break; 504 case R_MIPS_GOT_DISP: 505 case R_MIPS_GOT_PAGE: 506 case R_MIPS_GPREL16: 507 case R_MIPS_TLS_GD: 508 case R_MIPS_TLS_LDM: 509 checkInt<16>(Loc, Val, Type); 510 LLVM_FALLTHROUGH; 511 case R_MIPS_CALL16: 512 case R_MIPS_CALL_LO16: 513 case R_MIPS_GOT_LO16: 514 case R_MIPS_GOT_OFST: 515 case R_MIPS_LO16: 516 case R_MIPS_PCLO16: 517 case R_MIPS_TLS_DTPREL_LO16: 518 case R_MIPS_TLS_GOTTPREL: 519 case R_MIPS_TLS_TPREL_LO16: 520 writeRelocation<E>(Loc, Val, 16, 0); 521 break; 522 case R_MICROMIPS_GOT_DISP: 523 case R_MICROMIPS_GOT_PAGE: 524 case R_MICROMIPS_GPREL16: 525 case R_MICROMIPS_TLS_GD: 526 case R_MICROMIPS_TLS_LDM: 527 checkInt<16>(Loc, Val, Type); 528 writeMicroRelocation32<E>(Loc, Val, 16, 0); 529 break; 530 case R_MICROMIPS_CALL16: 531 case R_MICROMIPS_CALL_LO16: 532 case R_MICROMIPS_GOT_OFST: 533 case R_MICROMIPS_LO16: 534 case R_MICROMIPS_TLS_DTPREL_LO16: 535 case R_MICROMIPS_TLS_GOTTPREL: 536 case R_MICROMIPS_TLS_TPREL_LO16: 537 writeMicroRelocation32<E>(Loc, Val, 16, 0); 538 break; 539 case R_MICROMIPS_GPREL7_S2: 540 checkInt<7>(Loc, Val, Type); 541 writeMicroRelocation32<E>(Loc, Val, 7, 2); 542 break; 543 case R_MIPS_CALL_HI16: 544 case R_MIPS_GOT_HI16: 545 case R_MIPS_HI16: 546 case R_MIPS_PCHI16: 547 case R_MIPS_TLS_DTPREL_HI16: 548 case R_MIPS_TLS_TPREL_HI16: 549 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 550 break; 551 case R_MICROMIPS_CALL_HI16: 552 case R_MICROMIPS_GOT_HI16: 553 case R_MICROMIPS_HI16: 554 case R_MICROMIPS_TLS_DTPREL_HI16: 555 case R_MICROMIPS_TLS_TPREL_HI16: 556 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 557 break; 558 case R_MIPS_HIGHER: 559 writeRelocation<E>(Loc, Val + 0x80008000, 16, 32); 560 break; 561 case R_MIPS_HIGHEST: 562 writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48); 563 break; 564 case R_MICROMIPS_HIGHER: 565 writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32); 566 break; 567 case R_MICROMIPS_HIGHEST: 568 writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48); 569 break; 570 case R_MIPS_JALR: 571 case R_MICROMIPS_JALR: 572 // Ignore this optimization relocation for now 573 break; 574 case R_MIPS_PC16: 575 checkAlignment<4>(Loc, Val, Type); 576 checkInt<18>(Loc, Val, Type); 577 writeRelocation<E>(Loc, Val, 16, 2); 578 break; 579 case R_MIPS_PC19_S2: 580 checkAlignment<4>(Loc, Val, Type); 581 checkInt<21>(Loc, Val, Type); 582 writeRelocation<E>(Loc, Val, 19, 2); 583 break; 584 case R_MIPS_PC21_S2: 585 checkAlignment<4>(Loc, Val, Type); 586 checkInt<23>(Loc, Val, Type); 587 writeRelocation<E>(Loc, Val, 21, 2); 588 break; 589 case R_MIPS_PC26_S2: 590 checkAlignment<4>(Loc, Val, Type); 591 checkInt<28>(Loc, Val, Type); 592 writeRelocation<E>(Loc, Val, 26, 2); 593 break; 594 case R_MIPS_PC32: 595 writeRelocation<E>(Loc, Val, 32, 0); 596 break; 597 case R_MICROMIPS_26_S1: 598 case R_MICROMIPS_PC26_S1: 599 checkInt<27>(Loc, Val, Type); 600 writeMicroRelocation32<E>(Loc, Val, 26, 1); 601 break; 602 case R_MICROMIPS_PC7_S1: 603 checkInt<8>(Loc, Val, Type); 604 writeMicroRelocation16<E>(Loc, Val, 7, 1); 605 break; 606 case R_MICROMIPS_PC10_S1: 607 checkInt<11>(Loc, Val, Type); 608 writeMicroRelocation16<E>(Loc, Val, 10, 1); 609 break; 610 case R_MICROMIPS_PC16_S1: 611 checkInt<17>(Loc, Val, Type); 612 writeMicroRelocation32<E>(Loc, Val, 16, 1); 613 break; 614 case R_MICROMIPS_PC18_S3: 615 checkInt<21>(Loc, Val, Type); 616 writeMicroRelocation32<E>(Loc, Val, 18, 3); 617 break; 618 case R_MICROMIPS_PC19_S2: 619 checkInt<21>(Loc, Val, Type); 620 writeMicroRelocation32<E>(Loc, Val, 19, 2); 621 break; 622 case R_MICROMIPS_PC21_S1: 623 checkInt<22>(Loc, Val, Type); 624 writeMicroRelocation32<E>(Loc, Val, 21, 1); 625 break; 626 case R_MICROMIPS_PC23_S2: 627 checkInt<25>(Loc, Val, Type); 628 writeMicroRelocation32<E>(Loc, Val, 23, 2); 629 break; 630 default: 631 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 632 } 633 } 634 635 template <class ELFT> 636 bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const { 637 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST || 638 Type == R_MICROMIPS_LO16 || Type == R_MICROMIPS_GOT_OFST; 639 } 640 641 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 642 static MIPS<ELFT> Target; 643 return &Target; 644 } 645 646 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 647 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 648 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 649 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 650