1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "InputFiles.h" 11 #include "OutputSections.h" 12 #include "Symbols.h" 13 #include "SyntheticSections.h" 14 #include "Target.h" 15 #include "Thunks.h" 16 #include "lld/Common/ErrorHandler.h" 17 #include "llvm/Object/ELF.h" 18 #include "llvm/Support/Endian.h" 19 20 using namespace llvm; 21 using namespace llvm::object; 22 using namespace llvm::support::endian; 23 using namespace llvm::ELF; 24 using namespace lld; 25 using namespace lld::elf; 26 27 namespace { 28 template <class ELFT> class MIPS final : public TargetInfo { 29 public: 30 MIPS(); 31 uint32_t calcEFlags() const override; 32 RelExpr getRelExpr(RelType Type, const Symbol &S, 33 const uint8_t *Loc) const override; 34 int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override; 35 bool isPicRel(RelType Type) const override; 36 RelType getDynRel(RelType Type) const override; 37 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; 38 void writePltHeader(uint8_t *Buf) const override; 39 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 40 int32_t Index, unsigned RelOff) const override; 41 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 42 uint64_t BranchAddr, const Symbol &S) const override; 43 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 44 bool usesOnlyLowPageBits(RelType Type) const override; 45 }; 46 } // namespace 47 48 template <class ELFT> MIPS<ELFT>::MIPS() { 49 GotPltHeaderEntriesNum = 2; 50 DefaultMaxPageSize = 65536; 51 GotEntrySize = sizeof(typename ELFT::uint); 52 GotPltEntrySize = sizeof(typename ELFT::uint); 53 PltEntrySize = 16; 54 PltHeaderSize = 32; 55 CopyRel = R_MIPS_COPY; 56 PltRel = R_MIPS_JUMP_SLOT; 57 NeedsThunks = true; 58 TrapInstr = 0xefefefef; 59 60 if (ELFT::Is64Bits) { 61 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 62 TlsGotRel = R_MIPS_TLS_TPREL64; 63 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 64 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 65 } else { 66 RelativeRel = R_MIPS_REL32; 67 TlsGotRel = R_MIPS_TLS_TPREL32; 68 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 69 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 70 } 71 } 72 73 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 74 return calcMipsEFlags<ELFT>(); 75 } 76 77 template <class ELFT> 78 RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S, 79 const uint8_t *Loc) const { 80 // See comment in the calculateMipsRelChain. 81 if (ELFT::Is64Bits || Config->MipsN32Abi) 82 Type &= 0xff; 83 84 switch (Type) { 85 case R_MIPS_JALR: 86 case R_MICROMIPS_JALR: 87 return R_HINT; 88 case R_MIPS_GPREL16: 89 case R_MIPS_GPREL32: 90 case R_MICROMIPS_GPREL16: 91 case R_MICROMIPS_GPREL7_S2: 92 return R_MIPS_GOTREL; 93 case R_MIPS_26: 94 case R_MICROMIPS_26_S1: 95 return R_PLT; 96 case R_MICROMIPS_PC26_S1: 97 return R_PLT_PC; 98 case R_MIPS_HI16: 99 case R_MIPS_LO16: 100 case R_MIPS_HIGHER: 101 case R_MIPS_HIGHEST: 102 case R_MICROMIPS_HI16: 103 case R_MICROMIPS_LO16: 104 case R_MICROMIPS_HIGHER: 105 case R_MICROMIPS_HIGHEST: 106 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 107 // offset between start of function and 'gp' value which by default 108 // equal to the start of .got section. In that case we consider these 109 // relocations as relative. 110 if (&S == ElfSym::MipsGpDisp) 111 return R_MIPS_GOT_GP_PC; 112 if (&S == ElfSym::MipsLocalGp) 113 return R_MIPS_GOT_GP; 114 LLVM_FALLTHROUGH; 115 case R_MIPS_32: 116 case R_MIPS_64: 117 case R_MIPS_GOT_OFST: 118 case R_MIPS_SUB: 119 case R_MIPS_TLS_DTPREL_HI16: 120 case R_MIPS_TLS_DTPREL_LO16: 121 case R_MIPS_TLS_DTPREL32: 122 case R_MIPS_TLS_DTPREL64: 123 case R_MIPS_TLS_TPREL_HI16: 124 case R_MIPS_TLS_TPREL_LO16: 125 case R_MIPS_TLS_TPREL32: 126 case R_MIPS_TLS_TPREL64: 127 case R_MICROMIPS_GOT_OFST: 128 case R_MICROMIPS_SUB: 129 case R_MICROMIPS_TLS_DTPREL_HI16: 130 case R_MICROMIPS_TLS_DTPREL_LO16: 131 case R_MICROMIPS_TLS_TPREL_HI16: 132 case R_MICROMIPS_TLS_TPREL_LO16: 133 return R_ABS; 134 case R_MIPS_PC32: 135 case R_MIPS_PC16: 136 case R_MIPS_PC19_S2: 137 case R_MIPS_PC21_S2: 138 case R_MIPS_PC26_S2: 139 case R_MIPS_PCHI16: 140 case R_MIPS_PCLO16: 141 case R_MICROMIPS_PC7_S1: 142 case R_MICROMIPS_PC10_S1: 143 case R_MICROMIPS_PC16_S1: 144 case R_MICROMIPS_PC18_S3: 145 case R_MICROMIPS_PC19_S2: 146 case R_MICROMIPS_PC23_S2: 147 case R_MICROMIPS_PC21_S1: 148 return R_PC; 149 case R_MIPS_GOT16: 150 case R_MICROMIPS_GOT16: 151 if (S.isLocal()) 152 return R_MIPS_GOT_LOCAL_PAGE; 153 LLVM_FALLTHROUGH; 154 case R_MIPS_CALL16: 155 case R_MIPS_GOT_DISP: 156 case R_MIPS_TLS_GOTTPREL: 157 case R_MICROMIPS_CALL16: 158 case R_MICROMIPS_GOT_DISP: 159 case R_MICROMIPS_TLS_GOTTPREL: 160 return R_MIPS_GOT_OFF; 161 case R_MIPS_CALL_HI16: 162 case R_MIPS_CALL_LO16: 163 case R_MIPS_GOT_HI16: 164 case R_MIPS_GOT_LO16: 165 case R_MICROMIPS_CALL_HI16: 166 case R_MICROMIPS_CALL_LO16: 167 case R_MICROMIPS_GOT_HI16: 168 case R_MICROMIPS_GOT_LO16: 169 return R_MIPS_GOT_OFF32; 170 case R_MIPS_GOT_PAGE: 171 case R_MICROMIPS_GOT_PAGE: 172 return R_MIPS_GOT_LOCAL_PAGE; 173 case R_MIPS_TLS_GD: 174 case R_MICROMIPS_TLS_GD: 175 return R_MIPS_TLSGD; 176 case R_MIPS_TLS_LDM: 177 case R_MICROMIPS_TLS_LDM: 178 return R_MIPS_TLSLD; 179 case R_MIPS_NONE: 180 return R_NONE; 181 default: 182 return R_INVALID; 183 } 184 } 185 186 template <class ELFT> bool MIPS<ELFT>::isPicRel(RelType Type) const { 187 return Type == R_MIPS_32 || Type == R_MIPS_64; 188 } 189 190 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const { 191 return RelativeRel; 192 } 193 194 template <class ELFT> 195 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const { 196 write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA()); 197 } 198 199 template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) { 200 // The major opcode of a microMIPS instruction needs to appear 201 // in the first 16-bit word (lowest address) for efficient hardware 202 // decode so that it knows if the instruction is 16-bit or 32-bit 203 // as early as possible. To do so, little-endian binaries keep 16-bit 204 // words in a big-endian order. That is why we have to swap these 205 // words to get a correct value. 206 uint32_t V = read32<E>(Loc); 207 if (E == support::little) 208 return (V << 16) | (V >> 16); 209 return V; 210 } 211 212 template <endianness E> 213 static void writeRelocation(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 214 uint8_t Shift) { 215 uint32_t Instr = read32<E>(Loc); 216 uint32_t Mask = 0xffffffff >> (32 - BitsSize); 217 uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 218 write32<E>(Loc, Data); 219 } 220 221 template <endianness E> 222 static void writeMicroRelocation32(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 223 uint8_t Shift) { 224 // See comments in readShuffle for purpose of this code. 225 uint16_t *Words = (uint16_t *)Loc; 226 if (E == support::little) 227 std::swap(Words[0], Words[1]); 228 229 writeRelocation<E>(Loc, V, BitsSize, Shift); 230 231 if (E == support::little) 232 std::swap(Words[0], Words[1]); 233 } 234 235 template <endianness E> 236 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 237 uint8_t Shift) { 238 uint16_t Instr = read16<E>(Loc); 239 uint16_t Mask = 0xffff >> (16 - BitsSize); 240 uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 241 write16<E>(Loc, Data); 242 } 243 244 static bool isMicroMips() { return Config->EFlags & EF_MIPS_MICROMIPS; } 245 246 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const { 247 const endianness E = ELFT::TargetEndianness; 248 if (isMicroMips()) { 249 uint64_t GotPlt = InX::GotPlt->getVA(); 250 uint64_t Plt = InX::Plt->getVA(); 251 // Overwrite trap instructions written by Writer::writeTrapInstr. 252 memset(Buf, 0, PltHeaderSize); 253 254 write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 255 write16<E>(Buf + 4, 0xff23); // lw $25, 0($3) 256 write16<E>(Buf + 8, 0x0535); // subu16 $2, $2, $3 257 write16<E>(Buf + 10, 0x2525); // srl16 $2, $2, 2 258 write16<E>(Buf + 12, 0x3302); // addiu $24, $2, -2 259 write16<E>(Buf + 14, 0xfffe); 260 write16<E>(Buf + 16, 0x0dff); // move $15, $31 261 if (isMipsR6()) { 262 write16<E>(Buf + 18, 0x0f83); // move $28, $3 263 write16<E>(Buf + 20, 0x472b); // jalrc $25 264 write16<E>(Buf + 22, 0x0c00); // nop 265 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt); 266 } else { 267 write16<E>(Buf + 18, 0x45f9); // jalrc $25 268 write16<E>(Buf + 20, 0x0f83); // move $28, $3 269 write16<E>(Buf + 22, 0x0c00); // nop 270 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt); 271 } 272 return; 273 } 274 275 if (Config->MipsN32Abi) { 276 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 277 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 278 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 279 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 280 } else { 281 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 282 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 283 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 284 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 285 } 286 287 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 288 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 289 write32<E>(Buf + 24, 0x0320f809); // jalr $25 290 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 291 292 uint64_t GotPlt = InX::GotPlt->getVA(); 293 writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16); 294 writeRelocation<E>(Buf + 4, GotPlt, 16, 0); 295 writeRelocation<E>(Buf + 8, GotPlt, 16, 0); 296 } 297 298 template <class ELFT> 299 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 300 uint64_t PltEntryAddr, int32_t Index, 301 unsigned RelOff) const { 302 const endianness E = ELFT::TargetEndianness; 303 if (isMicroMips()) { 304 // Overwrite trap instructions written by Writer::writeTrapInstr. 305 memset(Buf, 0, PltEntrySize); 306 307 if (isMipsR6()) { 308 write16<E>(Buf, 0x7840); // addiupc $2, (GOTPLT) - . 309 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 310 write16<E>(Buf + 8, 0x0f02); // move $24, $2 311 write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25 312 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr); 313 } else { 314 write16<E>(Buf, 0x7900); // addiupc $2, (GOTPLT) - . 315 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 316 write16<E>(Buf + 8, 0x4599); // jrc $25 / jr16 $25 317 write16<E>(Buf + 10, 0x0f02); // move $24, $2 318 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr); 319 } 320 return; 321 } 322 323 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 324 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 325 write32<E>(Buf + 8, isMipsR6() ? 0x03200009 : 0x03200008); // jr $25 326 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 327 writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16); 328 writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0); 329 writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0); 330 } 331 332 template <class ELFT> 333 bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 334 uint64_t BranchAddr, const Symbol &S) const { 335 // Any MIPS PIC code function is invoked with its address in register $t9. 336 // So if we have a branch instruction from non-PIC code to the PIC one 337 // we cannot make the jump directly and need to create a small stubs 338 // to save the target function address. 339 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 340 if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 && 341 Type != R_MICROMIPS_PC26_S1) 342 return false; 343 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 344 if (!F) 345 return false; 346 // If current file has PIC code, LA25 stub is not required. 347 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 348 return false; 349 auto *D = dyn_cast<Defined>(&S); 350 // LA25 is required if target file has PIC code 351 // or target symbol is a PIC symbol. 352 return D && isMipsPIC<ELFT>(D); 353 } 354 355 template <class ELFT> 356 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const { 357 const endianness E = ELFT::TargetEndianness; 358 switch (Type) { 359 case R_MIPS_32: 360 case R_MIPS_GPREL32: 361 case R_MIPS_TLS_DTPREL32: 362 case R_MIPS_TLS_TPREL32: 363 return SignExtend64<32>(read32<E>(Buf)); 364 case R_MIPS_26: 365 // FIXME (simon): If the relocation target symbol is not a PLT entry 366 // we should use another expression for calculation: 367 // ((A << 2) | (P & 0xf0000000)) >> 2 368 return SignExtend64<28>(read32<E>(Buf) << 2); 369 case R_MIPS_GOT16: 370 case R_MIPS_HI16: 371 case R_MIPS_PCHI16: 372 return SignExtend64<16>(read32<E>(Buf)) << 16; 373 case R_MIPS_GPREL16: 374 case R_MIPS_LO16: 375 case R_MIPS_PCLO16: 376 case R_MIPS_TLS_DTPREL_HI16: 377 case R_MIPS_TLS_DTPREL_LO16: 378 case R_MIPS_TLS_TPREL_HI16: 379 case R_MIPS_TLS_TPREL_LO16: 380 return SignExtend64<16>(read32<E>(Buf)); 381 case R_MICROMIPS_GOT16: 382 case R_MICROMIPS_HI16: 383 return SignExtend64<16>(readShuffle<E>(Buf)) << 16; 384 case R_MICROMIPS_GPREL16: 385 case R_MICROMIPS_LO16: 386 case R_MICROMIPS_TLS_DTPREL_HI16: 387 case R_MICROMIPS_TLS_DTPREL_LO16: 388 case R_MICROMIPS_TLS_TPREL_HI16: 389 case R_MICROMIPS_TLS_TPREL_LO16: 390 return SignExtend64<16>(readShuffle<E>(Buf)); 391 case R_MICROMIPS_GPREL7_S2: 392 return SignExtend64<9>(readShuffle<E>(Buf) << 2); 393 case R_MIPS_PC16: 394 return SignExtend64<18>(read32<E>(Buf) << 2); 395 case R_MIPS_PC19_S2: 396 return SignExtend64<21>(read32<E>(Buf) << 2); 397 case R_MIPS_PC21_S2: 398 return SignExtend64<23>(read32<E>(Buf) << 2); 399 case R_MIPS_PC26_S2: 400 return SignExtend64<28>(read32<E>(Buf) << 2); 401 case R_MIPS_PC32: 402 return SignExtend64<32>(read32<E>(Buf)); 403 case R_MICROMIPS_26_S1: 404 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 405 case R_MICROMIPS_PC7_S1: 406 return SignExtend64<8>(read16<E>(Buf) << 1); 407 case R_MICROMIPS_PC10_S1: 408 return SignExtend64<11>(read16<E>(Buf) << 1); 409 case R_MICROMIPS_PC16_S1: 410 return SignExtend64<17>(readShuffle<E>(Buf) << 1); 411 case R_MICROMIPS_PC18_S3: 412 return SignExtend64<21>(readShuffle<E>(Buf) << 3); 413 case R_MICROMIPS_PC19_S2: 414 return SignExtend64<21>(readShuffle<E>(Buf) << 2); 415 case R_MICROMIPS_PC21_S1: 416 return SignExtend64<22>(readShuffle<E>(Buf) << 1); 417 case R_MICROMIPS_PC23_S2: 418 return SignExtend64<25>(readShuffle<E>(Buf) << 2); 419 case R_MICROMIPS_PC26_S1: 420 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 421 default: 422 return 0; 423 } 424 } 425 426 static std::pair<uint32_t, uint64_t> 427 calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) { 428 // MIPS N64 ABI packs multiple relocations into the single relocation 429 // record. In general, all up to three relocations can have arbitrary 430 // types. In fact, Clang and GCC uses only a few combinations. For now, 431 // we support two of them. That is allow to pass at least all LLVM 432 // test suite cases. 433 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 434 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 435 // The first relocation is a 'real' relocation which is calculated 436 // using the corresponding symbol's value. The second and the third 437 // relocations used to modify result of the first one: extend it to 438 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 439 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 440 RelType Type2 = (Type >> 8) & 0xff; 441 RelType Type3 = (Type >> 16) & 0xff; 442 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 443 return std::make_pair(Type, Val); 444 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 445 return std::make_pair(Type2, Val); 446 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 447 return std::make_pair(Type3, -Val); 448 if (Type2 == R_MICROMIPS_SUB && 449 (Type3 == R_MICROMIPS_HI16 || Type3 == R_MICROMIPS_LO16)) 450 return std::make_pair(Type3, -Val); 451 error(getErrorLocation(Loc) + "unsupported relocations combination " + 452 Twine(Type)); 453 return std::make_pair(Type & 0xff, Val); 454 } 455 456 template <class ELFT> 457 void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 458 const endianness E = ELFT::TargetEndianness; 459 460 // Thread pointer and DRP offsets from the start of TLS data area. 461 // https://www.linux-mips.org/wiki/NPTL 462 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 463 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 || 464 Type == R_MICROMIPS_TLS_DTPREL_HI16 || 465 Type == R_MICROMIPS_TLS_DTPREL_LO16) { 466 Val -= 0x8000; 467 } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 468 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 || 469 Type == R_MICROMIPS_TLS_TPREL_HI16 || 470 Type == R_MICROMIPS_TLS_TPREL_LO16) { 471 Val -= 0x7000; 472 } 473 474 if (ELFT::Is64Bits || Config->MipsN32Abi) 475 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 476 477 switch (Type) { 478 case R_MIPS_32: 479 case R_MIPS_GPREL32: 480 case R_MIPS_TLS_DTPREL32: 481 case R_MIPS_TLS_TPREL32: 482 write32<E>(Loc, Val); 483 break; 484 case R_MIPS_64: 485 case R_MIPS_TLS_DTPREL64: 486 case R_MIPS_TLS_TPREL64: 487 write64<E>(Loc, Val); 488 break; 489 case R_MIPS_26: 490 writeRelocation<E>(Loc, Val, 26, 2); 491 break; 492 case R_MIPS_GOT16: 493 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 494 // is updated addend (not a GOT index). In that case write high 16 bits 495 // to store a correct addend value. 496 if (Config->Relocatable) { 497 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 498 } else { 499 checkInt<16>(Loc, Val, Type); 500 writeRelocation<E>(Loc, Val, 16, 0); 501 } 502 break; 503 case R_MICROMIPS_GOT16: 504 if (Config->Relocatable) { 505 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 506 } else { 507 checkInt<16>(Loc, Val, Type); 508 writeMicroRelocation32<E>(Loc, Val, 16, 0); 509 } 510 break; 511 case R_MIPS_CALL16: 512 case R_MIPS_GOT_DISP: 513 case R_MIPS_GOT_PAGE: 514 case R_MIPS_GPREL16: 515 case R_MIPS_TLS_GD: 516 case R_MIPS_TLS_GOTTPREL: 517 case R_MIPS_TLS_LDM: 518 checkInt<16>(Loc, Val, Type); 519 LLVM_FALLTHROUGH; 520 case R_MIPS_CALL_LO16: 521 case R_MIPS_GOT_LO16: 522 case R_MIPS_GOT_OFST: 523 case R_MIPS_LO16: 524 case R_MIPS_PCLO16: 525 case R_MIPS_TLS_DTPREL_LO16: 526 case R_MIPS_TLS_TPREL_LO16: 527 writeRelocation<E>(Loc, Val, 16, 0); 528 break; 529 case R_MICROMIPS_GOT_DISP: 530 case R_MICROMIPS_GOT_PAGE: 531 case R_MICROMIPS_GPREL16: 532 case R_MICROMIPS_TLS_GD: 533 case R_MICROMIPS_TLS_LDM: 534 checkInt<16>(Loc, Val, Type); 535 writeMicroRelocation32<E>(Loc, Val, 16, 0); 536 break; 537 case R_MICROMIPS_CALL16: 538 case R_MICROMIPS_CALL_LO16: 539 case R_MICROMIPS_GOT_OFST: 540 case R_MICROMIPS_LO16: 541 case R_MICROMIPS_TLS_DTPREL_LO16: 542 case R_MICROMIPS_TLS_GOTTPREL: 543 case R_MICROMIPS_TLS_TPREL_LO16: 544 writeMicroRelocation32<E>(Loc, Val, 16, 0); 545 break; 546 case R_MICROMIPS_GPREL7_S2: 547 checkInt<7>(Loc, Val, Type); 548 writeMicroRelocation32<E>(Loc, Val, 7, 2); 549 break; 550 case R_MIPS_CALL_HI16: 551 case R_MIPS_GOT_HI16: 552 case R_MIPS_HI16: 553 case R_MIPS_PCHI16: 554 case R_MIPS_TLS_DTPREL_HI16: 555 case R_MIPS_TLS_TPREL_HI16: 556 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 557 break; 558 case R_MICROMIPS_CALL_HI16: 559 case R_MICROMIPS_GOT_HI16: 560 case R_MICROMIPS_HI16: 561 case R_MICROMIPS_TLS_DTPREL_HI16: 562 case R_MICROMIPS_TLS_TPREL_HI16: 563 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 564 break; 565 case R_MIPS_HIGHER: 566 writeRelocation<E>(Loc, Val + 0x80008000, 16, 32); 567 break; 568 case R_MIPS_HIGHEST: 569 writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48); 570 break; 571 case R_MICROMIPS_HIGHER: 572 writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32); 573 break; 574 case R_MICROMIPS_HIGHEST: 575 writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48); 576 break; 577 case R_MIPS_JALR: 578 case R_MICROMIPS_JALR: 579 // Ignore this optimization relocation for now 580 break; 581 case R_MIPS_PC16: 582 checkAlignment<4>(Loc, Val, Type); 583 checkInt<18>(Loc, Val, Type); 584 writeRelocation<E>(Loc, Val, 16, 2); 585 break; 586 case R_MIPS_PC19_S2: 587 checkAlignment<4>(Loc, Val, Type); 588 checkInt<21>(Loc, Val, Type); 589 writeRelocation<E>(Loc, Val, 19, 2); 590 break; 591 case R_MIPS_PC21_S2: 592 checkAlignment<4>(Loc, Val, Type); 593 checkInt<23>(Loc, Val, Type); 594 writeRelocation<E>(Loc, Val, 21, 2); 595 break; 596 case R_MIPS_PC26_S2: 597 checkAlignment<4>(Loc, Val, Type); 598 checkInt<28>(Loc, Val, Type); 599 writeRelocation<E>(Loc, Val, 26, 2); 600 break; 601 case R_MIPS_PC32: 602 writeRelocation<E>(Loc, Val, 32, 0); 603 break; 604 case R_MICROMIPS_26_S1: 605 case R_MICROMIPS_PC26_S1: 606 checkInt<27>(Loc, Val, Type); 607 writeMicroRelocation32<E>(Loc, Val, 26, 1); 608 break; 609 case R_MICROMIPS_PC7_S1: 610 checkInt<8>(Loc, Val, Type); 611 writeMicroRelocation16<E>(Loc, Val, 7, 1); 612 break; 613 case R_MICROMIPS_PC10_S1: 614 checkInt<11>(Loc, Val, Type); 615 writeMicroRelocation16<E>(Loc, Val, 10, 1); 616 break; 617 case R_MICROMIPS_PC16_S1: 618 checkInt<17>(Loc, Val, Type); 619 writeMicroRelocation32<E>(Loc, Val, 16, 1); 620 break; 621 case R_MICROMIPS_PC18_S3: 622 checkInt<21>(Loc, Val, Type); 623 writeMicroRelocation32<E>(Loc, Val, 18, 3); 624 break; 625 case R_MICROMIPS_PC19_S2: 626 checkInt<21>(Loc, Val, Type); 627 writeMicroRelocation32<E>(Loc, Val, 19, 2); 628 break; 629 case R_MICROMIPS_PC21_S1: 630 checkInt<22>(Loc, Val, Type); 631 writeMicroRelocation32<E>(Loc, Val, 21, 1); 632 break; 633 case R_MICROMIPS_PC23_S2: 634 checkInt<25>(Loc, Val, Type); 635 writeMicroRelocation32<E>(Loc, Val, 23, 2); 636 break; 637 default: 638 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 639 } 640 } 641 642 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const { 643 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST || 644 Type == R_MICROMIPS_LO16 || Type == R_MICROMIPS_GOT_OFST; 645 } 646 647 // Return true if the symbol is a PIC function. 648 template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) { 649 typedef typename ELFT::Ehdr Elf_Ehdr; 650 if (!Sym->Section || !Sym->isFunc()) 651 return false; 652 653 auto *Sec = cast<InputSectionBase>(Sym->Section); 654 const Elf_Ehdr *Hdr = Sec->template getFile<ELFT>()->getObj().getHeader(); 655 return (Sym->StOther & STO_MIPS_MIPS16) == STO_MIPS_PIC || 656 (Hdr->e_flags & EF_MIPS_PIC); 657 } 658 659 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 660 static MIPS<ELFT> Target; 661 return &Target; 662 } 663 664 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 665 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 666 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 667 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 668 669 template bool elf::isMipsPIC<ELF32LE>(const Defined *); 670 template bool elf::isMipsPIC<ELF32BE>(const Defined *); 671 template bool elf::isMipsPIC<ELF64LE>(const Defined *); 672 template bool elf::isMipsPIC<ELF64BE>(const Defined *); 673