1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "InputFiles.h" 11 #include "OutputSections.h" 12 #include "Symbols.h" 13 #include "SyntheticSections.h" 14 #include "Target.h" 15 #include "Thunks.h" 16 #include "lld/Common/ErrorHandler.h" 17 #include "llvm/Object/ELF.h" 18 #include "llvm/Support/Endian.h" 19 20 using namespace llvm; 21 using namespace llvm::object; 22 using namespace llvm::support::endian; 23 using namespace llvm::ELF; 24 using namespace lld; 25 using namespace lld::elf; 26 27 namespace { 28 template <class ELFT> class MIPS final : public TargetInfo { 29 public: 30 MIPS(); 31 uint32_t calcEFlags() const override; 32 RelExpr getRelExpr(RelType Type, const Symbol &S, 33 const uint8_t *Loc) const override; 34 int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override; 35 RelType getDynRel(RelType Type) const override; 36 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; 37 void writePltHeader(uint8_t *Buf) const override; 38 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 39 int32_t Index, unsigned RelOff) const override; 40 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 41 uint64_t BranchAddr, const Symbol &S) const override; 42 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 43 bool usesOnlyLowPageBits(RelType Type) const override; 44 }; 45 } // namespace 46 47 template <class ELFT> MIPS<ELFT>::MIPS() { 48 GotPltHeaderEntriesNum = 2; 49 DefaultMaxPageSize = 65536; 50 GotEntrySize = sizeof(typename ELFT::uint); 51 GotPltEntrySize = sizeof(typename ELFT::uint); 52 GotBaseSymInGotPlt = false; 53 PltEntrySize = 16; 54 PltHeaderSize = 32; 55 CopyRel = R_MIPS_COPY; 56 PltRel = R_MIPS_JUMP_SLOT; 57 NeedsThunks = true; 58 TrapInstr = 0xefefefef; 59 60 if (ELFT::Is64Bits) { 61 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 62 TlsGotRel = R_MIPS_TLS_TPREL64; 63 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 64 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 65 } else { 66 RelativeRel = R_MIPS_REL32; 67 TlsGotRel = R_MIPS_TLS_TPREL32; 68 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 69 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 70 } 71 } 72 73 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 74 return calcMipsEFlags<ELFT>(); 75 } 76 77 template <class ELFT> 78 RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S, 79 const uint8_t *Loc) const { 80 // See comment in the calculateMipsRelChain. 81 if (ELFT::Is64Bits || Config->MipsN32Abi) 82 Type &= 0xff; 83 84 switch (Type) { 85 case R_MIPS_JALR: 86 case R_MICROMIPS_JALR: 87 return R_HINT; 88 case R_MIPS_GPREL16: 89 case R_MIPS_GPREL32: 90 case R_MICROMIPS_GPREL16: 91 case R_MICROMIPS_GPREL7_S2: 92 return R_MIPS_GOTREL; 93 case R_MIPS_26: 94 case R_MICROMIPS_26_S1: 95 return R_PLT; 96 case R_MICROMIPS_PC26_S1: 97 return R_PLT_PC; 98 case R_MIPS_HI16: 99 case R_MIPS_LO16: 100 case R_MIPS_HIGHER: 101 case R_MIPS_HIGHEST: 102 case R_MICROMIPS_HI16: 103 case R_MICROMIPS_LO16: 104 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 105 // offset between start of function and 'gp' value which by default 106 // equal to the start of .got section. In that case we consider these 107 // relocations as relative. 108 if (&S == ElfSym::MipsGpDisp) 109 return R_MIPS_GOT_GP_PC; 110 if (&S == ElfSym::MipsLocalGp) 111 return R_MIPS_GOT_GP; 112 LLVM_FALLTHROUGH; 113 case R_MIPS_32: 114 case R_MIPS_64: 115 case R_MIPS_GOT_OFST: 116 case R_MIPS_SUB: 117 case R_MIPS_TLS_DTPREL_HI16: 118 case R_MIPS_TLS_DTPREL_LO16: 119 case R_MIPS_TLS_DTPREL32: 120 case R_MIPS_TLS_DTPREL64: 121 case R_MIPS_TLS_TPREL_HI16: 122 case R_MIPS_TLS_TPREL_LO16: 123 case R_MIPS_TLS_TPREL32: 124 case R_MIPS_TLS_TPREL64: 125 case R_MICROMIPS_TLS_DTPREL_HI16: 126 case R_MICROMIPS_TLS_DTPREL_LO16: 127 case R_MICROMIPS_TLS_TPREL_HI16: 128 case R_MICROMIPS_TLS_TPREL_LO16: 129 return R_ABS; 130 case R_MIPS_PC32: 131 case R_MIPS_PC16: 132 case R_MIPS_PC19_S2: 133 case R_MIPS_PC21_S2: 134 case R_MIPS_PC26_S2: 135 case R_MIPS_PCHI16: 136 case R_MIPS_PCLO16: 137 case R_MICROMIPS_PC7_S1: 138 case R_MICROMIPS_PC10_S1: 139 case R_MICROMIPS_PC16_S1: 140 case R_MICROMIPS_PC18_S3: 141 case R_MICROMIPS_PC19_S2: 142 case R_MICROMIPS_PC23_S2: 143 case R_MICROMIPS_PC21_S1: 144 return R_PC; 145 case R_MIPS_GOT16: 146 case R_MICROMIPS_GOT16: 147 if (S.isLocal()) 148 return R_MIPS_GOT_LOCAL_PAGE; 149 LLVM_FALLTHROUGH; 150 case R_MIPS_CALL16: 151 case R_MIPS_GOT_DISP: 152 case R_MIPS_TLS_GOTTPREL: 153 case R_MICROMIPS_CALL16: 154 case R_MICROMIPS_TLS_GOTTPREL: 155 return R_MIPS_GOT_OFF; 156 case R_MIPS_CALL_HI16: 157 case R_MIPS_CALL_LO16: 158 case R_MIPS_GOT_HI16: 159 case R_MIPS_GOT_LO16: 160 case R_MICROMIPS_CALL_HI16: 161 case R_MICROMIPS_CALL_LO16: 162 case R_MICROMIPS_GOT_HI16: 163 case R_MICROMIPS_GOT_LO16: 164 return R_MIPS_GOT_OFF32; 165 case R_MIPS_GOT_PAGE: 166 return R_MIPS_GOT_LOCAL_PAGE; 167 case R_MIPS_TLS_GD: 168 case R_MICROMIPS_TLS_GD: 169 return R_MIPS_TLSGD; 170 case R_MIPS_TLS_LDM: 171 case R_MICROMIPS_TLS_LDM: 172 return R_MIPS_TLSLD; 173 case R_MIPS_NONE: 174 return R_NONE; 175 default: 176 return R_INVALID; 177 } 178 } 179 180 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const { 181 if (Type == R_MIPS_32 || Type == R_MIPS_64) 182 return RelativeRel; 183 return R_MIPS_NONE; 184 } 185 186 template <class ELFT> 187 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const { 188 uint64_t VA = InX::Plt->getVA(); 189 if (isMicroMips()) 190 VA |= 1; 191 write32<ELFT::TargetEndianness>(Buf, VA); 192 } 193 194 template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) { 195 // The major opcode of a microMIPS instruction needs to appear 196 // in the first 16-bit word (lowest address) for efficient hardware 197 // decode so that it knows if the instruction is 16-bit or 32-bit 198 // as early as possible. To do so, little-endian binaries keep 16-bit 199 // words in a big-endian order. That is why we have to swap these 200 // words to get a correct value. 201 uint32_t V = read32<E>(Loc); 202 if (E == support::little) 203 return (V << 16) | (V >> 16); 204 return V; 205 } 206 207 template <endianness E> 208 static void writeValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 209 uint8_t Shift) { 210 uint32_t Instr = read32<E>(Loc); 211 uint32_t Mask = 0xffffffff >> (32 - BitsSize); 212 uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 213 write32<E>(Loc, Data); 214 } 215 216 template <endianness E> 217 static void writeShuffleValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 218 uint8_t Shift) { 219 // See comments in readShuffle for purpose of this code. 220 uint16_t *Words = (uint16_t *)Loc; 221 if (E == support::little) 222 std::swap(Words[0], Words[1]); 223 224 writeValue<E>(Loc, V, BitsSize, Shift); 225 226 if (E == support::little) 227 std::swap(Words[0], Words[1]); 228 } 229 230 template <endianness E> 231 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 232 uint8_t Shift) { 233 uint16_t Instr = read16<E>(Loc); 234 uint16_t Mask = 0xffff >> (16 - BitsSize); 235 uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 236 write16<E>(Loc, Data); 237 } 238 239 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const { 240 const endianness E = ELFT::TargetEndianness; 241 if (isMicroMips()) { 242 uint64_t GotPlt = InX::GotPlt->getVA(); 243 uint64_t Plt = InX::Plt->getVA(); 244 // Overwrite trap instructions written by Writer::writeTrapInstr. 245 memset(Buf, 0, PltHeaderSize); 246 247 write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 248 write16<E>(Buf + 4, 0xff23); // lw $25, 0($3) 249 write16<E>(Buf + 8, 0x0535); // subu16 $2, $2, $3 250 write16<E>(Buf + 10, 0x2525); // srl16 $2, $2, 2 251 write16<E>(Buf + 12, 0x3302); // addiu $24, $2, -2 252 write16<E>(Buf + 14, 0xfffe); 253 write16<E>(Buf + 16, 0x0dff); // move $15, $31 254 if (isMipsR6()) { 255 write16<E>(Buf + 18, 0x0f83); // move $28, $3 256 write16<E>(Buf + 20, 0x472b); // jalrc $25 257 write16<E>(Buf + 22, 0x0c00); // nop 258 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt); 259 } else { 260 write16<E>(Buf + 18, 0x45f9); // jalrc $25 261 write16<E>(Buf + 20, 0x0f83); // move $28, $3 262 write16<E>(Buf + 22, 0x0c00); // nop 263 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt); 264 } 265 return; 266 } 267 268 if (Config->MipsN32Abi) { 269 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 270 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 271 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 272 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 273 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 274 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 275 } else if (ELFT::Is64Bits) { 276 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 277 write32<E>(Buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14) 278 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 279 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 280 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 281 write32<E>(Buf + 20, 0x0018c0c2); // srl $24, $24, 3 282 } else { 283 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 284 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 285 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 286 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 287 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 288 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 289 } 290 291 uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809; 292 write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25 293 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 294 295 uint64_t GotPlt = InX::GotPlt->getVA(); 296 writeValue<E>(Buf, GotPlt + 0x8000, 16, 16); 297 writeValue<E>(Buf + 4, GotPlt, 16, 0); 298 writeValue<E>(Buf + 8, GotPlt, 16, 0); 299 } 300 301 template <class ELFT> 302 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 303 uint64_t PltEntryAddr, int32_t Index, 304 unsigned RelOff) const { 305 const endianness E = ELFT::TargetEndianness; 306 if (isMicroMips()) { 307 // Overwrite trap instructions written by Writer::writeTrapInstr. 308 memset(Buf, 0, PltEntrySize); 309 310 if (isMipsR6()) { 311 write16<E>(Buf, 0x7840); // addiupc $2, (GOTPLT) - . 312 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 313 write16<E>(Buf + 8, 0x0f02); // move $24, $2 314 write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25 315 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr); 316 } else { 317 write16<E>(Buf, 0x7900); // addiupc $2, (GOTPLT) - . 318 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 319 write16<E>(Buf + 8, 0x4599); // jrc $25 / jr16 $25 320 write16<E>(Buf + 10, 0x0f02); // move $24, $2 321 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr); 322 } 323 return; 324 } 325 326 uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009) 327 : (Config->ZHazardplt ? 0x03200408 : 0x03200008); 328 329 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 330 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 331 write32<E>(Buf + 8, JrInst); // jr $25 / jr.hb $25 332 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 333 writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16); 334 writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0); 335 writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0); 336 } 337 338 template <class ELFT> 339 bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 340 uint64_t BranchAddr, const Symbol &S) const { 341 // Any MIPS PIC code function is invoked with its address in register $t9. 342 // So if we have a branch instruction from non-PIC code to the PIC one 343 // we cannot make the jump directly and need to create a small stubs 344 // to save the target function address. 345 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 346 if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 && 347 Type != R_MICROMIPS_PC26_S1) 348 return false; 349 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 350 if (!F) 351 return false; 352 // If current file has PIC code, LA25 stub is not required. 353 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 354 return false; 355 auto *D = dyn_cast<Defined>(&S); 356 // LA25 is required if target file has PIC code 357 // or target symbol is a PIC symbol. 358 return D && isMipsPIC<ELFT>(D); 359 } 360 361 template <class ELFT> 362 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const { 363 const endianness E = ELFT::TargetEndianness; 364 switch (Type) { 365 case R_MIPS_32: 366 case R_MIPS_GPREL32: 367 case R_MIPS_TLS_DTPREL32: 368 case R_MIPS_TLS_TPREL32: 369 return SignExtend64<32>(read32<E>(Buf)); 370 case R_MIPS_26: 371 // FIXME (simon): If the relocation target symbol is not a PLT entry 372 // we should use another expression for calculation: 373 // ((A << 2) | (P & 0xf0000000)) >> 2 374 return SignExtend64<28>(read32<E>(Buf) << 2); 375 case R_MIPS_GOT16: 376 case R_MIPS_HI16: 377 case R_MIPS_PCHI16: 378 return SignExtend64<16>(read32<E>(Buf)) << 16; 379 case R_MIPS_GPREL16: 380 case R_MIPS_LO16: 381 case R_MIPS_PCLO16: 382 case R_MIPS_TLS_DTPREL_HI16: 383 case R_MIPS_TLS_DTPREL_LO16: 384 case R_MIPS_TLS_TPREL_HI16: 385 case R_MIPS_TLS_TPREL_LO16: 386 return SignExtend64<16>(read32<E>(Buf)); 387 case R_MICROMIPS_GOT16: 388 case R_MICROMIPS_HI16: 389 return SignExtend64<16>(readShuffle<E>(Buf)) << 16; 390 case R_MICROMIPS_GPREL16: 391 case R_MICROMIPS_LO16: 392 case R_MICROMIPS_TLS_DTPREL_HI16: 393 case R_MICROMIPS_TLS_DTPREL_LO16: 394 case R_MICROMIPS_TLS_TPREL_HI16: 395 case R_MICROMIPS_TLS_TPREL_LO16: 396 return SignExtend64<16>(readShuffle<E>(Buf)); 397 case R_MICROMIPS_GPREL7_S2: 398 return SignExtend64<9>(readShuffle<E>(Buf) << 2); 399 case R_MIPS_PC16: 400 return SignExtend64<18>(read32<E>(Buf) << 2); 401 case R_MIPS_PC19_S2: 402 return SignExtend64<21>(read32<E>(Buf) << 2); 403 case R_MIPS_PC21_S2: 404 return SignExtend64<23>(read32<E>(Buf) << 2); 405 case R_MIPS_PC26_S2: 406 return SignExtend64<28>(read32<E>(Buf) << 2); 407 case R_MIPS_PC32: 408 return SignExtend64<32>(read32<E>(Buf)); 409 case R_MICROMIPS_26_S1: 410 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 411 case R_MICROMIPS_PC7_S1: 412 return SignExtend64<8>(read16<E>(Buf) << 1); 413 case R_MICROMIPS_PC10_S1: 414 return SignExtend64<11>(read16<E>(Buf) << 1); 415 case R_MICROMIPS_PC16_S1: 416 return SignExtend64<17>(readShuffle<E>(Buf) << 1); 417 case R_MICROMIPS_PC18_S3: 418 return SignExtend64<21>(readShuffle<E>(Buf) << 3); 419 case R_MICROMIPS_PC19_S2: 420 return SignExtend64<21>(readShuffle<E>(Buf) << 2); 421 case R_MICROMIPS_PC21_S1: 422 return SignExtend64<22>(readShuffle<E>(Buf) << 1); 423 case R_MICROMIPS_PC23_S2: 424 return SignExtend64<25>(readShuffle<E>(Buf) << 2); 425 case R_MICROMIPS_PC26_S1: 426 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 427 default: 428 return 0; 429 } 430 } 431 432 static std::pair<uint32_t, uint64_t> 433 calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) { 434 // MIPS N64 ABI packs multiple relocations into the single relocation 435 // record. In general, all up to three relocations can have arbitrary 436 // types. In fact, Clang and GCC uses only a few combinations. For now, 437 // we support two of them. That is allow to pass at least all LLVM 438 // test suite cases. 439 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 440 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 441 // The first relocation is a 'real' relocation which is calculated 442 // using the corresponding symbol's value. The second and the third 443 // relocations used to modify result of the first one: extend it to 444 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 445 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 446 RelType Type2 = (Type >> 8) & 0xff; 447 RelType Type3 = (Type >> 16) & 0xff; 448 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 449 return std::make_pair(Type, Val); 450 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 451 return std::make_pair(Type2, Val); 452 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 453 return std::make_pair(Type3, -Val); 454 error(getErrorLocation(Loc) + "unsupported relocations combination " + 455 Twine(Type)); 456 return std::make_pair(Type & 0xff, Val); 457 } 458 459 template <class ELFT> 460 void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 461 const endianness E = ELFT::TargetEndianness; 462 463 if (ELFT::Is64Bits || Config->MipsN32Abi) 464 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 465 466 // Thread pointer and DRP offsets from the start of TLS data area. 467 // https://www.linux-mips.org/wiki/NPTL 468 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 469 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 || 470 Type == R_MICROMIPS_TLS_DTPREL_HI16 || 471 Type == R_MICROMIPS_TLS_DTPREL_LO16) { 472 Val -= 0x8000; 473 } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 474 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 || 475 Type == R_MICROMIPS_TLS_TPREL_HI16 || 476 Type == R_MICROMIPS_TLS_TPREL_LO16) { 477 Val -= 0x7000; 478 } 479 480 switch (Type) { 481 case R_MIPS_32: 482 case R_MIPS_GPREL32: 483 case R_MIPS_TLS_DTPREL32: 484 case R_MIPS_TLS_TPREL32: 485 write32<E>(Loc, Val); 486 break; 487 case R_MIPS_64: 488 case R_MIPS_TLS_DTPREL64: 489 case R_MIPS_TLS_TPREL64: 490 write64<E>(Loc, Val); 491 break; 492 case R_MIPS_26: 493 writeValue<E>(Loc, Val, 26, 2); 494 break; 495 case R_MIPS_GOT16: 496 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 497 // is updated addend (not a GOT index). In that case write high 16 bits 498 // to store a correct addend value. 499 if (Config->Relocatable) { 500 writeValue<E>(Loc, Val + 0x8000, 16, 16); 501 } else { 502 checkInt(Loc, Val, 16, Type); 503 writeValue<E>(Loc, Val, 16, 0); 504 } 505 break; 506 case R_MICROMIPS_GOT16: 507 if (Config->Relocatable) { 508 writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16); 509 } else { 510 checkInt(Loc, Val, 16, Type); 511 writeShuffleValue<E>(Loc, Val, 16, 0); 512 } 513 break; 514 case R_MIPS_CALL16: 515 case R_MIPS_GOT_DISP: 516 case R_MIPS_GOT_PAGE: 517 case R_MIPS_GPREL16: 518 case R_MIPS_TLS_GD: 519 case R_MIPS_TLS_GOTTPREL: 520 case R_MIPS_TLS_LDM: 521 checkInt(Loc, Val, 16, Type); 522 LLVM_FALLTHROUGH; 523 case R_MIPS_CALL_LO16: 524 case R_MIPS_GOT_LO16: 525 case R_MIPS_GOT_OFST: 526 case R_MIPS_LO16: 527 case R_MIPS_PCLO16: 528 case R_MIPS_TLS_DTPREL_LO16: 529 case R_MIPS_TLS_TPREL_LO16: 530 writeValue<E>(Loc, Val, 16, 0); 531 break; 532 case R_MICROMIPS_GPREL16: 533 case R_MICROMIPS_TLS_GD: 534 case R_MICROMIPS_TLS_LDM: 535 checkInt(Loc, Val, 16, Type); 536 writeShuffleValue<E>(Loc, Val, 16, 0); 537 break; 538 case R_MICROMIPS_CALL16: 539 case R_MICROMIPS_CALL_LO16: 540 case R_MICROMIPS_LO16: 541 case R_MICROMIPS_TLS_DTPREL_LO16: 542 case R_MICROMIPS_TLS_GOTTPREL: 543 case R_MICROMIPS_TLS_TPREL_LO16: 544 writeShuffleValue<E>(Loc, Val, 16, 0); 545 break; 546 case R_MICROMIPS_GPREL7_S2: 547 checkInt(Loc, Val, 7, Type); 548 writeShuffleValue<E>(Loc, Val, 7, 2); 549 break; 550 case R_MIPS_CALL_HI16: 551 case R_MIPS_GOT_HI16: 552 case R_MIPS_HI16: 553 case R_MIPS_PCHI16: 554 case R_MIPS_TLS_DTPREL_HI16: 555 case R_MIPS_TLS_TPREL_HI16: 556 writeValue<E>(Loc, Val + 0x8000, 16, 16); 557 break; 558 case R_MICROMIPS_CALL_HI16: 559 case R_MICROMIPS_GOT_HI16: 560 case R_MICROMIPS_HI16: 561 case R_MICROMIPS_TLS_DTPREL_HI16: 562 case R_MICROMIPS_TLS_TPREL_HI16: 563 writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16); 564 break; 565 case R_MIPS_HIGHER: 566 writeValue<E>(Loc, Val + 0x80008000, 16, 32); 567 break; 568 case R_MIPS_HIGHEST: 569 writeValue<E>(Loc, Val + 0x800080008000, 16, 48); 570 break; 571 case R_MIPS_JALR: 572 case R_MICROMIPS_JALR: 573 // Ignore this optimization relocation for now 574 break; 575 case R_MIPS_PC16: 576 checkAlignment(Loc, Val, 4, Type); 577 checkInt(Loc, Val, 18, Type); 578 writeValue<E>(Loc, Val, 16, 2); 579 break; 580 case R_MIPS_PC19_S2: 581 checkAlignment(Loc, Val, 4, Type); 582 checkInt(Loc, Val, 21, Type); 583 writeValue<E>(Loc, Val, 19, 2); 584 break; 585 case R_MIPS_PC21_S2: 586 checkAlignment(Loc, Val, 4, Type); 587 checkInt(Loc, Val, 23, Type); 588 writeValue<E>(Loc, Val, 21, 2); 589 break; 590 case R_MIPS_PC26_S2: 591 checkAlignment(Loc, Val, 4, Type); 592 checkInt(Loc, Val, 28, Type); 593 writeValue<E>(Loc, Val, 26, 2); 594 break; 595 case R_MIPS_PC32: 596 writeValue<E>(Loc, Val, 32, 0); 597 break; 598 case R_MICROMIPS_26_S1: 599 case R_MICROMIPS_PC26_S1: 600 checkInt(Loc, Val, 27, Type); 601 writeShuffleValue<E>(Loc, Val, 26, 1); 602 break; 603 case R_MICROMIPS_PC7_S1: 604 checkInt(Loc, Val, 8, Type); 605 writeMicroRelocation16<E>(Loc, Val, 7, 1); 606 break; 607 case R_MICROMIPS_PC10_S1: 608 checkInt(Loc, Val, 11, Type); 609 writeMicroRelocation16<E>(Loc, Val, 10, 1); 610 break; 611 case R_MICROMIPS_PC16_S1: 612 checkInt(Loc, Val, 17, Type); 613 writeShuffleValue<E>(Loc, Val, 16, 1); 614 break; 615 case R_MICROMIPS_PC18_S3: 616 checkInt(Loc, Val, 21, Type); 617 writeShuffleValue<E>(Loc, Val, 18, 3); 618 break; 619 case R_MICROMIPS_PC19_S2: 620 checkInt(Loc, Val, 21, Type); 621 writeShuffleValue<E>(Loc, Val, 19, 2); 622 break; 623 case R_MICROMIPS_PC21_S1: 624 checkInt(Loc, Val, 22, Type); 625 writeShuffleValue<E>(Loc, Val, 21, 1); 626 break; 627 case R_MICROMIPS_PC23_S2: 628 checkInt(Loc, Val, 25, Type); 629 writeShuffleValue<E>(Loc, Val, 23, 2); 630 break; 631 default: 632 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 633 } 634 } 635 636 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const { 637 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST || 638 Type == R_MICROMIPS_LO16; 639 } 640 641 // Return true if the symbol is a PIC function. 642 template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) { 643 if (!Sym->isFunc()) 644 return false; 645 646 if (Sym->StOther & STO_MIPS_PIC) 647 return true; 648 649 if (!Sym->Section) 650 return false; 651 652 ObjFile<ELFT> *File = 653 cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>(); 654 if (!File) 655 return false; 656 657 return File->getObj().getHeader()->e_flags & EF_MIPS_PIC; 658 } 659 660 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 661 static MIPS<ELFT> Target; 662 return &Target; 663 } 664 665 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 666 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 667 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 668 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 669 670 template bool elf::isMipsPIC<ELF32LE>(const Defined *); 671 template bool elf::isMipsPIC<ELF32BE>(const Defined *); 672 template bool elf::isMipsPIC<ELF64LE>(const Defined *); 673 template bool elf::isMipsPIC<ELF64BE>(const Defined *); 674