1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "InputFiles.h" 11 #include "OutputSections.h" 12 #include "Symbols.h" 13 #include "SyntheticSections.h" 14 #include "Target.h" 15 #include "Thunks.h" 16 #include "lld/Common/ErrorHandler.h" 17 #include "llvm/Object/ELF.h" 18 #include "llvm/Support/Endian.h" 19 20 using namespace llvm; 21 using namespace llvm::object; 22 using namespace llvm::support::endian; 23 using namespace llvm::ELF; 24 using namespace lld; 25 using namespace lld::elf; 26 27 namespace { 28 template <class ELFT> class MIPS final : public TargetInfo { 29 public: 30 MIPS(); 31 uint32_t calcEFlags() const override; 32 RelExpr getRelExpr(RelType Type, const Symbol &S, 33 const uint8_t *Loc) const override; 34 int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override; 35 bool isPicRel(RelType Type) const override; 36 RelType getDynRel(RelType Type) const override; 37 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; 38 void writePltHeader(uint8_t *Buf) const override; 39 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 40 int32_t Index, unsigned RelOff) const override; 41 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 42 uint64_t BranchAddr, const Symbol &S) const override; 43 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 44 bool usesOnlyLowPageBits(RelType Type) const override; 45 }; 46 } // namespace 47 48 template <class ELFT> MIPS<ELFT>::MIPS() { 49 GotPltHeaderEntriesNum = 2; 50 DefaultMaxPageSize = 65536; 51 GotEntrySize = sizeof(typename ELFT::uint); 52 GotPltEntrySize = sizeof(typename ELFT::uint); 53 GotBaseSymInGotPlt = false; 54 PltEntrySize = 16; 55 PltHeaderSize = 32; 56 CopyRel = R_MIPS_COPY; 57 PltRel = R_MIPS_JUMP_SLOT; 58 NeedsThunks = true; 59 TrapInstr = 0xefefefef; 60 61 if (ELFT::Is64Bits) { 62 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 63 TlsGotRel = R_MIPS_TLS_TPREL64; 64 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 65 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 66 } else { 67 RelativeRel = R_MIPS_REL32; 68 TlsGotRel = R_MIPS_TLS_TPREL32; 69 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 70 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 71 } 72 } 73 74 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 75 return calcMipsEFlags<ELFT>(); 76 } 77 78 template <class ELFT> 79 RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S, 80 const uint8_t *Loc) const { 81 // See comment in the calculateMipsRelChain. 82 if (ELFT::Is64Bits || Config->MipsN32Abi) 83 Type &= 0xff; 84 85 switch (Type) { 86 case R_MIPS_JALR: 87 case R_MICROMIPS_JALR: 88 return R_HINT; 89 case R_MIPS_GPREL16: 90 case R_MIPS_GPREL32: 91 case R_MICROMIPS_GPREL16: 92 case R_MICROMIPS_GPREL7_S2: 93 return R_MIPS_GOTREL; 94 case R_MIPS_26: 95 case R_MICROMIPS_26_S1: 96 return R_PLT; 97 case R_MICROMIPS_PC26_S1: 98 return R_PLT_PC; 99 case R_MIPS_HI16: 100 case R_MIPS_LO16: 101 case R_MIPS_HIGHER: 102 case R_MIPS_HIGHEST: 103 case R_MICROMIPS_HI16: 104 case R_MICROMIPS_LO16: 105 case R_MICROMIPS_HIGHER: 106 case R_MICROMIPS_HIGHEST: 107 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 108 // offset between start of function and 'gp' value which by default 109 // equal to the start of .got section. In that case we consider these 110 // relocations as relative. 111 if (&S == ElfSym::MipsGpDisp) 112 return R_MIPS_GOT_GP_PC; 113 if (&S == ElfSym::MipsLocalGp) 114 return R_MIPS_GOT_GP; 115 LLVM_FALLTHROUGH; 116 case R_MIPS_32: 117 case R_MIPS_64: 118 case R_MIPS_GOT_OFST: 119 case R_MIPS_SUB: 120 case R_MIPS_TLS_DTPREL_HI16: 121 case R_MIPS_TLS_DTPREL_LO16: 122 case R_MIPS_TLS_DTPREL32: 123 case R_MIPS_TLS_DTPREL64: 124 case R_MIPS_TLS_TPREL_HI16: 125 case R_MIPS_TLS_TPREL_LO16: 126 case R_MIPS_TLS_TPREL32: 127 case R_MIPS_TLS_TPREL64: 128 case R_MICROMIPS_GOT_OFST: 129 case R_MICROMIPS_SUB: 130 case R_MICROMIPS_TLS_DTPREL_HI16: 131 case R_MICROMIPS_TLS_DTPREL_LO16: 132 case R_MICROMIPS_TLS_TPREL_HI16: 133 case R_MICROMIPS_TLS_TPREL_LO16: 134 return R_ABS; 135 case R_MIPS_PC32: 136 case R_MIPS_PC16: 137 case R_MIPS_PC19_S2: 138 case R_MIPS_PC21_S2: 139 case R_MIPS_PC26_S2: 140 case R_MIPS_PCHI16: 141 case R_MIPS_PCLO16: 142 case R_MICROMIPS_PC7_S1: 143 case R_MICROMIPS_PC10_S1: 144 case R_MICROMIPS_PC16_S1: 145 case R_MICROMIPS_PC18_S3: 146 case R_MICROMIPS_PC19_S2: 147 case R_MICROMIPS_PC23_S2: 148 case R_MICROMIPS_PC21_S1: 149 return R_PC; 150 case R_MIPS_GOT16: 151 case R_MICROMIPS_GOT16: 152 if (S.isLocal()) 153 return R_MIPS_GOT_LOCAL_PAGE; 154 LLVM_FALLTHROUGH; 155 case R_MIPS_CALL16: 156 case R_MIPS_GOT_DISP: 157 case R_MIPS_TLS_GOTTPREL: 158 case R_MICROMIPS_CALL16: 159 case R_MICROMIPS_GOT_DISP: 160 case R_MICROMIPS_TLS_GOTTPREL: 161 return R_MIPS_GOT_OFF; 162 case R_MIPS_CALL_HI16: 163 case R_MIPS_CALL_LO16: 164 case R_MIPS_GOT_HI16: 165 case R_MIPS_GOT_LO16: 166 case R_MICROMIPS_CALL_HI16: 167 case R_MICROMIPS_CALL_LO16: 168 case R_MICROMIPS_GOT_HI16: 169 case R_MICROMIPS_GOT_LO16: 170 return R_MIPS_GOT_OFF32; 171 case R_MIPS_GOT_PAGE: 172 case R_MICROMIPS_GOT_PAGE: 173 return R_MIPS_GOT_LOCAL_PAGE; 174 case R_MIPS_TLS_GD: 175 case R_MICROMIPS_TLS_GD: 176 return R_MIPS_TLSGD; 177 case R_MIPS_TLS_LDM: 178 case R_MICROMIPS_TLS_LDM: 179 return R_MIPS_TLSLD; 180 case R_MIPS_NONE: 181 return R_NONE; 182 default: 183 return R_INVALID; 184 } 185 } 186 187 template <class ELFT> bool MIPS<ELFT>::isPicRel(RelType Type) const { 188 return Type == R_MIPS_32 || Type == R_MIPS_64; 189 } 190 191 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const { 192 return RelativeRel; 193 } 194 195 template <class ELFT> 196 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const { 197 uint64_t VA = InX::Plt->getVA(); 198 if (isMicroMips()) 199 VA |= 1; 200 write32<ELFT::TargetEndianness>(Buf, VA); 201 } 202 203 template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) { 204 // The major opcode of a microMIPS instruction needs to appear 205 // in the first 16-bit word (lowest address) for efficient hardware 206 // decode so that it knows if the instruction is 16-bit or 32-bit 207 // as early as possible. To do so, little-endian binaries keep 16-bit 208 // words in a big-endian order. That is why we have to swap these 209 // words to get a correct value. 210 uint32_t V = read32<E>(Loc); 211 if (E == support::little) 212 return (V << 16) | (V >> 16); 213 return V; 214 } 215 216 template <endianness E> 217 static void writeValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 218 uint8_t Shift) { 219 uint32_t Instr = read32<E>(Loc); 220 uint32_t Mask = 0xffffffff >> (32 - BitsSize); 221 uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 222 write32<E>(Loc, Data); 223 } 224 225 template <endianness E> 226 static void writeShuffleValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 227 uint8_t Shift) { 228 // See comments in readShuffle for purpose of this code. 229 uint16_t *Words = (uint16_t *)Loc; 230 if (E == support::little) 231 std::swap(Words[0], Words[1]); 232 233 writeValue<E>(Loc, V, BitsSize, Shift); 234 235 if (E == support::little) 236 std::swap(Words[0], Words[1]); 237 } 238 239 template <endianness E> 240 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 241 uint8_t Shift) { 242 uint16_t Instr = read16<E>(Loc); 243 uint16_t Mask = 0xffff >> (16 - BitsSize); 244 uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 245 write16<E>(Loc, Data); 246 } 247 248 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const { 249 const endianness E = ELFT::TargetEndianness; 250 if (isMicroMips()) { 251 uint64_t GotPlt = InX::GotPlt->getVA(); 252 uint64_t Plt = InX::Plt->getVA(); 253 // Overwrite trap instructions written by Writer::writeTrapInstr. 254 memset(Buf, 0, PltHeaderSize); 255 256 write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 257 write16<E>(Buf + 4, 0xff23); // lw $25, 0($3) 258 write16<E>(Buf + 8, 0x0535); // subu16 $2, $2, $3 259 write16<E>(Buf + 10, 0x2525); // srl16 $2, $2, 2 260 write16<E>(Buf + 12, 0x3302); // addiu $24, $2, -2 261 write16<E>(Buf + 14, 0xfffe); 262 write16<E>(Buf + 16, 0x0dff); // move $15, $31 263 if (isMipsR6()) { 264 write16<E>(Buf + 18, 0x0f83); // move $28, $3 265 write16<E>(Buf + 20, 0x472b); // jalrc $25 266 write16<E>(Buf + 22, 0x0c00); // nop 267 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt); 268 } else { 269 write16<E>(Buf + 18, 0x45f9); // jalrc $25 270 write16<E>(Buf + 20, 0x0f83); // move $28, $3 271 write16<E>(Buf + 22, 0x0c00); // nop 272 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt); 273 } 274 return; 275 } 276 277 if (Config->MipsN32Abi) { 278 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 279 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 280 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 281 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 282 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 283 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 284 } else if (ELFT::Is64Bits) { 285 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 286 write32<E>(Buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14) 287 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 288 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 289 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 290 write32<E>(Buf + 20, 0x0018c0c2); // srl $24, $24, 3 291 } else { 292 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 293 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 294 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 295 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 296 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 297 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 298 } 299 300 uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809; 301 write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25 302 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 303 304 uint64_t GotPlt = InX::GotPlt->getVA(); 305 writeValue<E>(Buf, GotPlt + 0x8000, 16, 16); 306 writeValue<E>(Buf + 4, GotPlt, 16, 0); 307 writeValue<E>(Buf + 8, GotPlt, 16, 0); 308 } 309 310 template <class ELFT> 311 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 312 uint64_t PltEntryAddr, int32_t Index, 313 unsigned RelOff) const { 314 const endianness E = ELFT::TargetEndianness; 315 if (isMicroMips()) { 316 // Overwrite trap instructions written by Writer::writeTrapInstr. 317 memset(Buf, 0, PltEntrySize); 318 319 if (isMipsR6()) { 320 write16<E>(Buf, 0x7840); // addiupc $2, (GOTPLT) - . 321 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 322 write16<E>(Buf + 8, 0x0f02); // move $24, $2 323 write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25 324 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr); 325 } else { 326 write16<E>(Buf, 0x7900); // addiupc $2, (GOTPLT) - . 327 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 328 write16<E>(Buf + 8, 0x4599); // jrc $25 / jr16 $25 329 write16<E>(Buf + 10, 0x0f02); // move $24, $2 330 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr); 331 } 332 return; 333 } 334 335 uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009) 336 : (Config->ZHazardplt ? 0x03200408 : 0x03200008); 337 338 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 339 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 340 write32<E>(Buf + 8, JrInst); // jr $25 / jr.hb $25 341 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 342 writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16); 343 writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0); 344 writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0); 345 } 346 347 template <class ELFT> 348 bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 349 uint64_t BranchAddr, const Symbol &S) const { 350 // Any MIPS PIC code function is invoked with its address in register $t9. 351 // So if we have a branch instruction from non-PIC code to the PIC one 352 // we cannot make the jump directly and need to create a small stubs 353 // to save the target function address. 354 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 355 if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 && 356 Type != R_MICROMIPS_PC26_S1) 357 return false; 358 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 359 if (!F) 360 return false; 361 // If current file has PIC code, LA25 stub is not required. 362 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 363 return false; 364 auto *D = dyn_cast<Defined>(&S); 365 // LA25 is required if target file has PIC code 366 // or target symbol is a PIC symbol. 367 return D && isMipsPIC<ELFT>(D); 368 } 369 370 template <class ELFT> 371 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const { 372 const endianness E = ELFT::TargetEndianness; 373 switch (Type) { 374 case R_MIPS_32: 375 case R_MIPS_GPREL32: 376 case R_MIPS_TLS_DTPREL32: 377 case R_MIPS_TLS_TPREL32: 378 return SignExtend64<32>(read32<E>(Buf)); 379 case R_MIPS_26: 380 // FIXME (simon): If the relocation target symbol is not a PLT entry 381 // we should use another expression for calculation: 382 // ((A << 2) | (P & 0xf0000000)) >> 2 383 return SignExtend64<28>(read32<E>(Buf) << 2); 384 case R_MIPS_GOT16: 385 case R_MIPS_HI16: 386 case R_MIPS_PCHI16: 387 return SignExtend64<16>(read32<E>(Buf)) << 16; 388 case R_MIPS_GPREL16: 389 case R_MIPS_LO16: 390 case R_MIPS_PCLO16: 391 case R_MIPS_TLS_DTPREL_HI16: 392 case R_MIPS_TLS_DTPREL_LO16: 393 case R_MIPS_TLS_TPREL_HI16: 394 case R_MIPS_TLS_TPREL_LO16: 395 return SignExtend64<16>(read32<E>(Buf)); 396 case R_MICROMIPS_GOT16: 397 case R_MICROMIPS_HI16: 398 return SignExtend64<16>(readShuffle<E>(Buf)) << 16; 399 case R_MICROMIPS_GPREL16: 400 case R_MICROMIPS_LO16: 401 case R_MICROMIPS_TLS_DTPREL_HI16: 402 case R_MICROMIPS_TLS_DTPREL_LO16: 403 case R_MICROMIPS_TLS_TPREL_HI16: 404 case R_MICROMIPS_TLS_TPREL_LO16: 405 return SignExtend64<16>(readShuffle<E>(Buf)); 406 case R_MICROMIPS_GPREL7_S2: 407 return SignExtend64<9>(readShuffle<E>(Buf) << 2); 408 case R_MIPS_PC16: 409 return SignExtend64<18>(read32<E>(Buf) << 2); 410 case R_MIPS_PC19_S2: 411 return SignExtend64<21>(read32<E>(Buf) << 2); 412 case R_MIPS_PC21_S2: 413 return SignExtend64<23>(read32<E>(Buf) << 2); 414 case R_MIPS_PC26_S2: 415 return SignExtend64<28>(read32<E>(Buf) << 2); 416 case R_MIPS_PC32: 417 return SignExtend64<32>(read32<E>(Buf)); 418 case R_MICROMIPS_26_S1: 419 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 420 case R_MICROMIPS_PC7_S1: 421 return SignExtend64<8>(read16<E>(Buf) << 1); 422 case R_MICROMIPS_PC10_S1: 423 return SignExtend64<11>(read16<E>(Buf) << 1); 424 case R_MICROMIPS_PC16_S1: 425 return SignExtend64<17>(readShuffle<E>(Buf) << 1); 426 case R_MICROMIPS_PC18_S3: 427 return SignExtend64<21>(readShuffle<E>(Buf) << 3); 428 case R_MICROMIPS_PC19_S2: 429 return SignExtend64<21>(readShuffle<E>(Buf) << 2); 430 case R_MICROMIPS_PC21_S1: 431 return SignExtend64<22>(readShuffle<E>(Buf) << 1); 432 case R_MICROMIPS_PC23_S2: 433 return SignExtend64<25>(readShuffle<E>(Buf) << 2); 434 case R_MICROMIPS_PC26_S1: 435 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 436 default: 437 return 0; 438 } 439 } 440 441 static std::pair<uint32_t, uint64_t> 442 calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) { 443 // MIPS N64 ABI packs multiple relocations into the single relocation 444 // record. In general, all up to three relocations can have arbitrary 445 // types. In fact, Clang and GCC uses only a few combinations. For now, 446 // we support two of them. That is allow to pass at least all LLVM 447 // test suite cases. 448 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 449 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 450 // The first relocation is a 'real' relocation which is calculated 451 // using the corresponding symbol's value. The second and the third 452 // relocations used to modify result of the first one: extend it to 453 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 454 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 455 RelType Type2 = (Type >> 8) & 0xff; 456 RelType Type3 = (Type >> 16) & 0xff; 457 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 458 return std::make_pair(Type, Val); 459 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 460 return std::make_pair(Type2, Val); 461 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 462 return std::make_pair(Type3, -Val); 463 if (Type2 == R_MICROMIPS_SUB && 464 (Type3 == R_MICROMIPS_HI16 || Type3 == R_MICROMIPS_LO16)) 465 return std::make_pair(Type3, -Val); 466 error(getErrorLocation(Loc) + "unsupported relocations combination " + 467 Twine(Type)); 468 return std::make_pair(Type & 0xff, Val); 469 } 470 471 template <class ELFT> 472 void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 473 const endianness E = ELFT::TargetEndianness; 474 475 if (ELFT::Is64Bits || Config->MipsN32Abi) 476 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 477 478 // Thread pointer and DRP offsets from the start of TLS data area. 479 // https://www.linux-mips.org/wiki/NPTL 480 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 481 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 || 482 Type == R_MICROMIPS_TLS_DTPREL_HI16 || 483 Type == R_MICROMIPS_TLS_DTPREL_LO16) { 484 Val -= 0x8000; 485 } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 486 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 || 487 Type == R_MICROMIPS_TLS_TPREL_HI16 || 488 Type == R_MICROMIPS_TLS_TPREL_LO16) { 489 Val -= 0x7000; 490 } 491 492 switch (Type) { 493 case R_MIPS_32: 494 case R_MIPS_GPREL32: 495 case R_MIPS_TLS_DTPREL32: 496 case R_MIPS_TLS_TPREL32: 497 write32<E>(Loc, Val); 498 break; 499 case R_MIPS_64: 500 case R_MIPS_TLS_DTPREL64: 501 case R_MIPS_TLS_TPREL64: 502 write64<E>(Loc, Val); 503 break; 504 case R_MIPS_26: 505 writeValue<E>(Loc, Val, 26, 2); 506 break; 507 case R_MIPS_GOT16: 508 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 509 // is updated addend (not a GOT index). In that case write high 16 bits 510 // to store a correct addend value. 511 if (Config->Relocatable) { 512 writeValue<E>(Loc, Val + 0x8000, 16, 16); 513 } else { 514 checkInt(Loc, Val, 16, Type); 515 writeValue<E>(Loc, Val, 16, 0); 516 } 517 break; 518 case R_MICROMIPS_GOT16: 519 if (Config->Relocatable) { 520 writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16); 521 } else { 522 checkInt(Loc, Val, 16, Type); 523 writeShuffleValue<E>(Loc, Val, 16, 0); 524 } 525 break; 526 case R_MIPS_CALL16: 527 case R_MIPS_GOT_DISP: 528 case R_MIPS_GOT_PAGE: 529 case R_MIPS_GPREL16: 530 case R_MIPS_TLS_GD: 531 case R_MIPS_TLS_GOTTPREL: 532 case R_MIPS_TLS_LDM: 533 checkInt(Loc, Val, 16, Type); 534 LLVM_FALLTHROUGH; 535 case R_MIPS_CALL_LO16: 536 case R_MIPS_GOT_LO16: 537 case R_MIPS_GOT_OFST: 538 case R_MIPS_LO16: 539 case R_MIPS_PCLO16: 540 case R_MIPS_TLS_DTPREL_LO16: 541 case R_MIPS_TLS_TPREL_LO16: 542 writeValue<E>(Loc, Val, 16, 0); 543 break; 544 case R_MICROMIPS_GOT_DISP: 545 case R_MICROMIPS_GOT_PAGE: 546 case R_MICROMIPS_GPREL16: 547 case R_MICROMIPS_TLS_GD: 548 case R_MICROMIPS_TLS_LDM: 549 checkInt(Loc, Val, 16, Type); 550 writeShuffleValue<E>(Loc, Val, 16, 0); 551 break; 552 case R_MICROMIPS_CALL16: 553 case R_MICROMIPS_CALL_LO16: 554 case R_MICROMIPS_GOT_OFST: 555 case R_MICROMIPS_LO16: 556 case R_MICROMIPS_TLS_DTPREL_LO16: 557 case R_MICROMIPS_TLS_GOTTPREL: 558 case R_MICROMIPS_TLS_TPREL_LO16: 559 writeShuffleValue<E>(Loc, Val, 16, 0); 560 break; 561 case R_MICROMIPS_GPREL7_S2: 562 checkInt(Loc, Val, 7, Type); 563 writeShuffleValue<E>(Loc, Val, 7, 2); 564 break; 565 case R_MIPS_CALL_HI16: 566 case R_MIPS_GOT_HI16: 567 case R_MIPS_HI16: 568 case R_MIPS_PCHI16: 569 case R_MIPS_TLS_DTPREL_HI16: 570 case R_MIPS_TLS_TPREL_HI16: 571 writeValue<E>(Loc, Val + 0x8000, 16, 16); 572 break; 573 case R_MICROMIPS_CALL_HI16: 574 case R_MICROMIPS_GOT_HI16: 575 case R_MICROMIPS_HI16: 576 case R_MICROMIPS_TLS_DTPREL_HI16: 577 case R_MICROMIPS_TLS_TPREL_HI16: 578 writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16); 579 break; 580 case R_MIPS_HIGHER: 581 writeValue<E>(Loc, Val + 0x80008000, 16, 32); 582 break; 583 case R_MIPS_HIGHEST: 584 writeValue<E>(Loc, Val + 0x800080008000, 16, 48); 585 break; 586 case R_MICROMIPS_HIGHER: 587 writeShuffleValue<E>(Loc, Val + 0x80008000, 16, 32); 588 break; 589 case R_MICROMIPS_HIGHEST: 590 writeShuffleValue<E>(Loc, Val + 0x800080008000, 16, 48); 591 break; 592 case R_MIPS_JALR: 593 case R_MICROMIPS_JALR: 594 // Ignore this optimization relocation for now 595 break; 596 case R_MIPS_PC16: 597 checkAlignment(Loc, Val, 4, Type); 598 checkInt(Loc, Val, 18, Type); 599 writeValue<E>(Loc, Val, 16, 2); 600 break; 601 case R_MIPS_PC19_S2: 602 checkAlignment(Loc, Val, 4, Type); 603 checkInt(Loc, Val, 21, Type); 604 writeValue<E>(Loc, Val, 19, 2); 605 break; 606 case R_MIPS_PC21_S2: 607 checkAlignment(Loc, Val, 4, Type); 608 checkInt(Loc, Val, 23, Type); 609 writeValue<E>(Loc, Val, 21, 2); 610 break; 611 case R_MIPS_PC26_S2: 612 checkAlignment(Loc, Val, 4, Type); 613 checkInt(Loc, Val, 28, Type); 614 writeValue<E>(Loc, Val, 26, 2); 615 break; 616 case R_MIPS_PC32: 617 writeValue<E>(Loc, Val, 32, 0); 618 break; 619 case R_MICROMIPS_26_S1: 620 case R_MICROMIPS_PC26_S1: 621 checkInt(Loc, Val, 27, Type); 622 writeShuffleValue<E>(Loc, Val, 26, 1); 623 break; 624 case R_MICROMIPS_PC7_S1: 625 checkInt(Loc, Val, 8, Type); 626 writeMicroRelocation16<E>(Loc, Val, 7, 1); 627 break; 628 case R_MICROMIPS_PC10_S1: 629 checkInt(Loc, Val, 11, Type); 630 writeMicroRelocation16<E>(Loc, Val, 10, 1); 631 break; 632 case R_MICROMIPS_PC16_S1: 633 checkInt(Loc, Val, 17, Type); 634 writeShuffleValue<E>(Loc, Val, 16, 1); 635 break; 636 case R_MICROMIPS_PC18_S3: 637 checkInt(Loc, Val, 21, Type); 638 writeShuffleValue<E>(Loc, Val, 18, 3); 639 break; 640 case R_MICROMIPS_PC19_S2: 641 checkInt(Loc, Val, 21, Type); 642 writeShuffleValue<E>(Loc, Val, 19, 2); 643 break; 644 case R_MICROMIPS_PC21_S1: 645 checkInt(Loc, Val, 22, Type); 646 writeShuffleValue<E>(Loc, Val, 21, 1); 647 break; 648 case R_MICROMIPS_PC23_S2: 649 checkInt(Loc, Val, 25, Type); 650 writeShuffleValue<E>(Loc, Val, 23, 2); 651 break; 652 default: 653 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 654 } 655 } 656 657 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const { 658 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST || 659 Type == R_MICROMIPS_LO16 || Type == R_MICROMIPS_GOT_OFST; 660 } 661 662 // Return true if the symbol is a PIC function. 663 template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) { 664 typedef typename ELFT::Ehdr Elf_Ehdr; 665 if (!Sym->Section || !Sym->isFunc()) 666 return false; 667 668 auto *Sec = cast<InputSectionBase>(Sym->Section); 669 const Elf_Ehdr *Hdr = Sec->template getFile<ELFT>()->getObj().getHeader(); 670 return (Sym->StOther & STO_MIPS_MIPS16) == STO_MIPS_PIC || 671 (Hdr->e_flags & EF_MIPS_PIC); 672 } 673 674 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 675 static MIPS<ELFT> Target; 676 return &Target; 677 } 678 679 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 680 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 681 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 682 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 683 684 template bool elf::isMipsPIC<ELF32LE>(const Defined *); 685 template bool elf::isMipsPIC<ELF32BE>(const Defined *); 686 template bool elf::isMipsPIC<ELF64LE>(const Defined *); 687 template bool elf::isMipsPIC<ELF64BE>(const Defined *); 688