1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "InputFiles.h" 11 #include "OutputSections.h" 12 #include "Symbols.h" 13 #include "SyntheticSections.h" 14 #include "Target.h" 15 #include "Thunks.h" 16 #include "lld/Common/ErrorHandler.h" 17 #include "llvm/Object/ELF.h" 18 #include "llvm/Support/Endian.h" 19 20 using namespace llvm; 21 using namespace llvm::object; 22 using namespace llvm::support::endian; 23 using namespace llvm::ELF; 24 using namespace lld; 25 using namespace lld::elf; 26 27 namespace { 28 template <class ELFT> class MIPS final : public TargetInfo { 29 public: 30 MIPS(); 31 uint32_t calcEFlags() const override; 32 RelExpr getRelExpr(RelType Type, const Symbol &S, 33 const uint8_t *Loc) const override; 34 int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override; 35 RelType getDynRel(RelType Type) const override; 36 void writeGotPlt(uint8_t *Buf, const Symbol &S) const override; 37 void writePltHeader(uint8_t *Buf) const override; 38 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 39 int32_t Index, unsigned RelOff) const override; 40 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 41 uint64_t BranchAddr, const Symbol &S) const override; 42 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 43 bool usesOnlyLowPageBits(RelType Type) const override; 44 }; 45 } // namespace 46 47 template <class ELFT> MIPS<ELFT>::MIPS() { 48 GotPltHeaderEntriesNum = 2; 49 DefaultMaxPageSize = 65536; 50 GotEntrySize = sizeof(typename ELFT::uint); 51 GotPltEntrySize = sizeof(typename ELFT::uint); 52 GotBaseSymInGotPlt = false; 53 PltEntrySize = 16; 54 PltHeaderSize = 32; 55 CopyRel = R_MIPS_COPY; 56 NoneRel = R_MIPS_NONE; 57 PltRel = R_MIPS_JUMP_SLOT; 58 NeedsThunks = true; 59 TrapInstr = 0xefefefef; 60 61 if (ELFT::Is64Bits) { 62 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 63 TlsGotRel = R_MIPS_TLS_TPREL64; 64 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 65 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 66 } else { 67 RelativeRel = R_MIPS_REL32; 68 TlsGotRel = R_MIPS_TLS_TPREL32; 69 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 70 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 71 } 72 } 73 74 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 75 return calcMipsEFlags<ELFT>(); 76 } 77 78 template <class ELFT> 79 RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const Symbol &S, 80 const uint8_t *Loc) const { 81 // See comment in the calculateMipsRelChain. 82 if (ELFT::Is64Bits || Config->MipsN32Abi) 83 Type &= 0xff; 84 85 switch (Type) { 86 case R_MIPS_JALR: 87 case R_MICROMIPS_JALR: 88 return R_HINT; 89 case R_MIPS_GPREL16: 90 case R_MIPS_GPREL32: 91 case R_MICROMIPS_GPREL16: 92 case R_MICROMIPS_GPREL7_S2: 93 return R_MIPS_GOTREL; 94 case R_MIPS_26: 95 case R_MICROMIPS_26_S1: 96 return R_PLT; 97 case R_MICROMIPS_PC26_S1: 98 return R_PLT_PC; 99 case R_MIPS_HI16: 100 case R_MIPS_LO16: 101 case R_MIPS_HIGHER: 102 case R_MIPS_HIGHEST: 103 case R_MICROMIPS_HI16: 104 case R_MICROMIPS_LO16: 105 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 106 // offset between start of function and 'gp' value which by default 107 // equal to the start of .got section. In that case we consider these 108 // relocations as relative. 109 if (&S == ElfSym::MipsGpDisp) 110 return R_MIPS_GOT_GP_PC; 111 if (&S == ElfSym::MipsLocalGp) 112 return R_MIPS_GOT_GP; 113 LLVM_FALLTHROUGH; 114 case R_MIPS_32: 115 case R_MIPS_64: 116 case R_MIPS_GOT_OFST: 117 case R_MIPS_SUB: 118 case R_MIPS_TLS_DTPREL_HI16: 119 case R_MIPS_TLS_DTPREL_LO16: 120 case R_MIPS_TLS_DTPREL32: 121 case R_MIPS_TLS_DTPREL64: 122 case R_MIPS_TLS_TPREL_HI16: 123 case R_MIPS_TLS_TPREL_LO16: 124 case R_MIPS_TLS_TPREL32: 125 case R_MIPS_TLS_TPREL64: 126 case R_MICROMIPS_TLS_DTPREL_HI16: 127 case R_MICROMIPS_TLS_DTPREL_LO16: 128 case R_MICROMIPS_TLS_TPREL_HI16: 129 case R_MICROMIPS_TLS_TPREL_LO16: 130 return R_ABS; 131 case R_MIPS_PC32: 132 case R_MIPS_PC16: 133 case R_MIPS_PC19_S2: 134 case R_MIPS_PC21_S2: 135 case R_MIPS_PC26_S2: 136 case R_MIPS_PCHI16: 137 case R_MIPS_PCLO16: 138 case R_MICROMIPS_PC7_S1: 139 case R_MICROMIPS_PC10_S1: 140 case R_MICROMIPS_PC16_S1: 141 case R_MICROMIPS_PC18_S3: 142 case R_MICROMIPS_PC19_S2: 143 case R_MICROMIPS_PC23_S2: 144 case R_MICROMIPS_PC21_S1: 145 return R_PC; 146 case R_MIPS_GOT16: 147 case R_MICROMIPS_GOT16: 148 if (S.isLocal()) 149 return R_MIPS_GOT_LOCAL_PAGE; 150 LLVM_FALLTHROUGH; 151 case R_MIPS_CALL16: 152 case R_MIPS_GOT_DISP: 153 case R_MIPS_TLS_GOTTPREL: 154 case R_MICROMIPS_CALL16: 155 case R_MICROMIPS_TLS_GOTTPREL: 156 return R_MIPS_GOT_OFF; 157 case R_MIPS_CALL_HI16: 158 case R_MIPS_CALL_LO16: 159 case R_MIPS_GOT_HI16: 160 case R_MIPS_GOT_LO16: 161 case R_MICROMIPS_CALL_HI16: 162 case R_MICROMIPS_CALL_LO16: 163 case R_MICROMIPS_GOT_HI16: 164 case R_MICROMIPS_GOT_LO16: 165 return R_MIPS_GOT_OFF32; 166 case R_MIPS_GOT_PAGE: 167 return R_MIPS_GOT_LOCAL_PAGE; 168 case R_MIPS_TLS_GD: 169 case R_MICROMIPS_TLS_GD: 170 return R_MIPS_TLSGD; 171 case R_MIPS_TLS_LDM: 172 case R_MICROMIPS_TLS_LDM: 173 return R_MIPS_TLSLD; 174 case R_MIPS_NONE: 175 return R_NONE; 176 default: 177 return R_INVALID; 178 } 179 } 180 181 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const { 182 if (Type == R_MIPS_32 || Type == R_MIPS_64) 183 return RelativeRel; 184 return R_MIPS_NONE; 185 } 186 187 template <class ELFT> 188 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const { 189 uint64_t VA = In.Plt->getVA(); 190 if (isMicroMips()) 191 VA |= 1; 192 write32<ELFT::TargetEndianness>(Buf, VA); 193 } 194 195 template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) { 196 // The major opcode of a microMIPS instruction needs to appear 197 // in the first 16-bit word (lowest address) for efficient hardware 198 // decode so that it knows if the instruction is 16-bit or 32-bit 199 // as early as possible. To do so, little-endian binaries keep 16-bit 200 // words in a big-endian order. That is why we have to swap these 201 // words to get a correct value. 202 uint32_t V = read32<E>(Loc); 203 if (E == support::little) 204 return (V << 16) | (V >> 16); 205 return V; 206 } 207 208 template <endianness E> 209 static void writeValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 210 uint8_t Shift) { 211 uint32_t Instr = read32<E>(Loc); 212 uint32_t Mask = 0xffffffff >> (32 - BitsSize); 213 uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 214 write32<E>(Loc, Data); 215 } 216 217 template <endianness E> 218 static void writeShuffleValue(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 219 uint8_t Shift) { 220 // See comments in readShuffle for purpose of this code. 221 uint16_t *Words = (uint16_t *)Loc; 222 if (E == support::little) 223 std::swap(Words[0], Words[1]); 224 225 writeValue<E>(Loc, V, BitsSize, Shift); 226 227 if (E == support::little) 228 std::swap(Words[0], Words[1]); 229 } 230 231 template <endianness E> 232 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 233 uint8_t Shift) { 234 uint16_t Instr = read16<E>(Loc); 235 uint16_t Mask = 0xffff >> (16 - BitsSize); 236 uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 237 write16<E>(Loc, Data); 238 } 239 240 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const { 241 const endianness E = ELFT::TargetEndianness; 242 if (isMicroMips()) { 243 uint64_t GotPlt = In.GotPlt->getVA(); 244 uint64_t Plt = In.Plt->getVA(); 245 // Overwrite trap instructions written by Writer::writeTrapInstr. 246 memset(Buf, 0, PltHeaderSize); 247 248 write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 249 write16<E>(Buf + 4, 0xff23); // lw $25, 0($3) 250 write16<E>(Buf + 8, 0x0535); // subu16 $2, $2, $3 251 write16<E>(Buf + 10, 0x2525); // srl16 $2, $2, 2 252 write16<E>(Buf + 12, 0x3302); // addiu $24, $2, -2 253 write16<E>(Buf + 14, 0xfffe); 254 write16<E>(Buf + 16, 0x0dff); // move $15, $31 255 if (isMipsR6()) { 256 write16<E>(Buf + 18, 0x0f83); // move $28, $3 257 write16<E>(Buf + 20, 0x472b); // jalrc $25 258 write16<E>(Buf + 22, 0x0c00); // nop 259 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt); 260 } else { 261 write16<E>(Buf + 18, 0x45f9); // jalrc $25 262 write16<E>(Buf + 20, 0x0f83); // move $28, $3 263 write16<E>(Buf + 22, 0x0c00); // nop 264 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt); 265 } 266 return; 267 } 268 269 if (Config->MipsN32Abi) { 270 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 271 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 272 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 273 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 274 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 275 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 276 } else if (ELFT::Is64Bits) { 277 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 278 write32<E>(Buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14) 279 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 280 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 281 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 282 write32<E>(Buf + 20, 0x0018c0c2); // srl $24, $24, 3 283 } else { 284 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 285 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 286 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 287 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 288 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 289 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 290 } 291 292 uint32_t JalrInst = Config->ZHazardplt ? 0x0320fc09 : 0x0320f809; 293 write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25 294 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 295 296 uint64_t GotPlt = In.GotPlt->getVA(); 297 writeValue<E>(Buf, GotPlt + 0x8000, 16, 16); 298 writeValue<E>(Buf + 4, GotPlt, 16, 0); 299 writeValue<E>(Buf + 8, GotPlt, 16, 0); 300 } 301 302 template <class ELFT> 303 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 304 uint64_t PltEntryAddr, int32_t Index, 305 unsigned RelOff) const { 306 const endianness E = ELFT::TargetEndianness; 307 if (isMicroMips()) { 308 // Overwrite trap instructions written by Writer::writeTrapInstr. 309 memset(Buf, 0, PltEntrySize); 310 311 if (isMipsR6()) { 312 write16<E>(Buf, 0x7840); // addiupc $2, (GOTPLT) - . 313 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 314 write16<E>(Buf + 8, 0x0f02); // move $24, $2 315 write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25 316 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr); 317 } else { 318 write16<E>(Buf, 0x7900); // addiupc $2, (GOTPLT) - . 319 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 320 write16<E>(Buf + 8, 0x4599); // jrc $25 / jr16 $25 321 write16<E>(Buf + 10, 0x0f02); // move $24, $2 322 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr); 323 } 324 return; 325 } 326 327 uint32_t JrInst = isMipsR6() ? (Config->ZHazardplt ? 0x03200409 : 0x03200009) 328 : (Config->ZHazardplt ? 0x03200408 : 0x03200008); 329 330 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 331 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 332 write32<E>(Buf + 8, JrInst); // jr $25 / jr.hb $25 333 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 334 writeValue<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16); 335 writeValue<E>(Buf + 4, GotPltEntryAddr, 16, 0); 336 writeValue<E>(Buf + 12, GotPltEntryAddr, 16, 0); 337 } 338 339 template <class ELFT> 340 bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 341 uint64_t BranchAddr, const Symbol &S) const { 342 // Any MIPS PIC code function is invoked with its address in register $t9. 343 // So if we have a branch instruction from non-PIC code to the PIC one 344 // we cannot make the jump directly and need to create a small stubs 345 // to save the target function address. 346 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 347 if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 && 348 Type != R_MICROMIPS_PC26_S1) 349 return false; 350 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 351 if (!F) 352 return false; 353 // If current file has PIC code, LA25 stub is not required. 354 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 355 return false; 356 auto *D = dyn_cast<Defined>(&S); 357 // LA25 is required if target file has PIC code 358 // or target symbol is a PIC symbol. 359 return D && isMipsPIC<ELFT>(D); 360 } 361 362 template <class ELFT> 363 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const { 364 const endianness E = ELFT::TargetEndianness; 365 switch (Type) { 366 case R_MIPS_32: 367 case R_MIPS_GPREL32: 368 case R_MIPS_TLS_DTPREL32: 369 case R_MIPS_TLS_TPREL32: 370 return SignExtend64<32>(read32<E>(Buf)); 371 case R_MIPS_26: 372 // FIXME (simon): If the relocation target symbol is not a PLT entry 373 // we should use another expression for calculation: 374 // ((A << 2) | (P & 0xf0000000)) >> 2 375 return SignExtend64<28>(read32<E>(Buf) << 2); 376 case R_MIPS_GOT16: 377 case R_MIPS_HI16: 378 case R_MIPS_PCHI16: 379 return SignExtend64<16>(read32<E>(Buf)) << 16; 380 case R_MIPS_GPREL16: 381 case R_MIPS_LO16: 382 case R_MIPS_PCLO16: 383 case R_MIPS_TLS_DTPREL_HI16: 384 case R_MIPS_TLS_DTPREL_LO16: 385 case R_MIPS_TLS_TPREL_HI16: 386 case R_MIPS_TLS_TPREL_LO16: 387 return SignExtend64<16>(read32<E>(Buf)); 388 case R_MICROMIPS_GOT16: 389 case R_MICROMIPS_HI16: 390 return SignExtend64<16>(readShuffle<E>(Buf)) << 16; 391 case R_MICROMIPS_GPREL16: 392 case R_MICROMIPS_LO16: 393 case R_MICROMIPS_TLS_DTPREL_HI16: 394 case R_MICROMIPS_TLS_DTPREL_LO16: 395 case R_MICROMIPS_TLS_TPREL_HI16: 396 case R_MICROMIPS_TLS_TPREL_LO16: 397 return SignExtend64<16>(readShuffle<E>(Buf)); 398 case R_MICROMIPS_GPREL7_S2: 399 return SignExtend64<9>(readShuffle<E>(Buf) << 2); 400 case R_MIPS_PC16: 401 return SignExtend64<18>(read32<E>(Buf) << 2); 402 case R_MIPS_PC19_S2: 403 return SignExtend64<21>(read32<E>(Buf) << 2); 404 case R_MIPS_PC21_S2: 405 return SignExtend64<23>(read32<E>(Buf) << 2); 406 case R_MIPS_PC26_S2: 407 return SignExtend64<28>(read32<E>(Buf) << 2); 408 case R_MIPS_PC32: 409 return SignExtend64<32>(read32<E>(Buf)); 410 case R_MICROMIPS_26_S1: 411 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 412 case R_MICROMIPS_PC7_S1: 413 return SignExtend64<8>(read16<E>(Buf) << 1); 414 case R_MICROMIPS_PC10_S1: 415 return SignExtend64<11>(read16<E>(Buf) << 1); 416 case R_MICROMIPS_PC16_S1: 417 return SignExtend64<17>(readShuffle<E>(Buf) << 1); 418 case R_MICROMIPS_PC18_S3: 419 return SignExtend64<21>(readShuffle<E>(Buf) << 3); 420 case R_MICROMIPS_PC19_S2: 421 return SignExtend64<21>(readShuffle<E>(Buf) << 2); 422 case R_MICROMIPS_PC21_S1: 423 return SignExtend64<22>(readShuffle<E>(Buf) << 1); 424 case R_MICROMIPS_PC23_S2: 425 return SignExtend64<25>(readShuffle<E>(Buf) << 2); 426 case R_MICROMIPS_PC26_S1: 427 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 428 default: 429 return 0; 430 } 431 } 432 433 static std::pair<uint32_t, uint64_t> 434 calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) { 435 // MIPS N64 ABI packs multiple relocations into the single relocation 436 // record. In general, all up to three relocations can have arbitrary 437 // types. In fact, Clang and GCC uses only a few combinations. For now, 438 // we support two of them. That is allow to pass at least all LLVM 439 // test suite cases. 440 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 441 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 442 // The first relocation is a 'real' relocation which is calculated 443 // using the corresponding symbol's value. The second and the third 444 // relocations used to modify result of the first one: extend it to 445 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 446 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 447 RelType Type2 = (Type >> 8) & 0xff; 448 RelType Type3 = (Type >> 16) & 0xff; 449 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 450 return std::make_pair(Type, Val); 451 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 452 return std::make_pair(Type2, Val); 453 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 454 return std::make_pair(Type3, -Val); 455 error(getErrorLocation(Loc) + "unsupported relocations combination " + 456 Twine(Type)); 457 return std::make_pair(Type & 0xff, Val); 458 } 459 460 template <class ELFT> 461 void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 462 const endianness E = ELFT::TargetEndianness; 463 464 if (ELFT::Is64Bits || Config->MipsN32Abi) 465 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 466 467 // Thread pointer and DRP offsets from the start of TLS data area. 468 // https://www.linux-mips.org/wiki/NPTL 469 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 470 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 || 471 Type == R_MICROMIPS_TLS_DTPREL_HI16 || 472 Type == R_MICROMIPS_TLS_DTPREL_LO16) { 473 Val -= 0x8000; 474 } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 475 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 || 476 Type == R_MICROMIPS_TLS_TPREL_HI16 || 477 Type == R_MICROMIPS_TLS_TPREL_LO16) { 478 Val -= 0x7000; 479 } 480 481 switch (Type) { 482 case R_MIPS_32: 483 case R_MIPS_GPREL32: 484 case R_MIPS_TLS_DTPREL32: 485 case R_MIPS_TLS_TPREL32: 486 write32<E>(Loc, Val); 487 break; 488 case R_MIPS_64: 489 case R_MIPS_TLS_DTPREL64: 490 case R_MIPS_TLS_TPREL64: 491 write64<E>(Loc, Val); 492 break; 493 case R_MIPS_26: 494 writeValue<E>(Loc, Val, 26, 2); 495 break; 496 case R_MIPS_GOT16: 497 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 498 // is updated addend (not a GOT index). In that case write high 16 bits 499 // to store a correct addend value. 500 if (Config->Relocatable) { 501 writeValue<E>(Loc, Val + 0x8000, 16, 16); 502 } else { 503 checkInt(Loc, Val, 16, Type); 504 writeValue<E>(Loc, Val, 16, 0); 505 } 506 break; 507 case R_MICROMIPS_GOT16: 508 if (Config->Relocatable) { 509 writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16); 510 } else { 511 checkInt(Loc, Val, 16, Type); 512 writeShuffleValue<E>(Loc, Val, 16, 0); 513 } 514 break; 515 case R_MIPS_CALL16: 516 case R_MIPS_GOT_DISP: 517 case R_MIPS_GOT_PAGE: 518 case R_MIPS_GPREL16: 519 case R_MIPS_TLS_GD: 520 case R_MIPS_TLS_GOTTPREL: 521 case R_MIPS_TLS_LDM: 522 checkInt(Loc, Val, 16, Type); 523 LLVM_FALLTHROUGH; 524 case R_MIPS_CALL_LO16: 525 case R_MIPS_GOT_LO16: 526 case R_MIPS_GOT_OFST: 527 case R_MIPS_LO16: 528 case R_MIPS_PCLO16: 529 case R_MIPS_TLS_DTPREL_LO16: 530 case R_MIPS_TLS_TPREL_LO16: 531 writeValue<E>(Loc, Val, 16, 0); 532 break; 533 case R_MICROMIPS_GPREL16: 534 case R_MICROMIPS_TLS_GD: 535 case R_MICROMIPS_TLS_LDM: 536 checkInt(Loc, Val, 16, Type); 537 writeShuffleValue<E>(Loc, Val, 16, 0); 538 break; 539 case R_MICROMIPS_CALL16: 540 case R_MICROMIPS_CALL_LO16: 541 case R_MICROMIPS_LO16: 542 case R_MICROMIPS_TLS_DTPREL_LO16: 543 case R_MICROMIPS_TLS_GOTTPREL: 544 case R_MICROMIPS_TLS_TPREL_LO16: 545 writeShuffleValue<E>(Loc, Val, 16, 0); 546 break; 547 case R_MICROMIPS_GPREL7_S2: 548 checkInt(Loc, Val, 7, Type); 549 writeShuffleValue<E>(Loc, Val, 7, 2); 550 break; 551 case R_MIPS_CALL_HI16: 552 case R_MIPS_GOT_HI16: 553 case R_MIPS_HI16: 554 case R_MIPS_PCHI16: 555 case R_MIPS_TLS_DTPREL_HI16: 556 case R_MIPS_TLS_TPREL_HI16: 557 writeValue<E>(Loc, Val + 0x8000, 16, 16); 558 break; 559 case R_MICROMIPS_CALL_HI16: 560 case R_MICROMIPS_GOT_HI16: 561 case R_MICROMIPS_HI16: 562 case R_MICROMIPS_TLS_DTPREL_HI16: 563 case R_MICROMIPS_TLS_TPREL_HI16: 564 writeShuffleValue<E>(Loc, Val + 0x8000, 16, 16); 565 break; 566 case R_MIPS_HIGHER: 567 writeValue<E>(Loc, Val + 0x80008000, 16, 32); 568 break; 569 case R_MIPS_HIGHEST: 570 writeValue<E>(Loc, Val + 0x800080008000, 16, 48); 571 break; 572 case R_MIPS_JALR: 573 case R_MICROMIPS_JALR: 574 // Ignore this optimization relocation for now 575 break; 576 case R_MIPS_PC16: 577 checkAlignment(Loc, Val, 4, Type); 578 checkInt(Loc, Val, 18, Type); 579 writeValue<E>(Loc, Val, 16, 2); 580 break; 581 case R_MIPS_PC19_S2: 582 checkAlignment(Loc, Val, 4, Type); 583 checkInt(Loc, Val, 21, Type); 584 writeValue<E>(Loc, Val, 19, 2); 585 break; 586 case R_MIPS_PC21_S2: 587 checkAlignment(Loc, Val, 4, Type); 588 checkInt(Loc, Val, 23, Type); 589 writeValue<E>(Loc, Val, 21, 2); 590 break; 591 case R_MIPS_PC26_S2: 592 checkAlignment(Loc, Val, 4, Type); 593 checkInt(Loc, Val, 28, Type); 594 writeValue<E>(Loc, Val, 26, 2); 595 break; 596 case R_MIPS_PC32: 597 writeValue<E>(Loc, Val, 32, 0); 598 break; 599 case R_MICROMIPS_26_S1: 600 case R_MICROMIPS_PC26_S1: 601 checkInt(Loc, Val, 27, Type); 602 writeShuffleValue<E>(Loc, Val, 26, 1); 603 break; 604 case R_MICROMIPS_PC7_S1: 605 checkInt(Loc, Val, 8, Type); 606 writeMicroRelocation16<E>(Loc, Val, 7, 1); 607 break; 608 case R_MICROMIPS_PC10_S1: 609 checkInt(Loc, Val, 11, Type); 610 writeMicroRelocation16<E>(Loc, Val, 10, 1); 611 break; 612 case R_MICROMIPS_PC16_S1: 613 checkInt(Loc, Val, 17, Type); 614 writeShuffleValue<E>(Loc, Val, 16, 1); 615 break; 616 case R_MICROMIPS_PC18_S3: 617 checkInt(Loc, Val, 21, Type); 618 writeShuffleValue<E>(Loc, Val, 18, 3); 619 break; 620 case R_MICROMIPS_PC19_S2: 621 checkInt(Loc, Val, 21, Type); 622 writeShuffleValue<E>(Loc, Val, 19, 2); 623 break; 624 case R_MICROMIPS_PC21_S1: 625 checkInt(Loc, Val, 22, Type); 626 writeShuffleValue<E>(Loc, Val, 21, 1); 627 break; 628 case R_MICROMIPS_PC23_S2: 629 checkInt(Loc, Val, 25, Type); 630 writeShuffleValue<E>(Loc, Val, 23, 2); 631 break; 632 default: 633 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 634 } 635 } 636 637 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const { 638 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST || 639 Type == R_MICROMIPS_LO16; 640 } 641 642 // Return true if the symbol is a PIC function. 643 template <class ELFT> bool elf::isMipsPIC(const Defined *Sym) { 644 if (!Sym->isFunc()) 645 return false; 646 647 if (Sym->StOther & STO_MIPS_PIC) 648 return true; 649 650 if (!Sym->Section) 651 return false; 652 653 ObjFile<ELFT> *File = 654 cast<InputSectionBase>(Sym->Section)->template getFile<ELFT>(); 655 if (!File) 656 return false; 657 658 return File->getObj().getHeader()->e_flags & EF_MIPS_PIC; 659 } 660 661 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 662 static MIPS<ELFT> Target; 663 return &Target; 664 } 665 666 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 667 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 668 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 669 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 670 671 template bool elf::isMipsPIC<ELF32LE>(const Defined *); 672 template bool elf::isMipsPIC<ELF32BE>(const Defined *); 673 template bool elf::isMipsPIC<ELF64LE>(const Defined *); 674 template bool elf::isMipsPIC<ELF64BE>(const Defined *); 675