1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Error.h" 11 #include "InputFiles.h" 12 #include "OutputSections.h" 13 #include "Symbols.h" 14 #include "SyntheticSections.h" 15 #include "Target.h" 16 #include "Thunks.h" 17 #include "llvm/Object/ELF.h" 18 #include "llvm/Support/Endian.h" 19 20 using namespace llvm; 21 using namespace llvm::object; 22 using namespace llvm::support::endian; 23 using namespace llvm::ELF; 24 using namespace lld; 25 using namespace lld::elf; 26 27 namespace { 28 template <class ELFT> class MIPS final : public TargetInfo { 29 public: 30 MIPS(); 31 RelExpr getRelExpr(RelType Type, const SymbolBody &S, 32 const uint8_t *Loc) const override; 33 int64_t getImplicitAddend(const uint8_t *Buf, RelType Type) const override; 34 bool isPicRel(RelType Type) const override; 35 RelType getDynRel(RelType Type) const override; 36 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 37 void writePltHeader(uint8_t *Buf) const override; 38 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 39 int32_t Index, unsigned RelOff) const override; 40 bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 41 const SymbolBody &S) const override; 42 void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override; 43 bool usesOnlyLowPageBits(RelType Type) const override; 44 }; 45 } // namespace 46 47 template <class ELFT> MIPS<ELFT>::MIPS() { 48 GotPltHeaderEntriesNum = 2; 49 DefaultMaxPageSize = 65536; 50 GotEntrySize = sizeof(typename ELFT::uint); 51 GotPltEntrySize = sizeof(typename ELFT::uint); 52 PltEntrySize = 16; 53 PltHeaderSize = 32; 54 CopyRel = R_MIPS_COPY; 55 PltRel = R_MIPS_JUMP_SLOT; 56 NeedsThunks = true; 57 TrapInstr = 0xefefefef; 58 59 if (ELFT::Is64Bits) { 60 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 61 TlsGotRel = R_MIPS_TLS_TPREL64; 62 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 63 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 64 } else { 65 RelativeRel = R_MIPS_REL32; 66 TlsGotRel = R_MIPS_TLS_TPREL32; 67 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 68 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 69 } 70 } 71 72 template <class ELFT> 73 RelExpr MIPS<ELFT>::getRelExpr(RelType Type, const SymbolBody &S, 74 const uint8_t *Loc) const { 75 // See comment in the calculateMipsRelChain. 76 if (ELFT::Is64Bits || Config->MipsN32Abi) 77 Type &= 0xff; 78 79 switch (Type) { 80 case R_MIPS_JALR: 81 case R_MICROMIPS_JALR: 82 return R_HINT; 83 case R_MIPS_GPREL16: 84 case R_MIPS_GPREL32: 85 case R_MICROMIPS_GPREL16: 86 case R_MICROMIPS_GPREL7_S2: 87 return R_MIPS_GOTREL; 88 case R_MIPS_26: 89 case R_MICROMIPS_26_S1: 90 return R_PLT; 91 case R_MICROMIPS_PC26_S1: 92 return R_PLT_PC; 93 case R_MIPS_HI16: 94 case R_MIPS_LO16: 95 case R_MIPS_HIGHER: 96 case R_MIPS_HIGHEST: 97 case R_MICROMIPS_HI16: 98 case R_MICROMIPS_LO16: 99 case R_MICROMIPS_HIGHER: 100 case R_MICROMIPS_HIGHEST: 101 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 102 // offset between start of function and 'gp' value which by default 103 // equal to the start of .got section. In that case we consider these 104 // relocations as relative. 105 if (&S == ElfSym::MipsGpDisp) 106 return R_MIPS_GOT_GP_PC; 107 if (&S == ElfSym::MipsLocalGp) 108 return R_MIPS_GOT_GP; 109 LLVM_FALLTHROUGH; 110 case R_MIPS_32: 111 case R_MIPS_64: 112 case R_MIPS_GOT_OFST: 113 case R_MIPS_SUB: 114 case R_MIPS_TLS_DTPREL_HI16: 115 case R_MIPS_TLS_DTPREL_LO16: 116 case R_MIPS_TLS_DTPREL32: 117 case R_MIPS_TLS_DTPREL64: 118 case R_MIPS_TLS_TPREL_HI16: 119 case R_MIPS_TLS_TPREL_LO16: 120 case R_MIPS_TLS_TPREL32: 121 case R_MIPS_TLS_TPREL64: 122 case R_MICROMIPS_GOT_OFST: 123 case R_MICROMIPS_SUB: 124 case R_MICROMIPS_TLS_DTPREL_HI16: 125 case R_MICROMIPS_TLS_DTPREL_LO16: 126 case R_MICROMIPS_TLS_TPREL_HI16: 127 case R_MICROMIPS_TLS_TPREL_LO16: 128 return R_ABS; 129 case R_MIPS_PC32: 130 case R_MIPS_PC16: 131 case R_MIPS_PC19_S2: 132 case R_MIPS_PC21_S2: 133 case R_MIPS_PC26_S2: 134 case R_MIPS_PCHI16: 135 case R_MIPS_PCLO16: 136 case R_MICROMIPS_PC7_S1: 137 case R_MICROMIPS_PC10_S1: 138 case R_MICROMIPS_PC16_S1: 139 case R_MICROMIPS_PC18_S3: 140 case R_MICROMIPS_PC19_S2: 141 case R_MICROMIPS_PC23_S2: 142 case R_MICROMIPS_PC21_S1: 143 return R_PC; 144 case R_MIPS_GOT16: 145 case R_MICROMIPS_GOT16: 146 if (S.isLocal()) 147 return R_MIPS_GOT_LOCAL_PAGE; 148 LLVM_FALLTHROUGH; 149 case R_MIPS_CALL16: 150 case R_MIPS_GOT_DISP: 151 case R_MIPS_TLS_GOTTPREL: 152 case R_MICROMIPS_CALL16: 153 case R_MICROMIPS_GOT_DISP: 154 case R_MICROMIPS_TLS_GOTTPREL: 155 return R_MIPS_GOT_OFF; 156 case R_MIPS_CALL_HI16: 157 case R_MIPS_CALL_LO16: 158 case R_MIPS_GOT_HI16: 159 case R_MIPS_GOT_LO16: 160 case R_MICROMIPS_CALL_HI16: 161 case R_MICROMIPS_CALL_LO16: 162 case R_MICROMIPS_GOT_HI16: 163 case R_MICROMIPS_GOT_LO16: 164 return R_MIPS_GOT_OFF32; 165 case R_MIPS_GOT_PAGE: 166 case R_MICROMIPS_GOT_PAGE: 167 return R_MIPS_GOT_LOCAL_PAGE; 168 case R_MIPS_TLS_GD: 169 case R_MICROMIPS_TLS_GD: 170 return R_MIPS_TLSGD; 171 case R_MIPS_TLS_LDM: 172 case R_MICROMIPS_TLS_LDM: 173 return R_MIPS_TLSLD; 174 case R_MIPS_NONE: 175 return R_NONE; 176 default: 177 return R_INVALID; 178 } 179 } 180 181 template <class ELFT> bool MIPS<ELFT>::isPicRel(RelType Type) const { 182 return Type == R_MIPS_32 || Type == R_MIPS_64; 183 } 184 185 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const { 186 return RelativeRel; 187 } 188 189 template <class ELFT> 190 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 191 write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA()); 192 } 193 194 template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) { 195 // The major opcode of a microMIPS instruction needs to appear 196 // in the first 16-bit word (lowest address) for efficient hardware 197 // decode so that it knows if the instruction is 16-bit or 32-bit 198 // as early as possible. To do so, little-endian binaries keep 16-bit 199 // words in a big-endian order. That is why we have to swap these 200 // words to get a correct value. 201 uint32_t V = read32<E>(Loc); 202 if (E == support::little) 203 return (V << 16) | (V >> 16); 204 return V; 205 } 206 207 template <endianness E> 208 static void writeRelocation(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 209 uint8_t Shift) { 210 uint32_t Instr = read32<E>(Loc); 211 uint32_t Mask = 0xffffffff >> (32 - BitsSize); 212 uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 213 write32<E>(Loc, Data); 214 } 215 216 template <endianness E> 217 static void writeMicroRelocation32(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 218 uint8_t Shift) { 219 // See comments in readShuffle for purpose of this code. 220 uint16_t *Words = (uint16_t *)Loc; 221 if (E == support::little) 222 std::swap(Words[0], Words[1]); 223 224 writeRelocation<E>(Loc, V, BitsSize, Shift); 225 226 if (E == support::little) 227 std::swap(Words[0], Words[1]); 228 } 229 230 template <endianness E> 231 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 232 uint8_t Shift) { 233 uint16_t Instr = read16<E>(Loc); 234 uint16_t Mask = 0xffff >> (16 - BitsSize); 235 uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 236 write16<E>(Loc, Data); 237 } 238 239 static bool isMicroMips() { return Config->MipsEFlags & EF_MIPS_MICROMIPS; } 240 241 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const { 242 const endianness E = ELFT::TargetEndianness; 243 if (isMicroMips()) { 244 uint64_t GotPlt = In<ELFT>::GotPlt->getVA(); 245 uint64_t Plt = In<ELFT>::Plt->getVA(); 246 // Overwrite trap instructions written by Writer::writeTrapInstr. 247 memset(Buf, 0, PltHeaderSize); 248 249 write16<E>(Buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 250 write16<E>(Buf + 4, 0xff23); // lw $25, 0($3) 251 write16<E>(Buf + 8, 0x0535); // subu16 $2, $2, $3 252 write16<E>(Buf + 10, 0x2525); // srl16 $2, $2, 2 253 write16<E>(Buf + 12, 0x3302); // addiu $24, $2, -2 254 write16<E>(Buf + 14, 0xfffe); 255 write16<E>(Buf + 16, 0x0dff); // move $15, $31 256 if (isMipsR6()) { 257 write16<E>(Buf + 18, 0x0f83); // move $28, $3 258 write16<E>(Buf + 20, 0x472b); // jalrc $25 259 write16<E>(Buf + 22, 0x0c00); // nop 260 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt); 261 } else { 262 write16<E>(Buf + 18, 0x45f9); // jalrc $25 263 write16<E>(Buf + 20, 0x0f83); // move $28, $3 264 write16<E>(Buf + 22, 0x0c00); // nop 265 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt); 266 } 267 return; 268 } 269 270 if (Config->MipsN32Abi) { 271 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 272 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 273 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 274 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 275 } else { 276 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 277 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 278 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 279 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 280 } 281 282 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 283 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 284 write32<E>(Buf + 24, 0x0320f809); // jalr $25 285 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 286 287 uint64_t GotPlt = InX::GotPlt->getVA(); 288 writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16); 289 writeRelocation<E>(Buf + 4, GotPlt, 16, 0); 290 writeRelocation<E>(Buf + 8, GotPlt, 16, 0); 291 } 292 293 template <class ELFT> 294 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 295 uint64_t PltEntryAddr, int32_t Index, 296 unsigned RelOff) const { 297 const endianness E = ELFT::TargetEndianness; 298 if (isMicroMips()) { 299 // Overwrite trap instructions written by Writer::writeTrapInstr. 300 memset(Buf, 0, PltEntrySize); 301 302 if (isMipsR6()) { 303 write16<E>(Buf, 0x7840); // addiupc $2, (GOTPLT) - . 304 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 305 write16<E>(Buf + 8, 0x0f02); // move $24, $2 306 write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25 307 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr); 308 } else { 309 write16<E>(Buf, 0x7900); // addiupc $2, (GOTPLT) - . 310 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 311 write16<E>(Buf + 8, 0x4599); // jrc $25 / jr16 $25 312 write16<E>(Buf + 10, 0x0f02); // move $24, $2 313 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr); 314 } 315 return; 316 } 317 318 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 319 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 320 write32<E>(Buf + 8, isMipsR6() ? 0x03200009 : 0x03200008); // jr $25 321 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 322 writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16); 323 writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0); 324 writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0); 325 } 326 327 template <class ELFT> 328 bool MIPS<ELFT>::needsThunk(RelExpr Expr, RelType Type, const InputFile *File, 329 const SymbolBody &S) const { 330 // Any MIPS PIC code function is invoked with its address in register $t9. 331 // So if we have a branch instruction from non-PIC code to the PIC one 332 // we cannot make the jump directly and need to create a small stubs 333 // to save the target function address. 334 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 335 if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 && 336 Type != R_MICROMIPS_PC26_S1) 337 return false; 338 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 339 if (!F) 340 return false; 341 // If current file has PIC code, LA25 stub is not required. 342 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 343 return false; 344 auto *D = dyn_cast<DefinedRegular>(&S); 345 // LA25 is required if target file has PIC code 346 // or target symbol is a PIC symbol. 347 return D && D->isMipsPIC<ELFT>(); 348 } 349 350 template <class ELFT> 351 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, RelType Type) const { 352 const endianness E = ELFT::TargetEndianness; 353 switch (Type) { 354 case R_MIPS_32: 355 case R_MIPS_GPREL32: 356 case R_MIPS_TLS_DTPREL32: 357 case R_MIPS_TLS_TPREL32: 358 return SignExtend64<32>(read32<E>(Buf)); 359 case R_MIPS_26: 360 // FIXME (simon): If the relocation target symbol is not a PLT entry 361 // we should use another expression for calculation: 362 // ((A << 2) | (P & 0xf0000000)) >> 2 363 return SignExtend64<28>(read32<E>(Buf) << 2); 364 case R_MIPS_GOT16: 365 case R_MIPS_HI16: 366 case R_MIPS_PCHI16: 367 return SignExtend64<16>(read32<E>(Buf)) << 16; 368 case R_MIPS_GPREL16: 369 case R_MIPS_LO16: 370 case R_MIPS_PCLO16: 371 case R_MIPS_TLS_DTPREL_HI16: 372 case R_MIPS_TLS_DTPREL_LO16: 373 case R_MIPS_TLS_TPREL_HI16: 374 case R_MIPS_TLS_TPREL_LO16: 375 return SignExtend64<16>(read32<E>(Buf)); 376 case R_MICROMIPS_GOT16: 377 case R_MICROMIPS_HI16: 378 return SignExtend64<16>(readShuffle<E>(Buf)) << 16; 379 case R_MICROMIPS_GPREL16: 380 case R_MICROMIPS_LO16: 381 case R_MICROMIPS_TLS_DTPREL_HI16: 382 case R_MICROMIPS_TLS_DTPREL_LO16: 383 case R_MICROMIPS_TLS_TPREL_HI16: 384 case R_MICROMIPS_TLS_TPREL_LO16: 385 return SignExtend64<16>(readShuffle<E>(Buf)); 386 case R_MICROMIPS_GPREL7_S2: 387 return SignExtend64<9>(readShuffle<E>(Buf) << 2); 388 case R_MIPS_PC16: 389 return SignExtend64<18>(read32<E>(Buf) << 2); 390 case R_MIPS_PC19_S2: 391 return SignExtend64<21>(read32<E>(Buf) << 2); 392 case R_MIPS_PC21_S2: 393 return SignExtend64<23>(read32<E>(Buf) << 2); 394 case R_MIPS_PC26_S2: 395 return SignExtend64<28>(read32<E>(Buf) << 2); 396 case R_MIPS_PC32: 397 return SignExtend64<32>(read32<E>(Buf)); 398 case R_MICROMIPS_26_S1: 399 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 400 case R_MICROMIPS_PC7_S1: 401 return SignExtend64<8>(read16<E>(Buf) << 1); 402 case R_MICROMIPS_PC10_S1: 403 return SignExtend64<11>(read16<E>(Buf) << 1); 404 case R_MICROMIPS_PC16_S1: 405 return SignExtend64<17>(readShuffle<E>(Buf) << 1); 406 case R_MICROMIPS_PC18_S3: 407 return SignExtend64<21>(readShuffle<E>(Buf) << 3); 408 case R_MICROMIPS_PC19_S2: 409 return SignExtend64<21>(readShuffle<E>(Buf) << 2); 410 case R_MICROMIPS_PC21_S1: 411 return SignExtend64<22>(readShuffle<E>(Buf) << 1); 412 case R_MICROMIPS_PC23_S2: 413 return SignExtend64<25>(readShuffle<E>(Buf) << 2); 414 case R_MICROMIPS_PC26_S1: 415 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 416 default: 417 return 0; 418 } 419 } 420 421 static std::pair<uint32_t, uint64_t> 422 calculateMipsRelChain(uint8_t *Loc, RelType Type, uint64_t Val) { 423 // MIPS N64 ABI packs multiple relocations into the single relocation 424 // record. In general, all up to three relocations can have arbitrary 425 // types. In fact, Clang and GCC uses only a few combinations. For now, 426 // we support two of them. That is allow to pass at least all LLVM 427 // test suite cases. 428 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 429 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 430 // The first relocation is a 'real' relocation which is calculated 431 // using the corresponding symbol's value. The second and the third 432 // relocations used to modify result of the first one: extend it to 433 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 434 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 435 RelType Type2 = (Type >> 8) & 0xff; 436 RelType Type3 = (Type >> 16) & 0xff; 437 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 438 return std::make_pair(Type, Val); 439 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 440 return std::make_pair(Type2, Val); 441 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 442 return std::make_pair(Type3, -Val); 443 if (Type2 == R_MICROMIPS_SUB && 444 (Type3 == R_MICROMIPS_HI16 || Type3 == R_MICROMIPS_LO16)) 445 return std::make_pair(Type3, -Val); 446 error(getErrorLocation(Loc) + "unsupported relocations combination " + 447 Twine(Type)); 448 return std::make_pair(Type & 0xff, Val); 449 } 450 451 template <class ELFT> 452 void MIPS<ELFT>::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const { 453 const endianness E = ELFT::TargetEndianness; 454 455 // Thread pointer and DRP offsets from the start of TLS data area. 456 // https://www.linux-mips.org/wiki/NPTL 457 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 458 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 || 459 Type == R_MICROMIPS_TLS_DTPREL_HI16 || 460 Type == R_MICROMIPS_TLS_DTPREL_LO16) { 461 Val -= 0x8000; 462 } else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 463 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 || 464 Type == R_MICROMIPS_TLS_TPREL_HI16 || 465 Type == R_MICROMIPS_TLS_TPREL_LO16) { 466 Val -= 0x7000; 467 } 468 469 if (ELFT::Is64Bits || Config->MipsN32Abi) 470 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 471 472 switch (Type) { 473 case R_MIPS_32: 474 case R_MIPS_GPREL32: 475 case R_MIPS_TLS_DTPREL32: 476 case R_MIPS_TLS_TPREL32: 477 write32<E>(Loc, Val); 478 break; 479 case R_MIPS_64: 480 case R_MIPS_TLS_DTPREL64: 481 case R_MIPS_TLS_TPREL64: 482 write64<E>(Loc, Val); 483 break; 484 case R_MIPS_26: 485 writeRelocation<E>(Loc, Val, 26, 2); 486 break; 487 case R_MIPS_GOT16: 488 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 489 // is updated addend (not a GOT index). In that case write high 16 bits 490 // to store a correct addend value. 491 if (Config->Relocatable) { 492 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 493 } else { 494 checkInt<16>(Loc, Val, Type); 495 writeRelocation<E>(Loc, Val, 16, 0); 496 } 497 break; 498 case R_MICROMIPS_GOT16: 499 if (Config->Relocatable) { 500 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 501 } else { 502 checkInt<16>(Loc, Val, Type); 503 writeMicroRelocation32<E>(Loc, Val, 16, 0); 504 } 505 break; 506 case R_MIPS_CALL16: 507 case R_MIPS_GOT_DISP: 508 case R_MIPS_GOT_PAGE: 509 case R_MIPS_GPREL16: 510 case R_MIPS_TLS_GD: 511 case R_MIPS_TLS_GOTTPREL: 512 case R_MIPS_TLS_LDM: 513 checkInt<16>(Loc, Val, Type); 514 LLVM_FALLTHROUGH; 515 case R_MIPS_CALL_LO16: 516 case R_MIPS_GOT_LO16: 517 case R_MIPS_GOT_OFST: 518 case R_MIPS_LO16: 519 case R_MIPS_PCLO16: 520 case R_MIPS_TLS_DTPREL_LO16: 521 case R_MIPS_TLS_TPREL_LO16: 522 writeRelocation<E>(Loc, Val, 16, 0); 523 break; 524 case R_MICROMIPS_GOT_DISP: 525 case R_MICROMIPS_GOT_PAGE: 526 case R_MICROMIPS_GPREL16: 527 case R_MICROMIPS_TLS_GD: 528 case R_MICROMIPS_TLS_LDM: 529 checkInt<16>(Loc, Val, Type); 530 writeMicroRelocation32<E>(Loc, Val, 16, 0); 531 break; 532 case R_MICROMIPS_CALL16: 533 case R_MICROMIPS_CALL_LO16: 534 case R_MICROMIPS_GOT_OFST: 535 case R_MICROMIPS_LO16: 536 case R_MICROMIPS_TLS_DTPREL_LO16: 537 case R_MICROMIPS_TLS_GOTTPREL: 538 case R_MICROMIPS_TLS_TPREL_LO16: 539 writeMicroRelocation32<E>(Loc, Val, 16, 0); 540 break; 541 case R_MICROMIPS_GPREL7_S2: 542 checkInt<7>(Loc, Val, Type); 543 writeMicroRelocation32<E>(Loc, Val, 7, 2); 544 break; 545 case R_MIPS_CALL_HI16: 546 case R_MIPS_GOT_HI16: 547 case R_MIPS_HI16: 548 case R_MIPS_PCHI16: 549 case R_MIPS_TLS_DTPREL_HI16: 550 case R_MIPS_TLS_TPREL_HI16: 551 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 552 break; 553 case R_MICROMIPS_CALL_HI16: 554 case R_MICROMIPS_GOT_HI16: 555 case R_MICROMIPS_HI16: 556 case R_MICROMIPS_TLS_DTPREL_HI16: 557 case R_MICROMIPS_TLS_TPREL_HI16: 558 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 559 break; 560 case R_MIPS_HIGHER: 561 writeRelocation<E>(Loc, Val + 0x80008000, 16, 32); 562 break; 563 case R_MIPS_HIGHEST: 564 writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48); 565 break; 566 case R_MICROMIPS_HIGHER: 567 writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32); 568 break; 569 case R_MICROMIPS_HIGHEST: 570 writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48); 571 break; 572 case R_MIPS_JALR: 573 case R_MICROMIPS_JALR: 574 // Ignore this optimization relocation for now 575 break; 576 case R_MIPS_PC16: 577 checkAlignment<4>(Loc, Val, Type); 578 checkInt<18>(Loc, Val, Type); 579 writeRelocation<E>(Loc, Val, 16, 2); 580 break; 581 case R_MIPS_PC19_S2: 582 checkAlignment<4>(Loc, Val, Type); 583 checkInt<21>(Loc, Val, Type); 584 writeRelocation<E>(Loc, Val, 19, 2); 585 break; 586 case R_MIPS_PC21_S2: 587 checkAlignment<4>(Loc, Val, Type); 588 checkInt<23>(Loc, Val, Type); 589 writeRelocation<E>(Loc, Val, 21, 2); 590 break; 591 case R_MIPS_PC26_S2: 592 checkAlignment<4>(Loc, Val, Type); 593 checkInt<28>(Loc, Val, Type); 594 writeRelocation<E>(Loc, Val, 26, 2); 595 break; 596 case R_MIPS_PC32: 597 writeRelocation<E>(Loc, Val, 32, 0); 598 break; 599 case R_MICROMIPS_26_S1: 600 case R_MICROMIPS_PC26_S1: 601 checkInt<27>(Loc, Val, Type); 602 writeMicroRelocation32<E>(Loc, Val, 26, 1); 603 break; 604 case R_MICROMIPS_PC7_S1: 605 checkInt<8>(Loc, Val, Type); 606 writeMicroRelocation16<E>(Loc, Val, 7, 1); 607 break; 608 case R_MICROMIPS_PC10_S1: 609 checkInt<11>(Loc, Val, Type); 610 writeMicroRelocation16<E>(Loc, Val, 10, 1); 611 break; 612 case R_MICROMIPS_PC16_S1: 613 checkInt<17>(Loc, Val, Type); 614 writeMicroRelocation32<E>(Loc, Val, 16, 1); 615 break; 616 case R_MICROMIPS_PC18_S3: 617 checkInt<21>(Loc, Val, Type); 618 writeMicroRelocation32<E>(Loc, Val, 18, 3); 619 break; 620 case R_MICROMIPS_PC19_S2: 621 checkInt<21>(Loc, Val, Type); 622 writeMicroRelocation32<E>(Loc, Val, 19, 2); 623 break; 624 case R_MICROMIPS_PC21_S1: 625 checkInt<22>(Loc, Val, Type); 626 writeMicroRelocation32<E>(Loc, Val, 21, 1); 627 break; 628 case R_MICROMIPS_PC23_S2: 629 checkInt<25>(Loc, Val, Type); 630 writeMicroRelocation32<E>(Loc, Val, 23, 2); 631 break; 632 default: 633 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 634 } 635 } 636 637 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType Type) const { 638 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST || 639 Type == R_MICROMIPS_LO16 || Type == R_MICROMIPS_GOT_OFST; 640 } 641 642 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 643 static MIPS<ELFT> Target; 644 return &Target; 645 } 646 647 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 648 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 649 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 650 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 651