1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // The LLVM Linker 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "Error.h" 11 #include "InputFiles.h" 12 #include "OutputSections.h" 13 #include "Symbols.h" 14 #include "SyntheticSections.h" 15 #include "Target.h" 16 #include "Thunks.h" 17 #include "llvm/Object/ELF.h" 18 #include "llvm/Support/Endian.h" 19 20 using namespace llvm; 21 using namespace llvm::object; 22 using namespace llvm::support::endian; 23 using namespace llvm::ELF; 24 using namespace lld; 25 using namespace lld::elf; 26 27 namespace { 28 template <class ELFT> class MIPS final : public TargetInfo { 29 public: 30 MIPS(); 31 RelExpr getRelExpr(uint32_t Type, const SymbolBody &S, const InputFile &File, 32 const uint8_t *Loc) const override; 33 int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override; 34 bool isPicRel(uint32_t Type) const override; 35 uint32_t getDynRel(uint32_t Type) const override; 36 void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override; 37 void writePltHeader(uint8_t *Buf) const override; 38 void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr, 39 int32_t Index, unsigned RelOff) const override; 40 bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File, 41 const SymbolBody &S) const override; 42 void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override; 43 bool usesOnlyLowPageBits(uint32_t Type) const override; 44 }; 45 } // namespace 46 47 template <class ELFT> MIPS<ELFT>::MIPS() { 48 GotPltHeaderEntriesNum = 2; 49 DefaultMaxPageSize = 65536; 50 GotEntrySize = sizeof(typename ELFT::uint); 51 GotPltEntrySize = sizeof(typename ELFT::uint); 52 PltEntrySize = 16; 53 PltHeaderSize = 32; 54 CopyRel = R_MIPS_COPY; 55 PltRel = R_MIPS_JUMP_SLOT; 56 NeedsThunks = true; 57 TrapInstr = 0xefefefef; 58 59 if (ELFT::Is64Bits) { 60 RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 61 TlsGotRel = R_MIPS_TLS_TPREL64; 62 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 63 TlsOffsetRel = R_MIPS_TLS_DTPREL64; 64 } else { 65 RelativeRel = R_MIPS_REL32; 66 TlsGotRel = R_MIPS_TLS_TPREL32; 67 TlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 68 TlsOffsetRel = R_MIPS_TLS_DTPREL32; 69 } 70 } 71 72 template <class ELFT> 73 RelExpr MIPS<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S, 74 const InputFile &File, 75 const uint8_t *Loc) const { 76 // See comment in the calculateMipsRelChain. 77 if (ELFT::Is64Bits || Config->MipsN32Abi) 78 Type &= 0xff; 79 switch (Type) { 80 case R_MIPS_JALR: 81 case R_MICROMIPS_JALR: 82 return R_HINT; 83 case R_MIPS_GPREL16: 84 case R_MIPS_GPREL32: 85 case R_MICROMIPS_GPREL16: 86 case R_MICROMIPS_GPREL7_S2: 87 return R_MIPS_GOTREL; 88 case R_MIPS_26: 89 case R_MICROMIPS_26_S1: 90 return R_PLT; 91 case R_MICROMIPS_PC26_S1: 92 return R_PLT_PC; 93 case R_MIPS_HI16: 94 case R_MIPS_LO16: 95 case R_MIPS_HIGHER: 96 case R_MIPS_HIGHEST: 97 case R_MICROMIPS_HI16: 98 case R_MICROMIPS_LO16: 99 case R_MICROMIPS_HIGHER: 100 case R_MICROMIPS_HIGHEST: 101 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 102 // offset between start of function and 'gp' value which by default 103 // equal to the start of .got section. In that case we consider these 104 // relocations as relative. 105 if (&S == ElfSym::MipsGpDisp) 106 return R_MIPS_GOT_GP_PC; 107 if (&S == ElfSym::MipsLocalGp) 108 return R_MIPS_GOT_GP; 109 LLVM_FALLTHROUGH; 110 case R_MIPS_32: 111 case R_MIPS_64: 112 case R_MIPS_GOT_OFST: 113 case R_MIPS_SUB: 114 case R_MIPS_TLS_DTPREL_HI16: 115 case R_MIPS_TLS_DTPREL_LO16: 116 case R_MIPS_TLS_DTPREL32: 117 case R_MIPS_TLS_DTPREL64: 118 case R_MIPS_TLS_TPREL_HI16: 119 case R_MIPS_TLS_TPREL_LO16: 120 case R_MIPS_TLS_TPREL32: 121 case R_MIPS_TLS_TPREL64: 122 case R_MICROMIPS_GOT_OFST: 123 case R_MICROMIPS_SUB: 124 case R_MICROMIPS_TLS_DTPREL_HI16: 125 case R_MICROMIPS_TLS_DTPREL_LO16: 126 case R_MICROMIPS_TLS_TPREL_HI16: 127 case R_MICROMIPS_TLS_TPREL_LO16: 128 return R_ABS; 129 case R_MIPS_PC32: 130 case R_MIPS_PC16: 131 case R_MIPS_PC19_S2: 132 case R_MIPS_PC21_S2: 133 case R_MIPS_PC26_S2: 134 case R_MIPS_PCHI16: 135 case R_MIPS_PCLO16: 136 case R_MICROMIPS_PC7_S1: 137 case R_MICROMIPS_PC10_S1: 138 case R_MICROMIPS_PC16_S1: 139 case R_MICROMIPS_PC18_S3: 140 case R_MICROMIPS_PC19_S2: 141 case R_MICROMIPS_PC23_S2: 142 case R_MICROMIPS_PC21_S1: 143 return R_PC; 144 case R_MIPS_GOT16: 145 case R_MICROMIPS_GOT16: 146 if (S.isLocal()) 147 return R_MIPS_GOT_LOCAL_PAGE; 148 LLVM_FALLTHROUGH; 149 case R_MIPS_CALL16: 150 case R_MIPS_GOT_DISP: 151 case R_MIPS_TLS_GOTTPREL: 152 case R_MICROMIPS_CALL16: 153 case R_MICROMIPS_GOT_DISP: 154 case R_MICROMIPS_TLS_GOTTPREL: 155 return R_MIPS_GOT_OFF; 156 case R_MIPS_CALL_HI16: 157 case R_MIPS_CALL_LO16: 158 case R_MIPS_GOT_HI16: 159 case R_MIPS_GOT_LO16: 160 case R_MICROMIPS_CALL_HI16: 161 case R_MICROMIPS_CALL_LO16: 162 case R_MICROMIPS_GOT_HI16: 163 case R_MICROMIPS_GOT_LO16: 164 return R_MIPS_GOT_OFF32; 165 case R_MIPS_GOT_PAGE: 166 case R_MICROMIPS_GOT_PAGE: 167 return R_MIPS_GOT_LOCAL_PAGE; 168 case R_MIPS_TLS_GD: 169 case R_MICROMIPS_TLS_GD: 170 return R_MIPS_TLSGD; 171 case R_MIPS_TLS_LDM: 172 case R_MICROMIPS_TLS_LDM: 173 return R_MIPS_TLSLD; 174 case R_MIPS_NONE: 175 return R_NONE; 176 default: 177 error("do not know how to handle relocation '" + toString(Type) + "' (" + 178 Twine(Type) + ")"); 179 return R_HINT; 180 } 181 } 182 183 template <class ELFT> bool MIPS<ELFT>::isPicRel(uint32_t Type) const { 184 return Type == R_MIPS_32 || Type == R_MIPS_64; 185 } 186 187 template <class ELFT> uint32_t MIPS<ELFT>::getDynRel(uint32_t Type) const { 188 return RelativeRel; 189 } 190 191 template <class ELFT> 192 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const SymbolBody &) const { 193 write32<ELFT::TargetEndianness>(Buf, InX::Plt->getVA()); 194 } 195 196 template <endianness E> static uint32_t readShuffle(const uint8_t *Loc) { 197 // The major opcode of a microMIPS instruction needs to appear 198 // in the first 16-bit word (lowest address) for efficient hardware 199 // decode so that it knows if the instruction is 16-bit or 32-bit 200 // as early as possible. To do so, little-endian binaries keep 16-bit 201 // words in a big-endian order. That is why we have to swap these 202 // words to get a correct value. 203 uint32_t V = read32<E>(Loc); 204 if (E == support::little) 205 return (V << 16) | (V >> 16); 206 return V; 207 } 208 209 template <endianness E> 210 static void writeRelocation(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 211 uint8_t Shift) { 212 uint32_t Instr = read32<E>(Loc); 213 uint32_t Mask = 0xffffffff >> (32 - BitsSize); 214 uint32_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 215 write32<E>(Loc, Data); 216 } 217 218 template <endianness E> 219 static void writeMicroRelocation32(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 220 uint8_t Shift) { 221 // See comments in readShuffle for purpose of this code. 222 uint16_t *Words = (uint16_t *)Loc; 223 if (E == support::little) 224 std::swap(Words[0], Words[1]); 225 226 writeRelocation<E>(Loc, V, BitsSize, Shift); 227 228 if (E == support::little) 229 std::swap(Words[0], Words[1]); 230 } 231 232 template <endianness E> 233 static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize, 234 uint8_t Shift) { 235 uint16_t Instr = read16<E>(Loc); 236 uint16_t Mask = 0xffff >> (16 - BitsSize); 237 uint16_t Data = (Instr & ~Mask) | ((V >> Shift) & Mask); 238 write16<E>(Loc, Data); 239 } 240 241 template <class ELFT> static bool isMicroMips() { 242 // FIXME (simon): This code does not support the case when both 243 // microMIPS and MIPS object files are linked together. 244 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf); 245 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH_ASE; 246 return Arch == EF_MIPS_MICROMIPS; 247 } 248 249 template <class ELFT> static bool isMipsR6() { 250 const auto &FirstObj = cast<ELFFileBase<ELFT>>(*Config->FirstElf); 251 uint32_t Arch = FirstObj.getObj().getHeader()->e_flags & EF_MIPS_ARCH; 252 return Arch == EF_MIPS_ARCH_32R6 || Arch == EF_MIPS_ARCH_64R6; 253 } 254 255 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const { 256 const endianness E = ELFT::TargetEndianness; 257 if (isMicroMips<ELFT>()) { 258 uint64_t GotPlt = In<ELFT>::GotPlt->getVA(); 259 uint64_t Plt = In<ELFT>::Plt->getVA(); 260 // Overwrite trap instructions written by Writer::writeTrapInstr. 261 memset(Buf, 0, PltHeaderSize); 262 263 write16<E>(Buf, isMipsR6<ELFT>() ? 0x7860 : 0x7980); 264 // addiupc v1, (GOTPLT) - . 265 write16<E>(Buf + 4, 0xff23); // lw $25, 0($3) 266 write16<E>(Buf + 8, 0x0535); // subu16 $2, $2, $3 267 write16<E>(Buf + 10, 0x2525); // srl16 $2, $2, 2 268 write16<E>(Buf + 12, 0x3302); // addiu $24, $2, -2 269 write16<E>(Buf + 14, 0xfffe); 270 write16<E>(Buf + 16, 0x0dff); // move $15, $31 271 if (isMipsR6<ELFT>()) { 272 write16<E>(Buf + 18, 0x0f83); // move $28, $3 273 write16<E>(Buf + 20, 0x472b); // jalrc $25 274 write16<E>(Buf + 22, 0x0c00); // nop 275 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPlt - Plt); 276 } else { 277 write16<E>(Buf + 18, 0x45f9); // jalrc $25 278 write16<E>(Buf + 20, 0x0f83); // move $28, $3 279 write16<E>(Buf + 22, 0x0c00); // nop 280 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPlt - Plt); 281 } 282 return; 283 } 284 285 if (Config->MipsN32Abi) { 286 write32<E>(Buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 287 write32<E>(Buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 288 write32<E>(Buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 289 write32<E>(Buf + 12, 0x030ec023); // subu $24, $24, $14 290 } else { 291 write32<E>(Buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 292 write32<E>(Buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 293 write32<E>(Buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 294 write32<E>(Buf + 12, 0x031cc023); // subu $24, $24, $28 295 } 296 297 write32<E>(Buf + 16, 0x03e07825); // move $15, $31 298 write32<E>(Buf + 20, 0x0018c082); // srl $24, $24, 2 299 write32<E>(Buf + 24, 0x0320f809); // jalr $25 300 write32<E>(Buf + 28, 0x2718fffe); // subu $24, $24, 2 301 302 uint64_t GotPlt = InX::GotPlt->getVA(); 303 writeRelocation<E>(Buf, GotPlt + 0x8000, 16, 16); 304 writeRelocation<E>(Buf + 4, GotPlt, 16, 0); 305 writeRelocation<E>(Buf + 8, GotPlt, 16, 0); 306 } 307 308 template <class ELFT> 309 void MIPS<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, 310 uint64_t PltEntryAddr, int32_t Index, 311 unsigned RelOff) const { 312 const endianness E = ELFT::TargetEndianness; 313 if (isMicroMips<ELFT>()) { 314 // Overwrite trap instructions written by Writer::writeTrapInstr. 315 memset(Buf, 0, PltEntrySize); 316 317 if (isMipsR6<ELFT>()) { 318 write16<E>(Buf, 0x7840); // addiupc $2, (GOTPLT) - . 319 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 320 write16<E>(Buf + 8, 0x0f02); // move $24, $2 321 write16<E>(Buf + 10, 0x4723); // jrc $25 / jr16 $25 322 relocateOne(Buf, R_MICROMIPS_PC19_S2, GotPltEntryAddr - PltEntryAddr); 323 } else { 324 write16<E>(Buf, 0x7900); // addiupc $2, (GOTPLT) - . 325 write16<E>(Buf + 4, 0xff22); // lw $25, 0($2) 326 write16<E>(Buf + 8, 0x4599); // jrc $25 / jr16 $25 327 write16<E>(Buf + 10, 0x0f02); // move $24, $2 328 relocateOne(Buf, R_MICROMIPS_PC23_S2, GotPltEntryAddr - PltEntryAddr); 329 } 330 return; 331 } 332 333 write32<E>(Buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 334 write32<E>(Buf + 4, 0x8df90000); // l[wd] $25, %lo(.got.plt entry)($15) 335 // jr $25 336 write32<E>(Buf + 8, isMipsR6<ELFT>() ? 0x03200009 : 0x03200008); 337 write32<E>(Buf + 12, 0x25f80000); // addiu $24, $15, %lo(.got.plt entry) 338 writeRelocation<E>(Buf, GotPltEntryAddr + 0x8000, 16, 16); 339 writeRelocation<E>(Buf + 4, GotPltEntryAddr, 16, 0); 340 writeRelocation<E>(Buf + 12, GotPltEntryAddr, 16, 0); 341 } 342 343 template <class ELFT> 344 bool MIPS<ELFT>::needsThunk(RelExpr Expr, uint32_t Type, const InputFile *File, 345 const SymbolBody &S) const { 346 // Any MIPS PIC code function is invoked with its address in register $t9. 347 // So if we have a branch instruction from non-PIC code to the PIC one 348 // we cannot make the jump directly and need to create a small stubs 349 // to save the target function address. 350 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 351 if (Type != R_MIPS_26 && Type != R_MICROMIPS_26_S1 && 352 Type != R_MICROMIPS_PC26_S1) 353 return false; 354 auto *F = dyn_cast_or_null<ELFFileBase<ELFT>>(File); 355 if (!F) 356 return false; 357 // If current file has PIC code, LA25 stub is not required. 358 if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC) 359 return false; 360 auto *D = dyn_cast<DefinedRegular>(&S); 361 // LA25 is required if target file has PIC code 362 // or target symbol is a PIC symbol. 363 return D && D->isMipsPIC<ELFT>(); 364 } 365 366 template <class ELFT> 367 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const { 368 const endianness E = ELFT::TargetEndianness; 369 switch (Type) { 370 default: 371 return 0; 372 case R_MIPS_32: 373 case R_MIPS_GPREL32: 374 case R_MIPS_TLS_DTPREL32: 375 case R_MIPS_TLS_TPREL32: 376 return SignExtend64<32>(read32<E>(Buf)); 377 case R_MIPS_26: 378 // FIXME (simon): If the relocation target symbol is not a PLT entry 379 // we should use another expression for calculation: 380 // ((A << 2) | (P & 0xf0000000)) >> 2 381 return SignExtend64<28>(read32<E>(Buf) << 2); 382 case R_MIPS_GOT16: 383 case R_MIPS_HI16: 384 case R_MIPS_PCHI16: 385 return SignExtend64<16>(read32<E>(Buf)) << 16; 386 case R_MIPS_GPREL16: 387 case R_MIPS_LO16: 388 case R_MIPS_PCLO16: 389 case R_MIPS_TLS_DTPREL_HI16: 390 case R_MIPS_TLS_DTPREL_LO16: 391 case R_MIPS_TLS_TPREL_HI16: 392 case R_MIPS_TLS_TPREL_LO16: 393 return SignExtend64<16>(read32<E>(Buf)); 394 case R_MICROMIPS_GOT16: 395 case R_MICROMIPS_HI16: 396 return SignExtend64<16>(readShuffle<E>(Buf)) << 16; 397 case R_MICROMIPS_GPREL16: 398 case R_MICROMIPS_LO16: 399 case R_MICROMIPS_TLS_DTPREL_HI16: 400 case R_MICROMIPS_TLS_DTPREL_LO16: 401 case R_MICROMIPS_TLS_TPREL_HI16: 402 case R_MICROMIPS_TLS_TPREL_LO16: 403 return SignExtend64<16>(readShuffle<E>(Buf)); 404 case R_MICROMIPS_GPREL7_S2: 405 return SignExtend64<9>(readShuffle<E>(Buf) << 2); 406 case R_MIPS_PC16: 407 return SignExtend64<18>(read32<E>(Buf) << 2); 408 case R_MIPS_PC19_S2: 409 return SignExtend64<21>(read32<E>(Buf) << 2); 410 case R_MIPS_PC21_S2: 411 return SignExtend64<23>(read32<E>(Buf) << 2); 412 case R_MIPS_PC26_S2: 413 return SignExtend64<28>(read32<E>(Buf) << 2); 414 case R_MIPS_PC32: 415 return SignExtend64<32>(read32<E>(Buf)); 416 case R_MICROMIPS_26_S1: 417 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 418 case R_MICROMIPS_PC7_S1: 419 return SignExtend64<8>(read16<E>(Buf) << 1); 420 case R_MICROMIPS_PC10_S1: 421 return SignExtend64<11>(read16<E>(Buf) << 1); 422 case R_MICROMIPS_PC16_S1: 423 return SignExtend64<17>(readShuffle<E>(Buf) << 1); 424 case R_MICROMIPS_PC18_S3: 425 return SignExtend64<21>(readShuffle<E>(Buf) << 3); 426 case R_MICROMIPS_PC19_S2: 427 return SignExtend64<21>(readShuffle<E>(Buf) << 2); 428 case R_MICROMIPS_PC21_S1: 429 return SignExtend64<22>(readShuffle<E>(Buf) << 1); 430 case R_MICROMIPS_PC23_S2: 431 return SignExtend64<25>(readShuffle<E>(Buf) << 2); 432 case R_MICROMIPS_PC26_S1: 433 return SignExtend64<27>(readShuffle<E>(Buf) << 1); 434 } 435 } 436 437 static std::pair<uint32_t, uint64_t> 438 calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) { 439 // MIPS N64 ABI packs multiple relocations into the single relocation 440 // record. In general, all up to three relocations can have arbitrary 441 // types. In fact, Clang and GCC uses only a few combinations. For now, 442 // we support two of them. That is allow to pass at least all LLVM 443 // test suite cases. 444 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 445 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 446 // The first relocation is a 'real' relocation which is calculated 447 // using the corresponding symbol's value. The second and the third 448 // relocations used to modify result of the first one: extend it to 449 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 450 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 451 uint32_t Type2 = (Type >> 8) & 0xff; 452 uint32_t Type3 = (Type >> 16) & 0xff; 453 if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE) 454 return std::make_pair(Type, Val); 455 if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE) 456 return std::make_pair(Type2, Val); 457 if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16)) 458 return std::make_pair(Type3, -Val); 459 if (Type2 == R_MICROMIPS_SUB && 460 (Type3 == R_MICROMIPS_HI16 || Type3 == R_MICROMIPS_LO16)) 461 return std::make_pair(Type3, -Val); 462 error(getErrorLocation(Loc) + "unsupported relocations combination " + 463 Twine(Type)); 464 return std::make_pair(Type & 0xff, Val); 465 } 466 467 template <class ELFT> 468 void MIPS<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const { 469 const endianness E = ELFT::TargetEndianness; 470 // Thread pointer and DRP offsets from the start of TLS data area. 471 // https://www.linux-mips.org/wiki/NPTL 472 if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 || 473 Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64 || 474 Type == R_MICROMIPS_TLS_DTPREL_HI16 || 475 Type == R_MICROMIPS_TLS_DTPREL_LO16) 476 Val -= 0x8000; 477 else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 || 478 Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64 || 479 Type == R_MICROMIPS_TLS_TPREL_HI16 || 480 Type == R_MICROMIPS_TLS_TPREL_LO16) 481 Val -= 0x7000; 482 if (ELFT::Is64Bits || Config->MipsN32Abi) 483 std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val); 484 switch (Type) { 485 case R_MIPS_32: 486 case R_MIPS_GPREL32: 487 case R_MIPS_TLS_DTPREL32: 488 case R_MIPS_TLS_TPREL32: 489 write32<E>(Loc, Val); 490 break; 491 case R_MIPS_64: 492 case R_MIPS_TLS_DTPREL64: 493 case R_MIPS_TLS_TPREL64: 494 write64<E>(Loc, Val); 495 break; 496 case R_MIPS_26: 497 writeRelocation<E>(Loc, Val, 26, 2); 498 break; 499 case R_MIPS_GOT16: 500 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 501 // is updated addend (not a GOT index). In that case write high 16 bits 502 // to store a correct addend value. 503 if (Config->Relocatable) { 504 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 505 } else { 506 checkInt<16>(Loc, Val, Type); 507 writeRelocation<E>(Loc, Val, 16, 0); 508 } 509 break; 510 case R_MICROMIPS_GOT16: 511 if (Config->Relocatable) { 512 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 513 } else { 514 checkInt<16>(Loc, Val, Type); 515 writeMicroRelocation32<E>(Loc, Val, 16, 0); 516 } 517 break; 518 case R_MIPS_GOT_DISP: 519 case R_MIPS_GOT_PAGE: 520 case R_MIPS_GPREL16: 521 case R_MIPS_TLS_GD: 522 case R_MIPS_TLS_LDM: 523 checkInt<16>(Loc, Val, Type); 524 LLVM_FALLTHROUGH; 525 case R_MIPS_CALL16: 526 case R_MIPS_CALL_LO16: 527 case R_MIPS_GOT_LO16: 528 case R_MIPS_GOT_OFST: 529 case R_MIPS_LO16: 530 case R_MIPS_PCLO16: 531 case R_MIPS_TLS_DTPREL_LO16: 532 case R_MIPS_TLS_GOTTPREL: 533 case R_MIPS_TLS_TPREL_LO16: 534 writeRelocation<E>(Loc, Val, 16, 0); 535 break; 536 case R_MICROMIPS_GOT_DISP: 537 case R_MICROMIPS_GOT_PAGE: 538 case R_MICROMIPS_GPREL16: 539 case R_MICROMIPS_TLS_GD: 540 case R_MICROMIPS_TLS_LDM: 541 checkInt<16>(Loc, Val, Type); 542 writeMicroRelocation32<E>(Loc, Val, 16, 0); 543 break; 544 case R_MICROMIPS_CALL16: 545 case R_MICROMIPS_CALL_LO16: 546 case R_MICROMIPS_GOT_OFST: 547 case R_MICROMIPS_LO16: 548 case R_MICROMIPS_TLS_DTPREL_LO16: 549 case R_MICROMIPS_TLS_GOTTPREL: 550 case R_MICROMIPS_TLS_TPREL_LO16: 551 writeMicroRelocation32<E>(Loc, Val, 16, 0); 552 break; 553 case R_MICROMIPS_GPREL7_S2: 554 checkInt<7>(Loc, Val, Type); 555 writeMicroRelocation32<E>(Loc, Val, 7, 2); 556 break; 557 case R_MIPS_CALL_HI16: 558 case R_MIPS_GOT_HI16: 559 case R_MIPS_HI16: 560 case R_MIPS_PCHI16: 561 case R_MIPS_TLS_DTPREL_HI16: 562 case R_MIPS_TLS_TPREL_HI16: 563 writeRelocation<E>(Loc, Val + 0x8000, 16, 16); 564 break; 565 case R_MICROMIPS_CALL_HI16: 566 case R_MICROMIPS_GOT_HI16: 567 case R_MICROMIPS_HI16: 568 case R_MICROMIPS_TLS_DTPREL_HI16: 569 case R_MICROMIPS_TLS_TPREL_HI16: 570 writeMicroRelocation32<E>(Loc, Val + 0x8000, 16, 16); 571 break; 572 case R_MIPS_HIGHER: 573 writeRelocation<E>(Loc, Val + 0x80008000, 16, 32); 574 break; 575 case R_MIPS_HIGHEST: 576 writeRelocation<E>(Loc, Val + 0x800080008000, 16, 48); 577 break; 578 case R_MICROMIPS_HIGHER: 579 writeMicroRelocation32<E>(Loc, Val + 0x80008000, 16, 32); 580 break; 581 case R_MICROMIPS_HIGHEST: 582 writeMicroRelocation32<E>(Loc, Val + 0x800080008000, 16, 48); 583 break; 584 case R_MIPS_JALR: 585 case R_MICROMIPS_JALR: 586 // Ignore this optimization relocation for now 587 break; 588 case R_MIPS_PC16: 589 checkAlignment<4>(Loc, Val, Type); 590 checkInt<18>(Loc, Val, Type); 591 writeRelocation<E>(Loc, Val, 16, 2); 592 break; 593 case R_MIPS_PC19_S2: 594 checkAlignment<4>(Loc, Val, Type); 595 checkInt<21>(Loc, Val, Type); 596 writeRelocation<E>(Loc, Val, 19, 2); 597 break; 598 case R_MIPS_PC21_S2: 599 checkAlignment<4>(Loc, Val, Type); 600 checkInt<23>(Loc, Val, Type); 601 writeRelocation<E>(Loc, Val, 21, 2); 602 break; 603 case R_MIPS_PC26_S2: 604 checkAlignment<4>(Loc, Val, Type); 605 checkInt<28>(Loc, Val, Type); 606 writeRelocation<E>(Loc, Val, 26, 2); 607 break; 608 case R_MIPS_PC32: 609 writeRelocation<E>(Loc, Val, 32, 0); 610 break; 611 case R_MICROMIPS_26_S1: 612 case R_MICROMIPS_PC26_S1: 613 checkInt<27>(Loc, Val, Type); 614 writeMicroRelocation32<E>(Loc, Val, 26, 1); 615 break; 616 case R_MICROMIPS_PC7_S1: 617 checkInt<8>(Loc, Val, Type); 618 writeMicroRelocation16<E>(Loc, Val, 7, 1); 619 break; 620 case R_MICROMIPS_PC10_S1: 621 checkInt<11>(Loc, Val, Type); 622 writeMicroRelocation16<E>(Loc, Val, 10, 1); 623 break; 624 case R_MICROMIPS_PC16_S1: 625 checkInt<17>(Loc, Val, Type); 626 writeMicroRelocation32<E>(Loc, Val, 16, 1); 627 break; 628 case R_MICROMIPS_PC18_S3: 629 checkInt<21>(Loc, Val, Type); 630 writeMicroRelocation32<E>(Loc, Val, 18, 3); 631 break; 632 case R_MICROMIPS_PC19_S2: 633 checkInt<21>(Loc, Val, Type); 634 writeMicroRelocation32<E>(Loc, Val, 19, 2); 635 break; 636 case R_MICROMIPS_PC21_S1: 637 checkInt<22>(Loc, Val, Type); 638 writeMicroRelocation32<E>(Loc, Val, 21, 1); 639 break; 640 case R_MICROMIPS_PC23_S2: 641 checkInt<25>(Loc, Val, Type); 642 writeMicroRelocation32<E>(Loc, Val, 23, 2); 643 break; 644 default: 645 error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type)); 646 } 647 } 648 649 template <class ELFT> 650 bool MIPS<ELFT>::usesOnlyLowPageBits(uint32_t Type) const { 651 return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST || 652 Type == R_MICROMIPS_LO16 || Type == R_MICROMIPS_GOT_OFST; 653 } 654 655 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 656 static MIPS<ELFT> Target; 657 return &Target; 658 } 659 660 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 661 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 662 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 663 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 664