1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "OutputSections.h" 11 #include "Symbols.h" 12 #include "SyntheticSections.h" 13 #include "Target.h" 14 #include "Thunks.h" 15 #include "lld/Common/ErrorHandler.h" 16 #include "llvm/Object/ELF.h" 17 #include "llvm/Support/Endian.h" 18 19 using namespace llvm; 20 using namespace llvm::object; 21 using namespace llvm::support::endian; 22 using namespace llvm::ELF; 23 using namespace lld; 24 using namespace lld::elf; 25 26 namespace { 27 template <class ELFT> class MIPS final : public TargetInfo { 28 public: 29 MIPS(); 30 uint32_t calcEFlags() const override; 31 RelExpr getRelExpr(RelType type, const Symbol &s, 32 const uint8_t *loc) const override; 33 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; 34 RelType getDynRel(RelType type) const override; 35 void writeGotPlt(uint8_t *buf, const Symbol &s) const override; 36 void writePltHeader(uint8_t *buf) const override; 37 void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr, 38 int32_t index, unsigned relOff) const override; 39 bool needsThunk(RelExpr expr, RelType type, const InputFile *file, 40 uint64_t branchAddr, const Symbol &s) const override; 41 void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override; 42 bool usesOnlyLowPageBits(RelType type) const override; 43 }; 44 } // namespace 45 46 template <class ELFT> MIPS<ELFT>::MIPS() { 47 gotPltHeaderEntriesNum = 2; 48 defaultMaxPageSize = 65536; 49 gotBaseSymInGotPlt = false; 50 pltEntrySize = 16; 51 pltHeaderSize = 32; 52 copyRel = R_MIPS_COPY; 53 noneRel = R_MIPS_NONE; 54 pltRel = R_MIPS_JUMP_SLOT; 55 needsThunks = true; 56 57 // Set `sigrie 1` as a trap instruction. 58 write32(trapInstr.data(), 0x04170001); 59 60 if (ELFT::Is64Bits) { 61 relativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 62 symbolicRel = R_MIPS_64; 63 tlsGotRel = R_MIPS_TLS_TPREL64; 64 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 65 tlsOffsetRel = R_MIPS_TLS_DTPREL64; 66 } else { 67 relativeRel = R_MIPS_REL32; 68 symbolicRel = R_MIPS_32; 69 tlsGotRel = R_MIPS_TLS_TPREL32; 70 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 71 tlsOffsetRel = R_MIPS_TLS_DTPREL32; 72 } 73 } 74 75 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 76 return calcMipsEFlags<ELFT>(); 77 } 78 79 template <class ELFT> 80 RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s, 81 const uint8_t *loc) const { 82 // See comment in the calculateMipsRelChain. 83 if (ELFT::Is64Bits || config->mipsN32Abi) 84 type &= 0xff; 85 86 switch (type) { 87 case R_MIPS_JALR: 88 // If the target symbol is not preemptible and is not microMIPS, 89 // it might be possible to replace jalr/jr instruction by bal/b. 90 // It depends on the target symbol's offset. 91 if (!s.isPreemptible && !(s.getVA() & 0x1)) 92 return R_PC; 93 return R_NONE; 94 case R_MICROMIPS_JALR: 95 return R_NONE; 96 case R_MIPS_GPREL16: 97 case R_MIPS_GPREL32: 98 case R_MICROMIPS_GPREL16: 99 case R_MICROMIPS_GPREL7_S2: 100 return R_MIPS_GOTREL; 101 case R_MIPS_26: 102 case R_MICROMIPS_26_S1: 103 return R_PLT; 104 case R_MICROMIPS_PC26_S1: 105 return R_PLT_PC; 106 case R_MIPS_HI16: 107 case R_MIPS_LO16: 108 case R_MIPS_HIGHER: 109 case R_MIPS_HIGHEST: 110 case R_MICROMIPS_HI16: 111 case R_MICROMIPS_LO16: 112 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 113 // offset between start of function and 'gp' value which by default 114 // equal to the start of .got section. In that case we consider these 115 // relocations as relative. 116 if (&s == ElfSym::mipsGpDisp) 117 return R_MIPS_GOT_GP_PC; 118 if (&s == ElfSym::mipsLocalGp) 119 return R_MIPS_GOT_GP; 120 LLVM_FALLTHROUGH; 121 case R_MIPS_32: 122 case R_MIPS_64: 123 case R_MIPS_GOT_OFST: 124 case R_MIPS_SUB: 125 case R_MIPS_TLS_DTPREL_HI16: 126 case R_MIPS_TLS_DTPREL_LO16: 127 case R_MIPS_TLS_DTPREL32: 128 case R_MIPS_TLS_DTPREL64: 129 case R_MICROMIPS_TLS_DTPREL_HI16: 130 case R_MICROMIPS_TLS_DTPREL_LO16: 131 return R_ABS; 132 case R_MIPS_TLS_TPREL_HI16: 133 case R_MIPS_TLS_TPREL_LO16: 134 case R_MIPS_TLS_TPREL32: 135 case R_MIPS_TLS_TPREL64: 136 case R_MICROMIPS_TLS_TPREL_HI16: 137 case R_MICROMIPS_TLS_TPREL_LO16: 138 return R_TLS; 139 case R_MIPS_PC32: 140 case R_MIPS_PC16: 141 case R_MIPS_PC19_S2: 142 case R_MIPS_PC21_S2: 143 case R_MIPS_PC26_S2: 144 case R_MIPS_PCHI16: 145 case R_MIPS_PCLO16: 146 case R_MICROMIPS_PC7_S1: 147 case R_MICROMIPS_PC10_S1: 148 case R_MICROMIPS_PC16_S1: 149 case R_MICROMIPS_PC18_S3: 150 case R_MICROMIPS_PC19_S2: 151 case R_MICROMIPS_PC23_S2: 152 case R_MICROMIPS_PC21_S1: 153 return R_PC; 154 case R_MIPS_GOT16: 155 case R_MICROMIPS_GOT16: 156 if (s.isLocal()) 157 return R_MIPS_GOT_LOCAL_PAGE; 158 LLVM_FALLTHROUGH; 159 case R_MIPS_CALL16: 160 case R_MIPS_GOT_DISP: 161 case R_MIPS_TLS_GOTTPREL: 162 case R_MICROMIPS_CALL16: 163 case R_MICROMIPS_TLS_GOTTPREL: 164 return R_MIPS_GOT_OFF; 165 case R_MIPS_CALL_HI16: 166 case R_MIPS_CALL_LO16: 167 case R_MIPS_GOT_HI16: 168 case R_MIPS_GOT_LO16: 169 case R_MICROMIPS_CALL_HI16: 170 case R_MICROMIPS_CALL_LO16: 171 case R_MICROMIPS_GOT_HI16: 172 case R_MICROMIPS_GOT_LO16: 173 return R_MIPS_GOT_OFF32; 174 case R_MIPS_GOT_PAGE: 175 return R_MIPS_GOT_LOCAL_PAGE; 176 case R_MIPS_TLS_GD: 177 case R_MICROMIPS_TLS_GD: 178 return R_MIPS_TLSGD; 179 case R_MIPS_TLS_LDM: 180 case R_MICROMIPS_TLS_LDM: 181 return R_MIPS_TLSLD; 182 case R_MIPS_NONE: 183 return R_NONE; 184 default: 185 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 186 ") against symbol " + toString(s)); 187 return R_NONE; 188 } 189 } 190 191 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType type) const { 192 if (type == symbolicRel) 193 return type; 194 return R_MIPS_NONE; 195 } 196 197 template <class ELFT> 198 void MIPS<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const { 199 uint64_t va = in.plt->getVA(); 200 if (isMicroMips()) 201 va |= 1; 202 write32<ELFT::TargetEndianness>(buf, va); 203 } 204 205 template <endianness E> static uint32_t readShuffle(const uint8_t *loc) { 206 // The major opcode of a microMIPS instruction needs to appear 207 // in the first 16-bit word (lowest address) for efficient hardware 208 // decode so that it knows if the instruction is 16-bit or 32-bit 209 // as early as possible. To do so, little-endian binaries keep 16-bit 210 // words in a big-endian order. That is why we have to swap these 211 // words to get a correct value. 212 uint32_t v = read32<E>(loc); 213 if (E == support::little) 214 return (v << 16) | (v >> 16); 215 return v; 216 } 217 218 template <endianness E> 219 static void writeValue(uint8_t *loc, uint64_t v, uint8_t bitsSize, 220 uint8_t shift) { 221 uint32_t instr = read32<E>(loc); 222 uint32_t mask = 0xffffffff >> (32 - bitsSize); 223 uint32_t data = (instr & ~mask) | ((v >> shift) & mask); 224 write32<E>(loc, data); 225 } 226 227 template <endianness E> 228 static void writeShuffleValue(uint8_t *loc, uint64_t v, uint8_t bitsSize, 229 uint8_t shift) { 230 // See comments in readShuffle for purpose of this code. 231 uint16_t *words = (uint16_t *)loc; 232 if (E == support::little) 233 std::swap(words[0], words[1]); 234 235 writeValue<E>(loc, v, bitsSize, shift); 236 237 if (E == support::little) 238 std::swap(words[0], words[1]); 239 } 240 241 template <endianness E> 242 static void writeMicroRelocation16(uint8_t *loc, uint64_t v, uint8_t bitsSize, 243 uint8_t shift) { 244 uint16_t instr = read16<E>(loc); 245 uint16_t mask = 0xffff >> (16 - bitsSize); 246 uint16_t data = (instr & ~mask) | ((v >> shift) & mask); 247 write16<E>(loc, data); 248 } 249 250 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const { 251 const endianness e = ELFT::TargetEndianness; 252 if (isMicroMips()) { 253 uint64_t gotPlt = in.gotPlt->getVA(); 254 uint64_t plt = in.plt->getVA(); 255 // Overwrite trap instructions written by Writer::writeTrapInstr. 256 memset(buf, 0, pltHeaderSize); 257 258 write16<e>(buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 259 write16<e>(buf + 4, 0xff23); // lw $25, 0($3) 260 write16<e>(buf + 8, 0x0535); // subu16 $2, $2, $3 261 write16<e>(buf + 10, 0x2525); // srl16 $2, $2, 2 262 write16<e>(buf + 12, 0x3302); // addiu $24, $2, -2 263 write16<e>(buf + 14, 0xfffe); 264 write16<e>(buf + 16, 0x0dff); // move $15, $31 265 if (isMipsR6()) { 266 write16<e>(buf + 18, 0x0f83); // move $28, $3 267 write16<e>(buf + 20, 0x472b); // jalrc $25 268 write16<e>(buf + 22, 0x0c00); // nop 269 relocateOne(buf, R_MICROMIPS_PC19_S2, gotPlt - plt); 270 } else { 271 write16<e>(buf + 18, 0x45f9); // jalrc $25 272 write16<e>(buf + 20, 0x0f83); // move $28, $3 273 write16<e>(buf + 22, 0x0c00); // nop 274 relocateOne(buf, R_MICROMIPS_PC23_S2, gotPlt - plt); 275 } 276 return; 277 } 278 279 if (config->mipsN32Abi) { 280 write32<e>(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 281 write32<e>(buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 282 write32<e>(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 283 write32<e>(buf + 12, 0x030ec023); // subu $24, $24, $14 284 write32<e>(buf + 16, 0x03e07825); // move $15, $31 285 write32<e>(buf + 20, 0x0018c082); // srl $24, $24, 2 286 } else if (ELFT::Is64Bits) { 287 write32<e>(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 288 write32<e>(buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14) 289 write32<e>(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 290 write32<e>(buf + 12, 0x030ec023); // subu $24, $24, $14 291 write32<e>(buf + 16, 0x03e07825); // move $15, $31 292 write32<e>(buf + 20, 0x0018c0c2); // srl $24, $24, 3 293 } else { 294 write32<e>(buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 295 write32<e>(buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 296 write32<e>(buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 297 write32<e>(buf + 12, 0x031cc023); // subu $24, $24, $28 298 write32<e>(buf + 16, 0x03e07825); // move $15, $31 299 write32<e>(buf + 20, 0x0018c082); // srl $24, $24, 2 300 } 301 302 uint32_t jalrInst = config->zHazardplt ? 0x0320fc09 : 0x0320f809; 303 write32<e>(buf + 24, jalrInst); // jalr.hb $25 or jalr $25 304 write32<e>(buf + 28, 0x2718fffe); // subu $24, $24, 2 305 306 uint64_t gotPlt = in.gotPlt->getVA(); 307 writeValue<e>(buf, gotPlt + 0x8000, 16, 16); 308 writeValue<e>(buf + 4, gotPlt, 16, 0); 309 writeValue<e>(buf + 8, gotPlt, 16, 0); 310 } 311 312 template <class ELFT> 313 void MIPS<ELFT>::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, 314 uint64_t pltEntryAddr, int32_t index, 315 unsigned relOff) const { 316 const endianness e = ELFT::TargetEndianness; 317 if (isMicroMips()) { 318 // Overwrite trap instructions written by Writer::writeTrapInstr. 319 memset(buf, 0, pltEntrySize); 320 321 if (isMipsR6()) { 322 write16<e>(buf, 0x7840); // addiupc $2, (GOTPLT) - . 323 write16<e>(buf + 4, 0xff22); // lw $25, 0($2) 324 write16<e>(buf + 8, 0x0f02); // move $24, $2 325 write16<e>(buf + 10, 0x4723); // jrc $25 / jr16 $25 326 relocateOne(buf, R_MICROMIPS_PC19_S2, gotPltEntryAddr - pltEntryAddr); 327 } else { 328 write16<e>(buf, 0x7900); // addiupc $2, (GOTPLT) - . 329 write16<e>(buf + 4, 0xff22); // lw $25, 0($2) 330 write16<e>(buf + 8, 0x4599); // jrc $25 / jr16 $25 331 write16<e>(buf + 10, 0x0f02); // move $24, $2 332 relocateOne(buf, R_MICROMIPS_PC23_S2, gotPltEntryAddr - pltEntryAddr); 333 } 334 return; 335 } 336 337 uint32_t loadInst = ELFT::Is64Bits ? 0xddf90000 : 0x8df90000; 338 uint32_t jrInst = isMipsR6() ? (config->zHazardplt ? 0x03200409 : 0x03200009) 339 : (config->zHazardplt ? 0x03200408 : 0x03200008); 340 uint32_t addInst = ELFT::Is64Bits ? 0x65f80000 : 0x25f80000; 341 342 write32<e>(buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 343 write32<e>(buf + 4, loadInst); // l[wd] $25, %lo(.got.plt entry)($15) 344 write32<e>(buf + 8, jrInst); // jr $25 / jr.hb $25 345 write32<e>(buf + 12, addInst); // [d]addiu $24, $15, %lo(.got.plt entry) 346 writeValue<e>(buf, gotPltEntryAddr + 0x8000, 16, 16); 347 writeValue<e>(buf + 4, gotPltEntryAddr, 16, 0); 348 writeValue<e>(buf + 12, gotPltEntryAddr, 16, 0); 349 } 350 351 template <class ELFT> 352 bool MIPS<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file, 353 uint64_t branchAddr, const Symbol &s) const { 354 // Any MIPS PIC code function is invoked with its address in register $t9. 355 // So if we have a branch instruction from non-PIC code to the PIC one 356 // we cannot make the jump directly and need to create a small stubs 357 // to save the target function address. 358 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 359 if (type != R_MIPS_26 && type != R_MIPS_PC26_S2 && 360 type != R_MICROMIPS_26_S1 && type != R_MICROMIPS_PC26_S1) 361 return false; 362 auto *f = dyn_cast_or_null<ObjFile<ELFT>>(file); 363 if (!f) 364 return false; 365 // If current file has PIC code, LA25 stub is not required. 366 if (f->getObj().getHeader()->e_flags & EF_MIPS_PIC) 367 return false; 368 auto *d = dyn_cast<Defined>(&s); 369 // LA25 is required if target file has PIC code 370 // or target symbol is a PIC symbol. 371 return d && isMipsPIC<ELFT>(d); 372 } 373 374 template <class ELFT> 375 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const { 376 const endianness e = ELFT::TargetEndianness; 377 switch (type) { 378 case R_MIPS_32: 379 case R_MIPS_GPREL32: 380 case R_MIPS_TLS_DTPREL32: 381 case R_MIPS_TLS_TPREL32: 382 return SignExtend64<32>(read32<e>(buf)); 383 case R_MIPS_26: 384 // FIXME (simon): If the relocation target symbol is not a PLT entry 385 // we should use another expression for calculation: 386 // ((A << 2) | (P & 0xf0000000)) >> 2 387 return SignExtend64<28>(read32<e>(buf) << 2); 388 case R_MIPS_GOT16: 389 case R_MIPS_HI16: 390 case R_MIPS_PCHI16: 391 return SignExtend64<16>(read32<e>(buf)) << 16; 392 case R_MIPS_GPREL16: 393 case R_MIPS_LO16: 394 case R_MIPS_PCLO16: 395 case R_MIPS_TLS_DTPREL_HI16: 396 case R_MIPS_TLS_DTPREL_LO16: 397 case R_MIPS_TLS_TPREL_HI16: 398 case R_MIPS_TLS_TPREL_LO16: 399 return SignExtend64<16>(read32<e>(buf)); 400 case R_MICROMIPS_GOT16: 401 case R_MICROMIPS_HI16: 402 return SignExtend64<16>(readShuffle<e>(buf)) << 16; 403 case R_MICROMIPS_GPREL16: 404 case R_MICROMIPS_LO16: 405 case R_MICROMIPS_TLS_DTPREL_HI16: 406 case R_MICROMIPS_TLS_DTPREL_LO16: 407 case R_MICROMIPS_TLS_TPREL_HI16: 408 case R_MICROMIPS_TLS_TPREL_LO16: 409 return SignExtend64<16>(readShuffle<e>(buf)); 410 case R_MICROMIPS_GPREL7_S2: 411 return SignExtend64<9>(readShuffle<e>(buf) << 2); 412 case R_MIPS_PC16: 413 return SignExtend64<18>(read32<e>(buf) << 2); 414 case R_MIPS_PC19_S2: 415 return SignExtend64<21>(read32<e>(buf) << 2); 416 case R_MIPS_PC21_S2: 417 return SignExtend64<23>(read32<e>(buf) << 2); 418 case R_MIPS_PC26_S2: 419 return SignExtend64<28>(read32<e>(buf) << 2); 420 case R_MIPS_PC32: 421 return SignExtend64<32>(read32<e>(buf)); 422 case R_MICROMIPS_26_S1: 423 return SignExtend64<27>(readShuffle<e>(buf) << 1); 424 case R_MICROMIPS_PC7_S1: 425 return SignExtend64<8>(read16<e>(buf) << 1); 426 case R_MICROMIPS_PC10_S1: 427 return SignExtend64<11>(read16<e>(buf) << 1); 428 case R_MICROMIPS_PC16_S1: 429 return SignExtend64<17>(readShuffle<e>(buf) << 1); 430 case R_MICROMIPS_PC18_S3: 431 return SignExtend64<21>(readShuffle<e>(buf) << 3); 432 case R_MICROMIPS_PC19_S2: 433 return SignExtend64<21>(readShuffle<e>(buf) << 2); 434 case R_MICROMIPS_PC21_S1: 435 return SignExtend64<22>(readShuffle<e>(buf) << 1); 436 case R_MICROMIPS_PC23_S2: 437 return SignExtend64<25>(readShuffle<e>(buf) << 2); 438 case R_MICROMIPS_PC26_S1: 439 return SignExtend64<27>(readShuffle<e>(buf) << 1); 440 default: 441 return 0; 442 } 443 } 444 445 static std::pair<uint32_t, uint64_t> 446 calculateMipsRelChain(uint8_t *loc, RelType type, uint64_t val) { 447 // MIPS N64 ABI packs multiple relocations into the single relocation 448 // record. In general, all up to three relocations can have arbitrary 449 // types. In fact, Clang and GCC uses only a few combinations. For now, 450 // we support two of them. That is allow to pass at least all LLVM 451 // test suite cases. 452 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 453 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 454 // The first relocation is a 'real' relocation which is calculated 455 // using the corresponding symbol's value. The second and the third 456 // relocations used to modify result of the first one: extend it to 457 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 458 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 459 RelType type2 = (type >> 8) & 0xff; 460 RelType type3 = (type >> 16) & 0xff; 461 if (type2 == R_MIPS_NONE && type3 == R_MIPS_NONE) 462 return std::make_pair(type, val); 463 if (type2 == R_MIPS_64 && type3 == R_MIPS_NONE) 464 return std::make_pair(type2, val); 465 if (type2 == R_MIPS_SUB && (type3 == R_MIPS_HI16 || type3 == R_MIPS_LO16)) 466 return std::make_pair(type3, -val); 467 error(getErrorLocation(loc) + "unsupported relocations combination " + 468 Twine(type)); 469 return std::make_pair(type & 0xff, val); 470 } 471 472 static bool isBranchReloc(RelType type) { 473 return type == R_MIPS_26 || type == R_MIPS_PC26_S2 || 474 type == R_MIPS_PC21_S2 || type == R_MIPS_PC16; 475 } 476 477 static bool isMicroBranchReloc(RelType type) { 478 return type == R_MICROMIPS_26_S1 || type == R_MICROMIPS_PC16_S1 || 479 type == R_MICROMIPS_PC10_S1 || type == R_MICROMIPS_PC7_S1; 480 } 481 482 template <class ELFT> 483 static uint64_t fixupCrossModeJump(uint8_t *loc, RelType type, uint64_t val) { 484 // Here we need to detect jump/branch from regular MIPS code 485 // to a microMIPS target and vice versa. In that cases jump 486 // instructions need to be replaced by their "cross-mode" 487 // equivalents. 488 const endianness e = ELFT::TargetEndianness; 489 bool isMicroTgt = val & 0x1; 490 bool isCrossJump = (isMicroTgt && isBranchReloc(type)) || 491 (!isMicroTgt && isMicroBranchReloc(type)); 492 if (!isCrossJump) 493 return val; 494 495 switch (type) { 496 case R_MIPS_26: { 497 uint32_t inst = read32<e>(loc) >> 26; 498 if (inst == 0x3 || inst == 0x1d) { // JAL or JALX 499 writeValue<e>(loc, 0x1d << 26, 32, 0); 500 return val; 501 } 502 break; 503 } 504 case R_MICROMIPS_26_S1: { 505 uint32_t inst = readShuffle<e>(loc) >> 26; 506 if (inst == 0x3d || inst == 0x3c) { // JAL32 or JALX32 507 val >>= 1; 508 writeShuffleValue<e>(loc, 0x3c << 26, 32, 0); 509 return val; 510 } 511 break; 512 } 513 case R_MIPS_PC26_S2: 514 case R_MIPS_PC21_S2: 515 case R_MIPS_PC16: 516 case R_MICROMIPS_PC16_S1: 517 case R_MICROMIPS_PC10_S1: 518 case R_MICROMIPS_PC7_S1: 519 // FIXME (simon): Support valid branch relocations. 520 break; 521 default: 522 llvm_unreachable("unexpected jump/branch relocation"); 523 } 524 525 error(getErrorLocation(loc) + 526 "unsupported jump/branch instruction between ISA modes referenced by " + 527 toString(type) + " relocation"); 528 return val; 529 } 530 531 template <class ELFT> 532 void MIPS<ELFT>::relocateOne(uint8_t *loc, RelType type, uint64_t val) const { 533 const endianness e = ELFT::TargetEndianness; 534 535 if (ELFT::Is64Bits || config->mipsN32Abi) 536 std::tie(type, val) = calculateMipsRelChain(loc, type, val); 537 538 // Detect cross-mode jump/branch and fix instruction. 539 val = fixupCrossModeJump<ELFT>(loc, type, val); 540 541 // Thread pointer and DRP offsets from the start of TLS data area. 542 // https://www.linux-mips.org/wiki/NPTL 543 if (type == R_MIPS_TLS_DTPREL_HI16 || type == R_MIPS_TLS_DTPREL_LO16 || 544 type == R_MIPS_TLS_DTPREL32 || type == R_MIPS_TLS_DTPREL64 || 545 type == R_MICROMIPS_TLS_DTPREL_HI16 || 546 type == R_MICROMIPS_TLS_DTPREL_LO16) { 547 val -= 0x8000; 548 } 549 550 switch (type) { 551 case R_MIPS_32: 552 case R_MIPS_GPREL32: 553 case R_MIPS_TLS_DTPREL32: 554 case R_MIPS_TLS_TPREL32: 555 write32<e>(loc, val); 556 break; 557 case R_MIPS_64: 558 case R_MIPS_TLS_DTPREL64: 559 case R_MIPS_TLS_TPREL64: 560 write64<e>(loc, val); 561 break; 562 case R_MIPS_26: 563 writeValue<e>(loc, val, 26, 2); 564 break; 565 case R_MIPS_GOT16: 566 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 567 // is updated addend (not a GOT index). In that case write high 16 bits 568 // to store a correct addend value. 569 if (config->relocatable) { 570 writeValue<e>(loc, val + 0x8000, 16, 16); 571 } else { 572 checkInt(loc, val, 16, type); 573 writeValue<e>(loc, val, 16, 0); 574 } 575 break; 576 case R_MICROMIPS_GOT16: 577 if (config->relocatable) { 578 writeShuffleValue<e>(loc, val + 0x8000, 16, 16); 579 } else { 580 checkInt(loc, val, 16, type); 581 writeShuffleValue<e>(loc, val, 16, 0); 582 } 583 break; 584 case R_MIPS_CALL16: 585 case R_MIPS_GOT_DISP: 586 case R_MIPS_GOT_PAGE: 587 case R_MIPS_GPREL16: 588 case R_MIPS_TLS_GD: 589 case R_MIPS_TLS_GOTTPREL: 590 case R_MIPS_TLS_LDM: 591 checkInt(loc, val, 16, type); 592 LLVM_FALLTHROUGH; 593 case R_MIPS_CALL_LO16: 594 case R_MIPS_GOT_LO16: 595 case R_MIPS_GOT_OFST: 596 case R_MIPS_LO16: 597 case R_MIPS_PCLO16: 598 case R_MIPS_TLS_DTPREL_LO16: 599 case R_MIPS_TLS_TPREL_LO16: 600 writeValue<e>(loc, val, 16, 0); 601 break; 602 case R_MICROMIPS_GPREL16: 603 case R_MICROMIPS_TLS_GD: 604 case R_MICROMIPS_TLS_LDM: 605 checkInt(loc, val, 16, type); 606 writeShuffleValue<e>(loc, val, 16, 0); 607 break; 608 case R_MICROMIPS_CALL16: 609 case R_MICROMIPS_CALL_LO16: 610 case R_MICROMIPS_LO16: 611 case R_MICROMIPS_TLS_DTPREL_LO16: 612 case R_MICROMIPS_TLS_GOTTPREL: 613 case R_MICROMIPS_TLS_TPREL_LO16: 614 writeShuffleValue<e>(loc, val, 16, 0); 615 break; 616 case R_MICROMIPS_GPREL7_S2: 617 checkInt(loc, val, 7, type); 618 writeShuffleValue<e>(loc, val, 7, 2); 619 break; 620 case R_MIPS_CALL_HI16: 621 case R_MIPS_GOT_HI16: 622 case R_MIPS_HI16: 623 case R_MIPS_PCHI16: 624 case R_MIPS_TLS_DTPREL_HI16: 625 case R_MIPS_TLS_TPREL_HI16: 626 writeValue<e>(loc, val + 0x8000, 16, 16); 627 break; 628 case R_MICROMIPS_CALL_HI16: 629 case R_MICROMIPS_GOT_HI16: 630 case R_MICROMIPS_HI16: 631 case R_MICROMIPS_TLS_DTPREL_HI16: 632 case R_MICROMIPS_TLS_TPREL_HI16: 633 writeShuffleValue<e>(loc, val + 0x8000, 16, 16); 634 break; 635 case R_MIPS_HIGHER: 636 writeValue<e>(loc, val + 0x80008000, 16, 32); 637 break; 638 case R_MIPS_HIGHEST: 639 writeValue<e>(loc, val + 0x800080008000, 16, 48); 640 break; 641 case R_MIPS_JALR: 642 val -= 4; 643 // Replace jalr/jr instructions by bal/b if the target 644 // offset fits into the 18-bit range. 645 if (isInt<18>(val)) { 646 switch (read32<e>(loc)) { 647 case 0x0320f809: // jalr $25 => bal sym 648 write32<e>(loc, 0x04110000 | ((val >> 2) & 0xffff)); 649 break; 650 case 0x03200008: // jr $25 => b sym 651 write32<e>(loc, 0x10000000 | ((val >> 2) & 0xffff)); 652 break; 653 } 654 } 655 break; 656 case R_MICROMIPS_JALR: 657 // Ignore this optimization relocation for now 658 break; 659 case R_MIPS_PC16: 660 checkAlignment(loc, val, 4, type); 661 checkInt(loc, val, 18, type); 662 writeValue<e>(loc, val, 16, 2); 663 break; 664 case R_MIPS_PC19_S2: 665 checkAlignment(loc, val, 4, type); 666 checkInt(loc, val, 21, type); 667 writeValue<e>(loc, val, 19, 2); 668 break; 669 case R_MIPS_PC21_S2: 670 checkAlignment(loc, val, 4, type); 671 checkInt(loc, val, 23, type); 672 writeValue<e>(loc, val, 21, 2); 673 break; 674 case R_MIPS_PC26_S2: 675 checkAlignment(loc, val, 4, type); 676 checkInt(loc, val, 28, type); 677 writeValue<e>(loc, val, 26, 2); 678 break; 679 case R_MIPS_PC32: 680 writeValue<e>(loc, val, 32, 0); 681 break; 682 case R_MICROMIPS_26_S1: 683 case R_MICROMIPS_PC26_S1: 684 checkInt(loc, val, 27, type); 685 writeShuffleValue<e>(loc, val, 26, 1); 686 break; 687 case R_MICROMIPS_PC7_S1: 688 checkInt(loc, val, 8, type); 689 writeMicroRelocation16<e>(loc, val, 7, 1); 690 break; 691 case R_MICROMIPS_PC10_S1: 692 checkInt(loc, val, 11, type); 693 writeMicroRelocation16<e>(loc, val, 10, 1); 694 break; 695 case R_MICROMIPS_PC16_S1: 696 checkInt(loc, val, 17, type); 697 writeShuffleValue<e>(loc, val, 16, 1); 698 break; 699 case R_MICROMIPS_PC18_S3: 700 checkInt(loc, val, 21, type); 701 writeShuffleValue<e>(loc, val, 18, 3); 702 break; 703 case R_MICROMIPS_PC19_S2: 704 checkInt(loc, val, 21, type); 705 writeShuffleValue<e>(loc, val, 19, 2); 706 break; 707 case R_MICROMIPS_PC21_S1: 708 checkInt(loc, val, 22, type); 709 writeShuffleValue<e>(loc, val, 21, 1); 710 break; 711 case R_MICROMIPS_PC23_S2: 712 checkInt(loc, val, 25, type); 713 writeShuffleValue<e>(loc, val, 23, 2); 714 break; 715 default: 716 llvm_unreachable("unknown relocation"); 717 } 718 } 719 720 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType type) const { 721 return type == R_MIPS_LO16 || type == R_MIPS_GOT_OFST || 722 type == R_MICROMIPS_LO16; 723 } 724 725 // Return true if the symbol is a PIC function. 726 template <class ELFT> bool elf::isMipsPIC(const Defined *sym) { 727 if (!sym->isFunc()) 728 return false; 729 730 if (sym->stOther & STO_MIPS_PIC) 731 return true; 732 733 if (!sym->section) 734 return false; 735 736 ObjFile<ELFT> *file = 737 cast<InputSectionBase>(sym->section)->template getFile<ELFT>(); 738 if (!file) 739 return false; 740 741 return file->getObj().getHeader()->e_flags & EF_MIPS_PIC; 742 } 743 744 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 745 static MIPS<ELFT> target; 746 return ⌖ 747 } 748 749 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 750 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 751 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 752 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 753 754 template bool elf::isMipsPIC<ELF32LE>(const Defined *); 755 template bool elf::isMipsPIC<ELF32BE>(const Defined *); 756 template bool elf::isMipsPIC<ELF64LE>(const Defined *); 757 template bool elf::isMipsPIC<ELF64BE>(const Defined *); 758