1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "OutputSections.h" 11 #include "Symbols.h" 12 #include "SyntheticSections.h" 13 #include "Target.h" 14 #include "Thunks.h" 15 #include "lld/Common/ErrorHandler.h" 16 #include "llvm/Object/ELF.h" 17 #include "llvm/Support/Endian.h" 18 19 using namespace llvm; 20 using namespace llvm::object; 21 using namespace llvm::support::endian; 22 using namespace llvm::ELF; 23 using namespace lld; 24 using namespace lld::elf; 25 26 namespace { 27 template <class ELFT> class MIPS final : public TargetInfo { 28 public: 29 MIPS(); 30 uint32_t calcEFlags() const override; 31 RelExpr getRelExpr(RelType type, const Symbol &s, 32 const uint8_t *loc) const override; 33 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; 34 RelType getDynRel(RelType type) const override; 35 void writeGotPlt(uint8_t *buf, const Symbol &s) const override; 36 void writePltHeader(uint8_t *buf) const override; 37 void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr, 38 int32_t index, unsigned relOff) const override; 39 bool needsThunk(RelExpr expr, RelType type, const InputFile *file, 40 uint64_t branchAddr, const Symbol &s) const override; 41 void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override; 42 bool usesOnlyLowPageBits(RelType type) const override; 43 }; 44 } // namespace 45 46 template <class ELFT> MIPS<ELFT>::MIPS() { 47 gotPltHeaderEntriesNum = 2; 48 defaultMaxPageSize = 65536; 49 gotBaseSymInGotPlt = false; 50 pltEntrySize = 16; 51 pltHeaderSize = 32; 52 copyRel = R_MIPS_COPY; 53 noneRel = R_MIPS_NONE; 54 pltRel = R_MIPS_JUMP_SLOT; 55 needsThunks = true; 56 57 // Set `sigrie 1` as a trap instruction. 58 write32(trapInstr.data(), 0x04170001); 59 60 if (ELFT::Is64Bits) { 61 relativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 62 symbolicRel = R_MIPS_64; 63 tlsGotRel = R_MIPS_TLS_TPREL64; 64 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 65 tlsOffsetRel = R_MIPS_TLS_DTPREL64; 66 } else { 67 relativeRel = R_MIPS_REL32; 68 symbolicRel = R_MIPS_32; 69 tlsGotRel = R_MIPS_TLS_TPREL32; 70 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 71 tlsOffsetRel = R_MIPS_TLS_DTPREL32; 72 } 73 } 74 75 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 76 return calcMipsEFlags<ELFT>(); 77 } 78 79 template <class ELFT> 80 RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s, 81 const uint8_t *loc) const { 82 // See comment in the calculateMipsRelChain. 83 if (ELFT::Is64Bits || config->mipsN32Abi) 84 type &= 0xff; 85 86 switch (type) { 87 case R_MIPS_JALR: 88 case R_MICROMIPS_JALR: 89 return R_HINT; 90 case R_MIPS_GPREL16: 91 case R_MIPS_GPREL32: 92 case R_MICROMIPS_GPREL16: 93 case R_MICROMIPS_GPREL7_S2: 94 return R_MIPS_GOTREL; 95 case R_MIPS_26: 96 case R_MICROMIPS_26_S1: 97 return R_PLT; 98 case R_MICROMIPS_PC26_S1: 99 return R_PLT_PC; 100 case R_MIPS_HI16: 101 case R_MIPS_LO16: 102 case R_MIPS_HIGHER: 103 case R_MIPS_HIGHEST: 104 case R_MICROMIPS_HI16: 105 case R_MICROMIPS_LO16: 106 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 107 // offset between start of function and 'gp' value which by default 108 // equal to the start of .got section. In that case we consider these 109 // relocations as relative. 110 if (&s == ElfSym::mipsGpDisp) 111 return R_MIPS_GOT_GP_PC; 112 if (&s == ElfSym::mipsLocalGp) 113 return R_MIPS_GOT_GP; 114 LLVM_FALLTHROUGH; 115 case R_MIPS_32: 116 case R_MIPS_64: 117 case R_MIPS_GOT_OFST: 118 case R_MIPS_SUB: 119 case R_MIPS_TLS_DTPREL_HI16: 120 case R_MIPS_TLS_DTPREL_LO16: 121 case R_MIPS_TLS_DTPREL32: 122 case R_MIPS_TLS_DTPREL64: 123 case R_MICROMIPS_TLS_DTPREL_HI16: 124 case R_MICROMIPS_TLS_DTPREL_LO16: 125 return R_ABS; 126 case R_MIPS_TLS_TPREL_HI16: 127 case R_MIPS_TLS_TPREL_LO16: 128 case R_MIPS_TLS_TPREL32: 129 case R_MIPS_TLS_TPREL64: 130 case R_MICROMIPS_TLS_TPREL_HI16: 131 case R_MICROMIPS_TLS_TPREL_LO16: 132 return R_TLS; 133 case R_MIPS_PC32: 134 case R_MIPS_PC16: 135 case R_MIPS_PC19_S2: 136 case R_MIPS_PC21_S2: 137 case R_MIPS_PC26_S2: 138 case R_MIPS_PCHI16: 139 case R_MIPS_PCLO16: 140 case R_MICROMIPS_PC7_S1: 141 case R_MICROMIPS_PC10_S1: 142 case R_MICROMIPS_PC16_S1: 143 case R_MICROMIPS_PC18_S3: 144 case R_MICROMIPS_PC19_S2: 145 case R_MICROMIPS_PC23_S2: 146 case R_MICROMIPS_PC21_S1: 147 return R_PC; 148 case R_MIPS_GOT16: 149 case R_MICROMIPS_GOT16: 150 if (s.isLocal()) 151 return R_MIPS_GOT_LOCAL_PAGE; 152 LLVM_FALLTHROUGH; 153 case R_MIPS_CALL16: 154 case R_MIPS_GOT_DISP: 155 case R_MIPS_TLS_GOTTPREL: 156 case R_MICROMIPS_CALL16: 157 case R_MICROMIPS_TLS_GOTTPREL: 158 return R_MIPS_GOT_OFF; 159 case R_MIPS_CALL_HI16: 160 case R_MIPS_CALL_LO16: 161 case R_MIPS_GOT_HI16: 162 case R_MIPS_GOT_LO16: 163 case R_MICROMIPS_CALL_HI16: 164 case R_MICROMIPS_CALL_LO16: 165 case R_MICROMIPS_GOT_HI16: 166 case R_MICROMIPS_GOT_LO16: 167 return R_MIPS_GOT_OFF32; 168 case R_MIPS_GOT_PAGE: 169 return R_MIPS_GOT_LOCAL_PAGE; 170 case R_MIPS_TLS_GD: 171 case R_MICROMIPS_TLS_GD: 172 return R_MIPS_TLSGD; 173 case R_MIPS_TLS_LDM: 174 case R_MICROMIPS_TLS_LDM: 175 return R_MIPS_TLSLD; 176 case R_MIPS_NONE: 177 return R_NONE; 178 default: 179 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 180 ") against symbol " + toString(s)); 181 return R_NONE; 182 } 183 } 184 185 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType type) const { 186 if (type == symbolicRel) 187 return type; 188 return R_MIPS_NONE; 189 } 190 191 template <class ELFT> 192 void MIPS<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const { 193 uint64_t va = in.plt->getVA(); 194 if (isMicroMips()) 195 va |= 1; 196 write32<ELFT::TargetEndianness>(buf, va); 197 } 198 199 template <endianness E> static uint32_t readShuffle(const uint8_t *loc) { 200 // The major opcode of a microMIPS instruction needs to appear 201 // in the first 16-bit word (lowest address) for efficient hardware 202 // decode so that it knows if the instruction is 16-bit or 32-bit 203 // as early as possible. To do so, little-endian binaries keep 16-bit 204 // words in a big-endian order. That is why we have to swap these 205 // words to get a correct value. 206 uint32_t v = read32<E>(loc); 207 if (E == support::little) 208 return (v << 16) | (v >> 16); 209 return v; 210 } 211 212 template <endianness E> 213 static void writeValue(uint8_t *loc, uint64_t v, uint8_t bitsSize, 214 uint8_t shift) { 215 uint32_t instr = read32<E>(loc); 216 uint32_t mask = 0xffffffff >> (32 - bitsSize); 217 uint32_t data = (instr & ~mask) | ((v >> shift) & mask); 218 write32<E>(loc, data); 219 } 220 221 template <endianness E> 222 static void writeShuffleValue(uint8_t *loc, uint64_t v, uint8_t bitsSize, 223 uint8_t shift) { 224 // See comments in readShuffle for purpose of this code. 225 uint16_t *words = (uint16_t *)loc; 226 if (E == support::little) 227 std::swap(words[0], words[1]); 228 229 writeValue<E>(loc, v, bitsSize, shift); 230 231 if (E == support::little) 232 std::swap(words[0], words[1]); 233 } 234 235 template <endianness E> 236 static void writeMicroRelocation16(uint8_t *loc, uint64_t v, uint8_t bitsSize, 237 uint8_t shift) { 238 uint16_t instr = read16<E>(loc); 239 uint16_t mask = 0xffff >> (16 - bitsSize); 240 uint16_t data = (instr & ~mask) | ((v >> shift) & mask); 241 write16<E>(loc, data); 242 } 243 244 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const { 245 const endianness e = ELFT::TargetEndianness; 246 if (isMicroMips()) { 247 uint64_t gotPlt = in.gotPlt->getVA(); 248 uint64_t plt = in.plt->getVA(); 249 // Overwrite trap instructions written by Writer::writeTrapInstr. 250 memset(buf, 0, pltHeaderSize); 251 252 write16<e>(buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 253 write16<e>(buf + 4, 0xff23); // lw $25, 0($3) 254 write16<e>(buf + 8, 0x0535); // subu16 $2, $2, $3 255 write16<e>(buf + 10, 0x2525); // srl16 $2, $2, 2 256 write16<e>(buf + 12, 0x3302); // addiu $24, $2, -2 257 write16<e>(buf + 14, 0xfffe); 258 write16<e>(buf + 16, 0x0dff); // move $15, $31 259 if (isMipsR6()) { 260 write16<e>(buf + 18, 0x0f83); // move $28, $3 261 write16<e>(buf + 20, 0x472b); // jalrc $25 262 write16<e>(buf + 22, 0x0c00); // nop 263 relocateOne(buf, R_MICROMIPS_PC19_S2, gotPlt - plt); 264 } else { 265 write16<e>(buf + 18, 0x45f9); // jalrc $25 266 write16<e>(buf + 20, 0x0f83); // move $28, $3 267 write16<e>(buf + 22, 0x0c00); // nop 268 relocateOne(buf, R_MICROMIPS_PC23_S2, gotPlt - plt); 269 } 270 return; 271 } 272 273 if (config->mipsN32Abi) { 274 write32<e>(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 275 write32<e>(buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 276 write32<e>(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 277 write32<e>(buf + 12, 0x030ec023); // subu $24, $24, $14 278 write32<e>(buf + 16, 0x03e07825); // move $15, $31 279 write32<e>(buf + 20, 0x0018c082); // srl $24, $24, 2 280 } else if (ELFT::Is64Bits) { 281 write32<e>(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 282 write32<e>(buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14) 283 write32<e>(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 284 write32<e>(buf + 12, 0x030ec023); // subu $24, $24, $14 285 write32<e>(buf + 16, 0x03e07825); // move $15, $31 286 write32<e>(buf + 20, 0x0018c0c2); // srl $24, $24, 3 287 } else { 288 write32<e>(buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 289 write32<e>(buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 290 write32<e>(buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 291 write32<e>(buf + 12, 0x031cc023); // subu $24, $24, $28 292 write32<e>(buf + 16, 0x03e07825); // move $15, $31 293 write32<e>(buf + 20, 0x0018c082); // srl $24, $24, 2 294 } 295 296 uint32_t jalrInst = config->zHazardplt ? 0x0320fc09 : 0x0320f809; 297 write32<e>(buf + 24, jalrInst); // jalr.hb $25 or jalr $25 298 write32<e>(buf + 28, 0x2718fffe); // subu $24, $24, 2 299 300 uint64_t gotPlt = in.gotPlt->getVA(); 301 writeValue<e>(buf, gotPlt + 0x8000, 16, 16); 302 writeValue<e>(buf + 4, gotPlt, 16, 0); 303 writeValue<e>(buf + 8, gotPlt, 16, 0); 304 } 305 306 template <class ELFT> 307 void MIPS<ELFT>::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, 308 uint64_t pltEntryAddr, int32_t index, 309 unsigned relOff) const { 310 const endianness e = ELFT::TargetEndianness; 311 if (isMicroMips()) { 312 // Overwrite trap instructions written by Writer::writeTrapInstr. 313 memset(buf, 0, pltEntrySize); 314 315 if (isMipsR6()) { 316 write16<e>(buf, 0x7840); // addiupc $2, (GOTPLT) - . 317 write16<e>(buf + 4, 0xff22); // lw $25, 0($2) 318 write16<e>(buf + 8, 0x0f02); // move $24, $2 319 write16<e>(buf + 10, 0x4723); // jrc $25 / jr16 $25 320 relocateOne(buf, R_MICROMIPS_PC19_S2, gotPltEntryAddr - pltEntryAddr); 321 } else { 322 write16<e>(buf, 0x7900); // addiupc $2, (GOTPLT) - . 323 write16<e>(buf + 4, 0xff22); // lw $25, 0($2) 324 write16<e>(buf + 8, 0x4599); // jrc $25 / jr16 $25 325 write16<e>(buf + 10, 0x0f02); // move $24, $2 326 relocateOne(buf, R_MICROMIPS_PC23_S2, gotPltEntryAddr - pltEntryAddr); 327 } 328 return; 329 } 330 331 uint32_t loadInst = ELFT::Is64Bits ? 0xddf90000 : 0x8df90000; 332 uint32_t jrInst = isMipsR6() ? (config->zHazardplt ? 0x03200409 : 0x03200009) 333 : (config->zHazardplt ? 0x03200408 : 0x03200008); 334 uint32_t addInst = ELFT::Is64Bits ? 0x65f80000 : 0x25f80000; 335 336 write32<e>(buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 337 write32<e>(buf + 4, loadInst); // l[wd] $25, %lo(.got.plt entry)($15) 338 write32<e>(buf + 8, jrInst); // jr $25 / jr.hb $25 339 write32<e>(buf + 12, addInst); // [d]addiu $24, $15, %lo(.got.plt entry) 340 writeValue<e>(buf, gotPltEntryAddr + 0x8000, 16, 16); 341 writeValue<e>(buf + 4, gotPltEntryAddr, 16, 0); 342 writeValue<e>(buf + 12, gotPltEntryAddr, 16, 0); 343 } 344 345 template <class ELFT> 346 bool MIPS<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file, 347 uint64_t branchAddr, const Symbol &s) const { 348 // Any MIPS PIC code function is invoked with its address in register $t9. 349 // So if we have a branch instruction from non-PIC code to the PIC one 350 // we cannot make the jump directly and need to create a small stubs 351 // to save the target function address. 352 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 353 if (type != R_MIPS_26 && type != R_MIPS_PC26_S2 && 354 type != R_MICROMIPS_26_S1 && type != R_MICROMIPS_PC26_S1) 355 return false; 356 auto *f = dyn_cast_or_null<ObjFile<ELFT>>(file); 357 if (!f) 358 return false; 359 // If current file has PIC code, LA25 stub is not required. 360 if (f->getObj().getHeader()->e_flags & EF_MIPS_PIC) 361 return false; 362 auto *d = dyn_cast<Defined>(&s); 363 // LA25 is required if target file has PIC code 364 // or target symbol is a PIC symbol. 365 return d && isMipsPIC<ELFT>(d); 366 } 367 368 template <class ELFT> 369 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const { 370 const endianness e = ELFT::TargetEndianness; 371 switch (type) { 372 case R_MIPS_32: 373 case R_MIPS_GPREL32: 374 case R_MIPS_TLS_DTPREL32: 375 case R_MIPS_TLS_TPREL32: 376 return SignExtend64<32>(read32<e>(buf)); 377 case R_MIPS_26: 378 // FIXME (simon): If the relocation target symbol is not a PLT entry 379 // we should use another expression for calculation: 380 // ((A << 2) | (P & 0xf0000000)) >> 2 381 return SignExtend64<28>(read32<e>(buf) << 2); 382 case R_MIPS_GOT16: 383 case R_MIPS_HI16: 384 case R_MIPS_PCHI16: 385 return SignExtend64<16>(read32<e>(buf)) << 16; 386 case R_MIPS_GPREL16: 387 case R_MIPS_LO16: 388 case R_MIPS_PCLO16: 389 case R_MIPS_TLS_DTPREL_HI16: 390 case R_MIPS_TLS_DTPREL_LO16: 391 case R_MIPS_TLS_TPREL_HI16: 392 case R_MIPS_TLS_TPREL_LO16: 393 return SignExtend64<16>(read32<e>(buf)); 394 case R_MICROMIPS_GOT16: 395 case R_MICROMIPS_HI16: 396 return SignExtend64<16>(readShuffle<e>(buf)) << 16; 397 case R_MICROMIPS_GPREL16: 398 case R_MICROMIPS_LO16: 399 case R_MICROMIPS_TLS_DTPREL_HI16: 400 case R_MICROMIPS_TLS_DTPREL_LO16: 401 case R_MICROMIPS_TLS_TPREL_HI16: 402 case R_MICROMIPS_TLS_TPREL_LO16: 403 return SignExtend64<16>(readShuffle<e>(buf)); 404 case R_MICROMIPS_GPREL7_S2: 405 return SignExtend64<9>(readShuffle<e>(buf) << 2); 406 case R_MIPS_PC16: 407 return SignExtend64<18>(read32<e>(buf) << 2); 408 case R_MIPS_PC19_S2: 409 return SignExtend64<21>(read32<e>(buf) << 2); 410 case R_MIPS_PC21_S2: 411 return SignExtend64<23>(read32<e>(buf) << 2); 412 case R_MIPS_PC26_S2: 413 return SignExtend64<28>(read32<e>(buf) << 2); 414 case R_MIPS_PC32: 415 return SignExtend64<32>(read32<e>(buf)); 416 case R_MICROMIPS_26_S1: 417 return SignExtend64<27>(readShuffle<e>(buf) << 1); 418 case R_MICROMIPS_PC7_S1: 419 return SignExtend64<8>(read16<e>(buf) << 1); 420 case R_MICROMIPS_PC10_S1: 421 return SignExtend64<11>(read16<e>(buf) << 1); 422 case R_MICROMIPS_PC16_S1: 423 return SignExtend64<17>(readShuffle<e>(buf) << 1); 424 case R_MICROMIPS_PC18_S3: 425 return SignExtend64<21>(readShuffle<e>(buf) << 3); 426 case R_MICROMIPS_PC19_S2: 427 return SignExtend64<21>(readShuffle<e>(buf) << 2); 428 case R_MICROMIPS_PC21_S1: 429 return SignExtend64<22>(readShuffle<e>(buf) << 1); 430 case R_MICROMIPS_PC23_S2: 431 return SignExtend64<25>(readShuffle<e>(buf) << 2); 432 case R_MICROMIPS_PC26_S1: 433 return SignExtend64<27>(readShuffle<e>(buf) << 1); 434 default: 435 return 0; 436 } 437 } 438 439 static std::pair<uint32_t, uint64_t> 440 calculateMipsRelChain(uint8_t *loc, RelType type, uint64_t val) { 441 // MIPS N64 ABI packs multiple relocations into the single relocation 442 // record. In general, all up to three relocations can have arbitrary 443 // types. In fact, Clang and GCC uses only a few combinations. For now, 444 // we support two of them. That is allow to pass at least all LLVM 445 // test suite cases. 446 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 447 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 448 // The first relocation is a 'real' relocation which is calculated 449 // using the corresponding symbol's value. The second and the third 450 // relocations used to modify result of the first one: extend it to 451 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 452 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 453 RelType type2 = (type >> 8) & 0xff; 454 RelType type3 = (type >> 16) & 0xff; 455 if (type2 == R_MIPS_NONE && type3 == R_MIPS_NONE) 456 return std::make_pair(type, val); 457 if (type2 == R_MIPS_64 && type3 == R_MIPS_NONE) 458 return std::make_pair(type2, val); 459 if (type2 == R_MIPS_SUB && (type3 == R_MIPS_HI16 || type3 == R_MIPS_LO16)) 460 return std::make_pair(type3, -val); 461 error(getErrorLocation(loc) + "unsupported relocations combination " + 462 Twine(type)); 463 return std::make_pair(type & 0xff, val); 464 } 465 466 static bool isBranchReloc(RelType type) { 467 return type == R_MIPS_26 || type == R_MIPS_PC26_S2 || 468 type == R_MIPS_PC21_S2 || type == R_MIPS_PC16; 469 } 470 471 static bool isMicroBranchReloc(RelType type) { 472 return type == R_MICROMIPS_26_S1 || type == R_MICROMIPS_PC16_S1 || 473 type == R_MICROMIPS_PC10_S1 || type == R_MICROMIPS_PC7_S1; 474 } 475 476 template <class ELFT> 477 static uint64_t fixupCrossModeJump(uint8_t *loc, RelType type, uint64_t val) { 478 // Here we need to detect jump/branch from regular MIPS code 479 // to a microMIPS target and vice versa. In that cases jump 480 // instructions need to be replaced by their "cross-mode" 481 // equivalents. 482 const endianness e = ELFT::TargetEndianness; 483 bool isMicroTgt = val & 0x1; 484 bool isCrossJump = (isMicroTgt && isBranchReloc(type)) || 485 (!isMicroTgt && isMicroBranchReloc(type)); 486 if (!isCrossJump) 487 return val; 488 489 switch (type) { 490 case R_MIPS_26: { 491 uint32_t inst = read32<e>(loc) >> 26; 492 if (inst == 0x3 || inst == 0x1d) { // JAL or JALX 493 writeValue<e>(loc, 0x1d << 26, 32, 0); 494 return val; 495 } 496 break; 497 } 498 case R_MICROMIPS_26_S1: { 499 uint32_t inst = readShuffle<e>(loc) >> 26; 500 if (inst == 0x3d || inst == 0x3c) { // JAL32 or JALX32 501 val >>= 1; 502 writeShuffleValue<e>(loc, 0x3c << 26, 32, 0); 503 return val; 504 } 505 break; 506 } 507 case R_MIPS_PC26_S2: 508 case R_MIPS_PC21_S2: 509 case R_MIPS_PC16: 510 case R_MICROMIPS_PC16_S1: 511 case R_MICROMIPS_PC10_S1: 512 case R_MICROMIPS_PC7_S1: 513 // FIXME (simon): Support valid branch relocations. 514 break; 515 default: 516 llvm_unreachable("unexpected jump/branch relocation"); 517 } 518 519 error(getErrorLocation(loc) + 520 "unsupported jump/branch instruction between ISA modes referenced by " + 521 toString(type) + " relocation"); 522 return val; 523 } 524 525 template <class ELFT> 526 void MIPS<ELFT>::relocateOne(uint8_t *loc, RelType type, uint64_t val) const { 527 const endianness e = ELFT::TargetEndianness; 528 529 if (ELFT::Is64Bits || config->mipsN32Abi) 530 std::tie(type, val) = calculateMipsRelChain(loc, type, val); 531 532 // Detect cross-mode jump/branch and fix instruction. 533 val = fixupCrossModeJump<ELFT>(loc, type, val); 534 535 // Thread pointer and DRP offsets from the start of TLS data area. 536 // https://www.linux-mips.org/wiki/NPTL 537 if (type == R_MIPS_TLS_DTPREL_HI16 || type == R_MIPS_TLS_DTPREL_LO16 || 538 type == R_MIPS_TLS_DTPREL32 || type == R_MIPS_TLS_DTPREL64 || 539 type == R_MICROMIPS_TLS_DTPREL_HI16 || 540 type == R_MICROMIPS_TLS_DTPREL_LO16) { 541 val -= 0x8000; 542 } 543 544 switch (type) { 545 case R_MIPS_32: 546 case R_MIPS_GPREL32: 547 case R_MIPS_TLS_DTPREL32: 548 case R_MIPS_TLS_TPREL32: 549 write32<e>(loc, val); 550 break; 551 case R_MIPS_64: 552 case R_MIPS_TLS_DTPREL64: 553 case R_MIPS_TLS_TPREL64: 554 write64<e>(loc, val); 555 break; 556 case R_MIPS_26: 557 writeValue<e>(loc, val, 26, 2); 558 break; 559 case R_MIPS_GOT16: 560 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 561 // is updated addend (not a GOT index). In that case write high 16 bits 562 // to store a correct addend value. 563 if (config->relocatable) { 564 writeValue<e>(loc, val + 0x8000, 16, 16); 565 } else { 566 checkInt(loc, val, 16, type); 567 writeValue<e>(loc, val, 16, 0); 568 } 569 break; 570 case R_MICROMIPS_GOT16: 571 if (config->relocatable) { 572 writeShuffleValue<e>(loc, val + 0x8000, 16, 16); 573 } else { 574 checkInt(loc, val, 16, type); 575 writeShuffleValue<e>(loc, val, 16, 0); 576 } 577 break; 578 case R_MIPS_CALL16: 579 case R_MIPS_GOT_DISP: 580 case R_MIPS_GOT_PAGE: 581 case R_MIPS_GPREL16: 582 case R_MIPS_TLS_GD: 583 case R_MIPS_TLS_GOTTPREL: 584 case R_MIPS_TLS_LDM: 585 checkInt(loc, val, 16, type); 586 LLVM_FALLTHROUGH; 587 case R_MIPS_CALL_LO16: 588 case R_MIPS_GOT_LO16: 589 case R_MIPS_GOT_OFST: 590 case R_MIPS_LO16: 591 case R_MIPS_PCLO16: 592 case R_MIPS_TLS_DTPREL_LO16: 593 case R_MIPS_TLS_TPREL_LO16: 594 writeValue<e>(loc, val, 16, 0); 595 break; 596 case R_MICROMIPS_GPREL16: 597 case R_MICROMIPS_TLS_GD: 598 case R_MICROMIPS_TLS_LDM: 599 checkInt(loc, val, 16, type); 600 writeShuffleValue<e>(loc, val, 16, 0); 601 break; 602 case R_MICROMIPS_CALL16: 603 case R_MICROMIPS_CALL_LO16: 604 case R_MICROMIPS_LO16: 605 case R_MICROMIPS_TLS_DTPREL_LO16: 606 case R_MICROMIPS_TLS_GOTTPREL: 607 case R_MICROMIPS_TLS_TPREL_LO16: 608 writeShuffleValue<e>(loc, val, 16, 0); 609 break; 610 case R_MICROMIPS_GPREL7_S2: 611 checkInt(loc, val, 7, type); 612 writeShuffleValue<e>(loc, val, 7, 2); 613 break; 614 case R_MIPS_CALL_HI16: 615 case R_MIPS_GOT_HI16: 616 case R_MIPS_HI16: 617 case R_MIPS_PCHI16: 618 case R_MIPS_TLS_DTPREL_HI16: 619 case R_MIPS_TLS_TPREL_HI16: 620 writeValue<e>(loc, val + 0x8000, 16, 16); 621 break; 622 case R_MICROMIPS_CALL_HI16: 623 case R_MICROMIPS_GOT_HI16: 624 case R_MICROMIPS_HI16: 625 case R_MICROMIPS_TLS_DTPREL_HI16: 626 case R_MICROMIPS_TLS_TPREL_HI16: 627 writeShuffleValue<e>(loc, val + 0x8000, 16, 16); 628 break; 629 case R_MIPS_HIGHER: 630 writeValue<e>(loc, val + 0x80008000, 16, 32); 631 break; 632 case R_MIPS_HIGHEST: 633 writeValue<e>(loc, val + 0x800080008000, 16, 48); 634 break; 635 case R_MIPS_JALR: 636 case R_MICROMIPS_JALR: 637 // Ignore this optimization relocation for now 638 break; 639 case R_MIPS_PC16: 640 checkAlignment(loc, val, 4, type); 641 checkInt(loc, val, 18, type); 642 writeValue<e>(loc, val, 16, 2); 643 break; 644 case R_MIPS_PC19_S2: 645 checkAlignment(loc, val, 4, type); 646 checkInt(loc, val, 21, type); 647 writeValue<e>(loc, val, 19, 2); 648 break; 649 case R_MIPS_PC21_S2: 650 checkAlignment(loc, val, 4, type); 651 checkInt(loc, val, 23, type); 652 writeValue<e>(loc, val, 21, 2); 653 break; 654 case R_MIPS_PC26_S2: 655 checkAlignment(loc, val, 4, type); 656 checkInt(loc, val, 28, type); 657 writeValue<e>(loc, val, 26, 2); 658 break; 659 case R_MIPS_PC32: 660 writeValue<e>(loc, val, 32, 0); 661 break; 662 case R_MICROMIPS_26_S1: 663 case R_MICROMIPS_PC26_S1: 664 checkInt(loc, val, 27, type); 665 writeShuffleValue<e>(loc, val, 26, 1); 666 break; 667 case R_MICROMIPS_PC7_S1: 668 checkInt(loc, val, 8, type); 669 writeMicroRelocation16<e>(loc, val, 7, 1); 670 break; 671 case R_MICROMIPS_PC10_S1: 672 checkInt(loc, val, 11, type); 673 writeMicroRelocation16<e>(loc, val, 10, 1); 674 break; 675 case R_MICROMIPS_PC16_S1: 676 checkInt(loc, val, 17, type); 677 writeShuffleValue<e>(loc, val, 16, 1); 678 break; 679 case R_MICROMIPS_PC18_S3: 680 checkInt(loc, val, 21, type); 681 writeShuffleValue<e>(loc, val, 18, 3); 682 break; 683 case R_MICROMIPS_PC19_S2: 684 checkInt(loc, val, 21, type); 685 writeShuffleValue<e>(loc, val, 19, 2); 686 break; 687 case R_MICROMIPS_PC21_S1: 688 checkInt(loc, val, 22, type); 689 writeShuffleValue<e>(loc, val, 21, 1); 690 break; 691 case R_MICROMIPS_PC23_S2: 692 checkInt(loc, val, 25, type); 693 writeShuffleValue<e>(loc, val, 23, 2); 694 break; 695 default: 696 llvm_unreachable("unknown relocation"); 697 } 698 } 699 700 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType type) const { 701 return type == R_MIPS_LO16 || type == R_MIPS_GOT_OFST || 702 type == R_MICROMIPS_LO16; 703 } 704 705 // Return true if the symbol is a PIC function. 706 template <class ELFT> bool elf::isMipsPIC(const Defined *sym) { 707 if (!sym->isFunc()) 708 return false; 709 710 if (sym->stOther & STO_MIPS_PIC) 711 return true; 712 713 if (!sym->section) 714 return false; 715 716 ObjFile<ELFT> *file = 717 cast<InputSectionBase>(sym->section)->template getFile<ELFT>(); 718 if (!file) 719 return false; 720 721 return file->getObj().getHeader()->e_flags & EF_MIPS_PIC; 722 } 723 724 template <class ELFT> TargetInfo *elf::getMipsTargetInfo() { 725 static MIPS<ELFT> target; 726 return ⌖ 727 } 728 729 template TargetInfo *elf::getMipsTargetInfo<ELF32LE>(); 730 template TargetInfo *elf::getMipsTargetInfo<ELF32BE>(); 731 template TargetInfo *elf::getMipsTargetInfo<ELF64LE>(); 732 template TargetInfo *elf::getMipsTargetInfo<ELF64BE>(); 733 734 template bool elf::isMipsPIC<ELF32LE>(const Defined *); 735 template bool elf::isMipsPIC<ELF32BE>(const Defined *); 736 template bool elf::isMipsPIC<ELF64LE>(const Defined *); 737 template bool elf::isMipsPIC<ELF64BE>(const Defined *); 738