1 //===- MIPS.cpp -----------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "OutputSections.h" 11 #include "Symbols.h" 12 #include "SyntheticSections.h" 13 #include "Target.h" 14 #include "Thunks.h" 15 #include "lld/Common/ErrorHandler.h" 16 #include "llvm/Object/ELF.h" 17 18 using namespace llvm; 19 using namespace llvm::object; 20 using namespace llvm::ELF; 21 22 namespace lld { 23 namespace elf { 24 namespace { 25 template <class ELFT> class MIPS final : public TargetInfo { 26 public: 27 MIPS(); 28 uint32_t calcEFlags() const override; 29 RelExpr getRelExpr(RelType type, const Symbol &s, 30 const uint8_t *loc) const override; 31 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override; 32 RelType getDynRel(RelType type) const override; 33 void writeGotPlt(uint8_t *buf, const Symbol &s) const override; 34 void writePltHeader(uint8_t *buf) const override; 35 void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr, 36 int32_t index, unsigned relOff) const override; 37 bool needsThunk(RelExpr expr, RelType type, const InputFile *file, 38 uint64_t branchAddr, const Symbol &s) const override; 39 void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override; 40 bool usesOnlyLowPageBits(RelType type) const override; 41 }; 42 } // namespace 43 44 template <class ELFT> MIPS<ELFT>::MIPS() { 45 gotPltHeaderEntriesNum = 2; 46 defaultMaxPageSize = 65536; 47 gotBaseSymInGotPlt = false; 48 pltEntrySize = 16; 49 pltHeaderSize = 32; 50 copyRel = R_MIPS_COPY; 51 noneRel = R_MIPS_NONE; 52 pltRel = R_MIPS_JUMP_SLOT; 53 needsThunks = true; 54 55 // Set `sigrie 1` as a trap instruction. 56 write32(trapInstr.data(), 0x04170001); 57 58 if (ELFT::Is64Bits) { 59 relativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32; 60 symbolicRel = R_MIPS_64; 61 tlsGotRel = R_MIPS_TLS_TPREL64; 62 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD64; 63 tlsOffsetRel = R_MIPS_TLS_DTPREL64; 64 } else { 65 relativeRel = R_MIPS_REL32; 66 symbolicRel = R_MIPS_32; 67 tlsGotRel = R_MIPS_TLS_TPREL32; 68 tlsModuleIndexRel = R_MIPS_TLS_DTPMOD32; 69 tlsOffsetRel = R_MIPS_TLS_DTPREL32; 70 } 71 } 72 73 template <class ELFT> uint32_t MIPS<ELFT>::calcEFlags() const { 74 return calcMipsEFlags<ELFT>(); 75 } 76 77 template <class ELFT> 78 RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s, 79 const uint8_t *loc) const { 80 // See comment in the calculateMipsRelChain. 81 if (ELFT::Is64Bits || config->mipsN32Abi) 82 type &= 0xff; 83 84 switch (type) { 85 case R_MIPS_JALR: 86 // If the target symbol is not preemptible and is not microMIPS, 87 // it might be possible to replace jalr/jr instruction by bal/b. 88 // It depends on the target symbol's offset. 89 if (!s.isPreemptible && !(s.getVA() & 0x1)) 90 return R_PC; 91 return R_NONE; 92 case R_MICROMIPS_JALR: 93 return R_NONE; 94 case R_MIPS_GPREL16: 95 case R_MIPS_GPREL32: 96 case R_MICROMIPS_GPREL16: 97 case R_MICROMIPS_GPREL7_S2: 98 return R_MIPS_GOTREL; 99 case R_MIPS_26: 100 case R_MICROMIPS_26_S1: 101 return R_PLT; 102 case R_MICROMIPS_PC26_S1: 103 return R_PLT_PC; 104 case R_MIPS_HI16: 105 case R_MIPS_LO16: 106 case R_MIPS_HIGHER: 107 case R_MIPS_HIGHEST: 108 case R_MICROMIPS_HI16: 109 case R_MICROMIPS_LO16: 110 // R_MIPS_HI16/R_MIPS_LO16 relocations against _gp_disp calculate 111 // offset between start of function and 'gp' value which by default 112 // equal to the start of .got section. In that case we consider these 113 // relocations as relative. 114 if (&s == ElfSym::mipsGpDisp) 115 return R_MIPS_GOT_GP_PC; 116 if (&s == ElfSym::mipsLocalGp) 117 return R_MIPS_GOT_GP; 118 LLVM_FALLTHROUGH; 119 case R_MIPS_32: 120 case R_MIPS_64: 121 case R_MIPS_GOT_OFST: 122 case R_MIPS_SUB: 123 case R_MIPS_TLS_DTPREL_HI16: 124 case R_MIPS_TLS_DTPREL_LO16: 125 case R_MIPS_TLS_DTPREL32: 126 case R_MIPS_TLS_DTPREL64: 127 case R_MICROMIPS_TLS_DTPREL_HI16: 128 case R_MICROMIPS_TLS_DTPREL_LO16: 129 return R_ABS; 130 case R_MIPS_TLS_TPREL_HI16: 131 case R_MIPS_TLS_TPREL_LO16: 132 case R_MIPS_TLS_TPREL32: 133 case R_MIPS_TLS_TPREL64: 134 case R_MICROMIPS_TLS_TPREL_HI16: 135 case R_MICROMIPS_TLS_TPREL_LO16: 136 return R_TLS; 137 case R_MIPS_PC32: 138 case R_MIPS_PC16: 139 case R_MIPS_PC19_S2: 140 case R_MIPS_PC21_S2: 141 case R_MIPS_PC26_S2: 142 case R_MIPS_PCHI16: 143 case R_MIPS_PCLO16: 144 case R_MICROMIPS_PC7_S1: 145 case R_MICROMIPS_PC10_S1: 146 case R_MICROMIPS_PC16_S1: 147 case R_MICROMIPS_PC18_S3: 148 case R_MICROMIPS_PC19_S2: 149 case R_MICROMIPS_PC23_S2: 150 case R_MICROMIPS_PC21_S1: 151 return R_PC; 152 case R_MIPS_GOT16: 153 case R_MICROMIPS_GOT16: 154 if (s.isLocal()) 155 return R_MIPS_GOT_LOCAL_PAGE; 156 LLVM_FALLTHROUGH; 157 case R_MIPS_CALL16: 158 case R_MIPS_GOT_DISP: 159 case R_MIPS_TLS_GOTTPREL: 160 case R_MICROMIPS_CALL16: 161 case R_MICROMIPS_TLS_GOTTPREL: 162 return R_MIPS_GOT_OFF; 163 case R_MIPS_CALL_HI16: 164 case R_MIPS_CALL_LO16: 165 case R_MIPS_GOT_HI16: 166 case R_MIPS_GOT_LO16: 167 case R_MICROMIPS_CALL_HI16: 168 case R_MICROMIPS_CALL_LO16: 169 case R_MICROMIPS_GOT_HI16: 170 case R_MICROMIPS_GOT_LO16: 171 return R_MIPS_GOT_OFF32; 172 case R_MIPS_GOT_PAGE: 173 return R_MIPS_GOT_LOCAL_PAGE; 174 case R_MIPS_TLS_GD: 175 case R_MICROMIPS_TLS_GD: 176 return R_MIPS_TLSGD; 177 case R_MIPS_TLS_LDM: 178 case R_MICROMIPS_TLS_LDM: 179 return R_MIPS_TLSLD; 180 case R_MIPS_NONE: 181 return R_NONE; 182 default: 183 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 184 ") against symbol " + toString(s)); 185 return R_NONE; 186 } 187 } 188 189 template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType type) const { 190 if (type == symbolicRel) 191 return type; 192 return R_MIPS_NONE; 193 } 194 195 template <class ELFT> 196 void MIPS<ELFT>::writeGotPlt(uint8_t *buf, const Symbol &) const { 197 uint64_t va = in.plt->getVA(); 198 if (isMicroMips()) 199 va |= 1; 200 write32(buf, va); 201 } 202 203 template <endianness E> static uint32_t readShuffle(const uint8_t *loc) { 204 // The major opcode of a microMIPS instruction needs to appear 205 // in the first 16-bit word (lowest address) for efficient hardware 206 // decode so that it knows if the instruction is 16-bit or 32-bit 207 // as early as possible. To do so, little-endian binaries keep 16-bit 208 // words in a big-endian order. That is why we have to swap these 209 // words to get a correct value. 210 uint32_t v = read32(loc); 211 if (E == support::little) 212 return (v << 16) | (v >> 16); 213 return v; 214 } 215 216 static void writeValue(uint8_t *loc, uint64_t v, uint8_t bitsSize, 217 uint8_t shift) { 218 uint32_t instr = read32(loc); 219 uint32_t mask = 0xffffffff >> (32 - bitsSize); 220 uint32_t data = (instr & ~mask) | ((v >> shift) & mask); 221 write32(loc, data); 222 } 223 224 template <endianness E> 225 static void writeShuffleValue(uint8_t *loc, uint64_t v, uint8_t bitsSize, 226 uint8_t shift) { 227 // See comments in readShuffle for purpose of this code. 228 uint16_t *words = (uint16_t *)loc; 229 if (E == support::little) 230 std::swap(words[0], words[1]); 231 232 writeValue(loc, v, bitsSize, shift); 233 234 if (E == support::little) 235 std::swap(words[0], words[1]); 236 } 237 238 template <endianness E> 239 static void writeMicroRelocation16(uint8_t *loc, uint64_t v, uint8_t bitsSize, 240 uint8_t shift) { 241 uint16_t instr = read16(loc); 242 uint16_t mask = 0xffff >> (16 - bitsSize); 243 uint16_t data = (instr & ~mask) | ((v >> shift) & mask); 244 write16(loc, data); 245 } 246 247 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *buf) const { 248 if (isMicroMips()) { 249 uint64_t gotPlt = in.gotPlt->getVA(); 250 uint64_t plt = in.plt->getVA(); 251 // Overwrite trap instructions written by Writer::writeTrapInstr. 252 memset(buf, 0, pltHeaderSize); 253 254 write16(buf, isMipsR6() ? 0x7860 : 0x7980); // addiupc v1, (GOTPLT) - . 255 write16(buf + 4, 0xff23); // lw $25, 0($3) 256 write16(buf + 8, 0x0535); // subu16 $2, $2, $3 257 write16(buf + 10, 0x2525); // srl16 $2, $2, 2 258 write16(buf + 12, 0x3302); // addiu $24, $2, -2 259 write16(buf + 14, 0xfffe); 260 write16(buf + 16, 0x0dff); // move $15, $31 261 if (isMipsR6()) { 262 write16(buf + 18, 0x0f83); // move $28, $3 263 write16(buf + 20, 0x472b); // jalrc $25 264 write16(buf + 22, 0x0c00); // nop 265 relocateOne(buf, R_MICROMIPS_PC19_S2, gotPlt - plt); 266 } else { 267 write16(buf + 18, 0x45f9); // jalrc $25 268 write16(buf + 20, 0x0f83); // move $28, $3 269 write16(buf + 22, 0x0c00); // nop 270 relocateOne(buf, R_MICROMIPS_PC23_S2, gotPlt - plt); 271 } 272 return; 273 } 274 275 if (config->mipsN32Abi) { 276 write32(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 277 write32(buf + 4, 0x8dd90000); // lw $25, %lo(&GOTPLT[0])($14) 278 write32(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 279 write32(buf + 12, 0x030ec023); // subu $24, $24, $14 280 write32(buf + 16, 0x03e07825); // move $15, $31 281 write32(buf + 20, 0x0018c082); // srl $24, $24, 2 282 } else if (ELFT::Is64Bits) { 283 write32(buf, 0x3c0e0000); // lui $14, %hi(&GOTPLT[0]) 284 write32(buf + 4, 0xddd90000); // ld $25, %lo(&GOTPLT[0])($14) 285 write32(buf + 8, 0x25ce0000); // addiu $14, $14, %lo(&GOTPLT[0]) 286 write32(buf + 12, 0x030ec023); // subu $24, $24, $14 287 write32(buf + 16, 0x03e07825); // move $15, $31 288 write32(buf + 20, 0x0018c0c2); // srl $24, $24, 3 289 } else { 290 write32(buf, 0x3c1c0000); // lui $28, %hi(&GOTPLT[0]) 291 write32(buf + 4, 0x8f990000); // lw $25, %lo(&GOTPLT[0])($28) 292 write32(buf + 8, 0x279c0000); // addiu $28, $28, %lo(&GOTPLT[0]) 293 write32(buf + 12, 0x031cc023); // subu $24, $24, $28 294 write32(buf + 16, 0x03e07825); // move $15, $31 295 write32(buf + 20, 0x0018c082); // srl $24, $24, 2 296 } 297 298 uint32_t jalrInst = config->zHazardplt ? 0x0320fc09 : 0x0320f809; 299 write32(buf + 24, jalrInst); // jalr.hb $25 or jalr $25 300 write32(buf + 28, 0x2718fffe); // subu $24, $24, 2 301 302 uint64_t gotPlt = in.gotPlt->getVA(); 303 writeValue(buf, gotPlt + 0x8000, 16, 16); 304 writeValue(buf + 4, gotPlt, 16, 0); 305 writeValue(buf + 8, gotPlt, 16, 0); 306 } 307 308 template <class ELFT> 309 void MIPS<ELFT>::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, 310 uint64_t pltEntryAddr, int32_t index, 311 unsigned relOff) const { 312 if (isMicroMips()) { 313 // Overwrite trap instructions written by Writer::writeTrapInstr. 314 memset(buf, 0, pltEntrySize); 315 316 if (isMipsR6()) { 317 write16(buf, 0x7840); // addiupc $2, (GOTPLT) - . 318 write16(buf + 4, 0xff22); // lw $25, 0($2) 319 write16(buf + 8, 0x0f02); // move $24, $2 320 write16(buf + 10, 0x4723); // jrc $25 / jr16 $25 321 relocateOne(buf, R_MICROMIPS_PC19_S2, gotPltEntryAddr - pltEntryAddr); 322 } else { 323 write16(buf, 0x7900); // addiupc $2, (GOTPLT) - . 324 write16(buf + 4, 0xff22); // lw $25, 0($2) 325 write16(buf + 8, 0x4599); // jrc $25 / jr16 $25 326 write16(buf + 10, 0x0f02); // move $24, $2 327 relocateOne(buf, R_MICROMIPS_PC23_S2, gotPltEntryAddr - pltEntryAddr); 328 } 329 return; 330 } 331 332 uint32_t loadInst = ELFT::Is64Bits ? 0xddf90000 : 0x8df90000; 333 uint32_t jrInst = isMipsR6() ? (config->zHazardplt ? 0x03200409 : 0x03200009) 334 : (config->zHazardplt ? 0x03200408 : 0x03200008); 335 uint32_t addInst = ELFT::Is64Bits ? 0x65f80000 : 0x25f80000; 336 337 write32(buf, 0x3c0f0000); // lui $15, %hi(.got.plt entry) 338 write32(buf + 4, loadInst); // l[wd] $25, %lo(.got.plt entry)($15) 339 write32(buf + 8, jrInst); // jr $25 / jr.hb $25 340 write32(buf + 12, addInst); // [d]addiu $24, $15, %lo(.got.plt entry) 341 writeValue(buf, gotPltEntryAddr + 0x8000, 16, 16); 342 writeValue(buf + 4, gotPltEntryAddr, 16, 0); 343 writeValue(buf + 12, gotPltEntryAddr, 16, 0); 344 } 345 346 template <class ELFT> 347 bool MIPS<ELFT>::needsThunk(RelExpr expr, RelType type, const InputFile *file, 348 uint64_t branchAddr, const Symbol &s) const { 349 // Any MIPS PIC code function is invoked with its address in register $t9. 350 // So if we have a branch instruction from non-PIC code to the PIC one 351 // we cannot make the jump directly and need to create a small stubs 352 // to save the target function address. 353 // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf 354 if (type != R_MIPS_26 && type != R_MIPS_PC26_S2 && 355 type != R_MICROMIPS_26_S1 && type != R_MICROMIPS_PC26_S1) 356 return false; 357 auto *f = dyn_cast_or_null<ObjFile<ELFT>>(file); 358 if (!f) 359 return false; 360 // If current file has PIC code, LA25 stub is not required. 361 if (f->getObj().getHeader()->e_flags & EF_MIPS_PIC) 362 return false; 363 auto *d = dyn_cast<Defined>(&s); 364 // LA25 is required if target file has PIC code 365 // or target symbol is a PIC symbol. 366 return d && isMipsPIC<ELFT>(d); 367 } 368 369 template <class ELFT> 370 int64_t MIPS<ELFT>::getImplicitAddend(const uint8_t *buf, RelType type) const { 371 const endianness e = ELFT::TargetEndianness; 372 switch (type) { 373 case R_MIPS_32: 374 case R_MIPS_GPREL32: 375 case R_MIPS_TLS_DTPREL32: 376 case R_MIPS_TLS_TPREL32: 377 return SignExtend64<32>(read32(buf)); 378 case R_MIPS_26: 379 // FIXME (simon): If the relocation target symbol is not a PLT entry 380 // we should use another expression for calculation: 381 // ((A << 2) | (P & 0xf0000000)) >> 2 382 return SignExtend64<28>(read32(buf) << 2); 383 case R_MIPS_GOT16: 384 case R_MIPS_HI16: 385 case R_MIPS_PCHI16: 386 return SignExtend64<16>(read32(buf)) << 16; 387 case R_MIPS_GPREL16: 388 case R_MIPS_LO16: 389 case R_MIPS_PCLO16: 390 case R_MIPS_TLS_DTPREL_HI16: 391 case R_MIPS_TLS_DTPREL_LO16: 392 case R_MIPS_TLS_TPREL_HI16: 393 case R_MIPS_TLS_TPREL_LO16: 394 return SignExtend64<16>(read32(buf)); 395 case R_MICROMIPS_GOT16: 396 case R_MICROMIPS_HI16: 397 return SignExtend64<16>(readShuffle<e>(buf)) << 16; 398 case R_MICROMIPS_GPREL16: 399 case R_MICROMIPS_LO16: 400 case R_MICROMIPS_TLS_DTPREL_HI16: 401 case R_MICROMIPS_TLS_DTPREL_LO16: 402 case R_MICROMIPS_TLS_TPREL_HI16: 403 case R_MICROMIPS_TLS_TPREL_LO16: 404 return SignExtend64<16>(readShuffle<e>(buf)); 405 case R_MICROMIPS_GPREL7_S2: 406 return SignExtend64<9>(readShuffle<e>(buf) << 2); 407 case R_MIPS_PC16: 408 return SignExtend64<18>(read32(buf) << 2); 409 case R_MIPS_PC19_S2: 410 return SignExtend64<21>(read32(buf) << 2); 411 case R_MIPS_PC21_S2: 412 return SignExtend64<23>(read32(buf) << 2); 413 case R_MIPS_PC26_S2: 414 return SignExtend64<28>(read32(buf) << 2); 415 case R_MIPS_PC32: 416 return SignExtend64<32>(read32(buf)); 417 case R_MICROMIPS_26_S1: 418 return SignExtend64<27>(readShuffle<e>(buf) << 1); 419 case R_MICROMIPS_PC7_S1: 420 return SignExtend64<8>(read16(buf) << 1); 421 case R_MICROMIPS_PC10_S1: 422 return SignExtend64<11>(read16(buf) << 1); 423 case R_MICROMIPS_PC16_S1: 424 return SignExtend64<17>(readShuffle<e>(buf) << 1); 425 case R_MICROMIPS_PC18_S3: 426 return SignExtend64<21>(readShuffle<e>(buf) << 3); 427 case R_MICROMIPS_PC19_S2: 428 return SignExtend64<21>(readShuffle<e>(buf) << 2); 429 case R_MICROMIPS_PC21_S1: 430 return SignExtend64<22>(readShuffle<e>(buf) << 1); 431 case R_MICROMIPS_PC23_S2: 432 return SignExtend64<25>(readShuffle<e>(buf) << 2); 433 case R_MICROMIPS_PC26_S1: 434 return SignExtend64<27>(readShuffle<e>(buf) << 1); 435 default: 436 return 0; 437 } 438 } 439 440 static std::pair<uint32_t, uint64_t> 441 calculateMipsRelChain(uint8_t *loc, RelType type, uint64_t val) { 442 // MIPS N64 ABI packs multiple relocations into the single relocation 443 // record. In general, all up to three relocations can have arbitrary 444 // types. In fact, Clang and GCC uses only a few combinations. For now, 445 // we support two of them. That is allow to pass at least all LLVM 446 // test suite cases. 447 // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16 448 // <any relocation> / R_MIPS_64 / R_MIPS_NONE 449 // The first relocation is a 'real' relocation which is calculated 450 // using the corresponding symbol's value. The second and the third 451 // relocations used to modify result of the first one: extend it to 452 // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation 453 // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf 454 RelType type2 = (type >> 8) & 0xff; 455 RelType type3 = (type >> 16) & 0xff; 456 if (type2 == R_MIPS_NONE && type3 == R_MIPS_NONE) 457 return std::make_pair(type, val); 458 if (type2 == R_MIPS_64 && type3 == R_MIPS_NONE) 459 return std::make_pair(type2, val); 460 if (type2 == R_MIPS_SUB && (type3 == R_MIPS_HI16 || type3 == R_MIPS_LO16)) 461 return std::make_pair(type3, -val); 462 error(getErrorLocation(loc) + "unsupported relocations combination " + 463 Twine(type)); 464 return std::make_pair(type & 0xff, val); 465 } 466 467 static bool isBranchReloc(RelType type) { 468 return type == R_MIPS_26 || type == R_MIPS_PC26_S2 || 469 type == R_MIPS_PC21_S2 || type == R_MIPS_PC16; 470 } 471 472 static bool isMicroBranchReloc(RelType type) { 473 return type == R_MICROMIPS_26_S1 || type == R_MICROMIPS_PC16_S1 || 474 type == R_MICROMIPS_PC10_S1 || type == R_MICROMIPS_PC7_S1; 475 } 476 477 template <class ELFT> 478 static uint64_t fixupCrossModeJump(uint8_t *loc, RelType type, uint64_t val) { 479 // Here we need to detect jump/branch from regular MIPS code 480 // to a microMIPS target and vice versa. In that cases jump 481 // instructions need to be replaced by their "cross-mode" 482 // equivalents. 483 const endianness e = ELFT::TargetEndianness; 484 bool isMicroTgt = val & 0x1; 485 bool isCrossJump = (isMicroTgt && isBranchReloc(type)) || 486 (!isMicroTgt && isMicroBranchReloc(type)); 487 if (!isCrossJump) 488 return val; 489 490 switch (type) { 491 case R_MIPS_26: { 492 uint32_t inst = read32(loc) >> 26; 493 if (inst == 0x3 || inst == 0x1d) { // JAL or JALX 494 writeValue(loc, 0x1d << 26, 32, 0); 495 return val; 496 } 497 break; 498 } 499 case R_MICROMIPS_26_S1: { 500 uint32_t inst = readShuffle<e>(loc) >> 26; 501 if (inst == 0x3d || inst == 0x3c) { // JAL32 or JALX32 502 val >>= 1; 503 writeShuffleValue<e>(loc, 0x3c << 26, 32, 0); 504 return val; 505 } 506 break; 507 } 508 case R_MIPS_PC26_S2: 509 case R_MIPS_PC21_S2: 510 case R_MIPS_PC16: 511 case R_MICROMIPS_PC16_S1: 512 case R_MICROMIPS_PC10_S1: 513 case R_MICROMIPS_PC7_S1: 514 // FIXME (simon): Support valid branch relocations. 515 break; 516 default: 517 llvm_unreachable("unexpected jump/branch relocation"); 518 } 519 520 error(getErrorLocation(loc) + 521 "unsupported jump/branch instruction between ISA modes referenced by " + 522 toString(type) + " relocation"); 523 return val; 524 } 525 526 template <class ELFT> 527 void MIPS<ELFT>::relocateOne(uint8_t *loc, RelType type, uint64_t val) const { 528 const endianness e = ELFT::TargetEndianness; 529 530 if (ELFT::Is64Bits || config->mipsN32Abi) 531 std::tie(type, val) = calculateMipsRelChain(loc, type, val); 532 533 // Detect cross-mode jump/branch and fix instruction. 534 val = fixupCrossModeJump<ELFT>(loc, type, val); 535 536 // Thread pointer and DRP offsets from the start of TLS data area. 537 // https://www.linux-mips.org/wiki/NPTL 538 if (type == R_MIPS_TLS_DTPREL_HI16 || type == R_MIPS_TLS_DTPREL_LO16 || 539 type == R_MIPS_TLS_DTPREL32 || type == R_MIPS_TLS_DTPREL64 || 540 type == R_MICROMIPS_TLS_DTPREL_HI16 || 541 type == R_MICROMIPS_TLS_DTPREL_LO16) { 542 val -= 0x8000; 543 } 544 545 switch (type) { 546 case R_MIPS_32: 547 case R_MIPS_GPREL32: 548 case R_MIPS_TLS_DTPREL32: 549 case R_MIPS_TLS_TPREL32: 550 write32(loc, val); 551 break; 552 case R_MIPS_64: 553 case R_MIPS_TLS_DTPREL64: 554 case R_MIPS_TLS_TPREL64: 555 write64(loc, val); 556 break; 557 case R_MIPS_26: 558 writeValue(loc, val, 26, 2); 559 break; 560 case R_MIPS_GOT16: 561 // The R_MIPS_GOT16 relocation's value in "relocatable" linking mode 562 // is updated addend (not a GOT index). In that case write high 16 bits 563 // to store a correct addend value. 564 if (config->relocatable) { 565 writeValue(loc, val + 0x8000, 16, 16); 566 } else { 567 checkInt(loc, val, 16, type); 568 writeValue(loc, val, 16, 0); 569 } 570 break; 571 case R_MICROMIPS_GOT16: 572 if (config->relocatable) { 573 writeShuffleValue<e>(loc, val + 0x8000, 16, 16); 574 } else { 575 checkInt(loc, val, 16, type); 576 writeShuffleValue<e>(loc, val, 16, 0); 577 } 578 break; 579 case R_MIPS_CALL16: 580 case R_MIPS_GOT_DISP: 581 case R_MIPS_GOT_PAGE: 582 case R_MIPS_GPREL16: 583 case R_MIPS_TLS_GD: 584 case R_MIPS_TLS_GOTTPREL: 585 case R_MIPS_TLS_LDM: 586 checkInt(loc, val, 16, type); 587 LLVM_FALLTHROUGH; 588 case R_MIPS_CALL_LO16: 589 case R_MIPS_GOT_LO16: 590 case R_MIPS_GOT_OFST: 591 case R_MIPS_LO16: 592 case R_MIPS_PCLO16: 593 case R_MIPS_TLS_DTPREL_LO16: 594 case R_MIPS_TLS_TPREL_LO16: 595 writeValue(loc, val, 16, 0); 596 break; 597 case R_MICROMIPS_GPREL16: 598 case R_MICROMIPS_TLS_GD: 599 case R_MICROMIPS_TLS_LDM: 600 checkInt(loc, val, 16, type); 601 writeShuffleValue<e>(loc, val, 16, 0); 602 break; 603 case R_MICROMIPS_CALL16: 604 case R_MICROMIPS_CALL_LO16: 605 case R_MICROMIPS_LO16: 606 case R_MICROMIPS_TLS_DTPREL_LO16: 607 case R_MICROMIPS_TLS_GOTTPREL: 608 case R_MICROMIPS_TLS_TPREL_LO16: 609 writeShuffleValue<e>(loc, val, 16, 0); 610 break; 611 case R_MICROMIPS_GPREL7_S2: 612 checkInt(loc, val, 7, type); 613 writeShuffleValue<e>(loc, val, 7, 2); 614 break; 615 case R_MIPS_CALL_HI16: 616 case R_MIPS_GOT_HI16: 617 case R_MIPS_HI16: 618 case R_MIPS_PCHI16: 619 case R_MIPS_TLS_DTPREL_HI16: 620 case R_MIPS_TLS_TPREL_HI16: 621 writeValue(loc, val + 0x8000, 16, 16); 622 break; 623 case R_MICROMIPS_CALL_HI16: 624 case R_MICROMIPS_GOT_HI16: 625 case R_MICROMIPS_HI16: 626 case R_MICROMIPS_TLS_DTPREL_HI16: 627 case R_MICROMIPS_TLS_TPREL_HI16: 628 writeShuffleValue<e>(loc, val + 0x8000, 16, 16); 629 break; 630 case R_MIPS_HIGHER: 631 writeValue(loc, val + 0x80008000, 16, 32); 632 break; 633 case R_MIPS_HIGHEST: 634 writeValue(loc, val + 0x800080008000, 16, 48); 635 break; 636 case R_MIPS_JALR: 637 val -= 4; 638 // Replace jalr/jr instructions by bal/b if the target 639 // offset fits into the 18-bit range. 640 if (isInt<18>(val)) { 641 switch (read32(loc)) { 642 case 0x0320f809: // jalr $25 => bal sym 643 write32(loc, 0x04110000 | ((val >> 2) & 0xffff)); 644 break; 645 case 0x03200008: // jr $25 => b sym 646 write32(loc, 0x10000000 | ((val >> 2) & 0xffff)); 647 break; 648 } 649 } 650 break; 651 case R_MICROMIPS_JALR: 652 // Ignore this optimization relocation for now 653 break; 654 case R_MIPS_PC16: 655 checkAlignment(loc, val, 4, type); 656 checkInt(loc, val, 18, type); 657 writeValue(loc, val, 16, 2); 658 break; 659 case R_MIPS_PC19_S2: 660 checkAlignment(loc, val, 4, type); 661 checkInt(loc, val, 21, type); 662 writeValue(loc, val, 19, 2); 663 break; 664 case R_MIPS_PC21_S2: 665 checkAlignment(loc, val, 4, type); 666 checkInt(loc, val, 23, type); 667 writeValue(loc, val, 21, 2); 668 break; 669 case R_MIPS_PC26_S2: 670 checkAlignment(loc, val, 4, type); 671 checkInt(loc, val, 28, type); 672 writeValue(loc, val, 26, 2); 673 break; 674 case R_MIPS_PC32: 675 writeValue(loc, val, 32, 0); 676 break; 677 case R_MICROMIPS_26_S1: 678 case R_MICROMIPS_PC26_S1: 679 checkInt(loc, val, 27, type); 680 writeShuffleValue<e>(loc, val, 26, 1); 681 break; 682 case R_MICROMIPS_PC7_S1: 683 checkInt(loc, val, 8, type); 684 writeMicroRelocation16<e>(loc, val, 7, 1); 685 break; 686 case R_MICROMIPS_PC10_S1: 687 checkInt(loc, val, 11, type); 688 writeMicroRelocation16<e>(loc, val, 10, 1); 689 break; 690 case R_MICROMIPS_PC16_S1: 691 checkInt(loc, val, 17, type); 692 writeShuffleValue<e>(loc, val, 16, 1); 693 break; 694 case R_MICROMIPS_PC18_S3: 695 checkInt(loc, val, 21, type); 696 writeShuffleValue<e>(loc, val, 18, 3); 697 break; 698 case R_MICROMIPS_PC19_S2: 699 checkInt(loc, val, 21, type); 700 writeShuffleValue<e>(loc, val, 19, 2); 701 break; 702 case R_MICROMIPS_PC21_S1: 703 checkInt(loc, val, 22, type); 704 writeShuffleValue<e>(loc, val, 21, 1); 705 break; 706 case R_MICROMIPS_PC23_S2: 707 checkInt(loc, val, 25, type); 708 writeShuffleValue<e>(loc, val, 23, 2); 709 break; 710 default: 711 llvm_unreachable("unknown relocation"); 712 } 713 } 714 715 template <class ELFT> bool MIPS<ELFT>::usesOnlyLowPageBits(RelType type) const { 716 return type == R_MIPS_LO16 || type == R_MIPS_GOT_OFST || 717 type == R_MICROMIPS_LO16; 718 } 719 720 // Return true if the symbol is a PIC function. 721 template <class ELFT> bool isMipsPIC(const Defined *sym) { 722 if (!sym->isFunc()) 723 return false; 724 725 if (sym->stOther & STO_MIPS_PIC) 726 return true; 727 728 if (!sym->section) 729 return false; 730 731 ObjFile<ELFT> *file = 732 cast<InputSectionBase>(sym->section)->template getFile<ELFT>(); 733 if (!file) 734 return false; 735 736 return file->getObj().getHeader()->e_flags & EF_MIPS_PIC; 737 } 738 739 template <class ELFT> TargetInfo *getMipsTargetInfo() { 740 static MIPS<ELFT> target; 741 return ⌖ 742 } 743 744 template TargetInfo *getMipsTargetInfo<ELF32LE>(); 745 template TargetInfo *getMipsTargetInfo<ELF32BE>(); 746 template TargetInfo *getMipsTargetInfo<ELF64LE>(); 747 template TargetInfo *getMipsTargetInfo<ELF64BE>(); 748 749 template bool isMipsPIC<ELF32LE>(const Defined *); 750 template bool isMipsPIC<ELF32BE>(const Defined *); 751 template bool isMipsPIC<ELF64LE>(const Defined *); 752 template bool isMipsPIC<ELF64BE>(const Defined *); 753 754 } // namespace elf 755 } // namespace lld 756