1 //===-- Hexagon.cpp -------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 #include "lld/Common/ErrorHandler.h" 14 #include "llvm/BinaryFormat/ELF.h" 15 #include "llvm/Object/ELF.h" 16 #include "llvm/Support/Endian.h" 17 18 using namespace llvm; 19 using namespace llvm::object; 20 using namespace llvm::support::endian; 21 using namespace llvm::ELF; 22 using namespace lld; 23 using namespace lld::elf; 24 25 namespace { 26 class Hexagon final : public TargetInfo { 27 public: 28 Hexagon(); 29 uint32_t calcEFlags() const override; 30 RelExpr getRelExpr(RelType type, const Symbol &s, 31 const uint8_t *loc) const override; 32 RelType getDynRel(RelType type) const override; 33 void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override; 34 void writePltHeader(uint8_t *buf) const override; 35 void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr, 36 int32_t index, unsigned relOff) const override; 37 }; 38 } // namespace 39 40 Hexagon::Hexagon() { 41 pltRel = R_HEX_JMP_SLOT; 42 relativeRel = R_HEX_RELATIVE; 43 gotRel = R_HEX_GLOB_DAT; 44 symbolicRel = R_HEX_32; 45 46 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The 47 // next 3 are reserved for the dynamic loader. 48 gotPltHeaderEntriesNum = 4; 49 50 pltEntrySize = 16; 51 pltHeaderSize = 32; 52 53 // Hexagon Linux uses 64K pages by default. 54 defaultMaxPageSize = 0x10000; 55 noneRel = R_HEX_NONE; 56 } 57 58 uint32_t Hexagon::calcEFlags() const { 59 assert(!objectFiles.empty()); 60 61 // The architecture revision must always be equal to or greater than 62 // greatest revision in the list of inputs. 63 uint32_t ret = 0; 64 for (InputFile *f : objectFiles) { 65 uint32_t eflags = cast<ObjFile<ELF32LE>>(f)->getObj().getHeader()->e_flags; 66 if (eflags > ret) 67 ret = eflags; 68 } 69 return ret; 70 } 71 72 static uint32_t applyMask(uint32_t mask, uint32_t data) { 73 uint32_t result = 0; 74 size_t off = 0; 75 76 for (size_t bit = 0; bit != 32; ++bit) { 77 uint32_t valBit = (data >> off) & 1; 78 uint32_t maskBit = (mask >> bit) & 1; 79 if (maskBit) { 80 result |= (valBit << bit); 81 ++off; 82 } 83 } 84 return result; 85 } 86 87 RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s, 88 const uint8_t *loc) const { 89 switch (type) { 90 case R_HEX_NONE: 91 return R_NONE; 92 case R_HEX_6_X: 93 case R_HEX_8_X: 94 case R_HEX_9_X: 95 case R_HEX_10_X: 96 case R_HEX_11_X: 97 case R_HEX_12_X: 98 case R_HEX_16_X: 99 case R_HEX_32: 100 case R_HEX_32_6_X: 101 case R_HEX_HI16: 102 case R_HEX_LO16: 103 return R_ABS; 104 case R_HEX_B9_PCREL: 105 case R_HEX_B9_PCREL_X: 106 case R_HEX_B13_PCREL: 107 case R_HEX_B15_PCREL: 108 case R_HEX_B15_PCREL_X: 109 case R_HEX_6_PCREL_X: 110 case R_HEX_32_PCREL: 111 return R_PC; 112 case R_HEX_B22_PCREL: 113 case R_HEX_PLT_B22_PCREL: 114 case R_HEX_B22_PCREL_X: 115 case R_HEX_B32_PCREL_X: 116 return R_PLT_PC; 117 case R_HEX_GOTREL_11_X: 118 case R_HEX_GOTREL_16_X: 119 case R_HEX_GOTREL_32_6_X: 120 case R_HEX_GOTREL_HI16: 121 case R_HEX_GOTREL_LO16: 122 return R_GOTPLTREL; 123 case R_HEX_GOT_11_X: 124 case R_HEX_GOT_16_X: 125 case R_HEX_GOT_32_6_X: 126 return R_GOTPLT; 127 default: 128 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 129 ") against symbol " + toString(s)); 130 return R_NONE; 131 } 132 } 133 134 static uint32_t findMaskR6(uint32_t insn) { 135 // There are (arguably too) many relocation masks for the DSP's 136 // R_HEX_6_X type. The table below is used to select the correct mask 137 // for the given instruction. 138 struct InstructionMask { 139 uint32_t cmpMask; 140 uint32_t relocMask; 141 }; 142 143 static const InstructionMask r6[] = { 144 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f}, 145 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80}, 146 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0}, 147 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0}, 148 {0x44000000, 0x000020f8}, {0x45000000, 0x000007e0}, 149 {0x46000000, 0x000020f8}, {0x47000000, 0x000007e0}, 150 {0x6a000000, 0x00001f80}, {0x7c000000, 0x001f2000}, 151 {0x9a000000, 0x00000f60}, {0x9b000000, 0x00000f60}, 152 {0x9c000000, 0x00000f60}, {0x9d000000, 0x00000f60}, 153 {0x9f000000, 0x001f0100}, {0xab000000, 0x0000003f}, 154 {0xad000000, 0x0000003f}, {0xaf000000, 0x00030078}, 155 {0xd7000000, 0x006020e0}, {0xd8000000, 0x006020e0}, 156 {0xdb000000, 0x006020e0}, {0xdf000000, 0x006020e0}}; 157 158 // Duplex forms have a fixed mask and parse bits 15:14 are always 159 // zero. Non-duplex insns will always have at least one bit set in the 160 // parse field. 161 if ((0xC000 & insn) == 0x0) 162 return 0x03f00000; 163 164 for (InstructionMask i : r6) 165 if ((0xff000000 & insn) == i.cmpMask) 166 return i.relocMask; 167 168 error("unrecognized instruction for R_HEX_6 relocation: 0x" + 169 utohexstr(insn)); 170 return 0; 171 } 172 173 static uint32_t findMaskR8(uint32_t insn) { 174 if ((0xff000000 & insn) == 0xde000000) 175 return 0x00e020e8; 176 if ((0xff000000 & insn) == 0x3c000000) 177 return 0x0000207f; 178 return 0x00001fe0; 179 } 180 181 static uint32_t findMaskR11(uint32_t insn) { 182 if ((0xff000000 & insn) == 0xa1000000) 183 return 0x060020ff; 184 return 0x06003fe0; 185 } 186 187 static uint32_t findMaskR16(uint32_t insn) { 188 if ((0xff000000 & insn) == 0x48000000) 189 return 0x061f20ff; 190 if ((0xff000000 & insn) == 0x49000000) 191 return 0x061f3fe0; 192 if ((0xff000000 & insn) == 0x78000000) 193 return 0x00df3fe0; 194 if ((0xff000000 & insn) == 0xb0000000) 195 return 0x0fe03fe0; 196 197 error("unrecognized instruction for R_HEX_16_X relocation: 0x" + 198 utohexstr(insn)); 199 return 0; 200 } 201 202 static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); } 203 204 void Hexagon::relocateOne(uint8_t *loc, RelType type, uint64_t val) const { 205 switch (type) { 206 case R_HEX_NONE: 207 break; 208 case R_HEX_6_PCREL_X: 209 case R_HEX_6_X: 210 or32le(loc, applyMask(findMaskR6(read32le(loc)), val)); 211 break; 212 case R_HEX_8_X: 213 or32le(loc, applyMask(findMaskR8(read32le(loc)), val)); 214 break; 215 case R_HEX_9_X: 216 or32le(loc, applyMask(0x00003fe0, val & 0x3f)); 217 break; 218 case R_HEX_10_X: 219 or32le(loc, applyMask(0x00203fe0, val & 0x3f)); 220 break; 221 case R_HEX_11_X: 222 case R_HEX_GOT_11_X: 223 case R_HEX_GOTREL_11_X: 224 or32le(loc, applyMask(findMaskR11(read32le(loc)), val & 0x3f)); 225 break; 226 case R_HEX_12_X: 227 or32le(loc, applyMask(0x000007e0, val)); 228 break; 229 case R_HEX_16_X: // These relocs only have 6 effective bits. 230 case R_HEX_GOT_16_X: 231 case R_HEX_GOTREL_16_X: 232 or32le(loc, applyMask(findMaskR16(read32le(loc)), val & 0x3f)); 233 break; 234 case R_HEX_32: 235 case R_HEX_32_PCREL: 236 or32le(loc, val); 237 break; 238 case R_HEX_32_6_X: 239 case R_HEX_GOT_32_6_X: 240 case R_HEX_GOTREL_32_6_X: 241 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 242 break; 243 case R_HEX_B9_PCREL: 244 or32le(loc, applyMask(0x003000fe, val >> 2)); 245 break; 246 case R_HEX_B9_PCREL_X: 247 or32le(loc, applyMask(0x003000fe, val & 0x3f)); 248 break; 249 case R_HEX_B13_PCREL: 250 or32le(loc, applyMask(0x00202ffe, val >> 2)); 251 break; 252 case R_HEX_B15_PCREL: 253 or32le(loc, applyMask(0x00df20fe, val >> 2)); 254 break; 255 case R_HEX_B15_PCREL_X: 256 or32le(loc, applyMask(0x00df20fe, val & 0x3f)); 257 break; 258 case R_HEX_B22_PCREL: 259 case R_HEX_PLT_B22_PCREL: 260 or32le(loc, applyMask(0x1ff3ffe, val >> 2)); 261 break; 262 case R_HEX_B22_PCREL_X: 263 or32le(loc, applyMask(0x1ff3ffe, val & 0x3f)); 264 break; 265 case R_HEX_B32_PCREL_X: 266 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 267 break; 268 case R_HEX_GOTREL_HI16: 269 case R_HEX_HI16: 270 or32le(loc, applyMask(0x00c03fff, val >> 16)); 271 break; 272 case R_HEX_GOTREL_LO16: 273 case R_HEX_LO16: 274 or32le(loc, applyMask(0x00c03fff, val)); 275 break; 276 default: 277 llvm_unreachable("unknown relocation"); 278 } 279 } 280 281 void Hexagon::writePltHeader(uint8_t *buf) const { 282 const uint8_t pltData[] = { 283 0x00, 0x40, 0x00, 0x00, // { immext (#0) 284 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0 285 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn 286 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2 287 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1 288 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn 289 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker 290 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment 291 }; 292 memcpy(buf, pltData, sizeof(pltData)); 293 294 // Offset from PLT0 to the GOT. 295 uint64_t off = in.gotPlt->getVA() - in.plt->getVA(); 296 relocateOne(buf, R_HEX_B32_PCREL_X, off); 297 relocateOne(buf + 4, R_HEX_6_PCREL_X, off); 298 } 299 300 void Hexagon::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, 301 uint64_t pltEntryAddr, int32_t index, 302 unsigned relOff) const { 303 const uint8_t inst[] = { 304 0x00, 0x40, 0x00, 0x00, // { immext (#0) 305 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) } 306 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14) 307 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 308 }; 309 memcpy(buf, inst, sizeof(inst)); 310 311 relocateOne(buf, R_HEX_B32_PCREL_X, gotPltEntryAddr - pltEntryAddr); 312 relocateOne(buf + 4, R_HEX_6_PCREL_X, gotPltEntryAddr - pltEntryAddr); 313 } 314 315 RelType Hexagon::getDynRel(RelType type) const { 316 if (type == R_HEX_32) 317 return type; 318 return R_HEX_NONE; 319 } 320 321 TargetInfo *elf::getHexagonTargetInfo() { 322 static Hexagon target; 323 return ⌖ 324 } 325