1 //===-- Hexagon.cpp -------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "InputFiles.h" 10 #include "Symbols.h" 11 #include "SyntheticSections.h" 12 #include "Target.h" 13 #include "lld/Common/ErrorHandler.h" 14 #include "llvm/BinaryFormat/ELF.h" 15 #include "llvm/Object/ELF.h" 16 #include "llvm/Support/Endian.h" 17 18 using namespace llvm; 19 using namespace llvm::object; 20 using namespace llvm::support::endian; 21 using namespace llvm::ELF; 22 23 namespace lld { 24 namespace elf { 25 26 namespace { 27 class Hexagon final : public TargetInfo { 28 public: 29 Hexagon(); 30 uint32_t calcEFlags() const override; 31 RelExpr getRelExpr(RelType type, const Symbol &s, 32 const uint8_t *loc) const override; 33 RelType getDynRel(RelType type) const override; 34 void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override; 35 void writePltHeader(uint8_t *buf) const override; 36 void writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, uint64_t pltEntryAddr, 37 int32_t index, unsigned relOff) const override; 38 }; 39 } // namespace 40 41 Hexagon::Hexagon() { 42 pltRel = R_HEX_JMP_SLOT; 43 relativeRel = R_HEX_RELATIVE; 44 gotRel = R_HEX_GLOB_DAT; 45 symbolicRel = R_HEX_32; 46 47 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The 48 // next 3 are reserved for the dynamic loader. 49 gotPltHeaderEntriesNum = 4; 50 51 pltEntrySize = 16; 52 pltHeaderSize = 32; 53 54 // Hexagon Linux uses 64K pages by default. 55 defaultMaxPageSize = 0x10000; 56 noneRel = R_HEX_NONE; 57 } 58 59 uint32_t Hexagon::calcEFlags() const { 60 assert(!objectFiles.empty()); 61 62 // The architecture revision must always be equal to or greater than 63 // greatest revision in the list of inputs. 64 uint32_t ret = 0; 65 for (InputFile *f : objectFiles) { 66 uint32_t eflags = cast<ObjFile<ELF32LE>>(f)->getObj().getHeader()->e_flags; 67 if (eflags > ret) 68 ret = eflags; 69 } 70 return ret; 71 } 72 73 static uint32_t applyMask(uint32_t mask, uint32_t data) { 74 uint32_t result = 0; 75 size_t off = 0; 76 77 for (size_t bit = 0; bit != 32; ++bit) { 78 uint32_t valBit = (data >> off) & 1; 79 uint32_t maskBit = (mask >> bit) & 1; 80 if (maskBit) { 81 result |= (valBit << bit); 82 ++off; 83 } 84 } 85 return result; 86 } 87 88 RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s, 89 const uint8_t *loc) const { 90 switch (type) { 91 case R_HEX_NONE: 92 return R_NONE; 93 case R_HEX_6_X: 94 case R_HEX_8_X: 95 case R_HEX_9_X: 96 case R_HEX_10_X: 97 case R_HEX_11_X: 98 case R_HEX_12_X: 99 case R_HEX_16_X: 100 case R_HEX_32: 101 case R_HEX_32_6_X: 102 case R_HEX_HI16: 103 case R_HEX_LO16: 104 return R_ABS; 105 case R_HEX_B9_PCREL: 106 case R_HEX_B13_PCREL: 107 case R_HEX_B15_PCREL: 108 case R_HEX_6_PCREL_X: 109 case R_HEX_32_PCREL: 110 return R_PC; 111 case R_HEX_B9_PCREL_X: 112 case R_HEX_B15_PCREL_X: 113 case R_HEX_B22_PCREL: 114 case R_HEX_PLT_B22_PCREL: 115 case R_HEX_B22_PCREL_X: 116 case R_HEX_B32_PCREL_X: 117 return R_PLT_PC; 118 case R_HEX_GOTREL_11_X: 119 case R_HEX_GOTREL_16_X: 120 case R_HEX_GOTREL_32_6_X: 121 case R_HEX_GOTREL_HI16: 122 case R_HEX_GOTREL_LO16: 123 return R_GOTPLTREL; 124 case R_HEX_GOT_11_X: 125 case R_HEX_GOT_16_X: 126 case R_HEX_GOT_32_6_X: 127 return R_GOTPLT; 128 default: 129 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 130 ") against symbol " + toString(s)); 131 return R_NONE; 132 } 133 } 134 135 static uint32_t findMaskR6(uint32_t insn) { 136 // There are (arguably too) many relocation masks for the DSP's 137 // R_HEX_6_X type. The table below is used to select the correct mask 138 // for the given instruction. 139 struct InstructionMask { 140 uint32_t cmpMask; 141 uint32_t relocMask; 142 }; 143 144 static const InstructionMask r6[] = { 145 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f}, 146 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80}, 147 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0}, 148 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0}, 149 {0x44000000, 0x000020f8}, {0x45000000, 0x000007e0}, 150 {0x46000000, 0x000020f8}, {0x47000000, 0x000007e0}, 151 {0x6a000000, 0x00001f80}, {0x7c000000, 0x001f2000}, 152 {0x9a000000, 0x00000f60}, {0x9b000000, 0x00000f60}, 153 {0x9c000000, 0x00000f60}, {0x9d000000, 0x00000f60}, 154 {0x9f000000, 0x001f0100}, {0xab000000, 0x0000003f}, 155 {0xad000000, 0x0000003f}, {0xaf000000, 0x00030078}, 156 {0xd7000000, 0x006020e0}, {0xd8000000, 0x006020e0}, 157 {0xdb000000, 0x006020e0}, {0xdf000000, 0x006020e0}}; 158 159 // Duplex forms have a fixed mask and parse bits 15:14 are always 160 // zero. Non-duplex insns will always have at least one bit set in the 161 // parse field. 162 if ((0xC000 & insn) == 0x0) 163 return 0x03f00000; 164 165 for (InstructionMask i : r6) 166 if ((0xff000000 & insn) == i.cmpMask) 167 return i.relocMask; 168 169 error("unrecognized instruction for R_HEX_6 relocation: 0x" + 170 utohexstr(insn)); 171 return 0; 172 } 173 174 static uint32_t findMaskR8(uint32_t insn) { 175 if ((0xff000000 & insn) == 0xde000000) 176 return 0x00e020e8; 177 if ((0xff000000 & insn) == 0x3c000000) 178 return 0x0000207f; 179 return 0x00001fe0; 180 } 181 182 static uint32_t findMaskR11(uint32_t insn) { 183 if ((0xff000000 & insn) == 0xa1000000) 184 return 0x060020ff; 185 return 0x06003fe0; 186 } 187 188 static uint32_t findMaskR16(uint32_t insn) { 189 if ((0xff000000 & insn) == 0x48000000) 190 return 0x061f20ff; 191 if ((0xff000000 & insn) == 0x49000000) 192 return 0x061f3fe0; 193 if ((0xff000000 & insn) == 0x78000000) 194 return 0x00df3fe0; 195 if ((0xff000000 & insn) == 0xb0000000) 196 return 0x0fe03fe0; 197 198 error("unrecognized instruction for R_HEX_16_X relocation: 0x" + 199 utohexstr(insn)); 200 return 0; 201 } 202 203 static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); } 204 205 void Hexagon::relocateOne(uint8_t *loc, RelType type, uint64_t val) const { 206 switch (type) { 207 case R_HEX_NONE: 208 break; 209 case R_HEX_6_PCREL_X: 210 case R_HEX_6_X: 211 or32le(loc, applyMask(findMaskR6(read32le(loc)), val)); 212 break; 213 case R_HEX_8_X: 214 or32le(loc, applyMask(findMaskR8(read32le(loc)), val)); 215 break; 216 case R_HEX_9_X: 217 or32le(loc, applyMask(0x00003fe0, val & 0x3f)); 218 break; 219 case R_HEX_10_X: 220 or32le(loc, applyMask(0x00203fe0, val & 0x3f)); 221 break; 222 case R_HEX_11_X: 223 case R_HEX_GOT_11_X: 224 case R_HEX_GOTREL_11_X: 225 or32le(loc, applyMask(findMaskR11(read32le(loc)), val & 0x3f)); 226 break; 227 case R_HEX_12_X: 228 or32le(loc, applyMask(0x000007e0, val)); 229 break; 230 case R_HEX_16_X: // These relocs only have 6 effective bits. 231 case R_HEX_GOT_16_X: 232 case R_HEX_GOTREL_16_X: 233 or32le(loc, applyMask(findMaskR16(read32le(loc)), val & 0x3f)); 234 break; 235 case R_HEX_32: 236 case R_HEX_32_PCREL: 237 or32le(loc, val); 238 break; 239 case R_HEX_32_6_X: 240 case R_HEX_GOT_32_6_X: 241 case R_HEX_GOTREL_32_6_X: 242 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 243 break; 244 case R_HEX_B9_PCREL: 245 checkInt(loc, val, 11, type); 246 or32le(loc, applyMask(0x003000fe, val >> 2)); 247 break; 248 case R_HEX_B9_PCREL_X: 249 or32le(loc, applyMask(0x003000fe, val & 0x3f)); 250 break; 251 case R_HEX_B13_PCREL: 252 checkInt(loc, val, 15, type); 253 or32le(loc, applyMask(0x00202ffe, val >> 2)); 254 break; 255 case R_HEX_B15_PCREL: 256 checkInt(loc, val, 17, type); 257 or32le(loc, applyMask(0x00df20fe, val >> 2)); 258 break; 259 case R_HEX_B15_PCREL_X: 260 or32le(loc, applyMask(0x00df20fe, val & 0x3f)); 261 break; 262 case R_HEX_B22_PCREL: 263 case R_HEX_PLT_B22_PCREL: 264 checkInt(loc, val, 22, type); 265 or32le(loc, applyMask(0x1ff3ffe, val >> 2)); 266 break; 267 case R_HEX_B22_PCREL_X: 268 or32le(loc, applyMask(0x1ff3ffe, val & 0x3f)); 269 break; 270 case R_HEX_B32_PCREL_X: 271 or32le(loc, applyMask(0x0fff3fff, val >> 6)); 272 break; 273 case R_HEX_GOTREL_HI16: 274 case R_HEX_HI16: 275 or32le(loc, applyMask(0x00c03fff, val >> 16)); 276 break; 277 case R_HEX_GOTREL_LO16: 278 case R_HEX_LO16: 279 or32le(loc, applyMask(0x00c03fff, val)); 280 break; 281 default: 282 llvm_unreachable("unknown relocation"); 283 } 284 } 285 286 void Hexagon::writePltHeader(uint8_t *buf) const { 287 const uint8_t pltData[] = { 288 0x00, 0x40, 0x00, 0x00, // { immext (#0) 289 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0 290 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn 291 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2 292 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1 293 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn 294 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker 295 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment 296 }; 297 memcpy(buf, pltData, sizeof(pltData)); 298 299 // Offset from PLT0 to the GOT. 300 uint64_t off = in.gotPlt->getVA() - in.plt->getVA(); 301 relocateOne(buf, R_HEX_B32_PCREL_X, off); 302 relocateOne(buf + 4, R_HEX_6_PCREL_X, off); 303 } 304 305 void Hexagon::writePlt(uint8_t *buf, uint64_t gotPltEntryAddr, 306 uint64_t pltEntryAddr, int32_t index, 307 unsigned relOff) const { 308 const uint8_t inst[] = { 309 0x00, 0x40, 0x00, 0x00, // { immext (#0) 310 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) } 311 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14) 312 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 313 }; 314 memcpy(buf, inst, sizeof(inst)); 315 316 relocateOne(buf, R_HEX_B32_PCREL_X, gotPltEntryAddr - pltEntryAddr); 317 relocateOne(buf + 4, R_HEX_6_PCREL_X, gotPltEntryAddr - pltEntryAddr); 318 } 319 320 RelType Hexagon::getDynRel(RelType type) const { 321 if (type == R_HEX_32) 322 return type; 323 return R_HEX_NONE; 324 } 325 326 TargetInfo *getHexagonTargetInfo() { 327 static Hexagon target; 328 return ⌖ 329 } 330 331 } // namespace elf 332 } // namespace lld 333