1 //===- AArch64.cpp --------------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "Symbols.h" 10 #include "SyntheticSections.h" 11 #include "Target.h" 12 #include "Thunks.h" 13 #include "lld/Common/ErrorHandler.h" 14 #include "llvm/Object/ELF.h" 15 #include "llvm/Support/Endian.h" 16 17 using namespace llvm; 18 using namespace llvm::support::endian; 19 using namespace llvm::ELF; 20 using namespace lld; 21 using namespace lld::elf; 22 23 // Page(Expr) is the page address of the expression Expr, defined 24 // as (Expr & ~0xFFF). (This applies even if the machine page size 25 // supported by the platform has a different value.) 26 uint64_t elf::getAArch64Page(uint64_t expr) { 27 return expr & ~static_cast<uint64_t>(0xFFF); 28 } 29 30 namespace { 31 class AArch64 : public TargetInfo { 32 public: 33 AArch64(); 34 RelExpr getRelExpr(RelType type, const Symbol &s, 35 const uint8_t *loc) const override; 36 RelType getDynRel(RelType type) const override; 37 void writeGotPlt(uint8_t *buf, const Symbol &s) const override; 38 void writePltHeader(uint8_t *buf) const override; 39 void writePlt(uint8_t *buf, const Symbol &sym, 40 uint64_t pltEntryAddr) const override; 41 bool needsThunk(RelExpr expr, RelType type, const InputFile *file, 42 uint64_t branchAddr, const Symbol &s, 43 int64_t a) const override; 44 uint32_t getThunkSectionSpacing() const override; 45 bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override; 46 bool usesOnlyLowPageBits(RelType type) const override; 47 void relocate(uint8_t *loc, const Relocation &rel, 48 uint64_t val) const override; 49 RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override; 50 void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, 51 uint64_t val) const override; 52 void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, 53 uint64_t val) const override; 54 void relaxTlsIeToLe(uint8_t *loc, const Relocation &rel, 55 uint64_t val) const override; 56 }; 57 } // namespace 58 59 AArch64::AArch64() { 60 copyRel = R_AARCH64_COPY; 61 relativeRel = R_AARCH64_RELATIVE; 62 iRelativeRel = R_AARCH64_IRELATIVE; 63 gotRel = R_AARCH64_GLOB_DAT; 64 noneRel = R_AARCH64_NONE; 65 pltRel = R_AARCH64_JUMP_SLOT; 66 symbolicRel = R_AARCH64_ABS64; 67 tlsDescRel = R_AARCH64_TLSDESC; 68 tlsGotRel = R_AARCH64_TLS_TPREL64; 69 pltHeaderSize = 32; 70 pltEntrySize = 16; 71 ipltEntrySize = 16; 72 defaultMaxPageSize = 65536; 73 74 // Align to the 2 MiB page size (known as a superpage or huge page). 75 // FreeBSD automatically promotes 2 MiB-aligned allocations. 76 defaultImageBase = 0x200000; 77 78 needsThunks = true; 79 } 80 81 RelExpr AArch64::getRelExpr(RelType type, const Symbol &s, 82 const uint8_t *loc) const { 83 switch (type) { 84 case R_AARCH64_ABS16: 85 case R_AARCH64_ABS32: 86 case R_AARCH64_ABS64: 87 case R_AARCH64_ADD_ABS_LO12_NC: 88 case R_AARCH64_LDST128_ABS_LO12_NC: 89 case R_AARCH64_LDST16_ABS_LO12_NC: 90 case R_AARCH64_LDST32_ABS_LO12_NC: 91 case R_AARCH64_LDST64_ABS_LO12_NC: 92 case R_AARCH64_LDST8_ABS_LO12_NC: 93 case R_AARCH64_MOVW_SABS_G0: 94 case R_AARCH64_MOVW_SABS_G1: 95 case R_AARCH64_MOVW_SABS_G2: 96 case R_AARCH64_MOVW_UABS_G0: 97 case R_AARCH64_MOVW_UABS_G0_NC: 98 case R_AARCH64_MOVW_UABS_G1: 99 case R_AARCH64_MOVW_UABS_G1_NC: 100 case R_AARCH64_MOVW_UABS_G2: 101 case R_AARCH64_MOVW_UABS_G2_NC: 102 case R_AARCH64_MOVW_UABS_G3: 103 return R_ABS; 104 case R_AARCH64_TLSDESC_ADR_PAGE21: 105 return R_AARCH64_TLSDESC_PAGE; 106 case R_AARCH64_TLSDESC_LD64_LO12: 107 case R_AARCH64_TLSDESC_ADD_LO12: 108 return R_TLSDESC; 109 case R_AARCH64_TLSDESC_CALL: 110 return R_TLSDESC_CALL; 111 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 112 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 113 case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC: 114 case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC: 115 case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC: 116 case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC: 117 case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC: 118 case R_AARCH64_TLSLE_MOVW_TPREL_G0: 119 case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: 120 case R_AARCH64_TLSLE_MOVW_TPREL_G1: 121 case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC: 122 case R_AARCH64_TLSLE_MOVW_TPREL_G2: 123 return R_TLS; 124 case R_AARCH64_CALL26: 125 case R_AARCH64_CONDBR19: 126 case R_AARCH64_JUMP26: 127 case R_AARCH64_TSTBR14: 128 case R_AARCH64_PLT32: 129 return R_PLT_PC; 130 case R_AARCH64_PREL16: 131 case R_AARCH64_PREL32: 132 case R_AARCH64_PREL64: 133 case R_AARCH64_ADR_PREL_LO21: 134 case R_AARCH64_LD_PREL_LO19: 135 case R_AARCH64_MOVW_PREL_G0: 136 case R_AARCH64_MOVW_PREL_G0_NC: 137 case R_AARCH64_MOVW_PREL_G1: 138 case R_AARCH64_MOVW_PREL_G1_NC: 139 case R_AARCH64_MOVW_PREL_G2: 140 case R_AARCH64_MOVW_PREL_G2_NC: 141 case R_AARCH64_MOVW_PREL_G3: 142 return R_PC; 143 case R_AARCH64_ADR_PREL_PG_HI21: 144 case R_AARCH64_ADR_PREL_PG_HI21_NC: 145 return R_AARCH64_PAGE_PC; 146 case R_AARCH64_LD64_GOT_LO12_NC: 147 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 148 return R_GOT; 149 case R_AARCH64_ADR_GOT_PAGE: 150 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 151 return R_AARCH64_GOT_PAGE_PC; 152 case R_AARCH64_NONE: 153 return R_NONE; 154 default: 155 error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) + 156 ") against symbol " + toString(s)); 157 return R_NONE; 158 } 159 } 160 161 RelExpr AArch64::adjustTlsExpr(RelType type, RelExpr expr) const { 162 if (expr == R_RELAX_TLS_GD_TO_IE) { 163 if (type == R_AARCH64_TLSDESC_ADR_PAGE21) 164 return R_AARCH64_RELAX_TLS_GD_TO_IE_PAGE_PC; 165 return R_RELAX_TLS_GD_TO_IE_ABS; 166 } 167 return expr; 168 } 169 170 bool AArch64::usesOnlyLowPageBits(RelType type) const { 171 switch (type) { 172 default: 173 return false; 174 case R_AARCH64_ADD_ABS_LO12_NC: 175 case R_AARCH64_LD64_GOT_LO12_NC: 176 case R_AARCH64_LDST128_ABS_LO12_NC: 177 case R_AARCH64_LDST16_ABS_LO12_NC: 178 case R_AARCH64_LDST32_ABS_LO12_NC: 179 case R_AARCH64_LDST64_ABS_LO12_NC: 180 case R_AARCH64_LDST8_ABS_LO12_NC: 181 case R_AARCH64_TLSDESC_ADD_LO12: 182 case R_AARCH64_TLSDESC_LD64_LO12: 183 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 184 return true; 185 } 186 } 187 188 RelType AArch64::getDynRel(RelType type) const { 189 if (type == R_AARCH64_ABS64) 190 return type; 191 return R_AARCH64_NONE; 192 } 193 194 void AArch64::writeGotPlt(uint8_t *buf, const Symbol &) const { 195 write64le(buf, in.plt->getVA()); 196 } 197 198 void AArch64::writePltHeader(uint8_t *buf) const { 199 const uint8_t pltData[] = { 200 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 201 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 202 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 203 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 204 0x20, 0x02, 0x1f, 0xd6, // br x17 205 0x1f, 0x20, 0x03, 0xd5, // nop 206 0x1f, 0x20, 0x03, 0xd5, // nop 207 0x1f, 0x20, 0x03, 0xd5 // nop 208 }; 209 memcpy(buf, pltData, sizeof(pltData)); 210 211 uint64_t got = in.gotPlt->getVA(); 212 uint64_t plt = in.plt->getVA(); 213 relocateNoSym(buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 214 getAArch64Page(got + 16) - getAArch64Page(plt + 4)); 215 relocateNoSym(buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, got + 16); 216 relocateNoSym(buf + 12, R_AARCH64_ADD_ABS_LO12_NC, got + 16); 217 } 218 219 void AArch64::writePlt(uint8_t *buf, const Symbol &sym, 220 uint64_t pltEntryAddr) const { 221 const uint8_t inst[] = { 222 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 223 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 224 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[n])) 225 0x20, 0x02, 0x1f, 0xd6 // br x17 226 }; 227 memcpy(buf, inst, sizeof(inst)); 228 229 uint64_t gotPltEntryAddr = sym.getGotPltVA(); 230 relocateNoSym(buf, R_AARCH64_ADR_PREL_PG_HI21, 231 getAArch64Page(gotPltEntryAddr) - getAArch64Page(pltEntryAddr)); 232 relocateNoSym(buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, gotPltEntryAddr); 233 relocateNoSym(buf + 8, R_AARCH64_ADD_ABS_LO12_NC, gotPltEntryAddr); 234 } 235 236 bool AArch64::needsThunk(RelExpr expr, RelType type, const InputFile *file, 237 uint64_t branchAddr, const Symbol &s, 238 int64_t a) const { 239 // If s is an undefined weak symbol and does not have a PLT entry then it 240 // will be resolved as a branch to the next instruction. 241 if (s.isUndefWeak() && !s.isInPlt()) 242 return false; 243 // ELF for the ARM 64-bit architecture, section Call and Jump relocations 244 // only permits range extension thunks for R_AARCH64_CALL26 and 245 // R_AARCH64_JUMP26 relocation types. 246 if (type != R_AARCH64_CALL26 && type != R_AARCH64_JUMP26 && 247 type != R_AARCH64_PLT32) 248 return false; 249 uint64_t dst = expr == R_PLT_PC ? s.getPltVA() : s.getVA(a); 250 return !inBranchRange(type, branchAddr, dst); 251 } 252 253 uint32_t AArch64::getThunkSectionSpacing() const { 254 // See comment in Arch/ARM.cpp for a more detailed explanation of 255 // getThunkSectionSpacing(). For AArch64 the only branches we are permitted to 256 // Thunk have a range of +/- 128 MiB 257 return (128 * 1024 * 1024) - 0x30000; 258 } 259 260 bool AArch64::inBranchRange(RelType type, uint64_t src, uint64_t dst) const { 261 if (type != R_AARCH64_CALL26 && type != R_AARCH64_JUMP26 && 262 type != R_AARCH64_PLT32) 263 return true; 264 // The AArch64 call and unconditional branch instructions have a range of 265 // +/- 128 MiB. The PLT32 relocation supports a range up to +/- 2 GiB. 266 uint64_t range = 267 type == R_AARCH64_PLT32 ? (UINT64_C(1) << 31) : (128 * 1024 * 1024); 268 if (dst > src) { 269 // Immediate of branch is signed. 270 range -= 4; 271 return dst - src <= range; 272 } 273 return src - dst <= range; 274 } 275 276 static void write32AArch64Addr(uint8_t *l, uint64_t imm) { 277 uint32_t immLo = (imm & 0x3) << 29; 278 uint32_t immHi = (imm & 0x1FFFFC) << 3; 279 uint64_t mask = (0x3 << 29) | (0x1FFFFC << 3); 280 write32le(l, (read32le(l) & ~mask) | immLo | immHi); 281 } 282 283 // Return the bits [Start, End] from Val shifted Start bits. 284 // For instance, getBits(0xF0, 4, 8) returns 0xF. 285 static uint64_t getBits(uint64_t val, int start, int end) { 286 uint64_t mask = ((uint64_t)1 << (end + 1 - start)) - 1; 287 return (val >> start) & mask; 288 } 289 290 static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); } 291 292 // Update the immediate field in a AARCH64 ldr, str, and add instruction. 293 static void or32AArch64Imm(uint8_t *l, uint64_t imm) { 294 or32le(l, (imm & 0xFFF) << 10); 295 } 296 297 // Update the immediate field in an AArch64 movk, movn or movz instruction 298 // for a signed relocation, and update the opcode of a movn or movz instruction 299 // to match the sign of the operand. 300 static void writeSMovWImm(uint8_t *loc, uint32_t imm) { 301 uint32_t inst = read32le(loc); 302 // Opcode field is bits 30, 29, with 10 = movz, 00 = movn and 11 = movk. 303 if (!(inst & (1 << 29))) { 304 // movn or movz. 305 if (imm & 0x10000) { 306 // Change opcode to movn, which takes an inverted operand. 307 imm ^= 0xFFFF; 308 inst &= ~(1 << 30); 309 } else { 310 // Change opcode to movz. 311 inst |= 1 << 30; 312 } 313 } 314 write32le(loc, inst | ((imm & 0xFFFF) << 5)); 315 } 316 317 void AArch64::relocate(uint8_t *loc, const Relocation &rel, 318 uint64_t val) const { 319 switch (rel.type) { 320 case R_AARCH64_ABS16: 321 case R_AARCH64_PREL16: 322 checkIntUInt(loc, val, 16, rel); 323 write16le(loc, val); 324 break; 325 case R_AARCH64_ABS32: 326 case R_AARCH64_PREL32: 327 checkIntUInt(loc, val, 32, rel); 328 write32le(loc, val); 329 break; 330 case R_AARCH64_PLT32: 331 checkInt(loc, val, 32, rel); 332 write32le(loc, val); 333 break; 334 case R_AARCH64_ABS64: 335 case R_AARCH64_PREL64: 336 write64le(loc, val); 337 break; 338 case R_AARCH64_ADD_ABS_LO12_NC: 339 or32AArch64Imm(loc, val); 340 break; 341 case R_AARCH64_ADR_GOT_PAGE: 342 case R_AARCH64_ADR_PREL_PG_HI21: 343 case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: 344 case R_AARCH64_TLSDESC_ADR_PAGE21: 345 checkInt(loc, val, 33, rel); 346 LLVM_FALLTHROUGH; 347 case R_AARCH64_ADR_PREL_PG_HI21_NC: 348 write32AArch64Addr(loc, val >> 12); 349 break; 350 case R_AARCH64_ADR_PREL_LO21: 351 checkInt(loc, val, 21, rel); 352 write32AArch64Addr(loc, val); 353 break; 354 case R_AARCH64_JUMP26: 355 // Normally we would just write the bits of the immediate field, however 356 // when patching instructions for the cpu errata fix -fix-cortex-a53-843419 357 // we want to replace a non-branch instruction with a branch immediate 358 // instruction. By writing all the bits of the instruction including the 359 // opcode and the immediate (0 001 | 01 imm26) we can do this 360 // transformation by placing a R_AARCH64_JUMP26 relocation at the offset of 361 // the instruction we want to patch. 362 write32le(loc, 0x14000000); 363 LLVM_FALLTHROUGH; 364 case R_AARCH64_CALL26: 365 checkInt(loc, val, 28, rel); 366 or32le(loc, (val & 0x0FFFFFFC) >> 2); 367 break; 368 case R_AARCH64_CONDBR19: 369 case R_AARCH64_LD_PREL_LO19: 370 checkAlignment(loc, val, 4, rel); 371 checkInt(loc, val, 21, rel); 372 or32le(loc, (val & 0x1FFFFC) << 3); 373 break; 374 case R_AARCH64_LDST8_ABS_LO12_NC: 375 case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC: 376 or32AArch64Imm(loc, getBits(val, 0, 11)); 377 break; 378 case R_AARCH64_LDST16_ABS_LO12_NC: 379 case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC: 380 checkAlignment(loc, val, 2, rel); 381 or32AArch64Imm(loc, getBits(val, 1, 11)); 382 break; 383 case R_AARCH64_LDST32_ABS_LO12_NC: 384 case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC: 385 checkAlignment(loc, val, 4, rel); 386 or32AArch64Imm(loc, getBits(val, 2, 11)); 387 break; 388 case R_AARCH64_LDST64_ABS_LO12_NC: 389 case R_AARCH64_LD64_GOT_LO12_NC: 390 case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: 391 case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC: 392 case R_AARCH64_TLSDESC_LD64_LO12: 393 checkAlignment(loc, val, 8, rel); 394 or32AArch64Imm(loc, getBits(val, 3, 11)); 395 break; 396 case R_AARCH64_LDST128_ABS_LO12_NC: 397 case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC: 398 checkAlignment(loc, val, 16, rel); 399 or32AArch64Imm(loc, getBits(val, 4, 11)); 400 break; 401 case R_AARCH64_MOVW_UABS_G0: 402 checkUInt(loc, val, 16, rel); 403 LLVM_FALLTHROUGH; 404 case R_AARCH64_MOVW_UABS_G0_NC: 405 or32le(loc, (val & 0xFFFF) << 5); 406 break; 407 case R_AARCH64_MOVW_UABS_G1: 408 checkUInt(loc, val, 32, rel); 409 LLVM_FALLTHROUGH; 410 case R_AARCH64_MOVW_UABS_G1_NC: 411 or32le(loc, (val & 0xFFFF0000) >> 11); 412 break; 413 case R_AARCH64_MOVW_UABS_G2: 414 checkUInt(loc, val, 48, rel); 415 LLVM_FALLTHROUGH; 416 case R_AARCH64_MOVW_UABS_G2_NC: 417 or32le(loc, (val & 0xFFFF00000000) >> 27); 418 break; 419 case R_AARCH64_MOVW_UABS_G3: 420 or32le(loc, (val & 0xFFFF000000000000) >> 43); 421 break; 422 case R_AARCH64_MOVW_PREL_G0: 423 case R_AARCH64_MOVW_SABS_G0: 424 case R_AARCH64_TLSLE_MOVW_TPREL_G0: 425 checkInt(loc, val, 17, rel); 426 LLVM_FALLTHROUGH; 427 case R_AARCH64_MOVW_PREL_G0_NC: 428 case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: 429 writeSMovWImm(loc, val); 430 break; 431 case R_AARCH64_MOVW_PREL_G1: 432 case R_AARCH64_MOVW_SABS_G1: 433 case R_AARCH64_TLSLE_MOVW_TPREL_G1: 434 checkInt(loc, val, 33, rel); 435 LLVM_FALLTHROUGH; 436 case R_AARCH64_MOVW_PREL_G1_NC: 437 case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC: 438 writeSMovWImm(loc, val >> 16); 439 break; 440 case R_AARCH64_MOVW_PREL_G2: 441 case R_AARCH64_MOVW_SABS_G2: 442 case R_AARCH64_TLSLE_MOVW_TPREL_G2: 443 checkInt(loc, val, 49, rel); 444 LLVM_FALLTHROUGH; 445 case R_AARCH64_MOVW_PREL_G2_NC: 446 writeSMovWImm(loc, val >> 32); 447 break; 448 case R_AARCH64_MOVW_PREL_G3: 449 writeSMovWImm(loc, val >> 48); 450 break; 451 case R_AARCH64_TSTBR14: 452 checkInt(loc, val, 16, rel); 453 or32le(loc, (val & 0xFFFC) << 3); 454 break; 455 case R_AARCH64_TLSLE_ADD_TPREL_HI12: 456 checkUInt(loc, val, 24, rel); 457 or32AArch64Imm(loc, val >> 12); 458 break; 459 case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC: 460 case R_AARCH64_TLSDESC_ADD_LO12: 461 or32AArch64Imm(loc, val); 462 break; 463 default: 464 llvm_unreachable("unknown relocation"); 465 } 466 } 467 468 void AArch64::relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, 469 uint64_t val) const { 470 // TLSDESC Global-Dynamic relocation are in the form: 471 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 472 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12] 473 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12] 474 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 475 // blr x1 476 // And it can optimized to: 477 // movz x0, #0x0, lsl #16 478 // movk x0, #0x10 479 // nop 480 // nop 481 checkUInt(loc, val, 32, rel); 482 483 switch (rel.type) { 484 case R_AARCH64_TLSDESC_ADD_LO12: 485 case R_AARCH64_TLSDESC_CALL: 486 write32le(loc, 0xd503201f); // nop 487 return; 488 case R_AARCH64_TLSDESC_ADR_PAGE21: 489 write32le(loc, 0xd2a00000 | (((val >> 16) & 0xffff) << 5)); // movz 490 return; 491 case R_AARCH64_TLSDESC_LD64_LO12: 492 write32le(loc, 0xf2800000 | ((val & 0xffff) << 5)); // movk 493 return; 494 default: 495 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 496 } 497 } 498 499 void AArch64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, 500 uint64_t val) const { 501 // TLSDESC Global-Dynamic relocation are in the form: 502 // adrp x0, :tlsdesc:v [R_AARCH64_TLSDESC_ADR_PAGE21] 503 // ldr x1, [x0, #:tlsdesc_lo12:v [R_AARCH64_TLSDESC_LD64_LO12] 504 // add x0, x0, :tlsdesc_los:v [R_AARCH64_TLSDESC_ADD_LO12] 505 // .tlsdesccall [R_AARCH64_TLSDESC_CALL] 506 // blr x1 507 // And it can optimized to: 508 // adrp x0, :gottprel:v 509 // ldr x0, [x0, :gottprel_lo12:v] 510 // nop 511 // nop 512 513 switch (rel.type) { 514 case R_AARCH64_TLSDESC_ADD_LO12: 515 case R_AARCH64_TLSDESC_CALL: 516 write32le(loc, 0xd503201f); // nop 517 break; 518 case R_AARCH64_TLSDESC_ADR_PAGE21: 519 write32le(loc, 0x90000000); // adrp 520 relocateNoSym(loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, val); 521 break; 522 case R_AARCH64_TLSDESC_LD64_LO12: 523 write32le(loc, 0xf9400000); // ldr 524 relocateNoSym(loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, val); 525 break; 526 default: 527 llvm_unreachable("unsupported relocation for TLS GD to LE relaxation"); 528 } 529 } 530 531 void AArch64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel, 532 uint64_t val) const { 533 checkUInt(loc, val, 32, rel); 534 535 if (rel.type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) { 536 // Generate MOVZ. 537 uint32_t regNo = read32le(loc) & 0x1f; 538 write32le(loc, (0xd2a00000 | regNo) | (((val >> 16) & 0xffff) << 5)); 539 return; 540 } 541 if (rel.type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) { 542 // Generate MOVK. 543 uint32_t regNo = read32le(loc) & 0x1f; 544 write32le(loc, (0xf2800000 | regNo) | ((val & 0xffff) << 5)); 545 return; 546 } 547 llvm_unreachable("invalid relocation for TLS IE to LE relaxation"); 548 } 549 550 // AArch64 may use security features in variant PLT sequences. These are: 551 // Pointer Authentication (PAC), introduced in armv8.3-a and Branch Target 552 // Indicator (BTI) introduced in armv8.5-a. The additional instructions used 553 // in the variant Plt sequences are encoded in the Hint space so they can be 554 // deployed on older architectures, which treat the instructions as a nop. 555 // PAC and BTI can be combined leading to the following combinations: 556 // writePltHeader 557 // writePltHeaderBti (no PAC Header needed) 558 // writePlt 559 // writePltBti (BTI only) 560 // writePltPac (PAC only) 561 // writePltBtiPac (BTI and PAC) 562 // 563 // When PAC is enabled the dynamic loader encrypts the address that it places 564 // in the .got.plt using the pacia1716 instruction which encrypts the value in 565 // x17 using the modifier in x16. The static linker places autia1716 before the 566 // indirect branch to x17 to authenticate the address in x17 with the modifier 567 // in x16. This makes it more difficult for an attacker to modify the value in 568 // the .got.plt. 569 // 570 // When BTI is enabled all indirect branches must land on a bti instruction. 571 // The static linker must place a bti instruction at the start of any PLT entry 572 // that may be the target of an indirect branch. As the PLT entries call the 573 // lazy resolver indirectly this must have a bti instruction at start. In 574 // general a bti instruction is not needed for a PLT entry as indirect calls 575 // are resolved to the function address and not the PLT entry for the function. 576 // There are a small number of cases where the PLT address can escape, such as 577 // taking the address of a function or ifunc via a non got-generating 578 // relocation, and a shared library refers to that symbol. 579 // 580 // We use the bti c variant of the instruction which permits indirect branches 581 // (br) via x16/x17 and indirect function calls (blr) via any register. The ABI 582 // guarantees that all indirect branches from code requiring BTI protection 583 // will go via x16/x17 584 585 namespace { 586 class AArch64BtiPac final : public AArch64 { 587 public: 588 AArch64BtiPac(); 589 void writePltHeader(uint8_t *buf) const override; 590 void writePlt(uint8_t *buf, const Symbol &sym, 591 uint64_t pltEntryAddr) const override; 592 593 private: 594 bool btiHeader; // bti instruction needed in PLT Header 595 bool btiEntry; // bti instruction needed in PLT Entry 596 bool pacEntry; // autia1716 instruction needed in PLT Entry 597 }; 598 } // namespace 599 600 AArch64BtiPac::AArch64BtiPac() { 601 btiHeader = (config->andFeatures & GNU_PROPERTY_AARCH64_FEATURE_1_BTI); 602 // A BTI (Branch Target Indicator) Plt Entry is only required if the 603 // address of the PLT entry can be taken by the program, which permits an 604 // indirect jump to the PLT entry. This can happen when the address 605 // of the PLT entry for a function is canonicalised due to the address of 606 // the function in an executable being taken by a shared library. 607 // FIXME: There is a potential optimization to omit the BTI if we detect 608 // that the address of the PLT entry isn't taken. 609 // The PAC PLT entries require dynamic loader support and this isn't known 610 // from properties in the objects, so we use the command line flag. 611 btiEntry = btiHeader && !config->shared; 612 pacEntry = config->zPacPlt; 613 614 if (btiEntry || pacEntry) { 615 pltEntrySize = 24; 616 ipltEntrySize = 24; 617 } 618 } 619 620 void AArch64BtiPac::writePltHeader(uint8_t *buf) const { 621 const uint8_t btiData[] = { 0x5f, 0x24, 0x03, 0xd5 }; // bti c 622 const uint8_t pltData[] = { 623 0xf0, 0x7b, 0xbf, 0xa9, // stp x16, x30, [sp,#-16]! 624 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[2])) 625 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[2]))] 626 0x10, 0x02, 0x00, 0x91, // add x16, x16, Offset(&(.plt.got[2])) 627 0x20, 0x02, 0x1f, 0xd6, // br x17 628 0x1f, 0x20, 0x03, 0xd5, // nop 629 0x1f, 0x20, 0x03, 0xd5 // nop 630 }; 631 const uint8_t nopData[] = { 0x1f, 0x20, 0x03, 0xd5 }; // nop 632 633 uint64_t got = in.gotPlt->getVA(); 634 uint64_t plt = in.plt->getVA(); 635 636 if (btiHeader) { 637 // PltHeader is called indirectly by plt[N]. Prefix pltData with a BTI C 638 // instruction. 639 memcpy(buf, btiData, sizeof(btiData)); 640 buf += sizeof(btiData); 641 plt += sizeof(btiData); 642 } 643 memcpy(buf, pltData, sizeof(pltData)); 644 645 relocateNoSym(buf + 4, R_AARCH64_ADR_PREL_PG_HI21, 646 getAArch64Page(got + 16) - getAArch64Page(plt + 8)); 647 relocateNoSym(buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, got + 16); 648 relocateNoSym(buf + 12, R_AARCH64_ADD_ABS_LO12_NC, got + 16); 649 if (!btiHeader) 650 // We didn't add the BTI c instruction so round out size with NOP. 651 memcpy(buf + sizeof(pltData), nopData, sizeof(nopData)); 652 } 653 654 void AArch64BtiPac::writePlt(uint8_t *buf, const Symbol &sym, 655 uint64_t pltEntryAddr) const { 656 // The PLT entry is of the form: 657 // [btiData] addrInst (pacBr | stdBr) [nopData] 658 const uint8_t btiData[] = { 0x5f, 0x24, 0x03, 0xd5 }; // bti c 659 const uint8_t addrInst[] = { 660 0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n])) 661 0x11, 0x02, 0x40, 0xf9, // ldr x17, [x16, Offset(&(.plt.got[n]))] 662 0x10, 0x02, 0x00, 0x91 // add x16, x16, Offset(&(.plt.got[n])) 663 }; 664 const uint8_t pacBr[] = { 665 0x9f, 0x21, 0x03, 0xd5, // autia1716 666 0x20, 0x02, 0x1f, 0xd6 // br x17 667 }; 668 const uint8_t stdBr[] = { 669 0x20, 0x02, 0x1f, 0xd6, // br x17 670 0x1f, 0x20, 0x03, 0xd5 // nop 671 }; 672 const uint8_t nopData[] = { 0x1f, 0x20, 0x03, 0xd5 }; // nop 673 674 if (btiEntry) { 675 memcpy(buf, btiData, sizeof(btiData)); 676 buf += sizeof(btiData); 677 pltEntryAddr += sizeof(btiData); 678 } 679 680 uint64_t gotPltEntryAddr = sym.getGotPltVA(); 681 memcpy(buf, addrInst, sizeof(addrInst)); 682 relocateNoSym(buf, R_AARCH64_ADR_PREL_PG_HI21, 683 getAArch64Page(gotPltEntryAddr) - getAArch64Page(pltEntryAddr)); 684 relocateNoSym(buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, gotPltEntryAddr); 685 relocateNoSym(buf + 8, R_AARCH64_ADD_ABS_LO12_NC, gotPltEntryAddr); 686 687 if (pacEntry) 688 memcpy(buf + sizeof(addrInst), pacBr, sizeof(pacBr)); 689 else 690 memcpy(buf + sizeof(addrInst), stdBr, sizeof(stdBr)); 691 if (!btiEntry) 692 // We didn't add the BTI c instruction so round out size with NOP. 693 memcpy(buf + sizeof(addrInst) + sizeof(stdBr), nopData, sizeof(nopData)); 694 } 695 696 static TargetInfo *getTargetInfo() { 697 if (config->andFeatures & (GNU_PROPERTY_AARCH64_FEATURE_1_BTI | 698 GNU_PROPERTY_AARCH64_FEATURE_1_PAC)) { 699 static AArch64BtiPac t; 700 return &t; 701 } 702 static AArch64 t; 703 return &t; 704 } 705 706 TargetInfo *elf::getAArch64TargetInfo() { return getTargetInfo(); } 707