1 /* ===-- clear_cache.c - Implement __clear_cache ---------------------------=== 2 * 3 * The LLVM Compiler Infrastructure 4 * 5 * This file is dual licensed under the MIT and the University of Illinois Open 6 * Source Licenses. See LICENSE.TXT for details. 7 * 8 * ===----------------------------------------------------------------------=== 9 */ 10 11 #include "int_lib.h" 12 #include <assert.h> 13 #include <stddef.h> 14 15 #if __APPLE__ 16 #include <libkern/OSCacheControl.h> 17 #endif 18 19 #if defined(_WIN32) 20 /* Forward declare Win32 APIs since the GCC mode driver does not handle the 21 newer SDKs as well as needed. */ 22 uint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress, 23 uintptr_t dwSize); 24 uintptr_t GetCurrentProcess(void); 25 #endif 26 27 #if defined(__FreeBSD__) && defined(__arm__) 28 #include <sys/types.h> 29 #include <machine/sysarch.h> 30 #endif 31 32 #if defined(__NetBSD__) && defined(__arm__) 33 #include <machine/sysarch.h> 34 #endif 35 36 #if defined(__mips__) 37 #include <sys/cachectl.h> 38 #include <sys/syscall.h> 39 #include <unistd.h> 40 #if defined(__ANDROID__) && defined(__LP64__) 41 /* 42 * clear_mips_cache - Invalidates instruction cache for Mips. 43 */ 44 static void clear_mips_cache(const void* Addr, size_t Size) { 45 __asm__ volatile ( 46 ".set push\n" 47 ".set noreorder\n" 48 ".set noat\n" 49 "beq %[Size], $zero, 20f\n" /* If size == 0, branch around. */ 50 "nop\n" 51 "daddu %[Size], %[Addr], %[Size]\n" /* Calculate end address + 1 */ 52 "rdhwr $v0, $1\n" /* Get step size for SYNCI. 53 $1 is $HW_SYNCI_Step */ 54 "beq $v0, $zero, 20f\n" /* If no caches require 55 synchronization, branch 56 around. */ 57 "nop\n" 58 "10:\n" 59 "synci 0(%[Addr])\n" /* Synchronize all caches around 60 address. */ 61 "daddu %[Addr], %[Addr], $v0\n" /* Add step size. */ 62 "sltu $at, %[Addr], %[Size]\n" /* Compare current with end 63 address. */ 64 "bne $at, $zero, 10b\n" /* Branch if more to do. */ 65 "nop\n" 66 "sync\n" /* Clear memory hazards. */ 67 "20:\n" 68 "bal 30f\n" 69 "nop\n" 70 "30:\n" 71 "daddiu $ra, $ra, 12\n" /* $ra has a value of $pc here. 72 Add offset of 12 to point to the 73 instruction after the last nop. 74 */ 75 "jr.hb $ra\n" /* Return, clearing instruction 76 hazards. */ 77 "nop\n" 78 ".set pop\n" 79 : [Addr] "+r"(Addr), [Size] "+r"(Size) 80 :: "at", "ra", "v0", "memory" 81 ); 82 } 83 #endif 84 #endif 85 86 /* 87 * The compiler generates calls to __clear_cache() when creating 88 * trampoline functions on the stack for use with nested functions. 89 * It is expected to invalidate the instruction cache for the 90 * specified range. 91 */ 92 93 void __clear_cache(void *start, void *end) { 94 #if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64) 95 /* 96 * Intel processors have a unified instruction and data cache 97 * so there is nothing to do 98 */ 99 #elif defined(__arm__) && !defined(__APPLE__) 100 #if defined(__FreeBSD__) || defined(__NetBSD__) 101 struct arm_sync_icache_args arg; 102 103 arg.addr = (uintptr_t)start; 104 arg.len = (uintptr_t)end - (uintptr_t)start; 105 106 sysarch(ARM_SYNC_ICACHE, &arg); 107 #elif defined(__linux__) 108 /* 109 * We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but 110 * it also brought many other unused defines, as well as a dependency on 111 * kernel headers to be installed. 112 * 113 * This value is stable at least since Linux 3.13 and should remain so for 114 * compatibility reasons, warranting it's re-definition here. 115 */ 116 #define __ARM_NR_cacheflush 0x0f0002 117 register int start_reg __asm("r0") = (int) (intptr_t) start; 118 const register int end_reg __asm("r1") = (int) (intptr_t) end; 119 const register int flags __asm("r2") = 0; 120 const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush; 121 __asm __volatile("svc 0x0" 122 : "=r"(start_reg) 123 : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), 124 "r"(flags)); 125 assert(start_reg == 0 && "Cache flush syscall failed."); 126 #elif defined(_WIN32) 127 FlushInstructionCache(GetCurrentProcess(), start, end - start); 128 #else 129 compilerrt_abort(); 130 #endif 131 #elif defined(__mips__) 132 const uintptr_t start_int = (uintptr_t) start; 133 const uintptr_t end_int = (uintptr_t) end; 134 #if defined(__ANDROID__) && defined(__LP64__) 135 // Call synci implementation for short address range. 136 const uintptr_t address_range_limit = 256; 137 if ((end_int - start_int) <= address_range_limit) { 138 clear_mips_cache(start, (end_int - start_int)); 139 } else { 140 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE); 141 } 142 #else 143 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE); 144 #endif 145 #elif defined(__aarch64__) && !defined(__APPLE__) 146 uint64_t xstart = (uint64_t)(uintptr_t) start; 147 uint64_t xend = (uint64_t)(uintptr_t) end; 148 uint64_t addr; 149 150 // Get Cache Type Info 151 uint64_t ctr_el0; 152 __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0)); 153 154 /* 155 * dc & ic instructions must use 64bit registers so we don't use 156 * uintptr_t in case this runs in an IPL32 environment. 157 */ 158 const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15); 159 for (addr = xstart; addr < xend; addr += dcache_line_size) 160 __asm __volatile("dc cvau, %0" :: "r"(addr)); 161 __asm __volatile("dsb ish"); 162 163 const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15); 164 for (addr = xstart; addr < xend; addr += icache_line_size) 165 __asm __volatile("ic ivau, %0" :: "r"(addr)); 166 __asm __volatile("isb sy"); 167 #elif defined (__powerpc64__) 168 const size_t line_size = 32; 169 const size_t len = (uintptr_t)end - (uintptr_t)start; 170 171 const uintptr_t mask = ~(line_size - 1); 172 const uintptr_t start_line = ((uintptr_t)start) & mask; 173 const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask; 174 175 for (uintptr_t line = start_line; line < end_line; line += line_size) 176 __asm__ volatile("dcbf 0, %0" : : "r"(line)); 177 __asm__ volatile("sync"); 178 179 for (uintptr_t line = start_line; line < end_line; line += line_size) 180 __asm__ volatile("icbi 0, %0" : : "r"(line)); 181 __asm__ volatile("isync"); 182 #else 183 #if __APPLE__ 184 /* On Darwin, sys_icache_invalidate() provides this functionality */ 185 sys_icache_invalidate(start, end-start); 186 #else 187 compilerrt_abort(); 188 #endif 189 #endif 190 } 191