1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 8 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 12 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK6 13 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7 14 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 15 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK8 16 17 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 18 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 19 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 20 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 23 24 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 26 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK14 27 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK15 28 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 29 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK16 30 31 // RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 33 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK18 34 // RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 35 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 36 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK20 37 38 // RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK21 39 // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 40 // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK22 41 // RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK23 42 // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 43 // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK24 44 // expected-no-diagnostics 45 #ifndef HEADER 46 #define HEADER 47 #ifndef ARRAY 48 struct St { 49 int a, b; 50 St() : a(0), b(0) {} 51 St(const St &st) : a(st.a + st.b), b(0) {} 52 ~St() {} 53 }; 54 55 volatile int g __attribute__((aligned(128))) = 1212; 56 57 template <class T> 58 struct S { 59 T f; 60 S(T a) : f(a + g) {} 61 S() : f(g) {} 62 S(const S &s, St t = St()) : f(s.f + t.a) {} 63 operator T() { return T(); } 64 ~S() {} 65 }; 66 67 68 template <typename T> 69 T tmain() { 70 S<T> test; 71 T t_var __attribute__((aligned(128))) = T(); 72 T vec[] __attribute__((aligned(128))) = {1, 2}; 73 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2}; 74 S<T> var __attribute__((aligned(128))) (3); 75 #pragma omp target 76 #pragma omp teams firstprivate(t_var, vec, s_arr, var) 77 { 78 vec[0] = t_var; 79 s_arr[0] = var; 80 } 81 #pragma omp target 82 #pragma omp teams firstprivate(t_var) 83 {} 84 return T(); 85 } 86 87 int main() { 88 static int sivar; 89 #ifdef LAMBDA 90 [&]() { 91 #pragma omp target 92 #pragma omp teams firstprivate(g, sivar) 93 { 94 g = 1; 95 sivar = 2; 96 [&]() { 97 g = 2; 98 sivar = 4; 99 }(); 100 } 101 }(); 102 return 0; 103 #else 104 S<float> test; 105 int t_var = 0; 106 int vec[] = {1, 2}; 107 S<float> s_arr[] = {1, 2}; 108 S<float> var(3); 109 #pragma omp target 110 #pragma omp teams firstprivate(t_var, vec, s_arr, var, sivar) 111 { 112 vec[0] = t_var; 113 s_arr[0] = var; 114 sivar = 2; 115 } 116 #pragma omp target 117 #pragma omp teams firstprivate(t_var) 118 {} 119 return tmain<int>(); 120 #endif 121 } 122 123 124 125 126 127 128 129 130 131 132 133 134 135 #else 136 struct St { 137 int a, b; 138 St() : a(0), b(0) {} 139 St(const St &) { } 140 ~St() {} 141 void St_func(St s[2], int n, long double vla1[n]) { 142 double vla2[n][n] __attribute__((aligned(128))); 143 a = b; 144 #pragma omp target 145 #pragma omp teams firstprivate(s, vla1, vla2) 146 vla1[b] = vla2[1][n - 1] = a = b; 147 } 148 }; 149 150 void array_func(float a[3], St s[2], int n, long double vla1[n]) { 151 double vla2[n][n] __attribute__((aligned(128))); 152 #pragma omp target 153 #pragma omp teams firstprivate(a, s, vla1, vla2) 154 s[0].St_func(s, n, vla1); 155 ; 156 } 157 158 #endif 159 #endif 160 // CHECK1-LABEL: define {{[^@]+}}@main 161 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 165 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 166 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 167 // CHECK1-NEXT: ret i32 0 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 171 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 174 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 175 // CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128 176 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 177 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 178 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 179 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 180 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 181 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 182 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 183 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 184 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 185 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 186 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 187 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i64 [[TMP3]]) 188 // CHECK1-NEXT: ret void 189 // 190 // 191 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 192 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2]] { 193 // CHECK1-NEXT: entry: 194 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 195 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 196 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 197 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 198 // CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128 199 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 200 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 201 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 202 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 203 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 204 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 205 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 206 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 207 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 208 // CHECK1-NEXT: store i32 1, i32* [[G1]], align 128 209 // CHECK1-NEXT: store i32 2, i32* [[CONV]], align 8 210 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 211 // CHECK1-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 212 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 213 // CHECK1-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 214 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) 215 // CHECK1-NEXT: ret void 216 // 217 // 218 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 219 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 220 // CHECK1-NEXT: entry: 221 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 222 // CHECK1-NEXT: ret void 223 // 224 // 225 // CHECK2-LABEL: define {{[^@]+}}@main 226 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 227 // CHECK2-NEXT: entry: 228 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 229 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 230 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 231 // CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 232 // CHECK2-NEXT: ret i32 0 233 // 234 // 235 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 236 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 237 // CHECK2-NEXT: entry: 238 // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 239 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 240 // CHECK2-NEXT: [[G1:%.*]] = alloca i32, align 128 241 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 242 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 243 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 244 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 245 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 246 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 247 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 248 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 249 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 250 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 251 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 252 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i64 [[TMP3]]) 253 // CHECK2-NEXT: ret void 254 // 255 // 256 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 257 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2]] { 258 // CHECK2-NEXT: entry: 259 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 260 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 261 // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 262 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 263 // CHECK2-NEXT: [[G1:%.*]] = alloca i32, align 128 264 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 265 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 266 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 267 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 268 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 269 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 270 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 271 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 272 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 273 // CHECK2-NEXT: store i32 1, i32* [[G1]], align 128 274 // CHECK2-NEXT: store i32 2, i32* [[CONV]], align 8 275 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 276 // CHECK2-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 277 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 278 // CHECK2-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 279 // CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) 280 // CHECK2-NEXT: ret void 281 // 282 // 283 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 284 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { 285 // CHECK2-NEXT: entry: 286 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 287 // CHECK2-NEXT: ret void 288 // 289 // 290 // CHECK3-LABEL: define {{[^@]+}}@main 291 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 292 // CHECK3-NEXT: entry: 293 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 294 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 295 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 296 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 297 // CHECK3-NEXT: ret i32 0 298 // 299 // 300 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 301 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 302 // CHECK3-NEXT: entry: 303 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 304 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 305 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 306 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 307 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 308 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 309 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 310 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 311 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 312 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 313 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 314 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 315 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i32 [[TMP3]]) 316 // CHECK3-NEXT: ret void 317 // 318 // 319 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 320 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2]] { 321 // CHECK3-NEXT: entry: 322 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 323 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 324 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 325 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 326 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 327 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 328 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 329 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 330 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 331 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 332 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 333 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 334 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 335 // CHECK3-NEXT: store i32 1, i32* [[G1]], align 128 336 // CHECK3-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 337 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 338 // CHECK3-NEXT: store i32* [[G1]], i32** [[TMP2]], align 4 339 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 340 // CHECK3-NEXT: store i32* [[SIVAR_ADDR]], i32** [[TMP3]], align 4 341 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(8) [[REF_TMP]]) 342 // CHECK3-NEXT: ret void 343 // 344 // 345 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 346 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 347 // CHECK3-NEXT: entry: 348 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 349 // CHECK3-NEXT: ret void 350 // 351 // 352 // CHECK4-LABEL: define {{[^@]+}}@main 353 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 354 // CHECK4-NEXT: entry: 355 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 356 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 357 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 358 // CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 359 // CHECK4-NEXT: ret i32 0 360 // 361 // 362 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 363 // CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 364 // CHECK4-NEXT: entry: 365 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 366 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 367 // CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 128 368 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 369 // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 370 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 371 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 372 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 373 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 374 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 375 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 376 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 377 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i32 [[TMP3]]) 378 // CHECK4-NEXT: ret void 379 // 380 // 381 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 382 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2]] { 383 // CHECK4-NEXT: entry: 384 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 385 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 386 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 387 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 388 // CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 128 389 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 390 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 391 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 392 // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 393 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 394 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 395 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 396 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 397 // CHECK4-NEXT: store i32 1, i32* [[G1]], align 128 398 // CHECK4-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 399 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 400 // CHECK4-NEXT: store i32* [[G1]], i32** [[TMP2]], align 4 401 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 402 // CHECK4-NEXT: store i32* [[SIVAR_ADDR]], i32** [[TMP3]], align 4 403 // CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(8) [[REF_TMP]]) 404 // CHECK4-NEXT: ret void 405 // 406 // 407 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 408 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] { 409 // CHECK4-NEXT: entry: 410 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 411 // CHECK4-NEXT: ret void 412 // 413 // 414 // CHECK5-LABEL: define {{[^@]+}}@main 415 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 416 // CHECK5-NEXT: entry: 417 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 418 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 419 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 420 // CHECK5-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 421 // CHECK5-NEXT: ret i32 0 422 // 423 // 424 // CHECK6-LABEL: define {{[^@]+}}@main 425 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 426 // CHECK6-NEXT: entry: 427 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 428 // CHECK6-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 429 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 430 // CHECK6-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 431 // CHECK6-NEXT: ret i32 0 432 // 433 // 434 // CHECK7-LABEL: define {{[^@]+}}@main 435 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 436 // CHECK7-NEXT: entry: 437 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 438 // CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 439 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 440 // CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 441 // CHECK7-NEXT: ret i32 0 442 // 443 // 444 // CHECK8-LABEL: define {{[^@]+}}@main 445 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 446 // CHECK8-NEXT: entry: 447 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 448 // CHECK8-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 449 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 450 // CHECK8-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 451 // CHECK8-NEXT: ret i32 0 452 // 453 // 454 // CHECK9-LABEL: define {{[^@]+}}@main 455 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 456 // CHECK9-NEXT: entry: 457 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 458 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 459 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 460 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 461 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 462 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 463 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 464 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 465 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 466 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 467 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 468 // CHECK9-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 469 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 470 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 471 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 472 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 473 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 474 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 475 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 476 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 477 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 478 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 479 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 480 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 481 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 482 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 483 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 484 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 485 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 486 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 487 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 488 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 489 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 490 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 491 // CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 492 // CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 493 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 494 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 495 // CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP8]], align 8 496 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 497 // CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 498 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 499 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 500 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 8 501 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 502 // CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 503 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 504 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 505 // CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 506 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 507 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 508 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 8 509 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 510 // CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 511 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 512 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 513 // CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 514 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 515 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 516 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 8 517 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 518 // CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 519 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 8 520 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 521 // CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 522 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 523 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 524 // CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP26]], align 8 525 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 526 // CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 527 // CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP28]], align 8 528 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 529 // CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 530 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 531 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 532 // CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 533 // CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 534 // CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 535 // CHECK9: omp_offload.failed: 536 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) #[[ATTR4:[0-9]+]] 537 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 538 // CHECK9: omp_offload.cont: 539 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 540 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* 541 // CHECK9-NEXT: store i32 [[TMP34]], i32* [[CONV3]], align 4 542 // CHECK9-NEXT: [[TMP35:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 543 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 544 // CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 545 // CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP37]], align 8 546 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 547 // CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 548 // CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP39]], align 8 549 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 550 // CHECK9-NEXT: store i8* null, i8** [[TMP40]], align 8 551 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 552 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 553 // CHECK9-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 554 // CHECK9-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 555 // CHECK9-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 556 // CHECK9: omp_offload.failed7: 557 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP35]]) #[[ATTR4]] 558 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] 559 // CHECK9: omp_offload.cont8: 560 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 561 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 562 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 563 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 564 // CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 565 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 566 // CHECK9: arraydestroy.body: 567 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 568 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 569 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 570 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 571 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 572 // CHECK9: arraydestroy.done9: 573 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 574 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 575 // CHECK9-NEXT: ret i32 [[TMP46]] 576 // 577 // 578 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 579 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 580 // CHECK9-NEXT: entry: 581 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 582 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 583 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 584 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 585 // CHECK9-NEXT: ret void 586 // 587 // 588 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 589 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 590 // CHECK9-NEXT: entry: 591 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 592 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 593 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 594 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 595 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 596 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 597 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 598 // CHECK9-NEXT: ret void 599 // 600 // 601 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 602 // CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 603 // CHECK9-NEXT: entry: 604 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 605 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 606 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 607 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 608 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 609 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 610 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 611 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 612 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 613 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 614 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 615 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 616 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 617 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 618 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 619 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 620 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 621 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 622 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 623 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 624 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 625 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 626 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 627 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 628 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 629 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 630 // CHECK9-NEXT: ret void 631 // 632 // 633 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 634 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { 635 // CHECK9-NEXT: entry: 636 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 637 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 638 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 639 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 640 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 641 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 642 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 643 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 644 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 645 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 646 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 647 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 648 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 649 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 650 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 651 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 652 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 653 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 654 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 655 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 656 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 657 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 658 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 659 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 660 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 661 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 662 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 663 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 664 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 665 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 666 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 667 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 668 // CHECK9: omp.arraycpy.body: 669 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 670 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 671 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 672 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 673 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 674 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 675 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 676 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 677 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 678 // CHECK9: omp.arraycpy.done4: 679 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 680 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 681 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 682 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 683 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 684 // CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 685 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 686 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 687 // CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 688 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) 689 // CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 8 690 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 691 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 692 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 693 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 694 // CHECK9: arraydestroy.body: 695 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 696 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 697 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 698 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 699 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 700 // CHECK9: arraydestroy.done9: 701 // CHECK9-NEXT: ret void 702 // 703 // 704 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev 705 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 706 // CHECK9-NEXT: entry: 707 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 708 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 709 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 710 // CHECK9-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 711 // CHECK9-NEXT: ret void 712 // 713 // 714 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 715 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 716 // CHECK9-NEXT: entry: 717 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 718 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 719 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 720 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 721 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 722 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 723 // CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 724 // CHECK9-NEXT: ret void 725 // 726 // 727 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev 728 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 729 // CHECK9-NEXT: entry: 730 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 731 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 732 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 733 // CHECK9-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 734 // CHECK9-NEXT: ret void 735 // 736 // 737 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 738 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 739 // CHECK9-NEXT: entry: 740 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 741 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 742 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 743 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 744 // CHECK9-NEXT: ret void 745 // 746 // 747 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 748 // CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { 749 // CHECK9-NEXT: entry: 750 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 751 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 752 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 753 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 754 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 755 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 756 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 757 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 758 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 759 // CHECK9-NEXT: ret void 760 // 761 // 762 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 763 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { 764 // CHECK9-NEXT: entry: 765 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 766 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 767 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 768 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 769 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 770 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 771 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 772 // CHECK9-NEXT: ret void 773 // 774 // 775 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 776 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { 777 // CHECK9-NEXT: entry: 778 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 779 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 780 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 781 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 782 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 783 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 784 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 785 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 786 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 787 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 788 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 789 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 790 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 791 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 792 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 793 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 794 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 795 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 796 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 797 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 798 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) 799 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 800 // CHECK9-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 801 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 802 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 803 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 804 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 805 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 806 // CHECK9-NEXT: store i8* null, i8** [[TMP5]], align 8 807 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 808 // CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 809 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 8 810 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 811 // CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 812 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 8 813 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 814 // CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 815 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 816 // CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 817 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 8 818 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 819 // CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 820 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 8 821 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 822 // CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 823 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 824 // CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 825 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 8 826 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 827 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 828 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 8 829 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 830 // CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 831 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 832 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 833 // CHECK9-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 834 // CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 835 // CHECK9-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 836 // CHECK9: omp_offload.failed: 837 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 838 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 839 // CHECK9: omp_offload.cont: 840 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 841 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 842 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 8 843 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 844 // CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 845 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 8 846 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 847 // CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 848 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 849 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 850 // CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 851 // CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 852 // CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 853 // CHECK9: omp_offload.failed4: 854 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 855 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT5]] 856 // CHECK9: omp_offload.cont5: 857 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 858 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 859 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 860 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 861 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 862 // CHECK9: arraydestroy.body: 863 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 864 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 865 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 866 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 867 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 868 // CHECK9: arraydestroy.done6: 869 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 870 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 871 // CHECK9-NEXT: ret i32 [[TMP35]] 872 // 873 // 874 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 875 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 876 // CHECK9-NEXT: entry: 877 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 878 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 879 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 880 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 881 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 882 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 883 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 884 // CHECK9-NEXT: ret void 885 // 886 // 887 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 888 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 889 // CHECK9-NEXT: entry: 890 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 891 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 892 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 893 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 894 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 895 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 896 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 897 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 898 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 899 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 900 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 901 // CHECK9-NEXT: ret void 902 // 903 // 904 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev 905 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 906 // CHECK9-NEXT: entry: 907 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 908 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 909 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 910 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 911 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 912 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 913 // CHECK9-NEXT: store i32 0, i32* [[B]], align 4 914 // CHECK9-NEXT: ret void 915 // 916 // 917 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 918 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 919 // CHECK9-NEXT: entry: 920 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 921 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 922 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 923 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 924 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 925 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 926 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 927 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 928 // CHECK9-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 929 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 930 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 931 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 932 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 933 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 934 // CHECK9-NEXT: ret void 935 // 936 // 937 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev 938 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 939 // CHECK9-NEXT: entry: 940 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 941 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 942 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 943 // CHECK9-NEXT: ret void 944 // 945 // 946 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 947 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 948 // CHECK9-NEXT: entry: 949 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 950 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 951 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 952 // CHECK9-NEXT: ret void 953 // 954 // 955 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 956 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 957 // CHECK9-NEXT: entry: 958 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 959 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 960 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 961 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 962 // CHECK9-NEXT: ret void 963 // 964 // 965 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 966 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 967 // CHECK9-NEXT: entry: 968 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 969 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 970 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 971 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 972 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 973 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 974 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 975 // CHECK9-NEXT: ret void 976 // 977 // 978 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 979 // CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 980 // CHECK9-NEXT: entry: 981 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 982 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 983 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 984 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 985 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 986 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 987 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 988 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 989 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 990 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 991 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 992 // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 993 // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 994 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 995 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 996 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 997 // CHECK9-NEXT: ret void 998 // 999 // 1000 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 1001 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1002 // CHECK9-NEXT: entry: 1003 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1004 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1005 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1006 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1007 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1008 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1009 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1010 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 1011 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 1012 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1013 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1014 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1015 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1016 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1017 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1018 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1019 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1020 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1021 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1022 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1023 // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1024 // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1025 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 1026 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 1027 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1028 // CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1029 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) 1030 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1031 // CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 1032 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1033 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 1034 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1035 // CHECK9: omp.arraycpy.body: 1036 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1037 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1038 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1039 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1040 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1041 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1042 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1043 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 1044 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1045 // CHECK9: omp.arraycpy.done4: 1046 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1047 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 1048 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 1049 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 1050 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 1051 // CHECK9-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 1052 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 1053 // CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 1054 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 1055 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) 1056 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1057 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1058 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 1059 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1060 // CHECK9: arraydestroy.body: 1061 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1062 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1063 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1064 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1065 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1066 // CHECK9: arraydestroy.done9: 1067 // CHECK9-NEXT: ret void 1068 // 1069 // 1070 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1071 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1072 // CHECK9-NEXT: entry: 1073 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1074 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1075 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1076 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1077 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1078 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1079 // CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1080 // CHECK9-NEXT: ret void 1081 // 1082 // 1083 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1084 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1085 // CHECK9-NEXT: entry: 1086 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1087 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1088 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1089 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1090 // CHECK9-NEXT: ret void 1091 // 1092 // 1093 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 1094 // CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1095 // CHECK9-NEXT: entry: 1096 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1097 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1098 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1099 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1100 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1101 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1102 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 1103 // CHECK9-NEXT: ret void 1104 // 1105 // 1106 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 1107 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1108 // CHECK9-NEXT: entry: 1109 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1110 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1111 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1112 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1113 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1114 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1115 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1116 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1117 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1118 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1119 // CHECK9-NEXT: ret void 1120 // 1121 // 1122 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1123 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1124 // CHECK9-NEXT: entry: 1125 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1126 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1127 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1128 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1129 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1130 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1131 // CHECK9-NEXT: ret void 1132 // 1133 // 1134 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1135 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1136 // CHECK9-NEXT: entry: 1137 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1138 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1139 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1140 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1141 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1142 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1143 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1144 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1145 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1146 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1147 // CHECK9-NEXT: ret void 1148 // 1149 // 1150 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1151 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1152 // CHECK9-NEXT: entry: 1153 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1154 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1155 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1156 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1157 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1158 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1159 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1160 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1161 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1162 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1163 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1164 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1165 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1166 // CHECK9-NEXT: ret void 1167 // 1168 // 1169 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1170 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1171 // CHECK9-NEXT: entry: 1172 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1173 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1174 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1175 // CHECK9-NEXT: ret void 1176 // 1177 // 1178 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1179 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { 1180 // CHECK9-NEXT: entry: 1181 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1182 // CHECK9-NEXT: ret void 1183 // 1184 // 1185 // CHECK10-LABEL: define {{[^@]+}}@main 1186 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 1187 // CHECK10-NEXT: entry: 1188 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1189 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1190 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1191 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1192 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1193 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1194 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1195 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1196 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1197 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1198 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1199 // CHECK10-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 1200 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 1201 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 1202 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 1203 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1204 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 1205 // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 1206 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1207 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 1208 // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 1209 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 1210 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 1211 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 1212 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 1213 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 1214 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1215 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 1216 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1217 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1218 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1219 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 1220 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1221 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1222 // CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1223 // CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 1224 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1225 // CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1226 // CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP8]], align 8 1227 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1228 // CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 1229 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1230 // CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 1231 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 8 1232 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1233 // CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 1234 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 1235 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1236 // CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 1237 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1238 // CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 1239 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 8 1240 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1241 // CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 1242 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 1243 // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1244 // CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 1245 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1246 // CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 1247 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 8 1248 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1249 // CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 1250 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 8 1251 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1252 // CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 1253 // CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1254 // CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 1255 // CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP26]], align 8 1256 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1257 // CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 1258 // CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP28]], align 8 1259 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1260 // CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 1261 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1262 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1263 // CHECK10-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1264 // CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1265 // CHECK10-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1266 // CHECK10: omp_offload.failed: 1267 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) #[[ATTR4:[0-9]+]] 1268 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1269 // CHECK10: omp_offload.cont: 1270 // CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 1271 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* 1272 // CHECK10-NEXT: store i32 [[TMP34]], i32* [[CONV3]], align 4 1273 // CHECK10-NEXT: [[TMP35:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 1274 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 1275 // CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 1276 // CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP37]], align 8 1277 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 1278 // CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 1279 // CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP39]], align 8 1280 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 1281 // CHECK10-NEXT: store i8* null, i8** [[TMP40]], align 8 1282 // CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 1283 // CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 1284 // CHECK10-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1285 // CHECK10-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 1286 // CHECK10-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 1287 // CHECK10: omp_offload.failed7: 1288 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP35]]) #[[ATTR4]] 1289 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT8]] 1290 // CHECK10: omp_offload.cont8: 1291 // CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 1292 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1293 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1294 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1295 // CHECK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1296 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1297 // CHECK10: arraydestroy.body: 1298 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1299 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1300 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1301 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1302 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1303 // CHECK10: arraydestroy.done9: 1304 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1305 // CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 1306 // CHECK10-NEXT: ret i32 [[TMP46]] 1307 // 1308 // 1309 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1310 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1311 // CHECK10-NEXT: entry: 1312 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1313 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1314 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1315 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1316 // CHECK10-NEXT: ret void 1317 // 1318 // 1319 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1320 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1321 // CHECK10-NEXT: entry: 1322 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1323 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1324 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1325 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1326 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1327 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1328 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1329 // CHECK10-NEXT: ret void 1330 // 1331 // 1332 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 1333 // CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 1334 // CHECK10-NEXT: entry: 1335 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1336 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1337 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1338 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1339 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1340 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1341 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1342 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1343 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1344 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1345 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1346 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1347 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1348 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1349 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1350 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1351 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1352 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1353 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1354 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 1355 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1356 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 1357 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1358 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 1359 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1360 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 1361 // CHECK10-NEXT: ret void 1362 // 1363 // 1364 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 1365 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { 1366 // CHECK10-NEXT: entry: 1367 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1368 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1369 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1370 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1371 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1372 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1373 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1374 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1375 // CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 1376 // CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1377 // CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1378 // CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1379 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1380 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1381 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1382 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1383 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1384 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1385 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1386 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1387 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1388 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1389 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1390 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1391 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1392 // CHECK10-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1393 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1394 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1395 // CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1396 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1397 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1398 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1399 // CHECK10: omp.arraycpy.body: 1400 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1401 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1402 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1403 // CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1404 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1405 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1406 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1407 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1408 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1409 // CHECK10: omp.arraycpy.done4: 1410 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1411 // CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 1412 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 1413 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 1414 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 1415 // CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 1416 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 1417 // CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 1418 // CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 1419 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) 1420 // CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 8 1421 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1422 // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1423 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 1424 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1425 // CHECK10: arraydestroy.body: 1426 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1427 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1428 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1429 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1430 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1431 // CHECK10: arraydestroy.done9: 1432 // CHECK10-NEXT: ret void 1433 // 1434 // 1435 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1436 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1437 // CHECK10-NEXT: entry: 1438 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1439 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1440 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1441 // CHECK10-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 1442 // CHECK10-NEXT: ret void 1443 // 1444 // 1445 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1446 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1447 // CHECK10-NEXT: entry: 1448 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1449 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1450 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1451 // CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1452 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1453 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1454 // CHECK10-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1455 // CHECK10-NEXT: ret void 1456 // 1457 // 1458 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1459 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1460 // CHECK10-NEXT: entry: 1461 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1462 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1463 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1464 // CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 1465 // CHECK10-NEXT: ret void 1466 // 1467 // 1468 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1469 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1470 // CHECK10-NEXT: entry: 1471 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1472 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1473 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1474 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1475 // CHECK10-NEXT: ret void 1476 // 1477 // 1478 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 1479 // CHECK10-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { 1480 // CHECK10-NEXT: entry: 1481 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1482 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1483 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1484 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1485 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 1486 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1487 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1488 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1489 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1490 // CHECK10-NEXT: ret void 1491 // 1492 // 1493 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 1494 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { 1495 // CHECK10-NEXT: entry: 1496 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1497 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1498 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1499 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1500 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1501 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1502 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1503 // CHECK10-NEXT: ret void 1504 // 1505 // 1506 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1507 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { 1508 // CHECK10-NEXT: entry: 1509 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1510 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1511 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1512 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1513 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1514 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 1515 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1516 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1517 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1518 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 1519 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 1520 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 1521 // CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1522 // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 1523 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1524 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1525 // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1526 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 1527 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1528 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 1529 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) 1530 // CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1531 // CHECK10-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 1532 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 1533 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1534 // CHECK10-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 1535 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 1536 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1537 // CHECK10-NEXT: store i8* null, i8** [[TMP5]], align 8 1538 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1539 // CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 1540 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 8 1541 // CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1542 // CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 1543 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 8 1544 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1545 // CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 1546 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1547 // CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 1548 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 8 1549 // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1550 // CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 1551 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 8 1552 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1553 // CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 1554 // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1555 // CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 1556 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 8 1557 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1558 // CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 1559 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 8 1560 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1561 // CHECK10-NEXT: store i8* null, i8** [[TMP20]], align 8 1562 // CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1563 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1564 // CHECK10-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1565 // CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 1566 // CHECK10-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1567 // CHECK10: omp_offload.failed: 1568 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 1569 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1570 // CHECK10: omp_offload.cont: 1571 // CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 1572 // CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 1573 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 8 1574 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 1575 // CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 1576 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 8 1577 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 1578 // CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 1579 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 1580 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 1581 // CHECK10-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1582 // CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1583 // CHECK10-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 1584 // CHECK10: omp_offload.failed4: 1585 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 1586 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT5]] 1587 // CHECK10: omp_offload.cont5: 1588 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1589 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1590 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1591 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1592 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1593 // CHECK10: arraydestroy.body: 1594 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1595 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1596 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1597 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1598 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1599 // CHECK10: arraydestroy.done6: 1600 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1601 // CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 1602 // CHECK10-NEXT: ret i32 [[TMP35]] 1603 // 1604 // 1605 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1606 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1607 // CHECK10-NEXT: entry: 1608 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1609 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1610 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1611 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1612 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1613 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1614 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 1615 // CHECK10-NEXT: ret void 1616 // 1617 // 1618 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1619 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1620 // CHECK10-NEXT: entry: 1621 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1622 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1623 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1624 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1625 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1626 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1627 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1628 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1629 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1630 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1631 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 1632 // CHECK10-NEXT: ret void 1633 // 1634 // 1635 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1636 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1637 // CHECK10-NEXT: entry: 1638 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1639 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1640 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1641 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1642 // CHECK10-NEXT: store i32 0, i32* [[A]], align 4 1643 // CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1644 // CHECK10-NEXT: store i32 0, i32* [[B]], align 4 1645 // CHECK10-NEXT: ret void 1646 // 1647 // 1648 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1649 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1650 // CHECK10-NEXT: entry: 1651 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1652 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1653 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1654 // CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1655 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1656 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1657 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1658 // CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1659 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1660 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1661 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1662 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1663 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1664 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 1665 // CHECK10-NEXT: ret void 1666 // 1667 // 1668 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1669 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1670 // CHECK10-NEXT: entry: 1671 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1672 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1673 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1674 // CHECK10-NEXT: ret void 1675 // 1676 // 1677 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1678 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1679 // CHECK10-NEXT: entry: 1680 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1681 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1682 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1683 // CHECK10-NEXT: ret void 1684 // 1685 // 1686 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1687 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1688 // CHECK10-NEXT: entry: 1689 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1690 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1691 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1692 // CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1693 // CHECK10-NEXT: ret void 1694 // 1695 // 1696 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1697 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1698 // CHECK10-NEXT: entry: 1699 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1700 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1701 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1702 // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1703 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1704 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1705 // CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 1706 // CHECK10-NEXT: ret void 1707 // 1708 // 1709 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 1710 // CHECK10-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1711 // CHECK10-NEXT: entry: 1712 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1713 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1714 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1715 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1716 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1717 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1718 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1719 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1720 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1721 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1722 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1723 // CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1724 // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1725 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 1726 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 1727 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 1728 // CHECK10-NEXT: ret void 1729 // 1730 // 1731 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 1732 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1733 // CHECK10-NEXT: entry: 1734 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1735 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1736 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1737 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1738 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1739 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1740 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1741 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 1742 // CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 1743 // CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1744 // CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1745 // CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1746 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1747 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1748 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1749 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1750 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1751 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1752 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1753 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1754 // CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1755 // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1756 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 1757 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 1758 // CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1759 // CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1760 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) 1761 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1762 // CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 1763 // CHECK10-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1764 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 1765 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1766 // CHECK10: omp.arraycpy.body: 1767 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1768 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1769 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1770 // CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1771 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1772 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1773 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1774 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 1775 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1776 // CHECK10: omp.arraycpy.done4: 1777 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1778 // CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 1779 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 1780 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 1781 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 1782 // CHECK10-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 1783 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 1784 // CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 1785 // CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 1786 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) 1787 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1788 // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1789 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 1790 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1791 // CHECK10: arraydestroy.body: 1792 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1793 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1794 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1795 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1796 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1797 // CHECK10: arraydestroy.done9: 1798 // CHECK10-NEXT: ret void 1799 // 1800 // 1801 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1802 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1803 // CHECK10-NEXT: entry: 1804 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1805 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1806 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1807 // CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1808 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1809 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1810 // CHECK10-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1811 // CHECK10-NEXT: ret void 1812 // 1813 // 1814 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1815 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1816 // CHECK10-NEXT: entry: 1817 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1818 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1819 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1820 // CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1821 // CHECK10-NEXT: ret void 1822 // 1823 // 1824 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 1825 // CHECK10-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1826 // CHECK10-NEXT: entry: 1827 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1828 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1829 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1830 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1831 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1832 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1833 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 1834 // CHECK10-NEXT: ret void 1835 // 1836 // 1837 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 1838 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1839 // CHECK10-NEXT: entry: 1840 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1841 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1842 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1843 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1844 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1845 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1846 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1847 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1848 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1849 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1850 // CHECK10-NEXT: ret void 1851 // 1852 // 1853 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1854 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1855 // CHECK10-NEXT: entry: 1856 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1857 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1858 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1859 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1860 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1861 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1862 // CHECK10-NEXT: ret void 1863 // 1864 // 1865 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1866 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1867 // CHECK10-NEXT: entry: 1868 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1869 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1870 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1871 // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1872 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1873 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1874 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1875 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1876 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1877 // CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1878 // CHECK10-NEXT: ret void 1879 // 1880 // 1881 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1882 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1883 // CHECK10-NEXT: entry: 1884 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1885 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1886 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1887 // CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1888 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1889 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1890 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1891 // CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1892 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1893 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1894 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1895 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1896 // CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1897 // CHECK10-NEXT: ret void 1898 // 1899 // 1900 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1901 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1902 // CHECK10-NEXT: entry: 1903 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1904 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1905 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1906 // CHECK10-NEXT: ret void 1907 // 1908 // 1909 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1910 // CHECK10-SAME: () #[[ATTR6:[0-9]+]] { 1911 // CHECK10-NEXT: entry: 1912 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 1913 // CHECK10-NEXT: ret void 1914 // 1915 // 1916 // CHECK11-LABEL: define {{[^@]+}}@main 1917 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1918 // CHECK11-NEXT: entry: 1919 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1920 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1921 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1922 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1923 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1924 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1925 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1926 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1927 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1928 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1929 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1930 // CHECK11-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 1931 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 1932 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 1933 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 1934 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1935 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 1936 // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 1937 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1938 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 1939 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1940 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 1941 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 1942 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 1943 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 1944 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 1945 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 1946 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1947 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1948 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 1949 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1950 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1951 // CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 1952 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 1953 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1954 // CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 1955 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP8]], align 4 1956 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1957 // CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 1958 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1959 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 1960 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 4 1961 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1962 // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 1963 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 1964 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1965 // CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 1966 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1967 // CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 1968 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 4 1969 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1970 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 1971 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 1972 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1973 // CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 1974 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1975 // CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 1976 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 4 1977 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1978 // CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 1979 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 4 1980 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1981 // CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 1982 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1983 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 1984 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP26]], align 4 1985 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1986 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1987 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP28]], align 4 1988 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1989 // CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 1990 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1991 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1992 // CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1993 // CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1994 // CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1995 // CHECK11: omp_offload.failed: 1996 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) #[[ATTR4:[0-9]+]] 1997 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1998 // CHECK11: omp_offload.cont: 1999 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 2000 // CHECK11-NEXT: store i32 [[TMP34]], i32* [[T_VAR_CASTED1]], align 4 2001 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 2002 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 2003 // CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 2004 // CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP37]], align 4 2005 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 2006 // CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 2007 // CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP39]], align 4 2008 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 2009 // CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 2010 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 2011 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 2012 // CHECK11-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2013 // CHECK11-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 2014 // CHECK11-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] 2015 // CHECK11: omp_offload.failed5: 2016 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP35]]) #[[ATTR4]] 2017 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] 2018 // CHECK11: omp_offload.cont6: 2019 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2020 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2021 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2022 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2023 // CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2024 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2025 // CHECK11: arraydestroy.body: 2026 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2027 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2028 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2029 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2030 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 2031 // CHECK11: arraydestroy.done7: 2032 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2033 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 2034 // CHECK11-NEXT: ret i32 [[TMP46]] 2035 // 2036 // 2037 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2038 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2039 // CHECK11-NEXT: entry: 2040 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2041 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2042 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2043 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2044 // CHECK11-NEXT: ret void 2045 // 2046 // 2047 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2048 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2049 // CHECK11-NEXT: entry: 2050 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2051 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2052 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2053 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2054 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2055 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2056 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2057 // CHECK11-NEXT: ret void 2058 // 2059 // 2060 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 2061 // CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 2062 // CHECK11-NEXT: entry: 2063 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2064 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2065 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2066 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2067 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2068 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2069 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2070 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2071 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2072 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2073 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2074 // CHECK11-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2075 // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2076 // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2077 // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2078 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2079 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2080 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2081 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2082 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 2083 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2084 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 2085 // CHECK11-NEXT: ret void 2086 // 2087 // 2088 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 2089 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { 2090 // CHECK11-NEXT: entry: 2091 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2092 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2093 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2094 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2095 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2096 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2097 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2098 // CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2099 // CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2100 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2101 // CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2102 // CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2103 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2104 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2105 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2106 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2107 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2108 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2109 // CHECK11-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2110 // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2111 // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2112 // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2113 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 2114 // CHECK11-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2115 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2116 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2117 // CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2118 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2119 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2120 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2121 // CHECK11: omp.arraycpy.body: 2122 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2123 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2124 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2125 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2126 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 2127 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2128 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2129 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2130 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2131 // CHECK11: omp.arraycpy.done3: 2132 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 2133 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 2134 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] 2135 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2136 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 2137 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 2138 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2139 // CHECK11-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 2140 // CHECK11-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2141 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) 2142 // CHECK11-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 2143 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] 2144 // CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2145 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 2146 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2147 // CHECK11: arraydestroy.body: 2148 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2149 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2150 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2151 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 2152 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 2153 // CHECK11: arraydestroy.done8: 2154 // CHECK11-NEXT: ret void 2155 // 2156 // 2157 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2158 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2159 // CHECK11-NEXT: entry: 2160 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2161 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2162 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2163 // CHECK11-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2164 // CHECK11-NEXT: ret void 2165 // 2166 // 2167 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2168 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2169 // CHECK11-NEXT: entry: 2170 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2171 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2172 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2173 // CHECK11-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2174 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2175 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2176 // CHECK11-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2177 // CHECK11-NEXT: ret void 2178 // 2179 // 2180 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2181 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2182 // CHECK11-NEXT: entry: 2183 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2184 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2185 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2186 // CHECK11-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 2187 // CHECK11-NEXT: ret void 2188 // 2189 // 2190 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2191 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2192 // CHECK11-NEXT: entry: 2193 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2194 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2195 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2196 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2197 // CHECK11-NEXT: ret void 2198 // 2199 // 2200 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 2201 // CHECK11-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { 2202 // CHECK11-NEXT: entry: 2203 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2204 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2205 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2206 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2207 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 2208 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2209 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2210 // CHECK11-NEXT: ret void 2211 // 2212 // 2213 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2214 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { 2215 // CHECK11-NEXT: entry: 2216 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2217 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2218 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2219 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2220 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2221 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2222 // CHECK11-NEXT: ret void 2223 // 2224 // 2225 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2226 // CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { 2227 // CHECK11-NEXT: entry: 2228 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2229 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2230 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 2231 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 2232 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 2233 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 2234 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2235 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2236 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2237 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 2238 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 2239 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 2240 // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2241 // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 128 2242 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2243 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2244 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2245 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2246 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2247 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2248 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 2249 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2250 // CHECK11-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 2251 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 2252 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2253 // CHECK11-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 2254 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 2255 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2256 // CHECK11-NEXT: store i8* null, i8** [[TMP5]], align 4 2257 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2258 // CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 2259 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 4 2260 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2261 // CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 2262 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 4 2263 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2264 // CHECK11-NEXT: store i8* null, i8** [[TMP10]], align 4 2265 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2266 // CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 2267 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 4 2268 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2269 // CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 2270 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 4 2271 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2272 // CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 2273 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2274 // CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 2275 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 4 2276 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2277 // CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 2278 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 4 2279 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2280 // CHECK11-NEXT: store i8* null, i8** [[TMP20]], align 4 2281 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2282 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2283 // CHECK11-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2284 // CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 2285 // CHECK11-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2286 // CHECK11: omp_offload.failed: 2287 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 2288 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2289 // CHECK11: omp_offload.cont: 2290 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 2291 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 2292 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 4 2293 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 2294 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 2295 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 4 2296 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 2297 // CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 2298 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 2299 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 2300 // CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2301 // CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2302 // CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 2303 // CHECK11: omp_offload.failed4: 2304 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 2305 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT5]] 2306 // CHECK11: omp_offload.cont5: 2307 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 2308 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2309 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2310 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2311 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2312 // CHECK11: arraydestroy.body: 2313 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2314 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2315 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2316 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2317 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 2318 // CHECK11: arraydestroy.done6: 2319 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2320 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 2321 // CHECK11-NEXT: ret i32 [[TMP35]] 2322 // 2323 // 2324 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2325 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2326 // CHECK11-NEXT: entry: 2327 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2328 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2329 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2330 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2331 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 2332 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2333 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 2334 // CHECK11-NEXT: ret void 2335 // 2336 // 2337 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2338 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2339 // CHECK11-NEXT: entry: 2340 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2341 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2342 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2343 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2344 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2345 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2346 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2347 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 2348 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2349 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2350 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 2351 // CHECK11-NEXT: ret void 2352 // 2353 // 2354 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2355 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2356 // CHECK11-NEXT: entry: 2357 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2358 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2359 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2360 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 2361 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 2362 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2363 // CHECK11-NEXT: store i32 0, i32* [[B]], align 4 2364 // CHECK11-NEXT: ret void 2365 // 2366 // 2367 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 2368 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2369 // CHECK11-NEXT: entry: 2370 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2371 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2372 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2373 // CHECK11-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2374 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2375 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2376 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2377 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 2378 // CHECK11-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 2379 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2380 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2381 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 2382 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 2383 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 2384 // CHECK11-NEXT: ret void 2385 // 2386 // 2387 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD2Ev 2388 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2389 // CHECK11-NEXT: entry: 2390 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2391 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2392 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2393 // CHECK11-NEXT: ret void 2394 // 2395 // 2396 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2397 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2398 // CHECK11-NEXT: entry: 2399 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2400 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2401 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2402 // CHECK11-NEXT: ret void 2403 // 2404 // 2405 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2406 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2407 // CHECK11-NEXT: entry: 2408 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2409 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2410 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2411 // CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2412 // CHECK11-NEXT: ret void 2413 // 2414 // 2415 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2416 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2417 // CHECK11-NEXT: entry: 2418 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2419 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2420 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2421 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2422 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2423 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2424 // CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 2425 // CHECK11-NEXT: ret void 2426 // 2427 // 2428 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 2429 // CHECK11-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2430 // CHECK11-NEXT: entry: 2431 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 2432 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2433 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2434 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2435 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2436 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 2437 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2438 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2439 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2440 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 2441 // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2442 // CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2443 // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2444 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 2445 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 2446 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 2447 // CHECK11-NEXT: ret void 2448 // 2449 // 2450 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 2451 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2452 // CHECK11-NEXT: entry: 2453 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2454 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2455 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2456 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 2457 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2458 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2459 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2460 // CHECK11-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 2461 // CHECK11-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 2462 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2463 // CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 2464 // CHECK11-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2465 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2466 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2467 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2468 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 2469 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2470 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2471 // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2472 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 2473 // CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2474 // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2475 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 2476 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 2477 // CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 2478 // CHECK11-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2479 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) 2480 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2481 // CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 2482 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2483 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 2484 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2485 // CHECK11: omp.arraycpy.body: 2486 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2487 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2488 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2489 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2490 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 2491 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2492 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2493 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 2494 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2495 // CHECK11: omp.arraycpy.done4: 2496 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2497 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 2498 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 2499 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 2500 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 2501 // CHECK11-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 2502 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2503 // CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 2504 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 2505 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) 2506 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2507 // CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2508 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 2509 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2510 // CHECK11: arraydestroy.body: 2511 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2512 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2513 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2514 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 2515 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 2516 // CHECK11: arraydestroy.done9: 2517 // CHECK11-NEXT: ret void 2518 // 2519 // 2520 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 2521 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2522 // CHECK11-NEXT: entry: 2523 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2524 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2525 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2526 // CHECK11-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2527 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2528 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2529 // CHECK11-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2530 // CHECK11-NEXT: ret void 2531 // 2532 // 2533 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2534 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2535 // CHECK11-NEXT: entry: 2536 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2537 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2538 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2539 // CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2540 // CHECK11-NEXT: ret void 2541 // 2542 // 2543 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 2544 // CHECK11-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 2545 // CHECK11-NEXT: entry: 2546 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 2547 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2548 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 2549 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 2550 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 2551 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 2552 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 2553 // CHECK11-NEXT: ret void 2554 // 2555 // 2556 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 2557 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 2558 // CHECK11-NEXT: entry: 2559 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2560 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2561 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 2562 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2563 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2564 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2565 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 2566 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 2567 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 2568 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 2569 // CHECK11-NEXT: ret void 2570 // 2571 // 2572 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2573 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2574 // CHECK11-NEXT: entry: 2575 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2576 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2577 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2578 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2579 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 2580 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2581 // CHECK11-NEXT: ret void 2582 // 2583 // 2584 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2585 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2586 // CHECK11-NEXT: entry: 2587 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2588 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2589 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2590 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2591 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2592 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2593 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2594 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 2595 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2596 // CHECK11-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2597 // CHECK11-NEXT: ret void 2598 // 2599 // 2600 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 2601 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2602 // CHECK11-NEXT: entry: 2603 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2604 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2605 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2606 // CHECK11-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2607 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2608 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2609 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2610 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 2611 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 2612 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2613 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2614 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 2615 // CHECK11-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2616 // CHECK11-NEXT: ret void 2617 // 2618 // 2619 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2620 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2621 // CHECK11-NEXT: entry: 2622 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2623 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2624 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2625 // CHECK11-NEXT: ret void 2626 // 2627 // 2628 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2629 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] { 2630 // CHECK11-NEXT: entry: 2631 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 2632 // CHECK11-NEXT: ret void 2633 // 2634 // 2635 // CHECK12-LABEL: define {{[^@]+}}@main 2636 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 2637 // CHECK12-NEXT: entry: 2638 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2639 // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2640 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2641 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2642 // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2643 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 2644 // CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2645 // CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2646 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2647 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2648 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2649 // CHECK12-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 2650 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 2651 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 2652 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 2653 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2654 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 2655 // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 2656 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2657 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 2658 // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2659 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 2660 // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 2661 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 2662 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 2663 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 2664 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 2665 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2666 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 2667 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 2668 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2669 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2670 // CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 2671 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 2672 // CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2673 // CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2674 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP8]], align 4 2675 // CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2676 // CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 2677 // CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2678 // CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 2679 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 4 2680 // CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2681 // CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 2682 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 2683 // CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2684 // CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 2685 // CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2686 // CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 2687 // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 4 2688 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2689 // CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 2690 // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 2691 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2692 // CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 2693 // CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2694 // CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 2695 // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 4 2696 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2697 // CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 2698 // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 4 2699 // CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2700 // CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 2701 // CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2702 // CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 2703 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP26]], align 4 2704 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2705 // CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 2706 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP28]], align 4 2707 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2708 // CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 2709 // CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2710 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2711 // CHECK12-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2712 // CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2713 // CHECK12-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2714 // CHECK12: omp_offload.failed: 2715 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) #[[ATTR4:[0-9]+]] 2716 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2717 // CHECK12: omp_offload.cont: 2718 // CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 2719 // CHECK12-NEXT: store i32 [[TMP34]], i32* [[T_VAR_CASTED1]], align 4 2720 // CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 2721 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 2722 // CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 2723 // CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP37]], align 4 2724 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 2725 // CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 2726 // CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP39]], align 4 2727 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 2728 // CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 2729 // CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 2730 // CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 2731 // CHECK12-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2732 // CHECK12-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 2733 // CHECK12-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] 2734 // CHECK12: omp_offload.failed5: 2735 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP35]]) #[[ATTR4]] 2736 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] 2737 // CHECK12: omp_offload.cont6: 2738 // CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2739 // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2740 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2741 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2742 // CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2743 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2744 // CHECK12: arraydestroy.body: 2745 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2746 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2747 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2748 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2749 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 2750 // CHECK12: arraydestroy.done7: 2751 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2752 // CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 2753 // CHECK12-NEXT: ret i32 [[TMP46]] 2754 // 2755 // 2756 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2757 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2758 // CHECK12-NEXT: entry: 2759 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2760 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2761 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2762 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2763 // CHECK12-NEXT: ret void 2764 // 2765 // 2766 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2767 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2768 // CHECK12-NEXT: entry: 2769 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2770 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2771 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2772 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2773 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2774 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2775 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2776 // CHECK12-NEXT: ret void 2777 // 2778 // 2779 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 2780 // CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 2781 // CHECK12-NEXT: entry: 2782 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2783 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2784 // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2785 // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2786 // CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2787 // CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2788 // CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2789 // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2790 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2791 // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2792 // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2793 // CHECK12-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2794 // CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2795 // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2796 // CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2797 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2798 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2799 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2800 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2801 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 2802 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2803 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 2804 // CHECK12-NEXT: ret void 2805 // 2806 // 2807 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 2808 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { 2809 // CHECK12-NEXT: entry: 2810 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2811 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2812 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2813 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2814 // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2815 // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2816 // CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2817 // CHECK12-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2818 // CHECK12-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2819 // CHECK12-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2820 // CHECK12-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2821 // CHECK12-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2822 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2823 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2824 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2825 // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2826 // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2827 // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2828 // CHECK12-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2829 // CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2830 // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2831 // CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2832 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 2833 // CHECK12-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2834 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2835 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2836 // CHECK12-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2837 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2838 // CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2839 // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2840 // CHECK12: omp.arraycpy.body: 2841 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2842 // CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2843 // CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2844 // CHECK12-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2845 // CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 2846 // CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2847 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2848 // CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2849 // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2850 // CHECK12: omp.arraycpy.done3: 2851 // CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 2852 // CHECK12-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 2853 // CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] 2854 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2855 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 2856 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 2857 // CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2858 // CHECK12-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 2859 // CHECK12-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2860 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) 2861 // CHECK12-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 2862 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] 2863 // CHECK12-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2864 // CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 2865 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2866 // CHECK12: arraydestroy.body: 2867 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2868 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2869 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2870 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 2871 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 2872 // CHECK12: arraydestroy.done8: 2873 // CHECK12-NEXT: ret void 2874 // 2875 // 2876 // CHECK12-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2877 // CHECK12-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2878 // CHECK12-NEXT: entry: 2879 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2880 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2881 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2882 // CHECK12-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2883 // CHECK12-NEXT: ret void 2884 // 2885 // 2886 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2887 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2888 // CHECK12-NEXT: entry: 2889 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2890 // CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2891 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2892 // CHECK12-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2893 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2894 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2895 // CHECK12-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2896 // CHECK12-NEXT: ret void 2897 // 2898 // 2899 // CHECK12-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2900 // CHECK12-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2901 // CHECK12-NEXT: entry: 2902 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2903 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2904 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2905 // CHECK12-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 2906 // CHECK12-NEXT: ret void 2907 // 2908 // 2909 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2910 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2911 // CHECK12-NEXT: entry: 2912 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2913 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2914 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2915 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2916 // CHECK12-NEXT: ret void 2917 // 2918 // 2919 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 2920 // CHECK12-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { 2921 // CHECK12-NEXT: entry: 2922 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2923 // CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2924 // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2925 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2926 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 2927 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2928 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2929 // CHECK12-NEXT: ret void 2930 // 2931 // 2932 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 2933 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { 2934 // CHECK12-NEXT: entry: 2935 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2936 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2937 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2938 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2939 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2940 // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2941 // CHECK12-NEXT: ret void 2942 // 2943 // 2944 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2945 // CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { 2946 // CHECK12-NEXT: entry: 2947 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2948 // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2949 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 2950 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 2951 // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 2952 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 2953 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2954 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2955 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2956 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 2957 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 2958 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 2959 // CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2960 // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 128 2961 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2962 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2963 // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2964 // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2965 // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2966 // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2967 // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 2968 // CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2969 // CHECK12-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 2970 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 2971 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2972 // CHECK12-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 2973 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 2974 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2975 // CHECK12-NEXT: store i8* null, i8** [[TMP5]], align 4 2976 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2977 // CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 2978 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 4 2979 // CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2980 // CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 2981 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 4 2982 // CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2983 // CHECK12-NEXT: store i8* null, i8** [[TMP10]], align 4 2984 // CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2985 // CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 2986 // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 4 2987 // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2988 // CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 2989 // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 4 2990 // CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2991 // CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 2992 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2993 // CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 2994 // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 4 2995 // CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2996 // CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 2997 // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 4 2998 // CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2999 // CHECK12-NEXT: store i8* null, i8** [[TMP20]], align 4 3000 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3001 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3002 // CHECK12-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3003 // CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 3004 // CHECK12-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3005 // CHECK12: omp_offload.failed: 3006 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 3007 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 3008 // CHECK12: omp_offload.cont: 3009 // CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 3010 // CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 3011 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 4 3012 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 3013 // CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 3014 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 4 3015 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 3016 // CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 3017 // CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 3018 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 3019 // CHECK12-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3020 // CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 3021 // CHECK12-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 3022 // CHECK12: omp_offload.failed4: 3023 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 3024 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT5]] 3025 // CHECK12: omp_offload.cont5: 3026 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 3027 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 3028 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3029 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3030 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3031 // CHECK12: arraydestroy.body: 3032 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3033 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3034 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3035 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3036 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 3037 // CHECK12: arraydestroy.done6: 3038 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 3039 // CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 3040 // CHECK12-NEXT: ret i32 [[TMP35]] 3041 // 3042 // 3043 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3044 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3045 // CHECK12-NEXT: entry: 3046 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3047 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3048 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3049 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3050 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3051 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3052 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 3053 // CHECK12-NEXT: ret void 3054 // 3055 // 3056 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3057 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3058 // CHECK12-NEXT: entry: 3059 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3060 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3061 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3062 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3063 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3064 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3065 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3066 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3067 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3068 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3069 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 3070 // CHECK12-NEXT: ret void 3071 // 3072 // 3073 // CHECK12-LABEL: define {{[^@]+}}@_ZN2StC2Ev 3074 // CHECK12-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3075 // CHECK12-NEXT: entry: 3076 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3077 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3078 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3079 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 3080 // CHECK12-NEXT: store i32 0, i32* [[A]], align 4 3081 // CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 3082 // CHECK12-NEXT: store i32 0, i32* [[B]], align 4 3083 // CHECK12-NEXT: ret void 3084 // 3085 // 3086 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 3087 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3088 // CHECK12-NEXT: entry: 3089 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3090 // CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 3091 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3092 // CHECK12-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 3093 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3094 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3095 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 3096 // CHECK12-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 3097 // CHECK12-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 3098 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3099 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3100 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 3101 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 3102 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 3103 // CHECK12-NEXT: ret void 3104 // 3105 // 3106 // CHECK12-LABEL: define {{[^@]+}}@_ZN2StD2Ev 3107 // CHECK12-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3108 // CHECK12-NEXT: entry: 3109 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3110 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3111 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3112 // CHECK12-NEXT: ret void 3113 // 3114 // 3115 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3116 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3117 // CHECK12-NEXT: entry: 3118 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3119 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3120 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3121 // CHECK12-NEXT: ret void 3122 // 3123 // 3124 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3125 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3126 // CHECK12-NEXT: entry: 3127 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3128 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3129 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3130 // CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3131 // CHECK12-NEXT: ret void 3132 // 3133 // 3134 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3135 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3136 // CHECK12-NEXT: entry: 3137 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3138 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3139 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3140 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3141 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3142 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3143 // CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3144 // CHECK12-NEXT: ret void 3145 // 3146 // 3147 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 3148 // CHECK12-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 3149 // CHECK12-NEXT: entry: 3150 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 3151 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3152 // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3153 // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3154 // CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3155 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 3156 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3157 // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3158 // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3159 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 3160 // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3161 // CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3162 // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3163 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 3164 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 3165 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 3166 // CHECK12-NEXT: ret void 3167 // 3168 // 3169 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 3170 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 3171 // CHECK12-NEXT: entry: 3172 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3173 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3174 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3175 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 3176 // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3177 // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3178 // CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3179 // CHECK12-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 3180 // CHECK12-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 3181 // CHECK12-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3182 // CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 3183 // CHECK12-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3184 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3185 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3186 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3187 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 3188 // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3189 // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3190 // CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3191 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 3192 // CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3193 // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3194 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 3195 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 3196 // CHECK12-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 3197 // CHECK12-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3198 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) 3199 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3200 // CHECK12-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 3201 // CHECK12-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3202 // CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 3203 // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3204 // CHECK12: omp.arraycpy.body: 3205 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3206 // CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3207 // CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3208 // CHECK12-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 3209 // CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 3210 // CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3211 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3212 // CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 3213 // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3214 // CHECK12: omp.arraycpy.done4: 3215 // CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3216 // CHECK12-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 3217 // CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 3218 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 3219 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 3220 // CHECK12-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 3221 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3222 // CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 3223 // CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 3224 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) 3225 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 3226 // CHECK12-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3227 // CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 3228 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3229 // CHECK12: arraydestroy.body: 3230 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3231 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3232 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3233 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 3234 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 3235 // CHECK12: arraydestroy.done9: 3236 // CHECK12-NEXT: ret void 3237 // 3238 // 3239 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3240 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3241 // CHECK12-NEXT: entry: 3242 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3243 // CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3244 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3245 // CHECK12-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3246 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3247 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3248 // CHECK12-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 3249 // CHECK12-NEXT: ret void 3250 // 3251 // 3252 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3253 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3254 // CHECK12-NEXT: entry: 3255 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3256 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3257 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3258 // CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 3259 // CHECK12-NEXT: ret void 3260 // 3261 // 3262 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 3263 // CHECK12-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 3264 // CHECK12-NEXT: entry: 3265 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 3266 // CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3267 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 3268 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 3269 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 3270 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 3271 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 3272 // CHECK12-NEXT: ret void 3273 // 3274 // 3275 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 3276 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 3277 // CHECK12-NEXT: entry: 3278 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3279 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3280 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 3281 // CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3282 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3283 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3284 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 3285 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 3286 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 3287 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 3288 // CHECK12-NEXT: ret void 3289 // 3290 // 3291 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3292 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3293 // CHECK12-NEXT: entry: 3294 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3295 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3296 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3297 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3298 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3299 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3300 // CHECK12-NEXT: ret void 3301 // 3302 // 3303 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3304 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3305 // CHECK12-NEXT: entry: 3306 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3307 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3308 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3309 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3310 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3311 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3312 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3313 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3314 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3315 // CHECK12-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3316 // CHECK12-NEXT: ret void 3317 // 3318 // 3319 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 3320 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3321 // CHECK12-NEXT: entry: 3322 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3323 // CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3324 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3325 // CHECK12-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3326 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3327 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3328 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3329 // CHECK12-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 3330 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 3331 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3332 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3333 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 3334 // CHECK12-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3335 // CHECK12-NEXT: ret void 3336 // 3337 // 3338 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3339 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3340 // CHECK12-NEXT: entry: 3341 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3342 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3343 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3344 // CHECK12-NEXT: ret void 3345 // 3346 // 3347 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3348 // CHECK12-SAME: () #[[ATTR6:[0-9]+]] { 3349 // CHECK12-NEXT: entry: 3350 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) 3351 // CHECK12-NEXT: ret void 3352 // 3353 // 3354 // CHECK13-LABEL: define {{[^@]+}}@main 3355 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { 3356 // CHECK13-NEXT: entry: 3357 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3358 // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3359 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3360 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3361 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3362 // CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 3363 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 3364 // CHECK13-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 3365 // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 4 3366 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3367 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 3368 // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 3369 // CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 3370 // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 3371 // CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 3372 // CHECK13-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 3373 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 3374 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 3375 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3376 // CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 3377 // CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 3378 // CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* 3379 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) 3380 // CHECK13-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 3381 // CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 3382 // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3383 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] 3384 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3385 // CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 3386 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3387 // CHECK13: arraydestroy.body: 3388 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3389 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3390 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3391 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3392 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 3393 // CHECK13: arraydestroy.done2: 3394 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 3395 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 3396 // CHECK13-NEXT: ret i32 [[TMP5]] 3397 // 3398 // 3399 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3400 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3401 // CHECK13-NEXT: entry: 3402 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3403 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3404 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3405 // CHECK13-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3406 // CHECK13-NEXT: ret void 3407 // 3408 // 3409 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3410 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3411 // CHECK13-NEXT: entry: 3412 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3413 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3414 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3415 // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3416 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3417 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3418 // CHECK13-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3419 // CHECK13-NEXT: ret void 3420 // 3421 // 3422 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3423 // CHECK13-SAME: () #[[ATTR3:[0-9]+]] comdat { 3424 // CHECK13-NEXT: entry: 3425 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3426 // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3427 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 3428 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 3429 // CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 3430 // CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 3431 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3432 // CHECK13-NEXT: store i32 0, i32* [[T_VAR]], align 128 3433 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3434 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3435 // CHECK13-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3436 // CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 3437 // CHECK13-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3438 // CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 3439 // CHECK13-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) 3440 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 3441 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 3442 // CHECK13-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 3443 // CHECK13-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3444 // CHECK13-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 3445 // CHECK13-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 3446 // CHECK13-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) 3447 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 3448 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 3449 // CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3450 // CHECK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3451 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3452 // CHECK13: arraydestroy.body: 3453 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3454 // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3455 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3456 // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3457 // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 3458 // CHECK13: arraydestroy.done2: 3459 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 3460 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 3461 // CHECK13-NEXT: ret i32 [[TMP5]] 3462 // 3463 // 3464 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3465 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3466 // CHECK13-NEXT: entry: 3467 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3468 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3469 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3470 // CHECK13-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 3471 // CHECK13-NEXT: ret void 3472 // 3473 // 3474 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3475 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3476 // CHECK13-NEXT: entry: 3477 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3478 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3479 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3480 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3481 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3482 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3483 // CHECK13-NEXT: store float [[CONV]], float* [[F]], align 4 3484 // CHECK13-NEXT: ret void 3485 // 3486 // 3487 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3488 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3489 // CHECK13-NEXT: entry: 3490 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3491 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3492 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3493 // CHECK13-NEXT: ret void 3494 // 3495 // 3496 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3497 // CHECK13-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3498 // CHECK13-NEXT: entry: 3499 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3500 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3501 // CHECK13-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3502 // CHECK13-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3503 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3504 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3505 // CHECK13-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3506 // CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3507 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3508 // CHECK13-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3509 // CHECK13-NEXT: store float [[ADD]], float* [[F]], align 4 3510 // CHECK13-NEXT: ret void 3511 // 3512 // 3513 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3514 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3515 // CHECK13-NEXT: entry: 3516 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3517 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3518 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3519 // CHECK13-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3520 // CHECK13-NEXT: ret void 3521 // 3522 // 3523 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3524 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3525 // CHECK13-NEXT: entry: 3526 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3527 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3528 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3529 // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3530 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3531 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3532 // CHECK13-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 3533 // CHECK13-NEXT: ret void 3534 // 3535 // 3536 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3537 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3538 // CHECK13-NEXT: entry: 3539 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3540 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3541 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3542 // CHECK13-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 3543 // CHECK13-NEXT: ret void 3544 // 3545 // 3546 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3547 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3548 // CHECK13-NEXT: entry: 3549 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3550 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3551 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3552 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3553 // CHECK13-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3554 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3555 // CHECK13-NEXT: ret void 3556 // 3557 // 3558 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3559 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3560 // CHECK13-NEXT: entry: 3561 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3562 // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3563 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3564 // CHECK13-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3565 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3566 // CHECK13-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3567 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3568 // CHECK13-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3569 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3570 // CHECK13-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3571 // CHECK13-NEXT: ret void 3572 // 3573 // 3574 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3575 // CHECK13-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3576 // CHECK13-NEXT: entry: 3577 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3578 // CHECK13-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3579 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3580 // CHECK13-NEXT: ret void 3581 // 3582 // 3583 // CHECK14-LABEL: define {{[^@]+}}@main 3584 // CHECK14-SAME: () #[[ATTR0:[0-9]+]] { 3585 // CHECK14-NEXT: entry: 3586 // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3587 // CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3588 // CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3589 // CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3590 // CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3591 // CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 3592 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 3593 // CHECK14-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 3594 // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 4 3595 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3596 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 3597 // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 3598 // CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 3599 // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 3600 // CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 3601 // CHECK14-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 3602 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 3603 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 3604 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3605 // CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 3606 // CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 3607 // CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* 3608 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) 3609 // CHECK14-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 3610 // CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 3611 // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3612 // CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] 3613 // CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3614 // CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 3615 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3616 // CHECK14: arraydestroy.body: 3617 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3618 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3619 // CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3620 // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3621 // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 3622 // CHECK14: arraydestroy.done2: 3623 // CHECK14-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 3624 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 3625 // CHECK14-NEXT: ret i32 [[TMP5]] 3626 // 3627 // 3628 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3629 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3630 // CHECK14-NEXT: entry: 3631 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3632 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3633 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3634 // CHECK14-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3635 // CHECK14-NEXT: ret void 3636 // 3637 // 3638 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3639 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3640 // CHECK14-NEXT: entry: 3641 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3642 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3643 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3644 // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3645 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3646 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3647 // CHECK14-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3648 // CHECK14-NEXT: ret void 3649 // 3650 // 3651 // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3652 // CHECK14-SAME: () #[[ATTR3:[0-9]+]] comdat { 3653 // CHECK14-NEXT: entry: 3654 // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3655 // CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3656 // CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 3657 // CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 3658 // CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 3659 // CHECK14-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 3660 // CHECK14-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3661 // CHECK14-NEXT: store i32 0, i32* [[T_VAR]], align 128 3662 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3663 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3664 // CHECK14-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3665 // CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 3666 // CHECK14-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3667 // CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 3668 // CHECK14-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) 3669 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 3670 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 3671 // CHECK14-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 3672 // CHECK14-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3673 // CHECK14-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 3674 // CHECK14-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 3675 // CHECK14-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i64 4, i1 false) 3676 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 3677 // CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 3678 // CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3679 // CHECK14-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3680 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3681 // CHECK14: arraydestroy.body: 3682 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3683 // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3684 // CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3685 // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3686 // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 3687 // CHECK14: arraydestroy.done2: 3688 // CHECK14-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 3689 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 3690 // CHECK14-NEXT: ret i32 [[TMP5]] 3691 // 3692 // 3693 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3694 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3695 // CHECK14-NEXT: entry: 3696 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3697 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3698 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3699 // CHECK14-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 3700 // CHECK14-NEXT: ret void 3701 // 3702 // 3703 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3704 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3705 // CHECK14-NEXT: entry: 3706 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3707 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3708 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3709 // CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3710 // CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3711 // CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3712 // CHECK14-NEXT: store float [[CONV]], float* [[F]], align 4 3713 // CHECK14-NEXT: ret void 3714 // 3715 // 3716 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3717 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3718 // CHECK14-NEXT: entry: 3719 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3720 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3721 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3722 // CHECK14-NEXT: ret void 3723 // 3724 // 3725 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3726 // CHECK14-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3727 // CHECK14-NEXT: entry: 3728 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3729 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3730 // CHECK14-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3731 // CHECK14-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3732 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3733 // CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3734 // CHECK14-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3735 // CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3736 // CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3737 // CHECK14-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3738 // CHECK14-NEXT: store float [[ADD]], float* [[F]], align 4 3739 // CHECK14-NEXT: ret void 3740 // 3741 // 3742 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3743 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3744 // CHECK14-NEXT: entry: 3745 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3746 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3747 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3748 // CHECK14-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3749 // CHECK14-NEXT: ret void 3750 // 3751 // 3752 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3753 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3754 // CHECK14-NEXT: entry: 3755 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3756 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3757 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3758 // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3759 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3760 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3761 // CHECK14-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 3762 // CHECK14-NEXT: ret void 3763 // 3764 // 3765 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3766 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3767 // CHECK14-NEXT: entry: 3768 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3769 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3770 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3771 // CHECK14-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 3772 // CHECK14-NEXT: ret void 3773 // 3774 // 3775 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3776 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3777 // CHECK14-NEXT: entry: 3778 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3779 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3780 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3781 // CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3782 // CHECK14-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3783 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3784 // CHECK14-NEXT: ret void 3785 // 3786 // 3787 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3788 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3789 // CHECK14-NEXT: entry: 3790 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3791 // CHECK14-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3792 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3793 // CHECK14-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3794 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3795 // CHECK14-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3796 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3797 // CHECK14-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3798 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3799 // CHECK14-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3800 // CHECK14-NEXT: ret void 3801 // 3802 // 3803 // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3804 // CHECK14-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3805 // CHECK14-NEXT: entry: 3806 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3807 // CHECK14-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3808 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3809 // CHECK14-NEXT: ret void 3810 // 3811 // 3812 // CHECK15-LABEL: define {{[^@]+}}@main 3813 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { 3814 // CHECK15-NEXT: entry: 3815 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3816 // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3817 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3818 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3819 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3820 // CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 3821 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 3822 // CHECK15-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 3823 // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 4 3824 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3825 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 3826 // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3827 // CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 3828 // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 3829 // CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 3830 // CHECK15-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 3831 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 3832 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 3833 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3834 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3835 // CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 3836 // CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* 3837 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) 3838 // CHECK15-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 3839 // CHECK15-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 3840 // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3841 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] 3842 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3843 // CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 3844 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3845 // CHECK15: arraydestroy.body: 3846 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3847 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3848 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3849 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3850 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 3851 // CHECK15: arraydestroy.done2: 3852 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 3853 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 3854 // CHECK15-NEXT: ret i32 [[TMP5]] 3855 // 3856 // 3857 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3858 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3859 // CHECK15-NEXT: entry: 3860 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3861 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3862 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3863 // CHECK15-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3864 // CHECK15-NEXT: ret void 3865 // 3866 // 3867 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3868 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3869 // CHECK15-NEXT: entry: 3870 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3871 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3872 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3873 // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3874 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3875 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3876 // CHECK15-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3877 // CHECK15-NEXT: ret void 3878 // 3879 // 3880 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3881 // CHECK15-SAME: () #[[ATTR3:[0-9]+]] comdat { 3882 // CHECK15-NEXT: entry: 3883 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3884 // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3885 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 3886 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 3887 // CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 3888 // CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 3889 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3890 // CHECK15-NEXT: store i32 0, i32* [[T_VAR]], align 128 3891 // CHECK15-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3892 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 3893 // CHECK15-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3894 // CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 3895 // CHECK15-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 3896 // CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 3897 // CHECK15-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 3898 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 3899 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 3900 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 3901 // CHECK15-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3902 // CHECK15-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 3903 // CHECK15-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 3904 // CHECK15-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) 3905 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 3906 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 3907 // CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3908 // CHECK15-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3909 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3910 // CHECK15: arraydestroy.body: 3911 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3912 // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3913 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3914 // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3915 // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 3916 // CHECK15: arraydestroy.done2: 3917 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 3918 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 3919 // CHECK15-NEXT: ret i32 [[TMP5]] 3920 // 3921 // 3922 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3923 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3924 // CHECK15-NEXT: entry: 3925 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3926 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3927 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3928 // CHECK15-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 3929 // CHECK15-NEXT: ret void 3930 // 3931 // 3932 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3933 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3934 // CHECK15-NEXT: entry: 3935 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3936 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3937 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3938 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3939 // CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3940 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3941 // CHECK15-NEXT: store float [[CONV]], float* [[F]], align 4 3942 // CHECK15-NEXT: ret void 3943 // 3944 // 3945 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3946 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3947 // CHECK15-NEXT: entry: 3948 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3949 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3950 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3951 // CHECK15-NEXT: ret void 3952 // 3953 // 3954 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3955 // CHECK15-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3956 // CHECK15-NEXT: entry: 3957 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3958 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3959 // CHECK15-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3960 // CHECK15-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3961 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3962 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3963 // CHECK15-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3964 // CHECK15-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3965 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3966 // CHECK15-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3967 // CHECK15-NEXT: store float [[ADD]], float* [[F]], align 4 3968 // CHECK15-NEXT: ret void 3969 // 3970 // 3971 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3972 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3973 // CHECK15-NEXT: entry: 3974 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3975 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3976 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3977 // CHECK15-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3978 // CHECK15-NEXT: ret void 3979 // 3980 // 3981 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3982 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3983 // CHECK15-NEXT: entry: 3984 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3985 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3986 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3987 // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3988 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3989 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3990 // CHECK15-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3991 // CHECK15-NEXT: ret void 3992 // 3993 // 3994 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3995 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3996 // CHECK15-NEXT: entry: 3997 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3998 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3999 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4000 // CHECK15-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 4001 // CHECK15-NEXT: ret void 4002 // 4003 // 4004 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4005 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4006 // CHECK15-NEXT: entry: 4007 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4008 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4009 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4010 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4011 // CHECK15-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 4012 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4013 // CHECK15-NEXT: ret void 4014 // 4015 // 4016 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4017 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4018 // CHECK15-NEXT: entry: 4019 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4020 // CHECK15-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4021 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4022 // CHECK15-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4023 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4024 // CHECK15-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4025 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4026 // CHECK15-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 4027 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4028 // CHECK15-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4029 // CHECK15-NEXT: ret void 4030 // 4031 // 4032 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4033 // CHECK15-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4034 // CHECK15-NEXT: entry: 4035 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4036 // CHECK15-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4037 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4038 // CHECK15-NEXT: ret void 4039 // 4040 // 4041 // CHECK16-LABEL: define {{[^@]+}}@main 4042 // CHECK16-SAME: () #[[ATTR0:[0-9]+]] { 4043 // CHECK16-NEXT: entry: 4044 // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4045 // CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 4046 // CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 4047 // CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4048 // CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 4049 // CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 4050 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 4051 // CHECK16-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 4052 // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 4 4053 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4054 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 4055 // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 4056 // CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 4057 // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 4058 // CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 4059 // CHECK16-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 4060 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 4061 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 4062 // CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 4063 // CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 4064 // CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 4065 // CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[VAR]] to i8* 4066 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i32 4, i1 false) 4067 // CHECK16-NEXT: store i32 2, i32* @_ZZ4mainE5sivar, align 4 4068 // CHECK16-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 4069 // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 4070 // CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] 4071 // CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 4072 // CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 4073 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4074 // CHECK16: arraydestroy.body: 4075 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4076 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4077 // CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 4078 // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4079 // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 4080 // CHECK16: arraydestroy.done2: 4081 // CHECK16-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 4082 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 4083 // CHECK16-NEXT: ret i32 [[TMP5]] 4084 // 4085 // 4086 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4087 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4088 // CHECK16-NEXT: entry: 4089 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4090 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4091 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4092 // CHECK16-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4093 // CHECK16-NEXT: ret void 4094 // 4095 // 4096 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4097 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4098 // CHECK16-NEXT: entry: 4099 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4100 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4101 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4102 // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4103 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4104 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4105 // CHECK16-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4106 // CHECK16-NEXT: ret void 4107 // 4108 // 4109 // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4110 // CHECK16-SAME: () #[[ATTR3:[0-9]+]] comdat { 4111 // CHECK16-NEXT: entry: 4112 // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4113 // CHECK16-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4114 // CHECK16-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 4115 // CHECK16-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 4116 // CHECK16-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 4117 // CHECK16-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 4118 // CHECK16-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 4119 // CHECK16-NEXT: store i32 0, i32* [[T_VAR]], align 128 4120 // CHECK16-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4121 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 4122 // CHECK16-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4123 // CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 4124 // CHECK16-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 4125 // CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 4126 // CHECK16-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 4127 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128 4128 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 0 4129 // CHECK16-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 128 4130 // CHECK16-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4131 // CHECK16-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 4132 // CHECK16-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 4133 // CHECK16-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP2]], i8* align 128 [[TMP3]], i32 4, i1 false) 4134 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 4135 // CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 4136 // CHECK16-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4137 // CHECK16-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4138 // CHECK16-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4139 // CHECK16: arraydestroy.body: 4140 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4141 // CHECK16-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4142 // CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 4143 // CHECK16-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4144 // CHECK16-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 4145 // CHECK16: arraydestroy.done2: 4146 // CHECK16-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 4147 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 4148 // CHECK16-NEXT: ret i32 [[TMP5]] 4149 // 4150 // 4151 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4152 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4153 // CHECK16-NEXT: entry: 4154 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4155 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4156 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4157 // CHECK16-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 4158 // CHECK16-NEXT: ret void 4159 // 4160 // 4161 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4162 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4163 // CHECK16-NEXT: entry: 4164 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4165 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4166 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4167 // CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4168 // CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 4169 // CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4170 // CHECK16-NEXT: store float [[CONV]], float* [[F]], align 4 4171 // CHECK16-NEXT: ret void 4172 // 4173 // 4174 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4175 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4176 // CHECK16-NEXT: entry: 4177 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4178 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4179 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4180 // CHECK16-NEXT: ret void 4181 // 4182 // 4183 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4184 // CHECK16-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4185 // CHECK16-NEXT: entry: 4186 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4187 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4188 // CHECK16-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4189 // CHECK16-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4190 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4191 // CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4192 // CHECK16-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4193 // CHECK16-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 4194 // CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4195 // CHECK16-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4196 // CHECK16-NEXT: store float [[ADD]], float* [[F]], align 4 4197 // CHECK16-NEXT: ret void 4198 // 4199 // 4200 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4201 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4202 // CHECK16-NEXT: entry: 4203 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4204 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4205 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4206 // CHECK16-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 4207 // CHECK16-NEXT: ret void 4208 // 4209 // 4210 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4211 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4212 // CHECK16-NEXT: entry: 4213 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4214 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4215 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4216 // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4217 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4218 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4219 // CHECK16-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 4220 // CHECK16-NEXT: ret void 4221 // 4222 // 4223 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4224 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4225 // CHECK16-NEXT: entry: 4226 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4227 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4228 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4229 // CHECK16-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 4230 // CHECK16-NEXT: ret void 4231 // 4232 // 4233 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4234 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4235 // CHECK16-NEXT: entry: 4236 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4237 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4238 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4239 // CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4240 // CHECK16-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 4241 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4242 // CHECK16-NEXT: ret void 4243 // 4244 // 4245 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4246 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4247 // CHECK16-NEXT: entry: 4248 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4249 // CHECK16-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4250 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4251 // CHECK16-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4252 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4253 // CHECK16-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4254 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4255 // CHECK16-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 4256 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4257 // CHECK16-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4258 // CHECK16-NEXT: ret void 4259 // 4260 // 4261 // CHECK16-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4262 // CHECK16-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4263 // CHECK16-NEXT: entry: 4264 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4265 // CHECK16-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4266 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4267 // CHECK16-NEXT: ret void 4268 // 4269 // 4270 // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg 4271 // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 4272 // CHECK17-NEXT: entry: 4273 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4274 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4275 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4276 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4277 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4278 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4279 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4280 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4281 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 8 4282 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 8 4283 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 8 4284 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 4285 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4286 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4287 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4288 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4289 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4290 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 4291 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4292 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 4293 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4294 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 4295 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 4296 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 4297 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4298 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 4299 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 4300 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 4301 // CHECK17-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 4302 // CHECK17-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4303 // CHECK17-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4304 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 4305 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 4306 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 4307 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 4308 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4309 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 4310 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4311 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** 4312 // CHECK17-NEXT: store float* [[TMP8]], float** [[TMP16]], align 8 4313 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4314 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to float** 4315 // CHECK17-NEXT: store float* [[TMP8]], float** [[TMP18]], align 8 4316 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4317 // CHECK17-NEXT: store i64 0, i64* [[TMP19]], align 8 4318 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4319 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 4320 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4321 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 4322 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP22]], align 8 4323 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4324 // CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** 4325 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 4326 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4327 // CHECK17-NEXT: store i64 0, i64* [[TMP25]], align 8 4328 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4329 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 4330 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4331 // CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 4332 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP28]], align 8 4333 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4334 // CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 4335 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP30]], align 8 4336 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4337 // CHECK17-NEXT: store i64 8, i64* [[TMP31]], align 8 4338 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4339 // CHECK17-NEXT: store i8* null, i8** [[TMP32]], align 8 4340 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4341 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** 4342 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 4343 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4344 // CHECK17-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to ppc_fp128** 4345 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP36]], align 8 4346 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4347 // CHECK17-NEXT: store i64 0, i64* [[TMP37]], align 8 4348 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4349 // CHECK17-NEXT: store i8* null, i8** [[TMP38]], align 8 4350 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4351 // CHECK17-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i64* 4352 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP40]], align 8 4353 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4354 // CHECK17-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* 4355 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP42]], align 8 4356 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4357 // CHECK17-NEXT: store i64 8, i64* [[TMP43]], align 8 4358 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4359 // CHECK17-NEXT: store i8* null, i8** [[TMP44]], align 8 4360 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4361 // CHECK17-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 4362 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP46]], align 8 4363 // CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4364 // CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 4365 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP48]], align 8 4366 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 4367 // CHECK17-NEXT: store i64 8, i64* [[TMP49]], align 8 4368 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4369 // CHECK17-NEXT: store i8* null, i8** [[TMP50]], align 8 4370 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 4371 // CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** 4372 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP52]], align 8 4373 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 4374 // CHECK17-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** 4375 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP54]], align 8 4376 // CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 4377 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP55]], align 8 4378 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 4379 // CHECK17-NEXT: store i8* null, i8** [[TMP56]], align 8 4380 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 4381 // CHECK17-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* 4382 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP58]], align 8 4383 // CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 4384 // CHECK17-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* 4385 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP60]], align 8 4386 // CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 4387 // CHECK17-NEXT: store i64 4, i64* [[TMP61]], align 8 4388 // CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 4389 // CHECK17-NEXT: store i8* null, i8** [[TMP62]], align 8 4390 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4391 // CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4392 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4393 // CHECK17-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, i32 8, i8** [[TMP63]], i8** [[TMP64]], i64* [[TMP65]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4394 // CHECK17-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 4395 // CHECK17-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4396 // CHECK17: omp_offload.failed: 4397 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(float* [[TMP8]], %struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 4398 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 4399 // CHECK17: omp_offload.cont: 4400 // CHECK17-NEXT: [[TMP68:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4401 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP68]]) 4402 // CHECK17-NEXT: ret void 4403 // 4404 // 4405 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 4406 // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 4407 // CHECK17-NEXT: entry: 4408 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4409 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4410 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4411 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4412 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4413 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4414 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4415 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4416 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4417 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4418 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4419 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4420 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4421 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4422 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4423 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 4424 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4425 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4426 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4427 // CHECK17-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4428 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 4429 // CHECK17-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4430 // CHECK17-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4431 // CHECK17-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 8 4432 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, ppc_fp128*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[CONV]], i64 [[TMP0]], ppc_fp128* [[TMP5]], float* [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]]) 4433 // CHECK17-NEXT: ret void 4434 // 4435 // 4436 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 4437 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 4438 // CHECK17-NEXT: entry: 4439 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4440 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4441 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4442 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 4443 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4444 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4445 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4446 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4447 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4448 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4449 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4450 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4451 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4452 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4453 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4454 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4455 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 4456 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4457 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4458 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4459 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4460 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4461 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4462 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 4463 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4464 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4465 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4466 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4467 // CHECK17-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 4468 // CHECK17-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 4469 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4470 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 4471 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 4472 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 4473 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4474 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 4475 // CHECK17-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 4476 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 4477 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) 4478 // CHECK17-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4479 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 4480 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4481 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 4482 // CHECK17-NEXT: [[TMP14:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4483 // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 signext [[TMP13]], ppc_fp128* [[TMP14]]) 4484 // CHECK17-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4485 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 4486 // CHECK17-NEXT: ret void 4487 // 4488 // 4489 // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg 4490 // CHECK17-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 4491 // CHECK17-NEXT: entry: 4492 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 4493 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4494 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4495 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4496 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4497 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4498 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4499 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4500 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 8 4501 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 8 4502 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 8 4503 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 4504 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 4505 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4506 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4507 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4508 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 4509 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4510 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 4511 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4512 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 4513 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4514 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 4515 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 4516 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 4517 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4518 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 4519 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 4520 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 4521 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 4522 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 4523 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 4524 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 4525 // CHECK17-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4526 // CHECK17-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4527 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 4528 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 4529 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 4530 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 4531 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4532 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 4533 // CHECK17-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 4534 // CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 4535 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr i32, i32* [[B2]], i32 1 4536 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i32* [[A3]] to i8* 4537 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP15]] to i8* 4538 // CHECK17-NEXT: [[TMP18:%.*]] = ptrtoint i8* [[TMP17]] to i64 4539 // CHECK17-NEXT: [[TMP19:%.*]] = ptrtoint i8* [[TMP16]] to i64 4540 // CHECK17-NEXT: [[TMP20:%.*]] = sub i64 [[TMP18]], [[TMP19]] 4541 // CHECK17-NEXT: [[TMP21:%.*]] = sdiv exact i64 [[TMP20]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 4542 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4543 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** 4544 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP23]], align 8 4545 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4546 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.St** 4547 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP25]], align 8 4548 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4549 // CHECK17-NEXT: store i64 0, i64* [[TMP26]], align 8 4550 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4551 // CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 4552 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4553 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 4554 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 4555 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4556 // CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 4557 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP31]], align 8 4558 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4559 // CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 4560 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4561 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 4562 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4563 // CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to ppc_fp128** 4564 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP35]], align 8 4565 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4566 // CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to ppc_fp128** 4567 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP37]], align 8 4568 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4569 // CHECK17-NEXT: store i64 0, i64* [[TMP38]], align 8 4570 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4571 // CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 4572 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4573 // CHECK17-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 4574 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP41]], align 8 4575 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4576 // CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* 4577 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP43]], align 8 4578 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4579 // CHECK17-NEXT: store i64 8, i64* [[TMP44]], align 8 4580 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4581 // CHECK17-NEXT: store i8* null, i8** [[TMP45]], align 8 4582 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4583 // CHECK17-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64* 4584 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP47]], align 8 4585 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4586 // CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64* 4587 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP49]], align 8 4588 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4589 // CHECK17-NEXT: store i64 8, i64* [[TMP50]], align 8 4590 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4591 // CHECK17-NEXT: store i8* null, i8** [[TMP51]], align 8 4592 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4593 // CHECK17-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** 4594 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP53]], align 8 4595 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4596 // CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** 4597 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP55]], align 8 4598 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 4599 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP56]], align 8 4600 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4601 // CHECK17-NEXT: store i8* null, i8** [[TMP57]], align 8 4602 // CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 4603 // CHECK17-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to %struct.St** 4604 // CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP59]], align 8 4605 // CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 4606 // CHECK17-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32** 4607 // CHECK17-NEXT: store i32* [[A3]], i32** [[TMP61]], align 8 4608 // CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 4609 // CHECK17-NEXT: store i64 [[TMP21]], i64* [[TMP62]], align 8 4610 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 4611 // CHECK17-NEXT: store i8* null, i8** [[TMP63]], align 8 4612 // CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 4613 // CHECK17-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to %struct.St** 4614 // CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP65]], align 8 4615 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 4616 // CHECK17-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32** 4617 // CHECK17-NEXT: store i32* [[B2]], i32** [[TMP67]], align 8 4618 // CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 4619 // CHECK17-NEXT: store i64 4, i64* [[TMP68]], align 8 4620 // CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 4621 // CHECK17-NEXT: store i8* null, i8** [[TMP69]], align 8 4622 // CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 4623 // CHECK17-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to %struct.St** 4624 // CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP71]], align 8 4625 // CHECK17-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 4626 // CHECK17-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32** 4627 // CHECK17-NEXT: store i32* [[A3]], i32** [[TMP73]], align 8 4628 // CHECK17-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 4629 // CHECK17-NEXT: store i64 4, i64* [[TMP74]], align 8 4630 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 4631 // CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8 4632 // CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 4633 // CHECK17-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* 4634 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP77]], align 8 4635 // CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 4636 // CHECK17-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 4637 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP79]], align 8 4638 // CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 4639 // CHECK17-NEXT: store i64 4, i64* [[TMP80]], align 8 4640 // CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 4641 // CHECK17-NEXT: store i8* null, i8** [[TMP81]], align 8 4642 // CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4643 // CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4644 // CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4645 // CHECK17-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, i32 10, i8** [[TMP82]], i8** [[TMP83]], i64* [[TMP84]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4646 // CHECK17-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 4647 // CHECK17-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4648 // CHECK17: omp_offload.failed: 4649 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(%struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], %struct.St* [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] 4650 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 4651 // CHECK17: omp_offload.cont: 4652 // CHECK17-NEXT: [[TMP87:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4653 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP87]]) 4654 // CHECK17-NEXT: ret void 4655 // 4656 // 4657 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 4658 // CHECK17-SAME: (%struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { 4659 // CHECK17-NEXT: entry: 4660 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4661 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4662 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4663 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4664 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4665 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4666 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 4667 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4668 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4669 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4670 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4671 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4672 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4673 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4674 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 4675 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 4676 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4677 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4678 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4679 // CHECK17-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4680 // CHECK17-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 4681 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 4682 // CHECK17-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4683 // CHECK17-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4684 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, ppc_fp128*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP0]], ppc_fp128* [[TMP5]], %struct.St* [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]], i32* [[CONV]], %struct.St* [[TMP6]]) 4685 // CHECK17-NEXT: ret void 4686 // 4687 // 4688 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 4689 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 4690 // CHECK17-NEXT: entry: 4691 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4692 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4693 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4694 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4695 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 4696 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4697 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4698 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4699 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 4700 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4701 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4702 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4703 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4704 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4705 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4706 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4707 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4708 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 4709 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4710 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4711 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4712 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 4713 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4714 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4715 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 4716 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4717 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4718 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4719 // CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 4720 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 4721 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 4722 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4723 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 4724 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 4725 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 4726 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4727 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 4728 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 4729 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 4730 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 [[TMP9]], i1 false) 4731 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 4732 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 4733 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 4734 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 4735 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 4736 // CHECK17-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP3]] 4737 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i64 [[TMP13]] 4738 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 4739 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 4740 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 4741 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] 4742 // CHECK17-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 4743 // CHECK17-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 4744 // CHECK17-NEXT: [[TMP15:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4745 // CHECK17-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 4746 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 4747 // CHECK17-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 4748 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP15]], i64 [[IDXPROM11]] 4749 // CHECK17-NEXT: store ppc_fp128 [[CONV9]], ppc_fp128* [[ARRAYIDX12]], align 16 4750 // CHECK17-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4751 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 4752 // CHECK17-NEXT: ret void 4753 // 4754 // 4755 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4756 // CHECK17-SAME: () #[[ATTR5:[0-9]+]] { 4757 // CHECK17-NEXT: entry: 4758 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 4759 // CHECK17-NEXT: ret void 4760 // 4761 // 4762 // CHECK18-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg 4763 // CHECK18-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 4764 // CHECK18-NEXT: entry: 4765 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4766 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4767 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4768 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4769 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4770 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4771 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4772 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4773 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 8 4774 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 8 4775 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 8 4776 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 4777 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4778 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4779 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4780 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4781 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4782 // CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 4783 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4784 // CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 4785 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4786 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 4787 // CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 4788 // CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 4789 // CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4790 // CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 4791 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 4792 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 4793 // CHECK18-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 4794 // CHECK18-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4795 // CHECK18-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4796 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 4797 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 4798 // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 4799 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 4800 // CHECK18-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4801 // CHECK18-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 4802 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4803 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** 4804 // CHECK18-NEXT: store float* [[TMP8]], float** [[TMP16]], align 8 4805 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4806 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to float** 4807 // CHECK18-NEXT: store float* [[TMP8]], float** [[TMP18]], align 8 4808 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4809 // CHECK18-NEXT: store i64 0, i64* [[TMP19]], align 8 4810 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4811 // CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 4812 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4813 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 4814 // CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP22]], align 8 4815 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4816 // CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** 4817 // CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 4818 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4819 // CHECK18-NEXT: store i64 0, i64* [[TMP25]], align 8 4820 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4821 // CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 4822 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4823 // CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 4824 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP28]], align 8 4825 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4826 // CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 4827 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP30]], align 8 4828 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4829 // CHECK18-NEXT: store i64 8, i64* [[TMP31]], align 8 4830 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4831 // CHECK18-NEXT: store i8* null, i8** [[TMP32]], align 8 4832 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4833 // CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** 4834 // CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 4835 // CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4836 // CHECK18-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to ppc_fp128** 4837 // CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP36]], align 8 4838 // CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4839 // CHECK18-NEXT: store i64 0, i64* [[TMP37]], align 8 4840 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4841 // CHECK18-NEXT: store i8* null, i8** [[TMP38]], align 8 4842 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4843 // CHECK18-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i64* 4844 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP40]], align 8 4845 // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4846 // CHECK18-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* 4847 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP42]], align 8 4848 // CHECK18-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4849 // CHECK18-NEXT: store i64 8, i64* [[TMP43]], align 8 4850 // CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4851 // CHECK18-NEXT: store i8* null, i8** [[TMP44]], align 8 4852 // CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4853 // CHECK18-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 4854 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP46]], align 8 4855 // CHECK18-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4856 // CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 4857 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP48]], align 8 4858 // CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 4859 // CHECK18-NEXT: store i64 8, i64* [[TMP49]], align 8 4860 // CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4861 // CHECK18-NEXT: store i8* null, i8** [[TMP50]], align 8 4862 // CHECK18-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 4863 // CHECK18-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** 4864 // CHECK18-NEXT: store double* [[VLA]], double** [[TMP52]], align 8 4865 // CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 4866 // CHECK18-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** 4867 // CHECK18-NEXT: store double* [[VLA]], double** [[TMP54]], align 8 4868 // CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 4869 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP55]], align 8 4870 // CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 4871 // CHECK18-NEXT: store i8* null, i8** [[TMP56]], align 8 4872 // CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 4873 // CHECK18-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* 4874 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP58]], align 8 4875 // CHECK18-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 4876 // CHECK18-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* 4877 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP60]], align 8 4878 // CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 4879 // CHECK18-NEXT: store i64 4, i64* [[TMP61]], align 8 4880 // CHECK18-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 4881 // CHECK18-NEXT: store i8* null, i8** [[TMP62]], align 8 4882 // CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4883 // CHECK18-NEXT: [[TMP64:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4884 // CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4885 // CHECK18-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, i32 8, i8** [[TMP63]], i8** [[TMP64]], i64* [[TMP65]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4886 // CHECK18-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 4887 // CHECK18-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4888 // CHECK18: omp_offload.failed: 4889 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(float* [[TMP8]], %struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 4890 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 4891 // CHECK18: omp_offload.cont: 4892 // CHECK18-NEXT: [[TMP68:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4893 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP68]]) 4894 // CHECK18-NEXT: ret void 4895 // 4896 // 4897 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 4898 // CHECK18-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 4899 // CHECK18-NEXT: entry: 4900 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4901 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4902 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4903 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4904 // CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4905 // CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4906 // CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4907 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4908 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4909 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4910 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4911 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4912 // CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4913 // CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4914 // CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4915 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 4916 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4917 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4918 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4919 // CHECK18-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4920 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 4921 // CHECK18-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4922 // CHECK18-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4923 // CHECK18-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 8 4924 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, ppc_fp128*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[CONV]], i64 [[TMP0]], ppc_fp128* [[TMP5]], float* [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]]) 4925 // CHECK18-NEXT: ret void 4926 // 4927 // 4928 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 4929 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 4930 // CHECK18-NEXT: entry: 4931 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4932 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4933 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4934 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 4935 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4936 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4937 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4938 // CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4939 // CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4940 // CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4941 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4942 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4943 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4944 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4945 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4946 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4947 // CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 4948 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4949 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4950 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4951 // CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4952 // CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4953 // CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4954 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 4955 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4956 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4957 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4958 // CHECK18-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4959 // CHECK18-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 4960 // CHECK18-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 4961 // CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4962 // CHECK18-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 4963 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 4964 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 4965 // CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4966 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 4967 // CHECK18-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 4968 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 4969 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) 4970 // CHECK18-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4971 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 4972 // CHECK18-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4973 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 4974 // CHECK18-NEXT: [[TMP14:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4975 // CHECK18-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 signext [[TMP13]], ppc_fp128* [[TMP14]]) 4976 // CHECK18-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4977 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 4978 // CHECK18-NEXT: ret void 4979 // 4980 // 4981 // CHECK18-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg 4982 // CHECK18-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 4983 // CHECK18-NEXT: entry: 4984 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 4985 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4986 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4987 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4988 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4989 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4990 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4991 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4992 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 8 4993 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 8 4994 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 8 4995 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 4996 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 4997 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4998 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4999 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 5000 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 5001 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5002 // CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 5003 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5004 // CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 5005 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5006 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 5007 // CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 5008 // CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 5009 // CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 5010 // CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 5011 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 5012 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 5013 // CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 5014 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 5015 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 5016 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 5017 // CHECK18-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 5018 // CHECK18-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 5019 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 5020 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 5021 // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 5022 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 5023 // CHECK18-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 5024 // CHECK18-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 5025 // CHECK18-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 5026 // CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 5027 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr i32, i32* [[B2]], i32 1 5028 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i32* [[A3]] to i8* 5029 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP15]] to i8* 5030 // CHECK18-NEXT: [[TMP18:%.*]] = ptrtoint i8* [[TMP17]] to i64 5031 // CHECK18-NEXT: [[TMP19:%.*]] = ptrtoint i8* [[TMP16]] to i64 5032 // CHECK18-NEXT: [[TMP20:%.*]] = sub i64 [[TMP18]], [[TMP19]] 5033 // CHECK18-NEXT: [[TMP21:%.*]] = sdiv exact i64 [[TMP20]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 5034 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5035 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** 5036 // CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP23]], align 8 5037 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5038 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.St** 5039 // CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP25]], align 8 5040 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5041 // CHECK18-NEXT: store i64 0, i64* [[TMP26]], align 8 5042 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 5043 // CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 5044 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5045 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 5046 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 5047 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5048 // CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 5049 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP31]], align 8 5050 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 5051 // CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 5052 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 5053 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 5054 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5055 // CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to ppc_fp128** 5056 // CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP35]], align 8 5057 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5058 // CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to ppc_fp128** 5059 // CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP37]], align 8 5060 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 5061 // CHECK18-NEXT: store i64 0, i64* [[TMP38]], align 8 5062 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 5063 // CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 5064 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5065 // CHECK18-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 5066 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP41]], align 8 5067 // CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5068 // CHECK18-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* 5069 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP43]], align 8 5070 // CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5071 // CHECK18-NEXT: store i64 8, i64* [[TMP44]], align 8 5072 // CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 5073 // CHECK18-NEXT: store i8* null, i8** [[TMP45]], align 8 5074 // CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 5075 // CHECK18-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64* 5076 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP47]], align 8 5077 // CHECK18-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 5078 // CHECK18-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64* 5079 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP49]], align 8 5080 // CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 5081 // CHECK18-NEXT: store i64 8, i64* [[TMP50]], align 8 5082 // CHECK18-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 5083 // CHECK18-NEXT: store i8* null, i8** [[TMP51]], align 8 5084 // CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 5085 // CHECK18-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** 5086 // CHECK18-NEXT: store double* [[VLA]], double** [[TMP53]], align 8 5087 // CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 5088 // CHECK18-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** 5089 // CHECK18-NEXT: store double* [[VLA]], double** [[TMP55]], align 8 5090 // CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 5091 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP56]], align 8 5092 // CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 5093 // CHECK18-NEXT: store i8* null, i8** [[TMP57]], align 8 5094 // CHECK18-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 5095 // CHECK18-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to %struct.St** 5096 // CHECK18-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP59]], align 8 5097 // CHECK18-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 5098 // CHECK18-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32** 5099 // CHECK18-NEXT: store i32* [[A3]], i32** [[TMP61]], align 8 5100 // CHECK18-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 5101 // CHECK18-NEXT: store i64 [[TMP21]], i64* [[TMP62]], align 8 5102 // CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 5103 // CHECK18-NEXT: store i8* null, i8** [[TMP63]], align 8 5104 // CHECK18-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 5105 // CHECK18-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to %struct.St** 5106 // CHECK18-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP65]], align 8 5107 // CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 5108 // CHECK18-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32** 5109 // CHECK18-NEXT: store i32* [[B2]], i32** [[TMP67]], align 8 5110 // CHECK18-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5111 // CHECK18-NEXT: store i64 4, i64* [[TMP68]], align 8 5112 // CHECK18-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 5113 // CHECK18-NEXT: store i8* null, i8** [[TMP69]], align 8 5114 // CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 5115 // CHECK18-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to %struct.St** 5116 // CHECK18-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP71]], align 8 5117 // CHECK18-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 5118 // CHECK18-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32** 5119 // CHECK18-NEXT: store i32* [[A3]], i32** [[TMP73]], align 8 5120 // CHECK18-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 5121 // CHECK18-NEXT: store i64 4, i64* [[TMP74]], align 8 5122 // CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 5123 // CHECK18-NEXT: store i8* null, i8** [[TMP75]], align 8 5124 // CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 5125 // CHECK18-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* 5126 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP77]], align 8 5127 // CHECK18-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 5128 // CHECK18-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 5129 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP79]], align 8 5130 // CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 5131 // CHECK18-NEXT: store i64 4, i64* [[TMP80]], align 8 5132 // CHECK18-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 5133 // CHECK18-NEXT: store i8* null, i8** [[TMP81]], align 8 5134 // CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5135 // CHECK18-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5136 // CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5137 // CHECK18-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, i32 10, i8** [[TMP82]], i8** [[TMP83]], i64* [[TMP84]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5138 // CHECK18-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 5139 // CHECK18-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5140 // CHECK18: omp_offload.failed: 5141 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(%struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], %struct.St* [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] 5142 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 5143 // CHECK18: omp_offload.cont: 5144 // CHECK18-NEXT: [[TMP87:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 5145 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP87]]) 5146 // CHECK18-NEXT: ret void 5147 // 5148 // 5149 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 5150 // CHECK18-SAME: (%struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { 5151 // CHECK18-NEXT: entry: 5152 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 5153 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5154 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 5155 // CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 5156 // CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 5157 // CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 5158 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 5159 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 5160 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 5161 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5162 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 5163 // CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 5164 // CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 5165 // CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 5166 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 5167 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 5168 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5169 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 5170 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 5171 // CHECK18-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 5172 // CHECK18-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 5173 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 5174 // CHECK18-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 5175 // CHECK18-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 5176 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, ppc_fp128*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP0]], ppc_fp128* [[TMP5]], %struct.St* [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]], i32* [[CONV]], %struct.St* [[TMP6]]) 5177 // CHECK18-NEXT: ret void 5178 // 5179 // 5180 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 5181 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 5182 // CHECK18-NEXT: entry: 5183 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5184 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5185 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5186 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 5187 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 5188 // CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 5189 // CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 5190 // CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 5191 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 5192 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 5193 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 5194 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 5195 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 5196 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5197 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5198 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5199 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 5200 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 5201 // CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 5202 // CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 5203 // CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 5204 // CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 5205 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 5206 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5207 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 5208 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 5209 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 5210 // CHECK18-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 5211 // CHECK18-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 5212 // CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 5213 // CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 5214 // CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 5215 // CHECK18-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 5216 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 5217 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 5218 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 5219 // CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 5220 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 5221 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 5222 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 [[TMP9]], i1 false) 5223 // CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 5224 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 5225 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 5226 // CHECK18-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 5227 // CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 5228 // CHECK18-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP3]] 5229 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i64 [[TMP13]] 5230 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 5231 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 5232 // CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 5233 // CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] 5234 // CHECK18-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 5235 // CHECK18-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 5236 // CHECK18-NEXT: [[TMP15:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 5237 // CHECK18-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 5238 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 5239 // CHECK18-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 5240 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP15]], i64 [[IDXPROM11]] 5241 // CHECK18-NEXT: store ppc_fp128 [[CONV9]], ppc_fp128* [[ARRAYIDX12]], align 16 5242 // CHECK18-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 5243 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 5244 // CHECK18-NEXT: ret void 5245 // 5246 // 5247 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5248 // CHECK18-SAME: () #[[ATTR5:[0-9]+]] { 5249 // CHECK18-NEXT: entry: 5250 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 5251 // CHECK18-NEXT: ret void 5252 // 5253 // 5254 // CHECK19-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 5255 // CHECK19-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 5256 // CHECK19-NEXT: entry: 5257 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5258 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5259 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5260 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5261 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5262 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5263 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5264 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 5265 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 4 5266 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 4 5267 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 4 5268 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 5269 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5270 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5271 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5272 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5273 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5274 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5275 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5276 // CHECK19-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 5277 // CHECK19-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 5278 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5279 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 5280 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5281 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 5282 // CHECK19-NEXT: [[TMP5:%.*]] = load float*, float** [[A_ADDR]], align 4 5283 // CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5284 // CHECK19-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5285 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 5286 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 5287 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 5288 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5289 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 5290 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 5291 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5292 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to float** 5293 // CHECK19-NEXT: store float* [[TMP5]], float** [[TMP14]], align 4 5294 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5295 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** 5296 // CHECK19-NEXT: store float* [[TMP5]], float** [[TMP16]], align 4 5297 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5298 // CHECK19-NEXT: store i64 0, i64* [[TMP17]], align 4 5299 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5300 // CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 5301 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5302 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.St** 5303 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP20]], align 4 5304 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5305 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 5306 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 5307 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 5308 // CHECK19-NEXT: store i64 0, i64* [[TMP23]], align 4 5309 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5310 // CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 5311 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5312 // CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 5313 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 5314 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5315 // CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 5316 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP28]], align 4 5317 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 5318 // CHECK19-NEXT: store i64 4, i64* [[TMP29]], align 4 5319 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5320 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 5321 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5322 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** 5323 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 5324 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5325 // CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to x86_fp80** 5326 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP34]], align 4 5327 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5328 // CHECK19-NEXT: store i64 0, i64* [[TMP35]], align 4 5329 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5330 // CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 5331 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 5332 // CHECK19-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* 5333 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP38]], align 4 5334 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 5335 // CHECK19-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* 5336 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP40]], align 4 5337 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 5338 // CHECK19-NEXT: store i64 4, i64* [[TMP41]], align 4 5339 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 5340 // CHECK19-NEXT: store i8* null, i8** [[TMP42]], align 4 5341 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 5342 // CHECK19-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* 5343 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP44]], align 4 5344 // CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 5345 // CHECK19-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* 5346 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP46]], align 4 5347 // CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 5348 // CHECK19-NEXT: store i64 4, i64* [[TMP47]], align 4 5349 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 5350 // CHECK19-NEXT: store i8* null, i8** [[TMP48]], align 4 5351 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 5352 // CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to double** 5353 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP50]], align 4 5354 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 5355 // CHECK19-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** 5356 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP52]], align 4 5357 // CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 5358 // CHECK19-NEXT: store i64 [[TMP12]], i64* [[TMP53]], align 4 5359 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 5360 // CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 5361 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 5362 // CHECK19-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* 5363 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP56]], align 4 5364 // CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 5365 // CHECK19-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* 5366 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP58]], align 4 5367 // CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5368 // CHECK19-NEXT: store i64 4, i64* [[TMP59]], align 4 5369 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 5370 // CHECK19-NEXT: store i8* null, i8** [[TMP60]], align 4 5371 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5372 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5373 // CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5374 // CHECK19-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, i32 8, i8** [[TMP61]], i8** [[TMP62]], i64* [[TMP63]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5375 // CHECK19-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 5376 // CHECK19-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5377 // CHECK19: omp_offload.failed: 5378 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(float* [[TMP5]], %struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] 5379 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 5380 // CHECK19: omp_offload.cont: 5381 // CHECK19-NEXT: [[TMP66:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5382 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP66]]) 5383 // CHECK19-NEXT: ret void 5384 // 5385 // 5386 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 5387 // CHECK19-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 5388 // CHECK19-NEXT: entry: 5389 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5390 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5391 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5392 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5393 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 5394 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 5395 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 5396 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5397 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5398 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5399 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5400 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5401 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 5402 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 5403 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 5404 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5405 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5406 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 5407 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 5408 // CHECK19-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 5409 // CHECK19-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5410 // CHECK19-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5411 // CHECK19-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 4 5412 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i32, x86_fp80*, float*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[N_ADDR]], i32 [[TMP0]], x86_fp80* [[TMP5]], float* [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]]) 5413 // CHECK19-NEXT: ret void 5414 // 5415 // 5416 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 5417 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 5418 // CHECK19-NEXT: entry: 5419 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5420 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5421 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5422 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 5423 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5424 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5425 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5426 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 5427 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 5428 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 5429 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5430 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5431 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5432 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5433 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5434 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5435 // CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 5436 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5437 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5438 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5439 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 5440 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 5441 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 5442 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 5443 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5444 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 5445 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 5446 // CHECK19-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 5447 // CHECK19-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 5448 // CHECK19-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 4 5449 // CHECK19-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 5450 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 5451 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 5452 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 5453 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 5454 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 5455 // CHECK19-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 5456 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 5457 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i32 [[TMP8]], i1 false) 5458 // CHECK19-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5459 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i32 0 5460 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5461 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 5462 // CHECK19-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5463 // CHECK19-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) 5464 // CHECK19-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5465 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 5466 // CHECK19-NEXT: ret void 5467 // 5468 // 5469 // CHECK19-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 5470 // CHECK19-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 5471 // CHECK19-NEXT: entry: 5472 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 5473 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5474 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5475 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5476 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5477 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5478 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5479 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 5480 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 4 5481 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 4 5482 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 4 5483 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5484 // CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 5485 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5486 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5487 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5488 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 5489 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5490 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5491 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5492 // CHECK19-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 5493 // CHECK19-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 5494 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5495 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 5496 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5497 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 5498 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 5499 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 5500 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 5501 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 5502 // CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5503 // CHECK19-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5504 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 5505 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 5506 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 5507 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5508 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 5509 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 5510 // CHECK19-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 5511 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 5512 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[B2]], i32 1 5513 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i32* [[A3]] to i8* 5514 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP13]] to i8* 5515 // CHECK19-NEXT: [[TMP16:%.*]] = ptrtoint i8* [[TMP15]] to i64 5516 // CHECK19-NEXT: [[TMP17:%.*]] = ptrtoint i8* [[TMP14]] to i64 5517 // CHECK19-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] 5518 // CHECK19-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 5519 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5520 // CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.St** 5521 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP21]], align 4 5522 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5523 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** 5524 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP23]], align 4 5525 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5526 // CHECK19-NEXT: store i64 0, i64* [[TMP24]], align 4 5527 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5528 // CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 5529 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5530 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 5531 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 5532 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5533 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 5534 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP29]], align 4 5535 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 5536 // CHECK19-NEXT: store i64 4, i64* [[TMP30]], align 4 5537 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5538 // CHECK19-NEXT: store i8* null, i8** [[TMP31]], align 4 5539 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5540 // CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to x86_fp80** 5541 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP33]], align 4 5542 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5543 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to x86_fp80** 5544 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP35]], align 4 5545 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 5546 // CHECK19-NEXT: store i64 0, i64* [[TMP36]], align 4 5547 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5548 // CHECK19-NEXT: store i8* null, i8** [[TMP37]], align 4 5549 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5550 // CHECK19-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 5551 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP39]], align 4 5552 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5553 // CHECK19-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* 5554 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP41]], align 4 5555 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5556 // CHECK19-NEXT: store i64 4, i64* [[TMP42]], align 4 5557 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5558 // CHECK19-NEXT: store i8* null, i8** [[TMP43]], align 4 5559 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 5560 // CHECK19-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* 5561 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP45]], align 4 5562 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 5563 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* 5564 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP47]], align 4 5565 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 5566 // CHECK19-NEXT: store i64 4, i64* [[TMP48]], align 4 5567 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 5568 // CHECK19-NEXT: store i8* null, i8** [[TMP49]], align 4 5569 // CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 5570 // CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** 5571 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP51]], align 4 5572 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 5573 // CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** 5574 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP53]], align 4 5575 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 5576 // CHECK19-NEXT: store i64 [[TMP12]], i64* [[TMP54]], align 4 5577 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 5578 // CHECK19-NEXT: store i8* null, i8** [[TMP55]], align 4 5579 // CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 5580 // CHECK19-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to %struct.St** 5581 // CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP57]], align 4 5582 // CHECK19-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 5583 // CHECK19-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i32** 5584 // CHECK19-NEXT: store i32* [[A3]], i32** [[TMP59]], align 4 5585 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 5586 // CHECK19-NEXT: store i64 [[TMP19]], i64* [[TMP60]], align 4 5587 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 5588 // CHECK19-NEXT: store i8* null, i8** [[TMP61]], align 4 5589 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 5590 // CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to %struct.St** 5591 // CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP63]], align 4 5592 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 5593 // CHECK19-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32** 5594 // CHECK19-NEXT: store i32* [[B2]], i32** [[TMP65]], align 4 5595 // CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5596 // CHECK19-NEXT: store i64 4, i64* [[TMP66]], align 4 5597 // CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 5598 // CHECK19-NEXT: store i8* null, i8** [[TMP67]], align 4 5599 // CHECK19-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 5600 // CHECK19-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to %struct.St** 5601 // CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP69]], align 4 5602 // CHECK19-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 5603 // CHECK19-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32** 5604 // CHECK19-NEXT: store i32* [[A3]], i32** [[TMP71]], align 4 5605 // CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 5606 // CHECK19-NEXT: store i64 4, i64* [[TMP72]], align 4 5607 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 5608 // CHECK19-NEXT: store i8* null, i8** [[TMP73]], align 4 5609 // CHECK19-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 5610 // CHECK19-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* 5611 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP75]], align 4 5612 // CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 5613 // CHECK19-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* 5614 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP77]], align 4 5615 // CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 5616 // CHECK19-NEXT: store i64 4, i64* [[TMP78]], align 4 5617 // CHECK19-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 5618 // CHECK19-NEXT: store i8* null, i8** [[TMP79]], align 4 5619 // CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5620 // CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5621 // CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5622 // CHECK19-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, i32 10, i8** [[TMP80]], i8** [[TMP81]], i64* [[TMP82]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5623 // CHECK19-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0 5624 // CHECK19-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5625 // CHECK19: omp_offload.failed: 5626 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(%struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], %struct.St* [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] 5627 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 5628 // CHECK19: omp_offload.cont: 5629 // CHECK19-NEXT: [[TMP85:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5630 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP85]]) 5631 // CHECK19-NEXT: ret void 5632 // 5633 // 5634 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 5635 // CHECK19-SAME: (%struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { 5636 // CHECK19-NEXT: entry: 5637 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5638 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5639 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5640 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 5641 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 5642 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 5643 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 5644 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5645 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5646 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5647 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5648 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 5649 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 5650 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 5651 // CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 5652 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5653 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5654 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 5655 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 5656 // CHECK19-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 5657 // CHECK19-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 5658 // CHECK19-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5659 // CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5660 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, x86_fp80*, %struct.St*, i32, i32, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP0]], x86_fp80* [[TMP5]], %struct.St* [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]], i32* [[N_ADDR]], %struct.St* [[TMP6]]) 5661 // CHECK19-NEXT: ret void 5662 // 5663 // 5664 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 5665 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 5666 // CHECK19-NEXT: entry: 5667 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5668 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5669 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5670 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5671 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 5672 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 5673 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 5674 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 5675 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 5676 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5677 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5678 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5679 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5680 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5681 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5682 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5683 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5684 // CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 5685 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 5686 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 5687 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 5688 // CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 5689 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5690 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5691 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 5692 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 5693 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 5694 // CHECK19-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 5695 // CHECK19-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 4 5696 // CHECK19-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 5697 // CHECK19-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 4 5698 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 5699 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 5700 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 5701 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 5702 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 5703 // CHECK19-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 5704 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 5705 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 5706 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 [[TMP9]], i1 false) 5707 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 5708 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 5709 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 5710 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 5711 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 5712 // CHECK19-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP3]] 5713 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i32 [[TMP13]] 5714 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 5715 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 5716 // CHECK19-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] 5717 // CHECK19-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 5718 // CHECK19-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 5719 // CHECK19-NEXT: [[TMP15:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5720 // CHECK19-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 5721 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 5722 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP15]], i32 [[TMP16]] 5723 // CHECK19-NEXT: store x86_fp80 [[CONV9]], x86_fp80* [[ARRAYIDX11]], align 4 5724 // CHECK19-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5725 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 5726 // CHECK19-NEXT: ret void 5727 // 5728 // 5729 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5730 // CHECK19-SAME: () #[[ATTR5:[0-9]+]] { 5731 // CHECK19-NEXT: entry: 5732 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 5733 // CHECK19-NEXT: ret void 5734 // 5735 // 5736 // CHECK20-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 5737 // CHECK20-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 5738 // CHECK20-NEXT: entry: 5739 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5740 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5741 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5742 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5743 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5744 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5745 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5746 // CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 5747 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 4 5748 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 4 5749 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 4 5750 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 5751 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5752 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5753 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5754 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5755 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5756 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5757 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5758 // CHECK20-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 5759 // CHECK20-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 5760 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5761 // CHECK20-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 5762 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5763 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 5764 // CHECK20-NEXT: [[TMP5:%.*]] = load float*, float** [[A_ADDR]], align 4 5765 // CHECK20-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5766 // CHECK20-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5767 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 5768 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 5769 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 5770 // CHECK20-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5771 // CHECK20-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 5772 // CHECK20-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 5773 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5774 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to float** 5775 // CHECK20-NEXT: store float* [[TMP5]], float** [[TMP14]], align 4 5776 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5777 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** 5778 // CHECK20-NEXT: store float* [[TMP5]], float** [[TMP16]], align 4 5779 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5780 // CHECK20-NEXT: store i64 0, i64* [[TMP17]], align 4 5781 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5782 // CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 5783 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5784 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.St** 5785 // CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP20]], align 4 5786 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5787 // CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 5788 // CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 5789 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 5790 // CHECK20-NEXT: store i64 0, i64* [[TMP23]], align 4 5791 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5792 // CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 5793 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5794 // CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 5795 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 5796 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5797 // CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 5798 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP28]], align 4 5799 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 5800 // CHECK20-NEXT: store i64 4, i64* [[TMP29]], align 4 5801 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5802 // CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 5803 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5804 // CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** 5805 // CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 5806 // CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5807 // CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to x86_fp80** 5808 // CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP34]], align 4 5809 // CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5810 // CHECK20-NEXT: store i64 0, i64* [[TMP35]], align 4 5811 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5812 // CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 5813 // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 5814 // CHECK20-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* 5815 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP38]], align 4 5816 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 5817 // CHECK20-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* 5818 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP40]], align 4 5819 // CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 5820 // CHECK20-NEXT: store i64 4, i64* [[TMP41]], align 4 5821 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 5822 // CHECK20-NEXT: store i8* null, i8** [[TMP42]], align 4 5823 // CHECK20-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 5824 // CHECK20-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* 5825 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP44]], align 4 5826 // CHECK20-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 5827 // CHECK20-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* 5828 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP46]], align 4 5829 // CHECK20-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 5830 // CHECK20-NEXT: store i64 4, i64* [[TMP47]], align 4 5831 // CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 5832 // CHECK20-NEXT: store i8* null, i8** [[TMP48]], align 4 5833 // CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 5834 // CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to double** 5835 // CHECK20-NEXT: store double* [[VLA]], double** [[TMP50]], align 4 5836 // CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 5837 // CHECK20-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** 5838 // CHECK20-NEXT: store double* [[VLA]], double** [[TMP52]], align 4 5839 // CHECK20-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 5840 // CHECK20-NEXT: store i64 [[TMP12]], i64* [[TMP53]], align 4 5841 // CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 5842 // CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 5843 // CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 5844 // CHECK20-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* 5845 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP56]], align 4 5846 // CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 5847 // CHECK20-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* 5848 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP58]], align 4 5849 // CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5850 // CHECK20-NEXT: store i64 4, i64* [[TMP59]], align 4 5851 // CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 5852 // CHECK20-NEXT: store i8* null, i8** [[TMP60]], align 4 5853 // CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5854 // CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5855 // CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5856 // CHECK20-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, i32 8, i8** [[TMP61]], i8** [[TMP62]], i64* [[TMP63]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5857 // CHECK20-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 5858 // CHECK20-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5859 // CHECK20: omp_offload.failed: 5860 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(float* [[TMP5]], %struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] 5861 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 5862 // CHECK20: omp_offload.cont: 5863 // CHECK20-NEXT: [[TMP66:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5864 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP66]]) 5865 // CHECK20-NEXT: ret void 5866 // 5867 // 5868 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 5869 // CHECK20-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 5870 // CHECK20-NEXT: entry: 5871 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5872 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5873 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5874 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5875 // CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 5876 // CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 5877 // CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 5878 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5879 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5880 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5881 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5882 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5883 // CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 5884 // CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 5885 // CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 5886 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5887 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5888 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 5889 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 5890 // CHECK20-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 5891 // CHECK20-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5892 // CHECK20-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5893 // CHECK20-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 4 5894 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i32, x86_fp80*, float*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[N_ADDR]], i32 [[TMP0]], x86_fp80* [[TMP5]], float* [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]]) 5895 // CHECK20-NEXT: ret void 5896 // 5897 // 5898 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 5899 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 5900 // CHECK20-NEXT: entry: 5901 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5902 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5903 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5904 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 5905 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5906 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5907 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 5908 // CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 5909 // CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 5910 // CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 5911 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5912 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5913 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5914 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5915 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5916 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5917 // CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 5918 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5919 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5920 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 5921 // CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 5922 // CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 5923 // CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 5924 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 5925 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5926 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 5927 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 5928 // CHECK20-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 5929 // CHECK20-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 5930 // CHECK20-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 4 5931 // CHECK20-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 5932 // CHECK20-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 5933 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 5934 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 5935 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 5936 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 5937 // CHECK20-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 5938 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 5939 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i32 [[TMP8]], i1 false) 5940 // CHECK20-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5941 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i32 0 5942 // CHECK20-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5943 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 5944 // CHECK20-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5945 // CHECK20-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) 5946 // CHECK20-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5947 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 5948 // CHECK20-NEXT: ret void 5949 // 5950 // 5951 // CHECK20-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 5952 // CHECK20-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 5953 // CHECK20-NEXT: entry: 5954 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 5955 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5956 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5957 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5958 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5959 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5960 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5961 // CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 5962 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 4 5963 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 4 5964 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 4 5965 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5966 // CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 5967 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5968 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5969 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5970 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 5971 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5972 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5973 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5974 // CHECK20-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 5975 // CHECK20-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 5976 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5977 // CHECK20-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 5978 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5979 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 5980 // CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 5981 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 5982 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 5983 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 5984 // CHECK20-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5985 // CHECK20-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5986 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 5987 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 5988 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 5989 // CHECK20-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5990 // CHECK20-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 5991 // CHECK20-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 5992 // CHECK20-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 5993 // CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 5994 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[B2]], i32 1 5995 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i32* [[A3]] to i8* 5996 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP13]] to i8* 5997 // CHECK20-NEXT: [[TMP16:%.*]] = ptrtoint i8* [[TMP15]] to i64 5998 // CHECK20-NEXT: [[TMP17:%.*]] = ptrtoint i8* [[TMP14]] to i64 5999 // CHECK20-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] 6000 // CHECK20-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 6001 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6002 // CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.St** 6003 // CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP21]], align 4 6004 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6005 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** 6006 // CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP23]], align 4 6007 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6008 // CHECK20-NEXT: store i64 0, i64* [[TMP24]], align 4 6009 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6010 // CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 6011 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6012 // CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 6013 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 6014 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6015 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 6016 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP29]], align 4 6017 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 6018 // CHECK20-NEXT: store i64 4, i64* [[TMP30]], align 4 6019 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6020 // CHECK20-NEXT: store i8* null, i8** [[TMP31]], align 4 6021 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6022 // CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to x86_fp80** 6023 // CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP33]], align 4 6024 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6025 // CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to x86_fp80** 6026 // CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP35]], align 4 6027 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 6028 // CHECK20-NEXT: store i64 0, i64* [[TMP36]], align 4 6029 // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6030 // CHECK20-NEXT: store i8* null, i8** [[TMP37]], align 4 6031 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6032 // CHECK20-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 6033 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP39]], align 4 6034 // CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6035 // CHECK20-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* 6036 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP41]], align 4 6037 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 6038 // CHECK20-NEXT: store i64 4, i64* [[TMP42]], align 4 6039 // CHECK20-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6040 // CHECK20-NEXT: store i8* null, i8** [[TMP43]], align 4 6041 // CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6042 // CHECK20-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* 6043 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP45]], align 4 6044 // CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6045 // CHECK20-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* 6046 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP47]], align 4 6047 // CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6048 // CHECK20-NEXT: store i64 4, i64* [[TMP48]], align 4 6049 // CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6050 // CHECK20-NEXT: store i8* null, i8** [[TMP49]], align 4 6051 // CHECK20-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 6052 // CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** 6053 // CHECK20-NEXT: store double* [[VLA]], double** [[TMP51]], align 4 6054 // CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 6055 // CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** 6056 // CHECK20-NEXT: store double* [[VLA]], double** [[TMP53]], align 4 6057 // CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 6058 // CHECK20-NEXT: store i64 [[TMP12]], i64* [[TMP54]], align 4 6059 // CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 6060 // CHECK20-NEXT: store i8* null, i8** [[TMP55]], align 4 6061 // CHECK20-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 6062 // CHECK20-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to %struct.St** 6063 // CHECK20-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP57]], align 4 6064 // CHECK20-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 6065 // CHECK20-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i32** 6066 // CHECK20-NEXT: store i32* [[A3]], i32** [[TMP59]], align 4 6067 // CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 6068 // CHECK20-NEXT: store i64 [[TMP19]], i64* [[TMP60]], align 4 6069 // CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 6070 // CHECK20-NEXT: store i8* null, i8** [[TMP61]], align 4 6071 // CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 6072 // CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to %struct.St** 6073 // CHECK20-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP63]], align 4 6074 // CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 6075 // CHECK20-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32** 6076 // CHECK20-NEXT: store i32* [[B2]], i32** [[TMP65]], align 4 6077 // CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 6078 // CHECK20-NEXT: store i64 4, i64* [[TMP66]], align 4 6079 // CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 6080 // CHECK20-NEXT: store i8* null, i8** [[TMP67]], align 4 6081 // CHECK20-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 6082 // CHECK20-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to %struct.St** 6083 // CHECK20-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP69]], align 4 6084 // CHECK20-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 6085 // CHECK20-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32** 6086 // CHECK20-NEXT: store i32* [[A3]], i32** [[TMP71]], align 4 6087 // CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 6088 // CHECK20-NEXT: store i64 4, i64* [[TMP72]], align 4 6089 // CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 6090 // CHECK20-NEXT: store i8* null, i8** [[TMP73]], align 4 6091 // CHECK20-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 6092 // CHECK20-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* 6093 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP75]], align 4 6094 // CHECK20-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 6095 // CHECK20-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* 6096 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP77]], align 4 6097 // CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 6098 // CHECK20-NEXT: store i64 4, i64* [[TMP78]], align 4 6099 // CHECK20-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 6100 // CHECK20-NEXT: store i8* null, i8** [[TMP79]], align 4 6101 // CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6102 // CHECK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6103 // CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6104 // CHECK20-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, i32 10, i8** [[TMP80]], i8** [[TMP81]], i64* [[TMP82]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 6105 // CHECK20-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0 6106 // CHECK20-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6107 // CHECK20: omp_offload.failed: 6108 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(%struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], %struct.St* [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] 6109 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 6110 // CHECK20: omp_offload.cont: 6111 // CHECK20-NEXT: [[TMP85:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6112 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP85]]) 6113 // CHECK20-NEXT: ret void 6114 // 6115 // 6116 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 6117 // CHECK20-SAME: (%struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { 6118 // CHECK20-NEXT: entry: 6119 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 6120 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6121 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 6122 // CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 6123 // CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 6124 // CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 6125 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 6126 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6127 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 6128 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6129 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 6130 // CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 6131 // CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 6132 // CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 6133 // CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 6134 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6135 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6136 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 6137 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 6138 // CHECK20-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 6139 // CHECK20-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 6140 // CHECK20-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 6141 // CHECK20-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 6142 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, x86_fp80*, %struct.St*, i32, i32, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP0]], x86_fp80* [[TMP5]], %struct.St* [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]], i32* [[N_ADDR]], %struct.St* [[TMP6]]) 6143 // CHECK20-NEXT: ret void 6144 // 6145 // 6146 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 6147 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 6148 // CHECK20-NEXT: entry: 6149 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6150 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6151 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6152 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 6153 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 6154 // CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 6155 // CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 6156 // CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 6157 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 6158 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 6159 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6160 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6161 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 6162 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6163 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6164 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6165 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 6166 // CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 6167 // CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 6168 // CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 6169 // CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 6170 // CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 6171 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 6172 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6173 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 6174 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 6175 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 6176 // CHECK20-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 6177 // CHECK20-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 4 6178 // CHECK20-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 6179 // CHECK20-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 4 6180 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 6181 // CHECK20-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 6182 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 6183 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 6184 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 6185 // CHECK20-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 6186 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 6187 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 6188 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 [[TMP9]], i1 false) 6189 // CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 6190 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 6191 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 6192 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 6193 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 6194 // CHECK20-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP3]] 6195 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i32 [[TMP13]] 6196 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 6197 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 6198 // CHECK20-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] 6199 // CHECK20-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 6200 // CHECK20-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 6201 // CHECK20-NEXT: [[TMP15:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 6202 // CHECK20-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 6203 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 6204 // CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP15]], i32 [[TMP16]] 6205 // CHECK20-NEXT: store x86_fp80 [[CONV9]], x86_fp80* [[ARRAYIDX11]], align 4 6206 // CHECK20-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6207 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 6208 // CHECK20-NEXT: ret void 6209 // 6210 // 6211 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 6212 // CHECK20-SAME: () #[[ATTR5:[0-9]+]] { 6213 // CHECK20-NEXT: entry: 6214 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 6215 // CHECK20-NEXT: ret void 6216 // 6217 // 6218 // CHECK21-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg 6219 // CHECK21-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 6220 // CHECK21-NEXT: entry: 6221 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6222 // CHECK21-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 6223 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6224 // CHECK21-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 6225 // CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6226 // CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6227 // CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6228 // CHECK21-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6229 // CHECK21-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 6230 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6231 // CHECK21-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 6232 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6233 // CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 6234 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6235 // CHECK21-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 6236 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6237 // CHECK21-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 6238 // CHECK21-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 6239 // CHECK21-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 6240 // CHECK21-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 6241 // CHECK21-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 6242 // CHECK21-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 6243 // CHECK21-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 6244 // CHECK21-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 6245 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP8]], i64 0 6246 // CHECK21-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 6247 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[N_ADDR]], align 4 6248 // CHECK21-NEXT: [[TMP11:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 6249 // CHECK21-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP9]], i32 signext [[TMP10]], ppc_fp128* [[TMP11]]) 6250 // CHECK21-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6251 // CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) 6252 // CHECK21-NEXT: ret void 6253 // 6254 // 6255 // CHECK21-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg 6256 // CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 6257 // CHECK21-NEXT: entry: 6258 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 6259 // CHECK21-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 6260 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6261 // CHECK21-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 6262 // CHECK21-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6263 // CHECK21-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6264 // CHECK21-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6265 // CHECK21-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 6266 // CHECK21-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 6267 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6268 // CHECK21-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 6269 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 6270 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6271 // CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 6272 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6273 // CHECK21-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 6274 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6275 // CHECK21-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 6276 // CHECK21-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 6277 // CHECK21-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 6278 // CHECK21-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 6279 // CHECK21-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 6280 // CHECK21-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 6281 // CHECK21-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 6282 // CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 6283 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 6284 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 6285 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 6286 // CHECK21-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 6287 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[B2]], align 4 6288 // CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 6289 // CHECK21-NEXT: store i32 [[TMP9]], i32* [[A3]], align 4 6290 // CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 6291 // CHECK21-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP5]] 6292 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i64 [[TMP10]] 6293 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 6294 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], 1 6295 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 6296 // CHECK21-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] 6297 // CHECK21-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 6298 // CHECK21-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to ppc_fp128 6299 // CHECK21-NEXT: [[TMP12:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 6300 // CHECK21-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 6301 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[B6]], align 4 6302 // CHECK21-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP13]] to i64 6303 // CHECK21-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP12]], i64 [[IDXPROM7]] 6304 // CHECK21-NEXT: store ppc_fp128 [[CONV5]], ppc_fp128* [[ARRAYIDX8]], align 16 6305 // CHECK21-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6306 // CHECK21-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) 6307 // CHECK21-NEXT: ret void 6308 // 6309 // 6310 // CHECK22-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg 6311 // CHECK22-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 6312 // CHECK22-NEXT: entry: 6313 // CHECK22-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6314 // CHECK22-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 6315 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6316 // CHECK22-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 6317 // CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6318 // CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6319 // CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6320 // CHECK22-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6321 // CHECK22-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 6322 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6323 // CHECK22-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 6324 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6325 // CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 6326 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6327 // CHECK22-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 6328 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6329 // CHECK22-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 6330 // CHECK22-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 6331 // CHECK22-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 6332 // CHECK22-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 6333 // CHECK22-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 6334 // CHECK22-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 6335 // CHECK22-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 6336 // CHECK22-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 6337 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP8]], i64 0 6338 // CHECK22-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 6339 // CHECK22-NEXT: [[TMP10:%.*]] = load i32, i32* [[N_ADDR]], align 4 6340 // CHECK22-NEXT: [[TMP11:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 6341 // CHECK22-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP9]], i32 signext [[TMP10]], ppc_fp128* [[TMP11]]) 6342 // CHECK22-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6343 // CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) 6344 // CHECK22-NEXT: ret void 6345 // 6346 // 6347 // CHECK22-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg 6348 // CHECK22-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 6349 // CHECK22-NEXT: entry: 6350 // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 6351 // CHECK22-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 6352 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6353 // CHECK22-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 6354 // CHECK22-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6355 // CHECK22-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6356 // CHECK22-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6357 // CHECK22-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 6358 // CHECK22-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 6359 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6360 // CHECK22-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 6361 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 6362 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6363 // CHECK22-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 6364 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6365 // CHECK22-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 6366 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6367 // CHECK22-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 6368 // CHECK22-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 6369 // CHECK22-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 6370 // CHECK22-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 6371 // CHECK22-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 6372 // CHECK22-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 6373 // CHECK22-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 6374 // CHECK22-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 6375 // CHECK22-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 6376 // CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 6377 // CHECK22-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 6378 // CHECK22-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 6379 // CHECK22-NEXT: [[TMP9:%.*]] = load i32, i32* [[B2]], align 4 6380 // CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 6381 // CHECK22-NEXT: store i32 [[TMP9]], i32* [[A3]], align 4 6382 // CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 6383 // CHECK22-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP5]] 6384 // CHECK22-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i64 [[TMP10]] 6385 // CHECK22-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 6386 // CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], 1 6387 // CHECK22-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 6388 // CHECK22-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] 6389 // CHECK22-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 6390 // CHECK22-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to ppc_fp128 6391 // CHECK22-NEXT: [[TMP12:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 6392 // CHECK22-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 6393 // CHECK22-NEXT: [[TMP13:%.*]] = load i32, i32* [[B6]], align 4 6394 // CHECK22-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP13]] to i64 6395 // CHECK22-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP12]], i64 [[IDXPROM7]] 6396 // CHECK22-NEXT: store ppc_fp128 [[CONV5]], ppc_fp128* [[ARRAYIDX8]], align 16 6397 // CHECK22-NEXT: [[TMP14:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6398 // CHECK22-NEXT: call void @llvm.stackrestore(i8* [[TMP14]]) 6399 // CHECK22-NEXT: ret void 6400 // 6401 // 6402 // CHECK23-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 6403 // CHECK23-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 6404 // CHECK23-NEXT: entry: 6405 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 6406 // CHECK23-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 6407 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6408 // CHECK23-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 6409 // CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6410 // CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6411 // CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 6412 // CHECK23-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 6413 // CHECK23-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 6414 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6415 // CHECK23-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 6416 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6417 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6418 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6419 // CHECK23-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6420 // CHECK23-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 6421 // CHECK23-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 6422 // CHECK23-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 6423 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6424 // CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 6425 // CHECK23-NEXT: [[TMP5:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 6426 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP5]], i32 0 6427 // CHECK23-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 6428 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 6429 // CHECK23-NEXT: [[TMP8:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 6430 // CHECK23-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP6]], i32 [[TMP7]], x86_fp80* [[TMP8]]) 6431 // CHECK23-NEXT: [[TMP9:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6432 // CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP9]]) 6433 // CHECK23-NEXT: ret void 6434 // 6435 // 6436 // CHECK23-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 6437 // CHECK23-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 6438 // CHECK23-NEXT: entry: 6439 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 6440 // CHECK23-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 6441 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6442 // CHECK23-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 6443 // CHECK23-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6444 // CHECK23-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6445 // CHECK23-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 6446 // CHECK23-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 6447 // CHECK23-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 6448 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6449 // CHECK23-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 6450 // CHECK23-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 6451 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6452 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6453 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6454 // CHECK23-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6455 // CHECK23-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 6456 // CHECK23-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 6457 // CHECK23-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 6458 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6459 // CHECK23-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 6460 // CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 6461 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 6462 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 6463 // CHECK23-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 6464 // CHECK23-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 6465 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[B2]], align 4 6466 // CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 6467 // CHECK23-NEXT: store i32 [[TMP6]], i32* [[A3]], align 4 6468 // CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double 6469 // CHECK23-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] 6470 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i32 [[TMP7]] 6471 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 6472 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 1 6473 // CHECK23-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] 6474 // CHECK23-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 6475 // CHECK23-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to x86_fp80 6476 // CHECK23-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 6477 // CHECK23-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 6478 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[B6]], align 4 6479 // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP9]], i32 [[TMP10]] 6480 // CHECK23-NEXT: store x86_fp80 [[CONV5]], x86_fp80* [[ARRAYIDX7]], align 4 6481 // CHECK23-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6482 // CHECK23-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 6483 // CHECK23-NEXT: ret void 6484 // 6485 // 6486 // CHECK24-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 6487 // CHECK24-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 6488 // CHECK24-NEXT: entry: 6489 // CHECK24-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 6490 // CHECK24-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 6491 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6492 // CHECK24-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 6493 // CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6494 // CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6495 // CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 6496 // CHECK24-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 6497 // CHECK24-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 6498 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6499 // CHECK24-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 6500 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6501 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6502 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6503 // CHECK24-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6504 // CHECK24-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 6505 // CHECK24-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 6506 // CHECK24-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 6507 // CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6508 // CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 6509 // CHECK24-NEXT: [[TMP5:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 6510 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP5]], i32 0 6511 // CHECK24-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 6512 // CHECK24-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 6513 // CHECK24-NEXT: [[TMP8:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 6514 // CHECK24-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP6]], i32 [[TMP7]], x86_fp80* [[TMP8]]) 6515 // CHECK24-NEXT: [[TMP9:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6516 // CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP9]]) 6517 // CHECK24-NEXT: ret void 6518 // 6519 // 6520 // CHECK24-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 6521 // CHECK24-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 6522 // CHECK24-NEXT: entry: 6523 // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 6524 // CHECK24-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 6525 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6526 // CHECK24-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 6527 // CHECK24-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6528 // CHECK24-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6529 // CHECK24-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 6530 // CHECK24-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 6531 // CHECK24-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 6532 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6533 // CHECK24-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 6534 // CHECK24-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 6535 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6536 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6537 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6538 // CHECK24-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6539 // CHECK24-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 6540 // CHECK24-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 6541 // CHECK24-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 6542 // CHECK24-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6543 // CHECK24-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 6544 // CHECK24-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 6545 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 6546 // CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 6547 // CHECK24-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 6548 // CHECK24-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 6549 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[B2]], align 4 6550 // CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 6551 // CHECK24-NEXT: store i32 [[TMP6]], i32* [[A3]], align 4 6552 // CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to double 6553 // CHECK24-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] 6554 // CHECK24-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA]], i32 [[TMP7]] 6555 // CHECK24-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 6556 // CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 1 6557 // CHECK24-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] 6558 // CHECK24-NEXT: store double [[CONV]], double* [[ARRAYIDX4]], align 8 6559 // CHECK24-NEXT: [[CONV5:%.*]] = fpext double [[CONV]] to x86_fp80 6560 // CHECK24-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 6561 // CHECK24-NEXT: [[B6:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 6562 // CHECK24-NEXT: [[TMP10:%.*]] = load i32, i32* [[B6]], align 4 6563 // CHECK24-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP9]], i32 [[TMP10]] 6564 // CHECK24-NEXT: store x86_fp80 [[CONV5]], x86_fp80* [[ARRAYIDX7]], align 4 6565 // CHECK24-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6566 // CHECK24-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 6567 // CHECK24-NEXT: ret void 6568 // 6569