1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 5 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 8 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 12 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 15 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 18 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 19 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 23 24 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 26 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 27 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 28 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 29 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 30 31 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 33 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 35 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 36 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 37 38 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 39 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 40 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 41 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 42 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 43 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 44 // expected-no-diagnostics 45 #ifndef HEADER 46 #define HEADER 47 #ifndef ARRAY 48 struct St { 49 int a, b; 50 St() : a(0), b(0) {} 51 St(const St &st) : a(st.a + st.b), b(0) {} 52 ~St() {} 53 }; 54 55 volatile int g __attribute__((aligned(128))) = 1212; 56 57 template <class T> 58 struct S { 59 T f; 60 S(T a) : f(a + g) {} 61 S() : f(g) {} 62 S(const S &s, St t = St()) : f(s.f + t.a) {} 63 operator T() { return T(); } 64 ~S() {} 65 }; 66 67 68 template <typename T> 69 T tmain() { 70 S<T> test; 71 T t_var __attribute__((aligned(128))) = T(); 72 T vec[] __attribute__((aligned(128))) = {1, 2}; 73 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2}; 74 S<T> var __attribute__((aligned(128))) (3); 75 #pragma omp target 76 #pragma omp teams firstprivate(t_var, vec, s_arr, var) 77 { 78 vec[0] = t_var; 79 s_arr[0] = var; 80 } 81 #pragma omp target 82 #pragma omp teams firstprivate(t_var) 83 {} 84 return T(); 85 } 86 87 int main() { 88 static int sivar; 89 #ifdef LAMBDA 90 [&]() { 91 #pragma omp target 92 #pragma omp teams firstprivate(g, sivar) 93 { 94 g = 1; 95 sivar = 2; 96 [&]() { 97 g = 2; 98 sivar = 4; 99 }(); 100 } 101 }(); 102 return 0; 103 #else 104 S<float> test; 105 int t_var = 0; 106 int vec[] = {1, 2}; 107 S<float> s_arr[] = {1, 2}; 108 S<float> var(3); 109 #pragma omp target 110 #pragma omp teams firstprivate(t_var, vec, s_arr, var, sivar) 111 { 112 vec[0] = t_var; 113 s_arr[0] = var; 114 sivar = 2; 115 } 116 #pragma omp target 117 #pragma omp teams firstprivate(t_var) 118 {} 119 return tmain<int>(); 120 #endif 121 } 122 123 124 125 126 127 128 129 130 131 132 133 134 135 #else 136 struct St { 137 int a, b; 138 St() : a(0), b(0) {} 139 St(const St &) { } 140 ~St() {} 141 void St_func(St s[2], int n, long double vla1[n]) { 142 double vla2[n][n] __attribute__((aligned(128))); 143 a = b; 144 #pragma omp target 145 #pragma omp teams firstprivate(s, vla1, vla2) 146 vla1[b] = vla2[1][n - 1] = a = b; 147 } 148 }; 149 150 void array_func(float a[3], St s[2], int n, long double vla1[n]) { 151 double vla2[n][n] __attribute__((aligned(128))); 152 #pragma omp target 153 #pragma omp teams firstprivate(a, s, vla1, vla2) 154 s[0].St_func(s, n, vla1); 155 ; 156 } 157 158 #endif 159 #endif 160 // CHECK1-LABEL: define {{[^@]+}}@main 161 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 165 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 166 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 167 // CHECK1-NEXT: ret i32 0 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 171 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 174 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 175 // CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128 176 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 177 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 178 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 179 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 180 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 181 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 182 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 183 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 4 184 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 185 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 186 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 187 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i64 [[TMP3]]) 188 // CHECK1-NEXT: ret void 189 // 190 // 191 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 192 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2]] { 193 // CHECK1-NEXT: entry: 194 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 195 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 196 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 197 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 198 // CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128 199 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 200 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 201 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 202 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 203 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 204 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 205 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 206 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 207 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 208 // CHECK1-NEXT: store i32 1, i32* [[G1]], align 128 209 // CHECK1-NEXT: store i32 2, i32* [[CONV]], align 4 210 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 211 // CHECK1-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 212 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 213 // CHECK1-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 214 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) 215 // CHECK1-NEXT: ret void 216 // 217 // 218 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 219 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 220 // CHECK1-NEXT: entry: 221 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 222 // CHECK1-NEXT: ret void 223 // 224 // 225 // CHECK3-LABEL: define {{[^@]+}}@main 226 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 227 // CHECK3-NEXT: entry: 228 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 229 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 230 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 231 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 232 // CHECK3-NEXT: ret i32 0 233 // 234 // 235 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 236 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 237 // CHECK3-NEXT: entry: 238 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 239 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 240 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 241 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 242 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 243 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 244 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 245 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 246 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 247 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 248 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 249 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 250 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i32 [[TMP3]]) 251 // CHECK3-NEXT: ret void 252 // 253 // 254 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 255 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2]] { 256 // CHECK3-NEXT: entry: 257 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 258 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 259 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 260 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 261 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 262 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 263 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 264 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 265 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 266 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 267 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 268 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 269 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 270 // CHECK3-NEXT: store i32 1, i32* [[G1]], align 128 271 // CHECK3-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 272 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 273 // CHECK3-NEXT: store i32* [[G1]], i32** [[TMP2]], align 4 274 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 275 // CHECK3-NEXT: store i32* [[SIVAR_ADDR]], i32** [[TMP3]], align 4 276 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(8) [[REF_TMP]]) 277 // CHECK3-NEXT: ret void 278 // 279 // 280 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 281 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 282 // CHECK3-NEXT: entry: 283 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 284 // CHECK3-NEXT: ret void 285 // 286 // 287 // CHECK9-LABEL: define {{[^@]+}}@main 288 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 289 // CHECK9-NEXT: entry: 290 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 291 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 292 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 293 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 294 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 295 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 296 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 297 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 298 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 299 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 300 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 301 // CHECK9-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 302 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 303 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 304 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 305 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 306 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 307 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 308 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 309 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 310 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 311 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 312 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 313 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 314 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 315 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 316 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 317 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 318 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 319 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 320 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 321 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 322 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 323 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 324 // CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 325 // CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 326 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 327 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 328 // CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP8]], align 8 329 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 330 // CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 331 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 332 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 333 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 8 334 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 335 // CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 336 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 337 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 338 // CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 339 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 340 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 341 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 8 342 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 343 // CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 344 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 345 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 346 // CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 347 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 348 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 349 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 8 350 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 351 // CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 352 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 8 353 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 354 // CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 355 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 356 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 357 // CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP26]], align 8 358 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 359 // CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 360 // CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP28]], align 8 361 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 362 // CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 363 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 364 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 365 // CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 366 // CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 367 // CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 368 // CHECK9: omp_offload.failed: 369 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) #[[ATTR4:[0-9]+]] 370 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 371 // CHECK9: omp_offload.cont: 372 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 373 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* 374 // CHECK9-NEXT: store i32 [[TMP34]], i32* [[CONV3]], align 4 375 // CHECK9-NEXT: [[TMP35:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 376 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 377 // CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 378 // CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP37]], align 8 379 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 380 // CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 381 // CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP39]], align 8 382 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 383 // CHECK9-NEXT: store i8* null, i8** [[TMP40]], align 8 384 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 385 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 386 // CHECK9-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 387 // CHECK9-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 388 // CHECK9-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 389 // CHECK9: omp_offload.failed7: 390 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP35]]) #[[ATTR4]] 391 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] 392 // CHECK9: omp_offload.cont8: 393 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 394 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 395 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 396 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 397 // CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 398 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 399 // CHECK9: arraydestroy.body: 400 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 401 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 402 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 403 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 404 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 405 // CHECK9: arraydestroy.done9: 406 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 407 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 408 // CHECK9-NEXT: ret i32 [[TMP46]] 409 // 410 // 411 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 412 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 413 // CHECK9-NEXT: entry: 414 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 415 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 416 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 417 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 418 // CHECK9-NEXT: ret void 419 // 420 // 421 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 422 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 423 // CHECK9-NEXT: entry: 424 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 425 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 426 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 427 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 428 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 429 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 430 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 431 // CHECK9-NEXT: ret void 432 // 433 // 434 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 435 // CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 436 // CHECK9-NEXT: entry: 437 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 438 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 439 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 440 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 441 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 442 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 443 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 444 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 445 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 446 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 447 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 448 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 449 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 450 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 451 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 452 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 453 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 454 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 455 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 456 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 457 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 458 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 459 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 460 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 461 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 462 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 463 // CHECK9-NEXT: ret void 464 // 465 // 466 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 467 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { 468 // CHECK9-NEXT: entry: 469 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 470 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 471 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 472 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 473 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 474 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 475 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 476 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 477 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 478 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 479 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 480 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 481 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 482 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 483 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 484 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 485 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 486 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 487 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 488 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 489 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 490 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 491 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 492 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 493 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 494 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 495 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 496 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 497 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 498 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 499 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 500 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 501 // CHECK9: omp.arraycpy.body: 502 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 503 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 504 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 505 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 506 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 507 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 508 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 509 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 510 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 511 // CHECK9: omp.arraycpy.done4: 512 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 513 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 514 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 515 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 4 516 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 517 // CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 518 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 519 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 520 // CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 521 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) 522 // CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 4 523 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 524 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 525 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 526 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 527 // CHECK9: arraydestroy.body: 528 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 529 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 530 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 531 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 532 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 533 // CHECK9: arraydestroy.done9: 534 // CHECK9-NEXT: ret void 535 // 536 // 537 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev 538 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 539 // CHECK9-NEXT: entry: 540 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 541 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 542 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 543 // CHECK9-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 544 // CHECK9-NEXT: ret void 545 // 546 // 547 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 548 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 549 // CHECK9-NEXT: entry: 550 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 551 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 552 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 553 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 554 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 555 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 556 // CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 557 // CHECK9-NEXT: ret void 558 // 559 // 560 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev 561 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 562 // CHECK9-NEXT: entry: 563 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 564 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 565 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 566 // CHECK9-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 567 // CHECK9-NEXT: ret void 568 // 569 // 570 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 571 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 572 // CHECK9-NEXT: entry: 573 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 574 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 575 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 576 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 577 // CHECK9-NEXT: ret void 578 // 579 // 580 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 581 // CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { 582 // CHECK9-NEXT: entry: 583 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 584 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 585 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 586 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 587 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 588 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 589 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 590 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 591 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 592 // CHECK9-NEXT: ret void 593 // 594 // 595 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 596 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { 597 // CHECK9-NEXT: entry: 598 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 599 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 600 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 601 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 602 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 603 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 604 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 605 // CHECK9-NEXT: ret void 606 // 607 // 608 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 609 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { 610 // CHECK9-NEXT: entry: 611 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 612 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 613 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 614 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 615 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 616 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 617 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 618 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 619 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 620 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 621 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 622 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 623 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 624 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 625 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 626 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 627 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 628 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 629 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 630 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 631 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) 632 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 633 // CHECK9-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 634 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 635 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 636 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 637 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 638 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 639 // CHECK9-NEXT: store i8* null, i8** [[TMP5]], align 8 640 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 641 // CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 642 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 8 643 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 644 // CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 645 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 8 646 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 647 // CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 648 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 649 // CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 650 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 8 651 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 652 // CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 653 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 8 654 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 655 // CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 656 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 657 // CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 658 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 8 659 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 660 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 661 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 8 662 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 663 // CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 664 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 665 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 666 // CHECK9-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 667 // CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 668 // CHECK9-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 669 // CHECK9: omp_offload.failed: 670 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 671 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 672 // CHECK9: omp_offload.cont: 673 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 674 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 675 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 8 676 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 677 // CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 678 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 8 679 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 680 // CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 681 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 682 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 683 // CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 684 // CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 685 // CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 686 // CHECK9: omp_offload.failed4: 687 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 688 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT5]] 689 // CHECK9: omp_offload.cont5: 690 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 691 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 692 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 693 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 694 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 695 // CHECK9: arraydestroy.body: 696 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 697 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 698 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 699 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 700 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 701 // CHECK9: arraydestroy.done6: 702 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 703 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 704 // CHECK9-NEXT: ret i32 [[TMP35]] 705 // 706 // 707 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 708 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 709 // CHECK9-NEXT: entry: 710 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 711 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 712 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 713 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 714 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 715 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 716 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 717 // CHECK9-NEXT: ret void 718 // 719 // 720 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 721 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 722 // CHECK9-NEXT: entry: 723 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 724 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 725 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 726 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 727 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 728 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 729 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 730 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 731 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 732 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 733 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 734 // CHECK9-NEXT: ret void 735 // 736 // 737 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev 738 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 739 // CHECK9-NEXT: entry: 740 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 741 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 742 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 743 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 744 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 745 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 746 // CHECK9-NEXT: store i32 0, i32* [[B]], align 4 747 // CHECK9-NEXT: ret void 748 // 749 // 750 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 751 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 752 // CHECK9-NEXT: entry: 753 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 754 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 755 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 756 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 757 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 758 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 759 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 760 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 761 // CHECK9-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 762 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 763 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 764 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 765 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 766 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 767 // CHECK9-NEXT: ret void 768 // 769 // 770 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev 771 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 772 // CHECK9-NEXT: entry: 773 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 774 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 775 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 776 // CHECK9-NEXT: ret void 777 // 778 // 779 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 780 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 781 // CHECK9-NEXT: entry: 782 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 783 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 784 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 785 // CHECK9-NEXT: ret void 786 // 787 // 788 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 789 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 790 // CHECK9-NEXT: entry: 791 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 792 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 793 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 794 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 795 // CHECK9-NEXT: ret void 796 // 797 // 798 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 799 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 800 // CHECK9-NEXT: entry: 801 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 802 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 803 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 804 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 805 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 806 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 807 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 808 // CHECK9-NEXT: ret void 809 // 810 // 811 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 812 // CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 813 // CHECK9-NEXT: entry: 814 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 815 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 816 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 817 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 818 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 819 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 820 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 821 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 822 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 823 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 824 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 825 // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 826 // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 827 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 828 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 829 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 830 // CHECK9-NEXT: ret void 831 // 832 // 833 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 834 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 835 // CHECK9-NEXT: entry: 836 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 837 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 838 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 839 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 840 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 841 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 842 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 843 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 844 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 845 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 846 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 847 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 848 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 849 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 850 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 851 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 852 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 853 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 854 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 855 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 856 // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 857 // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 858 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 859 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 860 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 861 // CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 862 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) 863 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 864 // CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 865 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 866 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 867 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 868 // CHECK9: omp.arraycpy.body: 869 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 870 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 871 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 872 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 873 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 874 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 875 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 876 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 877 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 878 // CHECK9: omp.arraycpy.done4: 879 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 880 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 881 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 882 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 883 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 884 // CHECK9-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 885 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 886 // CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 887 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 888 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) 889 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 890 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 891 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 892 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 893 // CHECK9: arraydestroy.body: 894 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 895 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 896 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 897 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 898 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 899 // CHECK9: arraydestroy.done9: 900 // CHECK9-NEXT: ret void 901 // 902 // 903 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 904 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 905 // CHECK9-NEXT: entry: 906 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 907 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 908 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 909 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 910 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 911 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 912 // CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 913 // CHECK9-NEXT: ret void 914 // 915 // 916 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 917 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 918 // CHECK9-NEXT: entry: 919 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 920 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 921 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 922 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 923 // CHECK9-NEXT: ret void 924 // 925 // 926 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 927 // CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 928 // CHECK9-NEXT: entry: 929 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 930 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 931 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 932 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 933 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 934 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 935 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 936 // CHECK9-NEXT: ret void 937 // 938 // 939 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 940 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 941 // CHECK9-NEXT: entry: 942 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 943 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 944 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 945 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 946 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 947 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 948 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 949 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 950 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 951 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 952 // CHECK9-NEXT: ret void 953 // 954 // 955 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 956 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 957 // CHECK9-NEXT: entry: 958 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 959 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 960 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 961 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 962 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 963 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 964 // CHECK9-NEXT: ret void 965 // 966 // 967 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 968 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 969 // CHECK9-NEXT: entry: 970 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 971 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 972 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 973 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 974 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 975 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 976 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 977 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 978 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 979 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 980 // CHECK9-NEXT: ret void 981 // 982 // 983 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 984 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 985 // CHECK9-NEXT: entry: 986 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 987 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 988 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 989 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 990 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 991 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 992 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 993 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 994 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 995 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 996 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 997 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 998 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 999 // CHECK9-NEXT: ret void 1000 // 1001 // 1002 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1003 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1004 // CHECK9-NEXT: entry: 1005 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1006 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1007 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1008 // CHECK9-NEXT: ret void 1009 // 1010 // 1011 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1012 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { 1013 // CHECK9-NEXT: entry: 1014 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1015 // CHECK9-NEXT: ret void 1016 // 1017 // 1018 // CHECK11-LABEL: define {{[^@]+}}@main 1019 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1020 // CHECK11-NEXT: entry: 1021 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1022 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1023 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1024 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1025 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1026 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1027 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1028 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1029 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1030 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1031 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1032 // CHECK11-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 1033 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 1034 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 1035 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 1036 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1037 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 1038 // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 1039 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1040 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 1041 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1042 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 1043 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 1044 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 1045 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 1046 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 1047 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 1048 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1049 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1050 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 1051 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1052 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1053 // CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 1054 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 1055 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1056 // CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 1057 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP8]], align 4 1058 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1059 // CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 1060 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1061 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 1062 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 4 1063 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1064 // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 1065 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 1066 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1067 // CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 1068 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1069 // CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 1070 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 4 1071 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1072 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 1073 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 1074 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1075 // CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 1076 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1077 // CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 1078 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 4 1079 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1080 // CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 1081 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 4 1082 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1083 // CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 1084 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1085 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 1086 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP26]], align 4 1087 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1088 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1089 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP28]], align 4 1090 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1091 // CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 1092 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1093 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1094 // CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1095 // CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1096 // CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1097 // CHECK11: omp_offload.failed: 1098 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) #[[ATTR4:[0-9]+]] 1099 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1100 // CHECK11: omp_offload.cont: 1101 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 1102 // CHECK11-NEXT: store i32 [[TMP34]], i32* [[T_VAR_CASTED1]], align 4 1103 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 1104 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1105 // CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 1106 // CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP37]], align 4 1107 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1108 // CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 1109 // CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP39]], align 4 1110 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 1111 // CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 1112 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1113 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1114 // CHECK11-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1115 // CHECK11-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 1116 // CHECK11-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] 1117 // CHECK11: omp_offload.failed5: 1118 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP35]]) #[[ATTR4]] 1119 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] 1120 // CHECK11: omp_offload.cont6: 1121 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1122 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1123 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1124 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1125 // CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1126 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1127 // CHECK11: arraydestroy.body: 1128 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1129 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1130 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1131 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1132 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1133 // CHECK11: arraydestroy.done7: 1134 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1135 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 1136 // CHECK11-NEXT: ret i32 [[TMP46]] 1137 // 1138 // 1139 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1140 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1141 // CHECK11-NEXT: entry: 1142 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1143 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1144 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1145 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1146 // CHECK11-NEXT: ret void 1147 // 1148 // 1149 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1150 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1151 // CHECK11-NEXT: entry: 1152 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1153 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1154 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1155 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1156 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1157 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1158 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1159 // CHECK11-NEXT: ret void 1160 // 1161 // 1162 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 1163 // CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 1164 // CHECK11-NEXT: entry: 1165 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1166 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1167 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1168 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1169 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1170 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1171 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1172 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1173 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1174 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1175 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1176 // CHECK11-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1177 // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1178 // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1179 // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1180 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1181 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 1182 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1183 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 1184 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 1185 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1186 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 1187 // CHECK11-NEXT: ret void 1188 // 1189 // 1190 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 1191 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { 1192 // CHECK11-NEXT: entry: 1193 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1194 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1195 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1196 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1197 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1198 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1199 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1200 // CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1201 // CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1202 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1203 // CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1204 // CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1205 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1206 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1207 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1208 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1209 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1210 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1211 // CHECK11-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1212 // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1213 // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1214 // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1215 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 1216 // CHECK11-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1217 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 1218 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1219 // CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1220 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1221 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1222 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1223 // CHECK11: omp.arraycpy.body: 1224 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1225 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1226 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1227 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1228 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1229 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1230 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1231 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1232 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1233 // CHECK11: omp.arraycpy.done3: 1234 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1235 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 1236 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] 1237 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1238 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 1239 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 1240 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1241 // CHECK11-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 1242 // CHECK11-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 1243 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) 1244 // CHECK11-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 1245 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] 1246 // CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1247 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 1248 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1249 // CHECK11: arraydestroy.body: 1250 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1251 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1252 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1253 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1254 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1255 // CHECK11: arraydestroy.done8: 1256 // CHECK11-NEXT: ret void 1257 // 1258 // 1259 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1260 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1261 // CHECK11-NEXT: entry: 1262 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1263 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1264 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1265 // CHECK11-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 1266 // CHECK11-NEXT: ret void 1267 // 1268 // 1269 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1270 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1271 // CHECK11-NEXT: entry: 1272 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1273 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 1274 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1275 // CHECK11-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 1276 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1277 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 1278 // CHECK11-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1279 // CHECK11-NEXT: ret void 1280 // 1281 // 1282 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1283 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1284 // CHECK11-NEXT: entry: 1285 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1286 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1287 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1288 // CHECK11-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 1289 // CHECK11-NEXT: ret void 1290 // 1291 // 1292 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1293 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1294 // CHECK11-NEXT: entry: 1295 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1296 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1297 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1298 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1299 // CHECK11-NEXT: ret void 1300 // 1301 // 1302 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 1303 // CHECK11-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { 1304 // CHECK11-NEXT: entry: 1305 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1306 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1307 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1308 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1309 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 1310 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1311 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 1312 // CHECK11-NEXT: ret void 1313 // 1314 // 1315 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 1316 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { 1317 // CHECK11-NEXT: entry: 1318 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1319 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1320 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1321 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1322 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1323 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1324 // CHECK11-NEXT: ret void 1325 // 1326 // 1327 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1328 // CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { 1329 // CHECK11-NEXT: entry: 1330 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1331 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1332 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1333 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1334 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1335 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 1336 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1337 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1338 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1339 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 1340 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 1341 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 1342 // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1343 // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 128 1344 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1345 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1346 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1347 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 1348 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1349 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 1350 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 1351 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1352 // CHECK11-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 1353 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 1354 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1355 // CHECK11-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 1356 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 1357 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1358 // CHECK11-NEXT: store i8* null, i8** [[TMP5]], align 4 1359 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1360 // CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 1361 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 4 1362 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1363 // CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 1364 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 4 1365 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1366 // CHECK11-NEXT: store i8* null, i8** [[TMP10]], align 4 1367 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1368 // CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 1369 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 4 1370 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1371 // CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 1372 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 4 1373 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1374 // CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 1375 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1376 // CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 1377 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 4 1378 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1379 // CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 1380 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 4 1381 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1382 // CHECK11-NEXT: store i8* null, i8** [[TMP20]], align 4 1383 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1384 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1385 // CHECK11-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1386 // CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 1387 // CHECK11-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1388 // CHECK11: omp_offload.failed: 1389 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 1390 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1391 // CHECK11: omp_offload.cont: 1392 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 1393 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 1394 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 4 1395 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 1396 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 1397 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 4 1398 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 1399 // CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 1400 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 1401 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 1402 // CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1403 // CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1404 // CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 1405 // CHECK11: omp_offload.failed4: 1406 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 1407 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT5]] 1408 // CHECK11: omp_offload.cont5: 1409 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1410 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1411 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1412 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1413 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1414 // CHECK11: arraydestroy.body: 1415 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1416 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1417 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1418 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1419 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1420 // CHECK11: arraydestroy.done6: 1421 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1422 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 1423 // CHECK11-NEXT: ret i32 [[TMP35]] 1424 // 1425 // 1426 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1427 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1428 // CHECK11-NEXT: entry: 1429 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1430 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1431 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1432 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1433 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1434 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1435 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 1436 // CHECK11-NEXT: ret void 1437 // 1438 // 1439 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1440 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1441 // CHECK11-NEXT: entry: 1442 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1443 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1444 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1445 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1446 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1447 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1448 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1449 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1450 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1451 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1452 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 1453 // CHECK11-NEXT: ret void 1454 // 1455 // 1456 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1457 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1458 // CHECK11-NEXT: entry: 1459 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1460 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1461 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1462 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1463 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 1464 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1465 // CHECK11-NEXT: store i32 0, i32* [[B]], align 4 1466 // CHECK11-NEXT: ret void 1467 // 1468 // 1469 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1470 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1471 // CHECK11-NEXT: entry: 1472 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1473 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 1474 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1475 // CHECK11-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 1476 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1477 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1478 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 1479 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1480 // CHECK11-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1481 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1482 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1483 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1484 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1485 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 1486 // CHECK11-NEXT: ret void 1487 // 1488 // 1489 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1490 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1491 // CHECK11-NEXT: entry: 1492 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1493 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1494 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1495 // CHECK11-NEXT: ret void 1496 // 1497 // 1498 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1499 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1500 // CHECK11-NEXT: entry: 1501 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1502 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1503 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1504 // CHECK11-NEXT: ret void 1505 // 1506 // 1507 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1508 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1509 // CHECK11-NEXT: entry: 1510 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1511 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1512 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1513 // CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1514 // CHECK11-NEXT: ret void 1515 // 1516 // 1517 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1518 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1519 // CHECK11-NEXT: entry: 1520 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1521 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1522 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1523 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1524 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1525 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1526 // CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1527 // CHECK11-NEXT: ret void 1528 // 1529 // 1530 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 1531 // CHECK11-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1532 // CHECK11-NEXT: entry: 1533 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 1534 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1535 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 1536 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 1537 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1538 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1539 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1540 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1541 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 1542 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1543 // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1544 // CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1545 // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 1546 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 1547 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 1548 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 1549 // CHECK11-NEXT: ret void 1550 // 1551 // 1552 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 1553 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1554 // CHECK11-NEXT: entry: 1555 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1556 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1557 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1558 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 1559 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 1560 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 1561 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1562 // CHECK11-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 1563 // CHECK11-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 1564 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1565 // CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1566 // CHECK11-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1567 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1568 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1569 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1570 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1571 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1572 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 1573 // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1574 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1575 // CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1576 // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 1577 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 1578 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 1579 // CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1580 // CHECK11-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1581 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) 1582 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1583 // CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 1584 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1585 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 1586 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1587 // CHECK11: omp.arraycpy.body: 1588 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1589 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1590 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1591 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1592 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1593 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1594 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1595 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 1596 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1597 // CHECK11: omp.arraycpy.done4: 1598 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1599 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 1600 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 1601 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 1602 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 1603 // CHECK11-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 1604 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1605 // CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 1606 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 1607 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) 1608 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1609 // CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1610 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 1611 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1612 // CHECK11: arraydestroy.body: 1613 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1614 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1615 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1616 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1617 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1618 // CHECK11: arraydestroy.done9: 1619 // CHECK11-NEXT: ret void 1620 // 1621 // 1622 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1623 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1624 // CHECK11-NEXT: entry: 1625 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1626 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 1627 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1628 // CHECK11-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 1629 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1630 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 1631 // CHECK11-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1632 // CHECK11-NEXT: ret void 1633 // 1634 // 1635 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1636 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1637 // CHECK11-NEXT: entry: 1638 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1639 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1640 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1641 // CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1642 // CHECK11-NEXT: ret void 1643 // 1644 // 1645 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 1646 // CHECK11-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1647 // CHECK11-NEXT: entry: 1648 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 1649 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1650 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1651 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1652 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1653 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1654 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 1655 // CHECK11-NEXT: ret void 1656 // 1657 // 1658 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 1659 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1660 // CHECK11-NEXT: entry: 1661 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1662 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1663 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 1664 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1665 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1666 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1667 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1668 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1669 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1670 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1671 // CHECK11-NEXT: ret void 1672 // 1673 // 1674 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1675 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1676 // CHECK11-NEXT: entry: 1677 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1678 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1679 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1680 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1681 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1682 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1683 // CHECK11-NEXT: ret void 1684 // 1685 // 1686 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1687 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1688 // CHECK11-NEXT: entry: 1689 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1690 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1691 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1692 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1693 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1694 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1695 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1696 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1697 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1698 // CHECK11-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1699 // CHECK11-NEXT: ret void 1700 // 1701 // 1702 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1703 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1704 // CHECK11-NEXT: entry: 1705 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1706 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 1707 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1708 // CHECK11-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 1709 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1710 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1711 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 1712 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1713 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1714 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1715 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1716 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1717 // CHECK11-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1718 // CHECK11-NEXT: ret void 1719 // 1720 // 1721 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1722 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1723 // CHECK11-NEXT: entry: 1724 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1725 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1726 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1727 // CHECK11-NEXT: ret void 1728 // 1729 // 1730 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1731 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] { 1732 // CHECK11-NEXT: entry: 1733 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 1734 // CHECK11-NEXT: ret void 1735 // 1736 // 1737 // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg 1738 // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 1739 // CHECK17-NEXT: entry: 1740 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1741 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 1742 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1743 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 1744 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1745 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1746 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1747 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1748 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 8 1749 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 8 1750 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 8 1751 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 1752 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1753 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 1754 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1755 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 1756 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1757 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1758 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1759 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1760 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1761 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 1762 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 1763 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 1764 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 1765 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 1766 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 1767 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 1768 // CHECK17-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 1769 // CHECK17-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 1770 // CHECK17-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 1771 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 1772 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1773 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 1774 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 1775 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 1776 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 1777 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast [8 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1778 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP15]], i8* align 8 bitcast ([8 x i64]* @.offload_sizes to i8*), i64 64, i1 false) 1779 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1780 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 1781 // CHECK17-NEXT: store float* [[TMP8]], float** [[TMP17]], align 8 1782 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1783 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to float** 1784 // CHECK17-NEXT: store float* [[TMP8]], float** [[TMP19]], align 8 1785 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1786 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 1787 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1788 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 1789 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP22]], align 8 1790 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1791 // CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** 1792 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 1793 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1794 // CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8 1795 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1796 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1797 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP27]], align 8 1798 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1799 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1800 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 1801 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1802 // CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 1803 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1804 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to ppc_fp128** 1805 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP32]], align 8 1806 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1807 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** 1808 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 1809 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1810 // CHECK17-NEXT: store i8* null, i8** [[TMP35]], align 8 1811 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1812 // CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 1813 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP37]], align 8 1814 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1815 // CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 1816 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP39]], align 8 1817 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1818 // CHECK17-NEXT: store i8* null, i8** [[TMP40]], align 8 1819 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 1820 // CHECK17-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* 1821 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP42]], align 8 1822 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 1823 // CHECK17-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64* 1824 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP44]], align 8 1825 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 1826 // CHECK17-NEXT: store i8* null, i8** [[TMP45]], align 8 1827 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 1828 // CHECK17-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to double** 1829 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP47]], align 8 1830 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 1831 // CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** 1832 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP49]], align 8 1833 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 1834 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP50]], align 8 1835 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 1836 // CHECK17-NEXT: store i8* null, i8** [[TMP51]], align 8 1837 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 1838 // CHECK17-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 1839 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP53]], align 8 1840 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 1841 // CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i64* 1842 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP55]], align 8 1843 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 1844 // CHECK17-NEXT: store i8* null, i8** [[TMP56]], align 8 1845 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1846 // CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1847 // CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1848 // CHECK17-NEXT: [[TMP60:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, i32 8, i8** [[TMP57]], i8** [[TMP58]], i64* [[TMP59]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1849 // CHECK17-NEXT: [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0 1850 // CHECK17-NEXT: br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1851 // CHECK17: omp_offload.failed: 1852 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(float* [[TMP8]], %struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 1853 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 1854 // CHECK17: omp_offload.cont: 1855 // CHECK17-NEXT: [[TMP62:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1856 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP62]]) 1857 // CHECK17-NEXT: ret void 1858 // 1859 // 1860 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 1861 // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 1862 // CHECK17-NEXT: entry: 1863 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1864 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 1865 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1866 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 1867 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 1868 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 1869 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 1870 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1871 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1872 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 1873 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1874 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 1875 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 1876 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 1877 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 1878 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1879 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1880 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 1881 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 1882 // CHECK17-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 1883 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1884 // CHECK17-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 1885 // CHECK17-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 1886 // CHECK17-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 8 1887 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, ppc_fp128*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[CONV]], i64 [[TMP0]], ppc_fp128* [[TMP5]], float* [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]]) 1888 // CHECK17-NEXT: ret void 1889 // 1890 // 1891 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 1892 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 1893 // CHECK17-NEXT: entry: 1894 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1895 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1896 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 1897 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 1898 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1899 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 1900 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1901 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 1902 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 1903 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 1904 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1905 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1906 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1907 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1908 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1909 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 1910 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 1911 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1912 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 1913 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1914 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 1915 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 1916 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 1917 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 1918 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1919 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 1920 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 1921 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 1922 // CHECK17-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 1923 // CHECK17-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 1924 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 1925 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 1926 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1927 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 1928 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 1929 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 1930 // CHECK17-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 1931 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 1932 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) 1933 // CHECK17-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 1934 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 1935 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 1936 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 1937 // CHECK17-NEXT: [[TMP14:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 1938 // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 signext [[TMP13]], ppc_fp128* [[TMP14]]) 1939 // CHECK17-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1940 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 1941 // CHECK17-NEXT: ret void 1942 // 1943 // 1944 // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg 1945 // CHECK17-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 1946 // CHECK17-NEXT: entry: 1947 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1948 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 1949 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1950 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 1951 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1952 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1953 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1954 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1955 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 8 1956 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 8 1957 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 8 1958 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 1959 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1960 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 1961 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1962 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 1963 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1964 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1965 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1966 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1967 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1968 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1969 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 1970 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 1971 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 1972 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 1973 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 1974 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 1975 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 1976 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 1977 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 1978 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 1979 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 1980 // CHECK17-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 1981 // CHECK17-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 1982 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 1983 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1984 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 1985 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 1986 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 1987 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 1988 // CHECK17-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1989 // CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 1990 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr i32, i32* [[B2]], i32 1 1991 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i32* [[A3]] to i8* 1992 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP15]] to i8* 1993 // CHECK17-NEXT: [[TMP18:%.*]] = ptrtoint i8* [[TMP17]] to i64 1994 // CHECK17-NEXT: [[TMP19:%.*]] = ptrtoint i8* [[TMP16]] to i64 1995 // CHECK17-NEXT: [[TMP20:%.*]] = sub i64 [[TMP18]], [[TMP19]] 1996 // CHECK17-NEXT: [[TMP21:%.*]] = sdiv exact i64 [[TMP20]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 1997 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1998 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP22]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.2 to i8*), i64 80, i1 false) 1999 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2000 // CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** 2001 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 2002 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2003 // CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to %struct.St** 2004 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP26]], align 8 2005 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2006 // CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 2007 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2008 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 2009 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 2010 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2011 // CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 2012 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP31]], align 8 2013 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2014 // CHECK17-NEXT: store i8* null, i8** [[TMP32]], align 8 2015 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2016 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** 2017 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 2018 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2019 // CHECK17-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to ppc_fp128** 2020 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP36]], align 8 2021 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2022 // CHECK17-NEXT: store i8* null, i8** [[TMP37]], align 8 2023 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2024 // CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 2025 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP39]], align 8 2026 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2027 // CHECK17-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 2028 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP41]], align 8 2029 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2030 // CHECK17-NEXT: store i8* null, i8** [[TMP42]], align 8 2031 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2032 // CHECK17-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64* 2033 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP44]], align 8 2034 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2035 // CHECK17-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 2036 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP46]], align 8 2037 // CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 2038 // CHECK17-NEXT: store i8* null, i8** [[TMP47]], align 8 2039 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 2040 // CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** 2041 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP49]], align 8 2042 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 2043 // CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** 2044 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP51]], align 8 2045 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 2046 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP52]], align 8 2047 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 2048 // CHECK17-NEXT: store i8* null, i8** [[TMP53]], align 8 2049 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 2050 // CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to %struct.St** 2051 // CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP55]], align 8 2052 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 2053 // CHECK17-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to i32** 2054 // CHECK17-NEXT: store i32* [[A3]], i32** [[TMP57]], align 8 2055 // CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2056 // CHECK17-NEXT: store i64 [[TMP21]], i64* [[TMP58]], align 8 2057 // CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 2058 // CHECK17-NEXT: store i8* null, i8** [[TMP59]], align 8 2059 // CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 2060 // CHECK17-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to %struct.St** 2061 // CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP61]], align 8 2062 // CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 2063 // CHECK17-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32** 2064 // CHECK17-NEXT: store i32* [[B2]], i32** [[TMP63]], align 8 2065 // CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 2066 // CHECK17-NEXT: store i8* null, i8** [[TMP64]], align 8 2067 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 2068 // CHECK17-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to %struct.St** 2069 // CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP66]], align 8 2070 // CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 2071 // CHECK17-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32** 2072 // CHECK17-NEXT: store i32* [[A3]], i32** [[TMP68]], align 8 2073 // CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 2074 // CHECK17-NEXT: store i8* null, i8** [[TMP69]], align 8 2075 // CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 2076 // CHECK17-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* 2077 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP71]], align 8 2078 // CHECK17-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 2079 // CHECK17-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64* 2080 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP73]], align 8 2081 // CHECK17-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 2082 // CHECK17-NEXT: store i8* null, i8** [[TMP74]], align 8 2083 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2084 // CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2085 // CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2086 // CHECK17-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, i32 10, i8** [[TMP75]], i8** [[TMP76]], i64* [[TMP77]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2087 // CHECK17-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0 2088 // CHECK17-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2089 // CHECK17: omp_offload.failed: 2090 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(%struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], %struct.St* [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] 2091 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 2092 // CHECK17: omp_offload.cont: 2093 // CHECK17-NEXT: [[TMP80:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2094 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP80]]) 2095 // CHECK17-NEXT: ret void 2096 // 2097 // 2098 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 2099 // CHECK17-SAME: (%struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { 2100 // CHECK17-NEXT: entry: 2101 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 2102 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2103 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 2104 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 2105 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 2106 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 2107 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 2108 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 2109 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 2110 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2111 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 2112 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 2113 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 2114 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 2115 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 2116 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 2117 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2118 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 2119 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 2120 // CHECK17-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 2121 // CHECK17-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 2122 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 2123 // CHECK17-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 2124 // CHECK17-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 2125 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, ppc_fp128*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP0]], ppc_fp128* [[TMP5]], %struct.St* [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]], i32* [[CONV]], %struct.St* [[TMP6]]) 2126 // CHECK17-NEXT: ret void 2127 // 2128 // 2129 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 2130 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 2131 // CHECK17-NEXT: entry: 2132 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2133 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2134 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2135 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 2136 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 2137 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 2138 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 2139 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 2140 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 2141 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 2142 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2143 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2144 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2145 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2146 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2147 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2148 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 2149 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 2150 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 2151 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 2152 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 2153 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 2154 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 2155 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2156 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 2157 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 2158 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 2159 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 2160 // CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 2161 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 2162 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 2163 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 2164 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 2165 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 2166 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 2167 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 2168 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 2169 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 2170 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 2171 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 [[TMP9]], i1 false) 2172 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 2173 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 2174 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 2175 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 2176 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 2177 // CHECK17-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP3]] 2178 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i64 [[TMP13]] 2179 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 2180 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 2181 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 2182 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] 2183 // CHECK17-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 2184 // CHECK17-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 2185 // CHECK17-NEXT: [[TMP15:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 2186 // CHECK17-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 2187 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 2188 // CHECK17-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 2189 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP15]], i64 [[IDXPROM11]] 2190 // CHECK17-NEXT: store ppc_fp128 [[CONV9]], ppc_fp128* [[ARRAYIDX12]], align 16 2191 // CHECK17-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2192 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 2193 // CHECK17-NEXT: ret void 2194 // 2195 // 2196 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2197 // CHECK17-SAME: () #[[ATTR5:[0-9]+]] { 2198 // CHECK17-NEXT: entry: 2199 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 2200 // CHECK17-NEXT: ret void 2201 // 2202 // 2203 // CHECK19-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 2204 // CHECK19-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 2205 // CHECK19-NEXT: entry: 2206 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2207 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 2208 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2209 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 2210 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2211 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2212 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2213 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2214 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 4 2215 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 4 2216 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 4 2217 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 2218 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2219 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 2220 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2221 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 2222 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2223 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2224 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2225 // CHECK19-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 2226 // CHECK19-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 2227 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2228 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 2229 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2230 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 2231 // CHECK19-NEXT: [[TMP5:%.*]] = load float*, float** [[A_ADDR]], align 4 2232 // CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 2233 // CHECK19-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 2234 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 2235 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 2236 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 2237 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2238 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 2239 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 2240 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast [8 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2241 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 bitcast ([8 x i64]* @.offload_sizes to i8*), i32 64, i1 false) 2242 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2243 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to float** 2244 // CHECK19-NEXT: store float* [[TMP5]], float** [[TMP15]], align 4 2245 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2246 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to float** 2247 // CHECK19-NEXT: store float* [[TMP5]], float** [[TMP17]], align 4 2248 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2249 // CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 2250 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2251 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.St** 2252 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP20]], align 4 2253 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2254 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 2255 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 2256 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2257 // CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 2258 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2259 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2260 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP25]], align 4 2261 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2262 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2263 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 2264 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2265 // CHECK19-NEXT: store i8* null, i8** [[TMP28]], align 4 2266 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2267 // CHECK19-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to x86_fp80** 2268 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP30]], align 4 2269 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2270 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** 2271 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 2272 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2273 // CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 2274 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2275 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 2276 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP35]], align 4 2277 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2278 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 2279 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP37]], align 4 2280 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2281 // CHECK19-NEXT: store i8* null, i8** [[TMP38]], align 4 2282 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 2283 // CHECK19-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* 2284 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP40]], align 4 2285 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 2286 // CHECK19-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32* 2287 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP42]], align 4 2288 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 2289 // CHECK19-NEXT: store i8* null, i8** [[TMP43]], align 4 2290 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 2291 // CHECK19-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to double** 2292 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP45]], align 4 2293 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 2294 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to double** 2295 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP47]], align 4 2296 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2297 // CHECK19-NEXT: store i64 [[TMP12]], i64* [[TMP48]], align 4 2298 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 2299 // CHECK19-NEXT: store i8* null, i8** [[TMP49]], align 4 2300 // CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 2301 // CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 2302 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP51]], align 4 2303 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 2304 // CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 2305 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP53]], align 4 2306 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 2307 // CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 2308 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2309 // CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2310 // CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2311 // CHECK19-NEXT: [[TMP58:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, i32 8, i8** [[TMP55]], i8** [[TMP56]], i64* [[TMP57]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2312 // CHECK19-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0 2313 // CHECK19-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2314 // CHECK19: omp_offload.failed: 2315 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(float* [[TMP5]], %struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] 2316 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 2317 // CHECK19: omp_offload.cont: 2318 // CHECK19-NEXT: [[TMP60:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2319 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP60]]) 2320 // CHECK19-NEXT: ret void 2321 // 2322 // 2323 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 2324 // CHECK19-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 2325 // CHECK19-NEXT: entry: 2326 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2327 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 2328 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2329 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 2330 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2331 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2332 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 2333 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2334 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2335 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 2336 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2337 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 2338 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 2339 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 2340 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 2341 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2342 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2343 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 2344 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 2345 // CHECK19-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 2346 // CHECK19-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 2347 // CHECK19-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 2348 // CHECK19-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 4 2349 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i32, x86_fp80*, float*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[N_ADDR]], i32 [[TMP0]], x86_fp80* [[TMP5]], float* [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]]) 2350 // CHECK19-NEXT: ret void 2351 // 2352 // 2353 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 2354 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 2355 // CHECK19-NEXT: entry: 2356 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2357 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2358 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 2359 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 2360 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2361 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 2362 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 2363 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2364 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2365 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 2366 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2367 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2368 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2369 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2370 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2371 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 2372 // CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 2373 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2374 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 2375 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 2376 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 2377 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 2378 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 2379 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 2380 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2381 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 2382 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 2383 // CHECK19-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 2384 // CHECK19-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 2385 // CHECK19-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 4 2386 // CHECK19-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2387 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 2388 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 2389 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 2390 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2391 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 2392 // CHECK19-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 2393 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 2394 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i32 [[TMP8]], i1 false) 2395 // CHECK19-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 2396 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i32 0 2397 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 2398 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 2399 // CHECK19-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 2400 // CHECK19-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) 2401 // CHECK19-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2402 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 2403 // CHECK19-NEXT: ret void 2404 // 2405 // 2406 // CHECK19-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 2407 // CHECK19-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 2408 // CHECK19-NEXT: entry: 2409 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2410 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 2411 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2412 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 2413 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2414 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2415 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2416 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2417 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 4 2418 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 4 2419 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 4 2420 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 2421 // CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2422 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 2423 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2424 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 2425 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2426 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2427 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2428 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2429 // CHECK19-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 2430 // CHECK19-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 2431 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2432 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 2433 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2434 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 2435 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 2436 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 2437 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 2438 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 2439 // CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 2440 // CHECK19-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 2441 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 2442 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 2443 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 2444 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2445 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 2446 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 2447 // CHECK19-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2448 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 2449 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[B2]], i32 1 2450 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i32* [[A3]] to i8* 2451 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP13]] to i8* 2452 // CHECK19-NEXT: [[TMP16:%.*]] = ptrtoint i8* [[TMP15]] to i64 2453 // CHECK19-NEXT: [[TMP17:%.*]] = ptrtoint i8* [[TMP14]] to i64 2454 // CHECK19-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] 2455 // CHECK19-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 2456 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2457 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.2 to i8*), i32 80, i1 false) 2458 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2459 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 2460 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 2461 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2462 // CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** 2463 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP24]], align 4 2464 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2465 // CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 2466 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2467 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2468 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 2469 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2470 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 2471 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP29]], align 4 2472 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2473 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 2474 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2475 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** 2476 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 2477 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2478 // CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to x86_fp80** 2479 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP34]], align 4 2480 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2481 // CHECK19-NEXT: store i8* null, i8** [[TMP35]], align 4 2482 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2483 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 2484 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP37]], align 4 2485 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2486 // CHECK19-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 2487 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP39]], align 4 2488 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2489 // CHECK19-NEXT: store i8* null, i8** [[TMP40]], align 4 2490 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2491 // CHECK19-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32* 2492 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP42]], align 4 2493 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2494 // CHECK19-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* 2495 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP44]], align 4 2496 // CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2497 // CHECK19-NEXT: store i8* null, i8** [[TMP45]], align 4 2498 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 2499 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to double** 2500 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP47]], align 4 2501 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 2502 // CHECK19-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to double** 2503 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP49]], align 4 2504 // CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 2505 // CHECK19-NEXT: store i64 [[TMP12]], i64* [[TMP50]], align 4 2506 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 2507 // CHECK19-NEXT: store i8* null, i8** [[TMP51]], align 4 2508 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 2509 // CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to %struct.St** 2510 // CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP53]], align 4 2511 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 2512 // CHECK19-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i32** 2513 // CHECK19-NEXT: store i32* [[A3]], i32** [[TMP55]], align 4 2514 // CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2515 // CHECK19-NEXT: store i64 [[TMP19]], i64* [[TMP56]], align 4 2516 // CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 2517 // CHECK19-NEXT: store i8* null, i8** [[TMP57]], align 4 2518 // CHECK19-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 2519 // CHECK19-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to %struct.St** 2520 // CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP59]], align 4 2521 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 2522 // CHECK19-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32** 2523 // CHECK19-NEXT: store i32* [[B2]], i32** [[TMP61]], align 4 2524 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 2525 // CHECK19-NEXT: store i8* null, i8** [[TMP62]], align 4 2526 // CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 2527 // CHECK19-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to %struct.St** 2528 // CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP64]], align 4 2529 // CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 2530 // CHECK19-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to i32** 2531 // CHECK19-NEXT: store i32* [[A3]], i32** [[TMP66]], align 4 2532 // CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 2533 // CHECK19-NEXT: store i8* null, i8** [[TMP67]], align 4 2534 // CHECK19-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 2535 // CHECK19-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32* 2536 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP69]], align 4 2537 // CHECK19-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 2538 // CHECK19-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* 2539 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP71]], align 4 2540 // CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 2541 // CHECK19-NEXT: store i8* null, i8** [[TMP72]], align 4 2542 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2543 // CHECK19-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2544 // CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2545 // CHECK19-NEXT: [[TMP76:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, i32 10, i8** [[TMP73]], i8** [[TMP74]], i64* [[TMP75]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2546 // CHECK19-NEXT: [[TMP77:%.*]] = icmp ne i32 [[TMP76]], 0 2547 // CHECK19-NEXT: br i1 [[TMP77]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2548 // CHECK19: omp_offload.failed: 2549 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(%struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], %struct.St* [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] 2550 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 2551 // CHECK19: omp_offload.cont: 2552 // CHECK19-NEXT: [[TMP78:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2553 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP78]]) 2554 // CHECK19-NEXT: ret void 2555 // 2556 // 2557 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 2558 // CHECK19-SAME: (%struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { 2559 // CHECK19-NEXT: entry: 2560 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 2561 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2562 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 2563 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2564 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2565 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 2566 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2567 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2568 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 2569 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2570 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 2571 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 2572 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 2573 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 2574 // CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2575 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2576 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2577 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 2578 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 2579 // CHECK19-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 2580 // CHECK19-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2581 // CHECK19-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 2582 // CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 2583 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, x86_fp80*, %struct.St*, i32, i32, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP0]], x86_fp80* [[TMP5]], %struct.St* [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]], i32* [[N_ADDR]], %struct.St* [[TMP6]]) 2584 // CHECK19-NEXT: ret void 2585 // 2586 // 2587 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 2588 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 2589 // CHECK19-NEXT: entry: 2590 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2591 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2592 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2593 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 2594 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2595 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2596 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2597 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 2598 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 2599 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 2600 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2601 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2602 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2603 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2604 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2605 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2606 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 2607 // CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2608 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 2609 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 2610 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 2611 // CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 2612 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 2613 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2614 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2615 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 2616 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 2617 // CHECK19-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 2618 // CHECK19-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 4 2619 // CHECK19-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 2620 // CHECK19-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 4 2621 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2622 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 2623 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 2624 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 2625 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2626 // CHECK19-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 2627 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 2628 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 2629 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 [[TMP9]], i1 false) 2630 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 2631 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 2632 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 2633 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 2634 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 2635 // CHECK19-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP3]] 2636 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i32 [[TMP13]] 2637 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 2638 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 2639 // CHECK19-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] 2640 // CHECK19-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 2641 // CHECK19-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 2642 // CHECK19-NEXT: [[TMP15:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 2643 // CHECK19-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 2644 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 2645 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP15]], i32 [[TMP16]] 2646 // CHECK19-NEXT: store x86_fp80 [[CONV9]], x86_fp80* [[ARRAYIDX11]], align 4 2647 // CHECK19-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2648 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 2649 // CHECK19-NEXT: ret void 2650 // 2651 // 2652 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2653 // CHECK19-SAME: () #[[ATTR5:[0-9]+]] { 2654 // CHECK19-NEXT: entry: 2655 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 2656 // CHECK19-NEXT: ret void 2657 // 2658