1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute simd firstprivate(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute simd firstprivate(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global and bound tid vars 80 // skip loop vars 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 [&]() { 85 g = 2; 86 g1 = 2; 87 sivar = 4; 88 89 }(); 90 } 91 }(); 92 return 0; 93 #else 94 #pragma omp target 95 #pragma omp teams distribute simd firstprivate(t_var, vec, s_arr, var, sivar) 96 for (int i = 0; i < 2; ++i) { 97 vec[i] = t_var; 98 s_arr[i] = var; 99 sivar += i; 100 } 101 return tmain<int>(); 102 #endif 103 } 104 105 106 107 108 109 // Skip global and bound tid vars 110 // Skip temp vars for loop 111 112 // param copy 113 114 // T_VAR and SIVAR 115 116 // preparation vars 117 118 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 119 120 // firstprivate(s_arr) 121 122 // firstprivate(var) 123 124 125 126 127 128 129 // Skip global and bound tid vars 130 // Skip temp vars for loop 131 132 // param copy 133 134 135 // T_VAR and preparation variables 136 137 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 138 139 // firstprivate(s_arr) 140 141 // firstprivate(var) 142 143 144 #endif 145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 147 // CHECK1-NEXT: entry: 148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 154 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 157 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 164 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 170 // CHECK1-NEXT: ret void 171 // 172 // 173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 174 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 175 // CHECK1-NEXT: entry: 176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 177 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 178 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 182 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 183 // CHECK1-NEXT: ret void 184 // 185 // 186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 187 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 188 // CHECK1-NEXT: entry: 189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 190 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 196 // CHECK1-SAME: () #[[ATTR0]] { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 201 // CHECK1-NEXT: ret void 202 // 203 // 204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 205 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 206 // CHECK1-NEXT: entry: 207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 209 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 210 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 211 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 214 // CHECK1-NEXT: ret void 215 // 216 // 217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 218 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 219 // CHECK1-NEXT: entry: 220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 221 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 223 // CHECK1: arraydestroy.body: 224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 229 // CHECK1: arraydestroy.done1: 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 234 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 238 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 239 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 246 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 247 // CHECK1-NEXT: ret void 248 // 249 // 250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 251 // CHECK1-SAME: () #[[ATTR0]] { 252 // CHECK1-NEXT: entry: 253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK1-LABEL: define {{[^@]+}}@main 259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 260 // CHECK1-NEXT: entry: 261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 262 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 263 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 264 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 265 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 266 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 267 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 269 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 270 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 271 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 272 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 273 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 274 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 275 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 276 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 277 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 278 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 279 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 280 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 281 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* 282 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 283 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 284 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 285 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 286 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 287 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8 288 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 289 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 290 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8 291 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 292 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 293 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 294 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 295 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 296 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 297 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 298 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 299 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 300 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 301 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 302 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 303 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 304 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 305 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 306 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 307 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 308 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 309 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 310 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 311 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 312 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 313 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 314 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 315 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 316 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 317 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 318 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 319 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 320 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 321 // CHECK1-NEXT: store i32 1, i32* [[TMP31]], align 4 322 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 323 // CHECK1-NEXT: store i32 5, i32* [[TMP32]], align 4 324 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 325 // CHECK1-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8 326 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 327 // CHECK1-NEXT: store i8** [[TMP30]], i8*** [[TMP34]], align 8 328 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 329 // CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP35]], align 8 330 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 331 // CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP36]], align 8 332 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 333 // CHECK1-NEXT: store i8** null, i8*** [[TMP37]], align 8 334 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 335 // CHECK1-NEXT: store i8** null, i8*** [[TMP38]], align 8 336 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 337 // CHECK1-NEXT: store i64 2, i64* [[TMP39]], align 8 338 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 339 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 340 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 341 // CHECK1: omp_offload.failed: 342 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 343 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 344 // CHECK1: omp_offload.cont: 345 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 346 // CHECK1-NEXT: ret i32 [[CALL]] 347 // 348 // 349 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 350 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 351 // CHECK1-NEXT: entry: 352 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 353 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 354 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 355 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 356 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 357 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 358 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 359 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 360 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 361 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 362 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 363 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 364 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 365 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 366 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 367 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 368 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 369 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 370 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 371 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 372 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 373 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 374 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 375 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 376 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 377 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 378 // CHECK1-NEXT: ret void 379 // 380 // 381 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 382 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 383 // CHECK1-NEXT: entry: 384 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 385 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 386 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 387 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 388 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 389 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 390 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 391 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 392 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 393 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 394 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 395 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 396 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 397 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 398 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 399 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 400 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 401 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 402 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 403 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 404 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 405 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 406 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 407 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 408 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 409 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 410 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 411 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 412 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 413 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 414 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 415 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 416 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 417 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 418 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 419 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 420 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 421 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 422 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 423 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 424 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 425 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 426 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 427 // CHECK1: omp.arraycpy.body: 428 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 429 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 430 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 431 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 432 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 433 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 434 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 435 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 436 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 437 // CHECK1: omp.arraycpy.done4: 438 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 439 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) 440 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 441 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 442 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 443 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 444 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 445 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 446 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 447 // CHECK1: cond.true: 448 // CHECK1-NEXT: br label [[COND_END:%.*]] 449 // CHECK1: cond.false: 450 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 451 // CHECK1-NEXT: br label [[COND_END]] 452 // CHECK1: cond.end: 453 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 454 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 455 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 456 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 457 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 458 // CHECK1: omp.inner.for.cond: 459 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 460 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 461 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 462 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 463 // CHECK1: omp.inner.for.cond.cleanup: 464 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 465 // CHECK1: omp.inner.for.body: 466 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 467 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 468 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 469 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 470 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5 471 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 472 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 473 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 474 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 475 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 476 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 477 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 478 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* 479 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 480 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 481 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 482 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5 483 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 484 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5 485 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 486 // CHECK1: omp.body.continue: 487 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 488 // CHECK1: omp.inner.for.inc: 489 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 490 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 491 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 492 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 493 // CHECK1: omp.inner.for.end: 494 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 495 // CHECK1: omp.loop.exit: 496 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 497 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 498 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 499 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 500 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 501 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 502 // CHECK1: .omp.final.then: 503 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 504 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 505 // CHECK1: .omp.final.done: 506 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 507 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 508 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 509 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 510 // CHECK1: arraydestroy.body: 511 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 512 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 513 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 514 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 515 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 516 // CHECK1: arraydestroy.done13: 517 // CHECK1-NEXT: ret void 518 // 519 // 520 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 521 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 522 // CHECK1-NEXT: entry: 523 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 524 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 525 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 526 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 527 // CHECK1-NEXT: ret void 528 // 529 // 530 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 531 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 532 // CHECK1-NEXT: entry: 533 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 534 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 535 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 536 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 537 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 538 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 539 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 540 // CHECK1-NEXT: ret void 541 // 542 // 543 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 544 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 545 // CHECK1-NEXT: entry: 546 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 547 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 548 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 549 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 550 // CHECK1-NEXT: ret void 551 // 552 // 553 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 554 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 555 // CHECK1-NEXT: entry: 556 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 557 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 558 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 559 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 560 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 561 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 562 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 563 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 564 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 565 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 566 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 567 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 568 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 569 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 570 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 571 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 572 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 573 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 574 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 575 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 576 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 577 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 578 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 579 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 580 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 581 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 582 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 583 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 584 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 585 // CHECK1-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 586 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 587 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 588 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 589 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 590 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 591 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 592 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 593 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 594 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 595 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 596 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 597 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 598 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 599 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 600 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 601 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 602 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 603 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 604 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 605 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 606 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 607 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 608 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 609 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 610 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 611 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 612 // CHECK1-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 613 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 614 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 615 // CHECK1-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 616 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 617 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 618 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 619 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 620 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 621 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 622 // CHECK1-NEXT: store i32 1, i32* [[TMP29]], align 4 623 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 624 // CHECK1-NEXT: store i32 4, i32* [[TMP30]], align 4 625 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 626 // CHECK1-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 8 627 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 628 // CHECK1-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8 629 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 630 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP33]], align 8 631 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 632 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP34]], align 8 633 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 634 // CHECK1-NEXT: store i8** null, i8*** [[TMP35]], align 8 635 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 636 // CHECK1-NEXT: store i8** null, i8*** [[TMP36]], align 8 637 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 638 // CHECK1-NEXT: store i64 2, i64* [[TMP37]], align 8 639 // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 640 // CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 641 // CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 642 // CHECK1: omp_offload.failed: 643 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 644 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 645 // CHECK1: omp_offload.cont: 646 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 647 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 648 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 649 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 650 // CHECK1: arraydestroy.body: 651 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 652 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 653 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 654 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 655 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 656 // CHECK1: arraydestroy.done2: 657 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 658 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[RETVAL]], align 4 659 // CHECK1-NEXT: ret i32 [[TMP41]] 660 // 661 // 662 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 663 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 664 // CHECK1-NEXT: entry: 665 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 666 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 667 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 668 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 669 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 670 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 671 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4 672 // CHECK1-NEXT: ret void 673 // 674 // 675 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 676 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 677 // CHECK1-NEXT: entry: 678 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 679 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 680 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 681 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 682 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 683 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 684 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 685 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 686 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 687 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 688 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 689 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 690 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 691 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 692 // CHECK1-NEXT: ret void 693 // 694 // 695 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 696 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 697 // CHECK1-NEXT: entry: 698 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 699 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 700 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 701 // CHECK1-NEXT: ret void 702 // 703 // 704 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 705 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 706 // CHECK1-NEXT: entry: 707 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 708 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 709 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 710 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 711 // CHECK1-NEXT: ret void 712 // 713 // 714 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 715 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 716 // CHECK1-NEXT: entry: 717 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 718 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 719 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 720 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 721 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 722 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 723 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 724 // CHECK1-NEXT: ret void 725 // 726 // 727 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 728 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 729 // CHECK1-NEXT: entry: 730 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 731 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 732 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 733 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 734 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 735 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 736 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 737 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 738 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 739 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 740 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 741 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 742 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 743 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 744 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 745 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 746 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 747 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 748 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 749 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 750 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 751 // CHECK1-NEXT: ret void 752 // 753 // 754 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 755 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 756 // CHECK1-NEXT: entry: 757 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 758 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 759 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 760 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 761 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 762 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 763 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 764 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 765 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 766 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 767 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 768 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 769 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 770 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 771 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 772 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 773 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 774 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 775 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 776 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 777 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 778 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 779 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 780 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 781 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 782 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 783 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 784 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 785 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 786 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 787 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 788 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 789 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 790 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 791 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 792 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 793 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 794 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 795 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 796 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 797 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 798 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 799 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 800 // CHECK1: omp.arraycpy.body: 801 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 802 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 803 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 804 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 805 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 806 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 807 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 808 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 809 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 810 // CHECK1: omp.arraycpy.done4: 811 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 812 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 813 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) 814 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 815 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 816 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 817 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 818 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 819 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 820 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 821 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 822 // CHECK1: cond.true: 823 // CHECK1-NEXT: br label [[COND_END:%.*]] 824 // CHECK1: cond.false: 825 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 826 // CHECK1-NEXT: br label [[COND_END]] 827 // CHECK1: cond.end: 828 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 829 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 830 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 831 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 832 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 833 // CHECK1: omp.inner.for.cond: 834 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 835 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 836 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 837 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 838 // CHECK1: omp.inner.for.cond.cleanup: 839 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 840 // CHECK1: omp.inner.for.body: 841 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 842 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 843 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 844 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 845 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11 846 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 847 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 848 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 849 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 850 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 851 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 852 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 853 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 854 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* 855 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 856 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !11 857 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 858 // CHECK1: omp.body.continue: 859 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 860 // CHECK1: omp.inner.for.inc: 861 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 862 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 863 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 864 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 865 // CHECK1: omp.inner.for.end: 866 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 867 // CHECK1: omp.loop.exit: 868 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 869 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 870 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 871 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 872 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 873 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 874 // CHECK1: .omp.final.then: 875 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 876 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 877 // CHECK1: .omp.final.done: 878 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 879 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 880 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 881 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 882 // CHECK1: arraydestroy.body: 883 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 884 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 885 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 886 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 887 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 888 // CHECK1: arraydestroy.done13: 889 // CHECK1-NEXT: ret void 890 // 891 // 892 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 893 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 894 // CHECK1-NEXT: entry: 895 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 896 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 897 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 898 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 899 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 900 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 901 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 902 // CHECK1-NEXT: ret void 903 // 904 // 905 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 906 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 907 // CHECK1-NEXT: entry: 908 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 909 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 910 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 911 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 912 // CHECK1-NEXT: ret void 913 // 914 // 915 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 916 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 917 // CHECK1-NEXT: entry: 918 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 919 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 920 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 921 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 922 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 923 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 924 // CHECK1-NEXT: ret void 925 // 926 // 927 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 928 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 929 // CHECK1-NEXT: entry: 930 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 931 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 932 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 933 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 934 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 935 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 936 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 937 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 938 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 939 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 940 // CHECK1-NEXT: ret void 941 // 942 // 943 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 944 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 945 // CHECK1-NEXT: entry: 946 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 947 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 948 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 949 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 950 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 951 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 952 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 953 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 954 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 955 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 956 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 957 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 958 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 959 // CHECK1-NEXT: ret void 960 // 961 // 962 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 963 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 964 // CHECK1-NEXT: entry: 965 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 966 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 967 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 968 // CHECK1-NEXT: ret void 969 // 970 // 971 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 972 // CHECK1-SAME: () #[[ATTR0]] { 973 // CHECK1-NEXT: entry: 974 // CHECK1-NEXT: call void @__cxx_global_var_init() 975 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 976 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 977 // CHECK1-NEXT: ret void 978 // 979 // 980 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 981 // CHECK1-SAME: () #[[ATTR0]] { 982 // CHECK1-NEXT: entry: 983 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 984 // CHECK1-NEXT: ret void 985 // 986 // 987 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 988 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 989 // CHECK3-NEXT: entry: 990 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 991 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 992 // CHECK3-NEXT: ret void 993 // 994 // 995 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 996 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 997 // CHECK3-NEXT: entry: 998 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 999 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1000 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1001 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1002 // CHECK3-NEXT: ret void 1003 // 1004 // 1005 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1006 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1007 // CHECK3-NEXT: entry: 1008 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1009 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1010 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1011 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1012 // CHECK3-NEXT: ret void 1013 // 1014 // 1015 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1016 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1017 // CHECK3-NEXT: entry: 1018 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1019 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1020 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1021 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1022 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1023 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1024 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 1025 // CHECK3-NEXT: ret void 1026 // 1027 // 1028 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1029 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1030 // CHECK3-NEXT: entry: 1031 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1032 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1033 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1034 // CHECK3-NEXT: ret void 1035 // 1036 // 1037 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1038 // CHECK3-SAME: () #[[ATTR0]] { 1039 // CHECK3-NEXT: entry: 1040 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 1041 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 1042 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1043 // CHECK3-NEXT: ret void 1044 // 1045 // 1046 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1047 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1048 // CHECK3-NEXT: entry: 1049 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1050 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1051 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1052 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1053 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1054 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1055 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1056 // CHECK3-NEXT: ret void 1057 // 1058 // 1059 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1060 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1061 // CHECK3-NEXT: entry: 1062 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1063 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1064 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1065 // CHECK3: arraydestroy.body: 1066 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1067 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1068 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1069 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1070 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1071 // CHECK3: arraydestroy.done1: 1072 // CHECK3-NEXT: ret void 1073 // 1074 // 1075 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1076 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1077 // CHECK3-NEXT: entry: 1078 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1079 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1080 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1081 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1082 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1083 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1084 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1085 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1086 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1087 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1088 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1089 // CHECK3-NEXT: ret void 1090 // 1091 // 1092 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1093 // CHECK3-SAME: () #[[ATTR0]] { 1094 // CHECK3-NEXT: entry: 1095 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1096 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1097 // CHECK3-NEXT: ret void 1098 // 1099 // 1100 // CHECK3-LABEL: define {{[^@]+}}@main 1101 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1102 // CHECK3-NEXT: entry: 1103 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1104 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1105 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1106 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1107 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1108 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1109 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1110 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1111 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1112 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 1113 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1114 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1115 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 1116 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1117 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1118 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1119 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1120 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1121 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* 1122 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 1123 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1124 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1125 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1126 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 1127 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4 1128 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1129 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 1130 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4 1131 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1132 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1133 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1134 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 1135 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 1136 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1137 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 1138 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 1139 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1140 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1141 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1142 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 1143 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 1144 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1145 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 1146 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 1147 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1148 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1149 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1150 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1151 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 1152 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1153 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 1154 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 1155 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1156 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 1157 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1158 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1159 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1160 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1161 // CHECK3-NEXT: store i32 1, i32* [[TMP31]], align 4 1162 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1163 // CHECK3-NEXT: store i32 5, i32* [[TMP32]], align 4 1164 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1165 // CHECK3-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 4 1166 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1167 // CHECK3-NEXT: store i8** [[TMP30]], i8*** [[TMP34]], align 4 1168 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1169 // CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP35]], align 4 1170 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1171 // CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP36]], align 4 1172 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1173 // CHECK3-NEXT: store i8** null, i8*** [[TMP37]], align 4 1174 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1175 // CHECK3-NEXT: store i8** null, i8*** [[TMP38]], align 4 1176 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1177 // CHECK3-NEXT: store i64 2, i64* [[TMP39]], align 8 1178 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1179 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1180 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1181 // CHECK3: omp_offload.failed: 1182 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 1183 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1184 // CHECK3: omp_offload.cont: 1185 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1186 // CHECK3-NEXT: ret i32 [[CALL]] 1187 // 1188 // 1189 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 1190 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1191 // CHECK3-NEXT: entry: 1192 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1193 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1194 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1195 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1196 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1197 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1198 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1199 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1200 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1201 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1202 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1203 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1204 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1205 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1206 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1207 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1208 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 1209 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1210 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 1211 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 1212 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1213 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 1214 // CHECK3-NEXT: ret void 1215 // 1216 // 1217 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1218 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4]] { 1219 // CHECK3-NEXT: entry: 1220 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1221 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1222 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1223 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1224 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1225 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1226 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1227 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1228 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1229 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1230 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1231 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1232 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1233 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1234 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1235 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1236 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1237 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1238 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1239 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1240 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1241 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1242 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1243 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1244 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1245 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1246 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1247 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1248 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1249 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1250 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1251 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1252 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1253 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 1254 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1255 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 1256 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1257 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1258 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1259 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1260 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1261 // CHECK3: omp.arraycpy.body: 1262 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1263 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1264 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1265 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 1266 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1267 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1268 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1269 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1270 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1271 // CHECK3: omp.arraycpy.done3: 1272 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1273 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) 1274 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1275 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1276 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1277 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1278 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1279 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1280 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1281 // CHECK3: cond.true: 1282 // CHECK3-NEXT: br label [[COND_END:%.*]] 1283 // CHECK3: cond.false: 1284 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1285 // CHECK3-NEXT: br label [[COND_END]] 1286 // CHECK3: cond.end: 1287 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1288 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1289 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1290 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 1291 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1292 // CHECK3: omp.inner.for.cond: 1293 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1294 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1295 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1296 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1297 // CHECK3: omp.inner.for.cond.cleanup: 1298 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1299 // CHECK3: omp.inner.for.body: 1300 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1301 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 1302 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1303 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1304 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 1305 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1306 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] 1307 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 1308 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1309 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] 1310 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 1311 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 1312 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6 1313 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1314 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 1315 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 1316 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 1317 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1318 // CHECK3: omp.body.continue: 1319 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1320 // CHECK3: omp.inner.for.inc: 1321 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1322 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 1323 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1324 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1325 // CHECK3: omp.inner.for.end: 1326 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1327 // CHECK3: omp.loop.exit: 1328 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1329 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1330 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1331 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1332 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1333 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1334 // CHECK3: .omp.final.then: 1335 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 1336 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1337 // CHECK3: .omp.final.done: 1338 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1339 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1340 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 1341 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1342 // CHECK3: arraydestroy.body: 1343 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1344 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1345 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1346 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1347 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1348 // CHECK3: arraydestroy.done11: 1349 // CHECK3-NEXT: ret void 1350 // 1351 // 1352 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1353 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1354 // CHECK3-NEXT: entry: 1355 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1356 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1357 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1358 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 1359 // CHECK3-NEXT: ret void 1360 // 1361 // 1362 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1363 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1364 // CHECK3-NEXT: entry: 1365 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1366 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 1367 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1368 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 1369 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1370 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 1371 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 1372 // CHECK3-NEXT: ret void 1373 // 1374 // 1375 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1376 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1377 // CHECK3-NEXT: entry: 1378 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1379 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1380 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1381 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1382 // CHECK3-NEXT: ret void 1383 // 1384 // 1385 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1386 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 1387 // CHECK3-NEXT: entry: 1388 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1389 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1390 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1391 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1392 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1393 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1394 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 1395 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1396 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1397 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1398 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1399 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1400 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1401 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 1402 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1403 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1404 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1405 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 1406 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1407 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1408 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1409 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 1410 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 1411 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 1412 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 1413 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1414 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 1415 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 1416 // CHECK3-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 1417 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1418 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 1419 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 1420 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1421 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1422 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 1423 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1424 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 1425 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1426 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 1427 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 1428 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1429 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 1430 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 1431 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1432 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 1433 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1434 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 1435 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 1436 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1437 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 1438 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 1439 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1440 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 1441 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1442 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 1443 // CHECK3-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 1444 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1445 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 1446 // CHECK3-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 1447 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1448 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 1449 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1450 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1451 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1452 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1453 // CHECK3-NEXT: store i32 1, i32* [[TMP29]], align 4 1454 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1455 // CHECK3-NEXT: store i32 4, i32* [[TMP30]], align 4 1456 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1457 // CHECK3-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4 1458 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1459 // CHECK3-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 4 1460 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1461 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP33]], align 4 1462 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1463 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP34]], align 4 1464 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1465 // CHECK3-NEXT: store i8** null, i8*** [[TMP35]], align 4 1466 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1467 // CHECK3-NEXT: store i8** null, i8*** [[TMP36]], align 4 1468 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1469 // CHECK3-NEXT: store i64 2, i64* [[TMP37]], align 8 1470 // CHECK3-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1471 // CHECK3-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 1472 // CHECK3-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1473 // CHECK3: omp_offload.failed: 1474 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 1475 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1476 // CHECK3: omp_offload.cont: 1477 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1478 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1479 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1480 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1481 // CHECK3: arraydestroy.body: 1482 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1483 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1484 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1485 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1486 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1487 // CHECK3: arraydestroy.done2: 1488 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1489 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[RETVAL]], align 4 1490 // CHECK3-NEXT: ret i32 [[TMP41]] 1491 // 1492 // 1493 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1494 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1495 // CHECK3-NEXT: entry: 1496 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1497 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1498 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1499 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1500 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1501 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1502 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4 1503 // CHECK3-NEXT: ret void 1504 // 1505 // 1506 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1507 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1508 // CHECK3-NEXT: entry: 1509 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1510 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 1511 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1512 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 1513 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1514 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1515 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 1516 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1517 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1518 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1519 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1520 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1521 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1522 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1523 // CHECK3-NEXT: ret void 1524 // 1525 // 1526 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1527 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1528 // CHECK3-NEXT: entry: 1529 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1530 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1531 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1532 // CHECK3-NEXT: ret void 1533 // 1534 // 1535 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1536 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1537 // CHECK3-NEXT: entry: 1538 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1539 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1540 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1541 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1542 // CHECK3-NEXT: ret void 1543 // 1544 // 1545 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1546 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1547 // CHECK3-NEXT: entry: 1548 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1549 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1550 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1551 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1552 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1553 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1554 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1555 // CHECK3-NEXT: ret void 1556 // 1557 // 1558 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1559 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1560 // CHECK3-NEXT: entry: 1561 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1562 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1563 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 1564 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 1565 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 1566 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1567 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1568 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1569 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1570 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 1571 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1572 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1573 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 1574 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 1575 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1576 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 1577 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1578 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 1579 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 1580 // CHECK3-NEXT: ret void 1581 // 1582 // 1583 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 1584 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1585 // CHECK3-NEXT: entry: 1586 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1587 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1588 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1589 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1590 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 1591 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 1592 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 1593 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1594 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1595 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1596 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1597 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1598 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1599 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1600 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1601 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1602 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1603 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1604 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 1605 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1606 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1607 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1608 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1609 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1610 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1611 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 1612 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1613 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1614 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 1615 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 1616 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1617 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1618 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1619 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1620 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1621 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1622 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 1623 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1624 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 1625 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1626 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 1627 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1628 // CHECK3: omp.arraycpy.body: 1629 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1630 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1631 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1632 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 1633 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1634 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1635 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1636 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1637 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1638 // CHECK3: omp.arraycpy.done4: 1639 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 1640 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1641 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) 1642 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1643 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 1644 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1645 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 1646 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1647 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1648 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 1649 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1650 // CHECK3: cond.true: 1651 // CHECK3-NEXT: br label [[COND_END:%.*]] 1652 // CHECK3: cond.false: 1653 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1654 // CHECK3-NEXT: br label [[COND_END]] 1655 // CHECK3: cond.end: 1656 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1657 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1658 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1659 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1660 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1661 // CHECK3: omp.inner.for.cond: 1662 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1663 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 1664 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1665 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1666 // CHECK3: omp.inner.for.cond.cleanup: 1667 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1668 // CHECK3: omp.inner.for.body: 1669 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1670 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 1671 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1672 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 1673 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !12 1674 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1675 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] 1676 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 1677 // CHECK3-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12 1678 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1679 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] 1680 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 1681 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 1682 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !12 1683 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1684 // CHECK3: omp.body.continue: 1685 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1686 // CHECK3: omp.inner.for.inc: 1687 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1688 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 1689 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1690 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1691 // CHECK3: omp.inner.for.end: 1692 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1693 // CHECK3: omp.loop.exit: 1694 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1695 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1696 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1697 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1698 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1699 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1700 // CHECK3: .omp.final.then: 1701 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 1702 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1703 // CHECK3: .omp.final.done: 1704 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1705 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1706 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 1707 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1708 // CHECK3: arraydestroy.body: 1709 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1710 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1711 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1712 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 1713 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 1714 // CHECK3: arraydestroy.done12: 1715 // CHECK3-NEXT: ret void 1716 // 1717 // 1718 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1719 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1720 // CHECK3-NEXT: entry: 1721 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1722 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 1723 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1724 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 1725 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1726 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 1727 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 1728 // CHECK3-NEXT: ret void 1729 // 1730 // 1731 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1732 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1733 // CHECK3-NEXT: entry: 1734 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1735 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1736 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1737 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1738 // CHECK3-NEXT: ret void 1739 // 1740 // 1741 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1742 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1743 // CHECK3-NEXT: entry: 1744 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1745 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1746 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1747 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1748 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1749 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1750 // CHECK3-NEXT: ret void 1751 // 1752 // 1753 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1754 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1755 // CHECK3-NEXT: entry: 1756 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1757 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1758 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1759 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1760 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1761 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1762 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1763 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1764 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1765 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1766 // CHECK3-NEXT: ret void 1767 // 1768 // 1769 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1770 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1771 // CHECK3-NEXT: entry: 1772 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1773 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 1774 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1775 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 1776 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1777 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1778 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 1779 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1780 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1781 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1782 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1783 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1784 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1785 // CHECK3-NEXT: ret void 1786 // 1787 // 1788 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1789 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1790 // CHECK3-NEXT: entry: 1791 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1792 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1793 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1794 // CHECK3-NEXT: ret void 1795 // 1796 // 1797 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 1798 // CHECK3-SAME: () #[[ATTR0]] { 1799 // CHECK3-NEXT: entry: 1800 // CHECK3-NEXT: call void @__cxx_global_var_init() 1801 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1802 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1803 // CHECK3-NEXT: ret void 1804 // 1805 // 1806 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1807 // CHECK3-SAME: () #[[ATTR0]] { 1808 // CHECK3-NEXT: entry: 1809 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1810 // CHECK3-NEXT: ret void 1811 // 1812 // 1813 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1814 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1815 // CHECK5-NEXT: entry: 1816 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1817 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1818 // CHECK5-NEXT: ret void 1819 // 1820 // 1821 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1822 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1823 // CHECK5-NEXT: entry: 1824 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1825 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1826 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1827 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1828 // CHECK5-NEXT: ret void 1829 // 1830 // 1831 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1832 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1833 // CHECK5-NEXT: entry: 1834 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1835 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1836 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1837 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1838 // CHECK5-NEXT: ret void 1839 // 1840 // 1841 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1842 // CHECK5-SAME: () #[[ATTR0]] { 1843 // CHECK5-NEXT: entry: 1844 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 1845 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 1846 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1847 // CHECK5-NEXT: ret void 1848 // 1849 // 1850 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1851 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1852 // CHECK5-NEXT: entry: 1853 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1854 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1855 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1856 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1857 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1858 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1859 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1860 // CHECK5-NEXT: ret void 1861 // 1862 // 1863 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1864 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1865 // CHECK5-NEXT: entry: 1866 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1867 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1868 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1869 // CHECK5: arraydestroy.body: 1870 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1871 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1872 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1873 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1874 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1875 // CHECK5: arraydestroy.done1: 1876 // CHECK5-NEXT: ret void 1877 // 1878 // 1879 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1880 // CHECK5-SAME: () #[[ATTR0]] { 1881 // CHECK5-NEXT: entry: 1882 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1883 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1884 // CHECK5-NEXT: ret void 1885 // 1886 // 1887 // CHECK5-LABEL: define {{[^@]+}}@main 1888 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1889 // CHECK5-NEXT: entry: 1890 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1891 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1892 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1893 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1894 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1895 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1896 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1897 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1898 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1899 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1900 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1901 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1902 // CHECK5: omp.inner.for.cond: 1903 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1904 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 1905 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1906 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1907 // CHECK5: omp.inner.for.body: 1908 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1909 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1910 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1911 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 1912 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !2 1913 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1914 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1915 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 1916 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2 1917 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1918 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 1919 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 1920 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1921 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false), !llvm.access.group !2 1922 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1923 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2 1924 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 1925 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2 1926 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1927 // CHECK5: omp.body.continue: 1928 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1929 // CHECK5: omp.inner.for.inc: 1930 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1931 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 1932 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1933 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1934 // CHECK5: omp.inner.for.end: 1935 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1936 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1937 // CHECK5-NEXT: ret i32 [[CALL]] 1938 // 1939 // 1940 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1941 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 1942 // CHECK5-NEXT: entry: 1943 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1944 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1945 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1946 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1947 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1948 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 1949 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1950 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 1951 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1952 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1953 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1954 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1955 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1956 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1957 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 1958 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1959 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1960 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1961 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 1962 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1963 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1964 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 1965 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 1966 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 1967 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 1968 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1969 // CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 1970 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1971 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1972 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1973 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1974 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1975 // CHECK5: omp.inner.for.cond: 1976 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1977 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1978 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1979 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1980 // CHECK5: omp.inner.for.body: 1981 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1982 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1983 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1984 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1985 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 1986 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1987 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 1988 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 1989 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 1990 // CHECK5-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8, !llvm.access.group !6 1991 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1992 // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP11]] to i64 1993 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] 1994 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1995 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1996 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6 1997 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1998 // CHECK5: omp.body.continue: 1999 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2000 // CHECK5: omp.inner.for.inc: 2001 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2002 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 2003 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2004 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2005 // CHECK5: omp.inner.for.end: 2006 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 2007 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 2008 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2009 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 2010 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2011 // CHECK5: arraydestroy.body: 2012 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2013 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2014 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2015 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2016 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 2017 // CHECK5: arraydestroy.done6: 2018 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2019 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 2020 // CHECK5-NEXT: ret i32 [[TMP16]] 2021 // 2022 // 2023 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2024 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2025 // CHECK5-NEXT: entry: 2026 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2027 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2028 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2029 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2030 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2031 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2032 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 2033 // CHECK5-NEXT: ret void 2034 // 2035 // 2036 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2037 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2038 // CHECK5-NEXT: entry: 2039 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2040 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2041 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2042 // CHECK5-NEXT: ret void 2043 // 2044 // 2045 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2046 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2047 // CHECK5-NEXT: entry: 2048 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2049 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2050 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2051 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2052 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2053 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2054 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2055 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2056 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2057 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2058 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 2059 // CHECK5-NEXT: ret void 2060 // 2061 // 2062 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2063 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2064 // CHECK5-NEXT: entry: 2065 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2066 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2067 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2068 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2069 // CHECK5-NEXT: ret void 2070 // 2071 // 2072 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2073 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2074 // CHECK5-NEXT: entry: 2075 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2076 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2077 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2078 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2079 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2080 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2081 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 2082 // CHECK5-NEXT: ret void 2083 // 2084 // 2085 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2086 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2087 // CHECK5-NEXT: entry: 2088 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2089 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2090 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2091 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2092 // CHECK5-NEXT: ret void 2093 // 2094 // 2095 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2096 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2097 // CHECK5-NEXT: entry: 2098 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2099 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2100 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2101 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2102 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2103 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2104 // CHECK5-NEXT: ret void 2105 // 2106 // 2107 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2108 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2109 // CHECK5-NEXT: entry: 2110 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2111 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2112 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2113 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2114 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2115 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2116 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2117 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2118 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2119 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2120 // CHECK5-NEXT: ret void 2121 // 2122 // 2123 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2124 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2125 // CHECK5-NEXT: entry: 2126 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2127 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2128 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2129 // CHECK5-NEXT: ret void 2130 // 2131 // 2132 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 2133 // CHECK5-SAME: () #[[ATTR0]] { 2134 // CHECK5-NEXT: entry: 2135 // CHECK5-NEXT: call void @__cxx_global_var_init() 2136 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 2137 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 2138 // CHECK5-NEXT: ret void 2139 // 2140 // 2141 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 2142 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 2143 // CHECK7-NEXT: entry: 2144 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 2145 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2146 // CHECK7-NEXT: ret void 2147 // 2148 // 2149 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2150 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2151 // CHECK7-NEXT: entry: 2152 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2153 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2154 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2155 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2156 // CHECK7-NEXT: ret void 2157 // 2158 // 2159 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2160 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2161 // CHECK7-NEXT: entry: 2162 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2163 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2164 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2165 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2166 // CHECK7-NEXT: ret void 2167 // 2168 // 2169 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2170 // CHECK7-SAME: () #[[ATTR0]] { 2171 // CHECK7-NEXT: entry: 2172 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 2173 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 2174 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2175 // CHECK7-NEXT: ret void 2176 // 2177 // 2178 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2179 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2180 // CHECK7-NEXT: entry: 2181 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2182 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2183 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2184 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2185 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2186 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2187 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2188 // CHECK7-NEXT: ret void 2189 // 2190 // 2191 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2192 // CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2193 // CHECK7-NEXT: entry: 2194 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 2195 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 2196 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2197 // CHECK7: arraydestroy.body: 2198 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2199 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2200 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2201 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2202 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2203 // CHECK7: arraydestroy.done1: 2204 // CHECK7-NEXT: ret void 2205 // 2206 // 2207 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2208 // CHECK7-SAME: () #[[ATTR0]] { 2209 // CHECK7-NEXT: entry: 2210 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2211 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2212 // CHECK7-NEXT: ret void 2213 // 2214 // 2215 // CHECK7-LABEL: define {{[^@]+}}@main 2216 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 2217 // CHECK7-NEXT: entry: 2218 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2219 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2220 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2221 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2222 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2223 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2224 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 2225 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2226 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2227 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2228 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 2229 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2230 // CHECK7: omp.inner.for.cond: 2231 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2232 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 2233 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2234 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2235 // CHECK7: omp.inner.for.body: 2236 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2237 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2238 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2239 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 2240 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !3 2241 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 2242 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP5]] 2243 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3 2244 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 2245 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP6]] 2246 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 2247 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false), !llvm.access.group !3 2248 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 2249 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3 2250 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 2251 // CHECK7-NEXT: store i32 [[ADD2]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3 2252 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2253 // CHECK7: omp.body.continue: 2254 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2255 // CHECK7: omp.inner.for.inc: 2256 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2257 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2258 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2259 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2260 // CHECK7: omp.inner.for.end: 2261 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 2262 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 2263 // CHECK7-NEXT: ret i32 [[CALL]] 2264 // 2265 // 2266 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2267 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 2268 // CHECK7-NEXT: entry: 2269 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2270 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2271 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2272 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2273 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2274 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2275 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2276 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 2277 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 2278 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2279 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2280 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2281 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2282 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2283 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 2284 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2285 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2286 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2287 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 2288 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2289 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2290 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2291 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2292 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 2293 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2294 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2295 // CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 2296 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2297 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2298 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2299 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2300 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2301 // CHECK7: omp.inner.for.cond: 2302 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 2303 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 2304 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2305 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2306 // CHECK7: omp.inner.for.body: 2307 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 2308 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2309 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2310 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 2311 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7 2312 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 2313 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 2314 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7 2315 // CHECK7-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4, !llvm.access.group !7 2316 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 2317 // CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 2318 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* 2319 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 2320 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7 2321 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2322 // CHECK7: omp.body.continue: 2323 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2324 // CHECK7: omp.inner.for.inc: 2325 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 2326 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 2327 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 2328 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2329 // CHECK7: omp.inner.for.end: 2330 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 2331 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 2332 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2333 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2334 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2335 // CHECK7: arraydestroy.body: 2336 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2337 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2338 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2339 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2340 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 2341 // CHECK7: arraydestroy.done5: 2342 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2343 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 2344 // CHECK7-NEXT: ret i32 [[TMP16]] 2345 // 2346 // 2347 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2348 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2349 // CHECK7-NEXT: entry: 2350 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2351 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2352 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2353 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2354 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2355 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2356 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 2357 // CHECK7-NEXT: ret void 2358 // 2359 // 2360 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2361 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2362 // CHECK7-NEXT: entry: 2363 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2364 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2365 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2366 // CHECK7-NEXT: ret void 2367 // 2368 // 2369 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2370 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2371 // CHECK7-NEXT: entry: 2372 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2373 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2374 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2375 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2376 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2377 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2378 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2379 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2380 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2381 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2382 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 2383 // CHECK7-NEXT: ret void 2384 // 2385 // 2386 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2387 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2388 // CHECK7-NEXT: entry: 2389 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2390 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2391 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2392 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2393 // CHECK7-NEXT: ret void 2394 // 2395 // 2396 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2397 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2398 // CHECK7-NEXT: entry: 2399 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2400 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2401 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2402 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2403 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2404 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2405 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2406 // CHECK7-NEXT: ret void 2407 // 2408 // 2409 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2410 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2411 // CHECK7-NEXT: entry: 2412 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2413 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2414 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2415 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2416 // CHECK7-NEXT: ret void 2417 // 2418 // 2419 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2420 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2421 // CHECK7-NEXT: entry: 2422 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2423 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2424 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2425 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2426 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2427 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2428 // CHECK7-NEXT: ret void 2429 // 2430 // 2431 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2432 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2433 // CHECK7-NEXT: entry: 2434 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2435 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2436 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2437 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2438 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2439 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2440 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2441 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2442 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2443 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2444 // CHECK7-NEXT: ret void 2445 // 2446 // 2447 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2448 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2449 // CHECK7-NEXT: entry: 2450 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2451 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2452 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2453 // CHECK7-NEXT: ret void 2454 // 2455 // 2456 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 2457 // CHECK7-SAME: () #[[ATTR0]] { 2458 // CHECK7-NEXT: entry: 2459 // CHECK7-NEXT: call void @__cxx_global_var_init() 2460 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 2461 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 2462 // CHECK7-NEXT: ret void 2463 // 2464 // 2465 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 2466 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2467 // CHECK9-NEXT: entry: 2468 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 2469 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2470 // CHECK9-NEXT: ret void 2471 // 2472 // 2473 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2474 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2475 // CHECK9-NEXT: entry: 2476 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2477 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2478 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2479 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2480 // CHECK9-NEXT: ret void 2481 // 2482 // 2483 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2484 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2485 // CHECK9-NEXT: entry: 2486 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2487 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2488 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2489 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2490 // CHECK9-NEXT: ret void 2491 // 2492 // 2493 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2494 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2495 // CHECK9-NEXT: entry: 2496 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2497 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2498 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2499 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2500 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2501 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2502 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 2503 // CHECK9-NEXT: ret void 2504 // 2505 // 2506 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2507 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2508 // CHECK9-NEXT: entry: 2509 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2510 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2511 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2512 // CHECK9-NEXT: ret void 2513 // 2514 // 2515 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2516 // CHECK9-SAME: () #[[ATTR0]] { 2517 // CHECK9-NEXT: entry: 2518 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 2519 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 2520 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2521 // CHECK9-NEXT: ret void 2522 // 2523 // 2524 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2525 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2526 // CHECK9-NEXT: entry: 2527 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2528 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2529 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2530 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2531 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2532 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2533 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2534 // CHECK9-NEXT: ret void 2535 // 2536 // 2537 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2538 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2539 // CHECK9-NEXT: entry: 2540 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2541 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2542 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2543 // CHECK9: arraydestroy.body: 2544 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2545 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2546 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2547 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2548 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2549 // CHECK9: arraydestroy.done1: 2550 // CHECK9-NEXT: ret void 2551 // 2552 // 2553 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2554 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2555 // CHECK9-NEXT: entry: 2556 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2557 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2558 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2559 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2560 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2561 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2562 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2563 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2564 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2565 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2566 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 2567 // CHECK9-NEXT: ret void 2568 // 2569 // 2570 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2571 // CHECK9-SAME: () #[[ATTR0]] { 2572 // CHECK9-NEXT: entry: 2573 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2574 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2575 // CHECK9-NEXT: ret void 2576 // 2577 // 2578 // CHECK9-LABEL: define {{[^@]+}}@main 2579 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2580 // CHECK9-NEXT: entry: 2581 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2582 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2583 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 2584 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2585 // CHECK9-NEXT: ret i32 0 2586 // 2587 // 2588 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 2589 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 2590 // CHECK9-NEXT: entry: 2591 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2592 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2593 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2594 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2595 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 2596 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 2597 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2598 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 2599 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 2600 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 2601 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 2602 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 2603 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 2604 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 2605 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2606 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 2607 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 2608 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 2609 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 2610 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 2611 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 2612 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 2613 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 2614 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 2615 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 2616 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 2617 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 2618 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 2619 // CHECK9-NEXT: ret void 2620 // 2621 // 2622 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2623 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] { 2624 // CHECK9-NEXT: entry: 2625 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2626 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2627 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2628 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2629 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2630 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2631 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2632 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2633 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2634 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2635 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2636 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2637 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2638 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2639 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2640 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2641 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 2642 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 2643 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 2644 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 2645 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 2646 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 2647 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 2648 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2649 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2650 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2651 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2652 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2653 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2654 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2655 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2656 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2657 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2658 // CHECK9: cond.true: 2659 // CHECK9-NEXT: br label [[COND_END:%.*]] 2660 // CHECK9: cond.false: 2661 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2662 // CHECK9-NEXT: br label [[COND_END]] 2663 // CHECK9: cond.end: 2664 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2665 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2666 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2667 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2668 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2669 // CHECK9: omp.inner.for.cond: 2670 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2671 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 2672 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2673 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2674 // CHECK9: omp.inner.for.body: 2675 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2676 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2677 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2678 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 2679 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4 2680 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 2681 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 2682 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4 2683 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 2684 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 2685 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 2686 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 2687 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 2688 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 2689 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 2690 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 2691 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2692 // CHECK9: omp.body.continue: 2693 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2694 // CHECK9: omp.inner.for.inc: 2695 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2696 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 2697 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2698 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2699 // CHECK9: omp.inner.for.end: 2700 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2701 // CHECK9: omp.loop.exit: 2702 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2703 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2704 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2705 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2706 // CHECK9: .omp.final.then: 2707 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 2708 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 2709 // CHECK9: .omp.final.done: 2710 // CHECK9-NEXT: ret void 2711 // 2712 // 2713 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 2714 // CHECK9-SAME: () #[[ATTR0]] { 2715 // CHECK9-NEXT: entry: 2716 // CHECK9-NEXT: call void @__cxx_global_var_init() 2717 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2718 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2719 // CHECK9-NEXT: ret void 2720 // 2721 // 2722 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2723 // CHECK9-SAME: () #[[ATTR0]] { 2724 // CHECK9-NEXT: entry: 2725 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 2726 // CHECK9-NEXT: ret void 2727 // 2728 // 2729 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 2730 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2731 // CHECK11-NEXT: entry: 2732 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 2733 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2734 // CHECK11-NEXT: ret void 2735 // 2736 // 2737 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2738 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2739 // CHECK11-NEXT: entry: 2740 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2741 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2742 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2743 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2744 // CHECK11-NEXT: ret void 2745 // 2746 // 2747 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2748 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2749 // CHECK11-NEXT: entry: 2750 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2751 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2752 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2753 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2754 // CHECK11-NEXT: ret void 2755 // 2756 // 2757 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2758 // CHECK11-SAME: () #[[ATTR0]] { 2759 // CHECK11-NEXT: entry: 2760 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 2761 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 2762 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2763 // CHECK11-NEXT: ret void 2764 // 2765 // 2766 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2767 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2768 // CHECK11-NEXT: entry: 2769 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2770 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2771 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2772 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2773 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2774 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2775 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2776 // CHECK11-NEXT: ret void 2777 // 2778 // 2779 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2780 // CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2781 // CHECK11-NEXT: entry: 2782 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2783 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2784 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2785 // CHECK11: arraydestroy.body: 2786 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2787 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2788 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2789 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2790 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2791 // CHECK11: arraydestroy.done1: 2792 // CHECK11-NEXT: ret void 2793 // 2794 // 2795 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2796 // CHECK11-SAME: () #[[ATTR0]] { 2797 // CHECK11-NEXT: entry: 2798 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2799 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2800 // CHECK11-NEXT: ret void 2801 // 2802 // 2803 // CHECK11-LABEL: define {{[^@]+}}@main 2804 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2805 // CHECK11-NEXT: entry: 2806 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2807 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2808 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 2809 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2810 // CHECK11-NEXT: ret i32 0 2811 // 2812 // 2813 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2814 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2815 // CHECK11-NEXT: entry: 2816 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2817 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2818 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2819 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2820 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2821 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2822 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 2823 // CHECK11-NEXT: ret void 2824 // 2825 // 2826 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2827 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2828 // CHECK11-NEXT: entry: 2829 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2830 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2831 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2832 // CHECK11-NEXT: ret void 2833 // 2834 // 2835 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2836 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2837 // CHECK11-NEXT: entry: 2838 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2839 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2840 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2841 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2842 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2843 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2844 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2845 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2846 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2847 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2848 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 2849 // CHECK11-NEXT: ret void 2850 // 2851 // 2852 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_firstprivate_codegen.cpp 2853 // CHECK11-SAME: () #[[ATTR0]] { 2854 // CHECK11-NEXT: entry: 2855 // CHECK11-NEXT: call void @__cxx_global_var_init() 2856 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 2857 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 2858 // CHECK11-NEXT: ret void 2859 // 2860