1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // expected-no-diagnostics 3 #ifndef HEADER 4 #define HEADER 5 6 // Test host codegen. 7 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 8 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 9 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 10 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 11 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 13 14 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 15 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 16 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 17 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 18 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 20 #ifdef CK1 21 22 template <typename T, int X, long long Y> 23 struct SS{ 24 T a[X][Y]; 25 26 int foo(void) { 27 28 #pragma omp target 29 #pragma omp teams distribute simd collapse(2) 30 for(int i = 0; i < X; i++) { 31 for(int j = 0; j < Y; j++) { 32 a[i][j] = (T)0; 33 } 34 } 35 36 // discard loop variables not needed here 37 38 return a[0][0]; 39 } 40 }; 41 42 int teams_template_struct(void) { 43 SS<int, 123, 456> V; 44 return V.foo(); 45 46 } 47 48 #endif // CK1 49 50 // Test host codegen. 51 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 52 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 53 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 54 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 55 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 56 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 57 58 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 60 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 61 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 62 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 63 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 64 #ifdef CK2 65 66 template <typename T, int n, int m> 67 int tmain(T argc) { 68 T a[n][m]; 69 #pragma omp target 70 #pragma omp teams distribute simd collapse(2) 71 for(int i = 0; i < n; i++) { 72 for(int j = 0; j < m; j++) { 73 a[i][j] = (T)0; 74 } 75 } 76 return 0; 77 } 78 79 int main (int argc, char **argv) { 80 int n = 100; 81 int m = 2; 82 int a[n][m]; 83 #pragma omp target 84 #pragma omp teams distribute simd collapse(2) 85 for(int i = 0; i < n; i++) { 86 for(int j = 0; j < m; j++) { 87 a[i][j] = 0; 88 } 89 } 90 return tmain<int, 10, 2>(argc); 91 } 92 93 94 95 96 97 // discard loop variables not needed here 98 99 #endif // CK2 100 #endif // #ifndef HEADER 101 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv 102 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 103 // CHECK1-NEXT: entry: 104 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 105 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 106 // CHECK1-NEXT: ret i32 [[CALL]] 107 // 108 // 109 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 110 // CHECK1-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 111 // CHECK1-NEXT: entry: 112 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 113 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 114 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 115 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 116 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 117 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 118 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 119 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 120 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 121 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 122 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 123 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 124 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 125 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 126 // CHECK1-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 127 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 128 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8 129 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 130 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 131 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 132 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 133 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 134 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 135 // CHECK1: omp_offload.failed: 136 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 137 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 138 // CHECK1: omp_offload.cont: 139 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 140 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 141 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 142 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 143 // CHECK1-NEXT: ret i32 [[TMP9]] 144 // 145 // 146 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 147 // CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 148 // CHECK1-NEXT: entry: 149 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 150 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 151 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 152 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 153 // CHECK1-NEXT: ret void 154 // 155 // 156 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 157 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { 158 // CHECK1-NEXT: entry: 159 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 160 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 161 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 162 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 163 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 165 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 166 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 167 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 168 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 169 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 170 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 171 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 172 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 173 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 174 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 175 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 176 // CHECK1-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 177 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 178 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 179 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 180 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 181 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 182 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 183 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 184 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 185 // CHECK1: cond.true: 186 // CHECK1-NEXT: br label [[COND_END:%.*]] 187 // CHECK1: cond.false: 188 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 189 // CHECK1-NEXT: br label [[COND_END]] 190 // CHECK1: cond.end: 191 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 192 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 193 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 194 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 195 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 196 // CHECK1: omp.inner.for.cond: 197 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 198 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 199 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 200 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 201 // CHECK1: omp.inner.for.body: 202 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 203 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 204 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 205 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 206 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 207 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 208 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 209 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 210 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 211 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 212 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 213 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 214 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 215 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 216 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 217 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 218 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 219 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 220 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 221 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 222 // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 223 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 224 // CHECK1: omp.body.continue: 225 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 226 // CHECK1: omp.inner.for.inc: 227 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 228 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 229 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 230 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 231 // CHECK1: omp.inner.for.end: 232 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 233 // CHECK1: omp.loop.exit: 234 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 235 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 236 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 237 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 238 // CHECK1: .omp.final.then: 239 // CHECK1-NEXT: store i32 123, i32* [[I]], align 4 240 // CHECK1-NEXT: store i32 456, i32* [[J]], align 4 241 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 242 // CHECK1: .omp.final.done: 243 // CHECK1-NEXT: ret void 244 // 245 // 246 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 247 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 248 // CHECK1-NEXT: entry: 249 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 250 // CHECK1-NEXT: ret void 251 // 252 // 253 // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_template_structv 254 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 255 // CHECK2-NEXT: entry: 256 // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 257 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 258 // CHECK2-NEXT: ret i32 [[CALL]] 259 // 260 // 261 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 262 // CHECK2-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 263 // CHECK2-NEXT: entry: 264 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 265 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 266 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 267 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 268 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 269 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 270 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 271 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 272 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 273 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 274 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 275 // CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 276 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 277 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 278 // CHECK2-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 279 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 280 // CHECK2-NEXT: store i8* null, i8** [[TMP4]], align 8 281 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 282 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 283 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 284 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 285 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 286 // CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 287 // CHECK2: omp_offload.failed: 288 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 289 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 290 // CHECK2: omp_offload.cont: 291 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 292 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 293 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 294 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 295 // CHECK2-NEXT: ret i32 [[TMP9]] 296 // 297 // 298 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 299 // CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 300 // CHECK2-NEXT: entry: 301 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 302 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 303 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 304 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 305 // CHECK2-NEXT: ret void 306 // 307 // 308 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 309 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { 310 // CHECK2-NEXT: entry: 311 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 312 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 313 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 314 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 315 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 316 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 317 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 318 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 319 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 320 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 321 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 322 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 323 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 324 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 325 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 326 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 327 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 328 // CHECK2-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 329 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 330 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 331 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 332 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 333 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 334 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 335 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 336 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 337 // CHECK2: cond.true: 338 // CHECK2-NEXT: br label [[COND_END:%.*]] 339 // CHECK2: cond.false: 340 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 341 // CHECK2-NEXT: br label [[COND_END]] 342 // CHECK2: cond.end: 343 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 344 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 345 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 346 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 347 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 348 // CHECK2: omp.inner.for.cond: 349 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 350 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 351 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 352 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 353 // CHECK2: omp.inner.for.body: 354 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 355 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 356 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 357 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 358 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 359 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 360 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 361 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 362 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 363 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 364 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 365 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 366 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 367 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 368 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 369 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 370 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 371 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 372 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 373 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 374 // CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 375 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 376 // CHECK2: omp.body.continue: 377 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 378 // CHECK2: omp.inner.for.inc: 379 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 380 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 381 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 382 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 383 // CHECK2: omp.inner.for.end: 384 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 385 // CHECK2: omp.loop.exit: 386 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 387 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 388 // CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 389 // CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 390 // CHECK2: .omp.final.then: 391 // CHECK2-NEXT: store i32 123, i32* [[I]], align 4 392 // CHECK2-NEXT: store i32 456, i32* [[J]], align 4 393 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 394 // CHECK2: .omp.final.done: 395 // CHECK2-NEXT: ret void 396 // 397 // 398 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 399 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 400 // CHECK2-NEXT: entry: 401 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 402 // CHECK2-NEXT: ret void 403 // 404 // 405 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv 406 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 407 // CHECK3-NEXT: entry: 408 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 409 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 410 // CHECK3-NEXT: ret i32 [[CALL]] 411 // 412 // 413 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 414 // CHECK3-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 415 // CHECK3-NEXT: entry: 416 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 417 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 418 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 419 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 420 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 421 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 422 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 423 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 424 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 425 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 426 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 427 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 428 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 429 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 430 // CHECK3-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 431 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 432 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4 433 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 434 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 435 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 436 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 437 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 438 // CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 439 // CHECK3: omp_offload.failed: 440 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 441 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 442 // CHECK3: omp_offload.cont: 443 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 444 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 445 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 446 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 447 // CHECK3-NEXT: ret i32 [[TMP9]] 448 // 449 // 450 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 451 // CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 452 // CHECK3-NEXT: entry: 453 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 454 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 455 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 456 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 457 // CHECK3-NEXT: ret void 458 // 459 // 460 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 461 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { 462 // CHECK3-NEXT: entry: 463 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 464 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 465 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 466 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 467 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 468 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 469 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 470 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 471 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 472 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 473 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 474 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 475 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 476 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 477 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 478 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 479 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 480 // CHECK3-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 481 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 482 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 483 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 484 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 485 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 486 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 487 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 488 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 489 // CHECK3: cond.true: 490 // CHECK3-NEXT: br label [[COND_END:%.*]] 491 // CHECK3: cond.false: 492 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 493 // CHECK3-NEXT: br label [[COND_END]] 494 // CHECK3: cond.end: 495 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 496 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 497 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 498 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 499 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 500 // CHECK3: omp.inner.for.cond: 501 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 502 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 503 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 504 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 505 // CHECK3: omp.inner.for.body: 506 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 507 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 508 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 509 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 510 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 511 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 512 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 513 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 514 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 515 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 516 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 517 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 518 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 519 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 520 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 521 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 522 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 523 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 524 // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 525 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 526 // CHECK3: omp.body.continue: 527 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 528 // CHECK3: omp.inner.for.inc: 529 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 530 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 531 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 532 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 533 // CHECK3: omp.inner.for.end: 534 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 535 // CHECK3: omp.loop.exit: 536 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 537 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 538 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 539 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 540 // CHECK3: .omp.final.then: 541 // CHECK3-NEXT: store i32 123, i32* [[I]], align 4 542 // CHECK3-NEXT: store i32 456, i32* [[J]], align 4 543 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 544 // CHECK3: .omp.final.done: 545 // CHECK3-NEXT: ret void 546 // 547 // 548 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 549 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 550 // CHECK3-NEXT: entry: 551 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 552 // CHECK3-NEXT: ret void 553 // 554 // 555 // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_template_structv 556 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 557 // CHECK4-NEXT: entry: 558 // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 559 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 560 // CHECK4-NEXT: ret i32 [[CALL]] 561 // 562 // 563 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 564 // CHECK4-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 565 // CHECK4-NEXT: entry: 566 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 567 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 568 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 569 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 570 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 571 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 572 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 573 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 574 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 575 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 576 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 577 // CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 578 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 579 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 580 // CHECK4-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 581 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 582 // CHECK4-NEXT: store i8* null, i8** [[TMP4]], align 4 583 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 584 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 585 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 586 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 587 // CHECK4-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 588 // CHECK4-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 589 // CHECK4: omp_offload.failed: 590 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR2:[0-9]+]] 591 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 592 // CHECK4: omp_offload.cont: 593 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 594 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 595 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 596 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 597 // CHECK4-NEXT: ret i32 [[TMP9]] 598 // 599 // 600 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 601 // CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 602 // CHECK4-NEXT: entry: 603 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 604 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 605 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 606 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 607 // CHECK4-NEXT: ret void 608 // 609 // 610 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 611 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR1]] { 612 // CHECK4-NEXT: entry: 613 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 614 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 615 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 616 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 617 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 618 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 619 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 620 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 621 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 622 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 623 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 624 // CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 625 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 626 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 627 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 628 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 629 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 630 // CHECK4-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 631 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 632 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 633 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 634 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 635 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 636 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 637 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 638 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 639 // CHECK4: cond.true: 640 // CHECK4-NEXT: br label [[COND_END:%.*]] 641 // CHECK4: cond.false: 642 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 643 // CHECK4-NEXT: br label [[COND_END]] 644 // CHECK4: cond.end: 645 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 646 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 647 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 648 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 649 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 650 // CHECK4: omp.inner.for.cond: 651 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 652 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 653 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 654 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 655 // CHECK4: omp.inner.for.body: 656 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 657 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 658 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 659 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 660 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 661 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 662 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 663 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 664 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 665 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 666 // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 667 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 668 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 669 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 670 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 671 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 672 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 673 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 674 // CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 675 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 676 // CHECK4: omp.body.continue: 677 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 678 // CHECK4: omp.inner.for.inc: 679 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 680 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 681 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 682 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 683 // CHECK4: omp.inner.for.end: 684 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 685 // CHECK4: omp.loop.exit: 686 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 687 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 688 // CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 689 // CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 690 // CHECK4: .omp.final.then: 691 // CHECK4-NEXT: store i32 123, i32* [[I]], align 4 692 // CHECK4-NEXT: store i32 456, i32* [[J]], align 4 693 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 694 // CHECK4: .omp.final.done: 695 // CHECK4-NEXT: ret void 696 // 697 // 698 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 699 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 700 // CHECK4-NEXT: entry: 701 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 702 // CHECK4-NEXT: ret void 703 // 704 // 705 // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv 706 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 707 // CHECK5-NEXT: entry: 708 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 709 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 710 // CHECK5-NEXT: ret i32 [[CALL]] 711 // 712 // 713 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 714 // CHECK5-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 715 // CHECK5-NEXT: entry: 716 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 717 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 718 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 719 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 720 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 721 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 722 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 723 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 724 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 725 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 726 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 727 // CHECK5-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 728 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 729 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 730 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 731 // CHECK5: omp.inner.for.cond: 732 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 733 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 734 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 735 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 736 // CHECK5: omp.inner.for.body: 737 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 738 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 739 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 740 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 741 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 742 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 743 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 744 // CHECK5-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 745 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 746 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 747 // CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 748 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 749 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !2 750 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 751 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 752 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 753 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 754 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !2 755 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 756 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 757 // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !2 758 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 759 // CHECK5: omp.body.continue: 760 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 761 // CHECK5: omp.inner.for.inc: 762 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 763 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 764 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 765 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 766 // CHECK5: omp.inner.for.end: 767 // CHECK5-NEXT: store i32 123, i32* [[I]], align 4 768 // CHECK5-NEXT: store i32 456, i32* [[J]], align 4 769 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 770 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 771 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 772 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 773 // CHECK5-NEXT: ret i32 [[TMP9]] 774 // 775 // 776 // CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv 777 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 778 // CHECK6-NEXT: entry: 779 // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 780 // CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 781 // CHECK6-NEXT: ret i32 [[CALL]] 782 // 783 // 784 // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 785 // CHECK6-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 786 // CHECK6-NEXT: entry: 787 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 788 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 789 // CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 790 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 791 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 792 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 793 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 794 // CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 795 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 796 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 797 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 798 // CHECK6-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 799 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 800 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 801 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 802 // CHECK6: omp.inner.for.cond: 803 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 804 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 805 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 806 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 807 // CHECK6: omp.inner.for.body: 808 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 809 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 810 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 811 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 812 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 813 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 814 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 815 // CHECK6-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 816 // CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 817 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 818 // CHECK6-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 819 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 820 // CHECK6-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !2 821 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 822 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 823 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 824 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 825 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !2 826 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 827 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 828 // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !2 829 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 830 // CHECK6: omp.body.continue: 831 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 832 // CHECK6: omp.inner.for.inc: 833 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 834 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 835 // CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 836 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 837 // CHECK6: omp.inner.for.end: 838 // CHECK6-NEXT: store i32 123, i32* [[I]], align 4 839 // CHECK6-NEXT: store i32 456, i32* [[J]], align 4 840 // CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 841 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 842 // CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 843 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 844 // CHECK6-NEXT: ret i32 [[TMP9]] 845 // 846 // 847 // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv 848 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 849 // CHECK7-NEXT: entry: 850 // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 851 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 852 // CHECK7-NEXT: ret i32 [[CALL]] 853 // 854 // 855 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 856 // CHECK7-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 857 // CHECK7-NEXT: entry: 858 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 859 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 860 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 861 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 862 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 863 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 864 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 865 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 866 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 867 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 868 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 869 // CHECK7-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 870 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 871 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 872 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 873 // CHECK7: omp.inner.for.cond: 874 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 875 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 876 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 877 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 878 // CHECK7: omp.inner.for.body: 879 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 880 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 881 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 882 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 883 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 884 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 885 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 886 // CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 887 // CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 888 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 889 // CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 890 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 891 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !3 892 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 893 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 894 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP6]] 895 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !3 896 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 897 // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !3 898 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 899 // CHECK7: omp.body.continue: 900 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 901 // CHECK7: omp.inner.for.inc: 902 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 903 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 904 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 905 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 906 // CHECK7: omp.inner.for.end: 907 // CHECK7-NEXT: store i32 123, i32* [[I]], align 4 908 // CHECK7-NEXT: store i32 456, i32* [[J]], align 4 909 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 910 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 911 // CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 912 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 913 // CHECK7-NEXT: ret i32 [[TMP9]] 914 // 915 // 916 // CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv 917 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 918 // CHECK8-NEXT: entry: 919 // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 920 // CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 921 // CHECK8-NEXT: ret i32 [[CALL]] 922 // 923 // 924 // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 925 // CHECK8-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 926 // CHECK8-NEXT: entry: 927 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 928 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 929 // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 930 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 931 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 932 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 933 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 934 // CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 935 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 936 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 937 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 938 // CHECK8-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 939 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 940 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 941 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 942 // CHECK8: omp.inner.for.cond: 943 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 944 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 945 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 946 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 947 // CHECK8: omp.inner.for.body: 948 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 949 // CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 950 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 951 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 952 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 953 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 954 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 955 // CHECK8-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 956 // CHECK8-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 957 // CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 958 // CHECK8-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 959 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 960 // CHECK8-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !3 961 // CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 962 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 963 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP6]] 964 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !3 965 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 966 // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !3 967 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 968 // CHECK8: omp.body.continue: 969 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 970 // CHECK8: omp.inner.for.inc: 971 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 972 // CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 973 // CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 974 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 975 // CHECK8: omp.inner.for.end: 976 // CHECK8-NEXT: store i32 123, i32* [[I]], align 4 977 // CHECK8-NEXT: store i32 456, i32* [[J]], align 4 978 // CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 979 // CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 980 // CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 981 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 982 // CHECK8-NEXT: ret i32 [[TMP9]] 983 // 984 // 985 // CHECK9-LABEL: define {{[^@]+}}@main 986 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 987 // CHECK9-NEXT: entry: 988 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 989 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 990 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 991 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 992 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 993 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 994 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 995 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 996 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 997 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 998 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 999 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1000 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1001 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1002 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1003 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1004 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1005 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 1006 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 1007 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 1008 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1009 // CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 1010 // CHECK9-NEXT: store i32 100, i32* [[N]], align 4 1011 // CHECK9-NEXT: store i32 2, i32* [[M]], align 4 1012 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1013 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1014 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 1015 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1016 // CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 1017 // CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 1018 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1019 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 1020 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1021 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 1022 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 1023 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1024 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 1025 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 1026 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 1027 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 1028 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 1029 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 1030 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1031 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 1032 // CHECK9-NEXT: [[TMP12:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1033 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP12]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes to i8*), i64 40, i1 false) 1034 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1035 // CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 1036 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP14]], align 8 1037 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1038 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 1039 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP16]], align 8 1040 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1041 // CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 1042 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1043 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1044 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 1045 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1046 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 1047 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 1048 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1049 // CHECK9-NEXT: store i8* null, i8** [[TMP22]], align 8 1050 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1051 // CHECK9-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1052 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8 1053 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1054 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 1055 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP26]], align 8 1056 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1057 // CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 1058 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1059 // CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1060 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8 1061 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1062 // CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 1063 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 1064 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1065 // CHECK9-NEXT: store i8* null, i8** [[TMP32]], align 8 1066 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1067 // CHECK9-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32** 1068 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP34]], align 8 1069 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1070 // CHECK9-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 1071 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 8 1072 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1073 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP37]], align 8 1074 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1075 // CHECK9-NEXT: store i8* null, i8** [[TMP38]], align 8 1076 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1077 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1078 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1079 // CHECK9-NEXT: [[TMP42:%.*]] = load i32, i32* [[N]], align 4 1080 // CHECK9-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 1081 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 1082 // CHECK9-NEXT: store i32 [[TMP43]], i32* [[DOTCAPTURE_EXPR_3]], align 4 1083 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1084 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP44]], 0 1085 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1086 // CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 1087 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 1088 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP45]], 0 1089 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1090 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1091 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 1092 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1093 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 1094 // CHECK9-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 1095 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP46]], 1 1096 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1097 // CHECK9-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP39]], i8** [[TMP40]], i64* [[TMP41]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1098 // CHECK9-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 1099 // CHECK9-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1100 // CHECK9: omp_offload.failed: 1101 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 1102 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1103 // CHECK9: omp_offload.cont: 1104 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1105 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP49]]) 1106 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1107 // CHECK9-NEXT: [[TMP50:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1108 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP50]]) 1109 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, i32* [[RETVAL]], align 4 1110 // CHECK9-NEXT: ret i32 [[TMP51]] 1111 // 1112 // 1113 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 1114 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1115 // CHECK9-NEXT: entry: 1116 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1117 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1118 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1119 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1120 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1121 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1122 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1123 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1124 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1125 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1126 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1127 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1128 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1129 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1130 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1131 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 1132 // CHECK9-NEXT: ret void 1133 // 1134 // 1135 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 1136 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1137 // CHECK9-NEXT: entry: 1138 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1139 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1140 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 1141 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 1142 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1143 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1144 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1145 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1146 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1147 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1148 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1149 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1150 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1151 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1152 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1153 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1154 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1155 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1156 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1157 // CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 1158 // CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4 1159 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1160 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1161 // CHECK9-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 1162 // CHECK9-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 1163 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1164 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1165 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1166 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 1167 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 1168 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1169 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1170 // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1171 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 1172 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 1173 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 1174 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1175 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1176 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 1177 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1178 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1179 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1180 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 1181 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1182 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1183 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1184 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1185 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 1186 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4 1187 // CHECK9-NEXT: store i32 0, i32* [[J]], align 4 1188 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1189 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1190 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1191 // CHECK9: land.lhs.true: 1192 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1193 // CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 1194 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1195 // CHECK9: omp.precond.then: 1196 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1197 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1198 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 1199 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1200 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1201 // CHECK9-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1202 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 1203 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1204 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1205 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1206 // CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 1207 // CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1208 // CHECK9: cond.true: 1209 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1210 // CHECK9-NEXT: br label [[COND_END:%.*]] 1211 // CHECK9: cond.false: 1212 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1213 // CHECK9-NEXT: br label [[COND_END]] 1214 // CHECK9: cond.end: 1215 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 1216 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1217 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1218 // CHECK9-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 1219 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1220 // CHECK9: omp.inner.for.cond: 1221 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1222 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 1223 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 1224 // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1225 // CHECK9: omp.inner.for.body: 1226 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1227 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 1228 // CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 1229 // CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1230 // CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 1231 // CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 1232 // CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] 1233 // CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 1234 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 1235 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 1236 // CHECK9-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !5 1237 // CHECK9-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1238 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1239 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 1240 // CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 1241 // CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 1242 // CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 1243 // CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 1244 // CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] 1245 // CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 1246 // CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 1247 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 1248 // CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 1249 // CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 1250 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 1251 // CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] 1252 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 1253 // CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 1254 // CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 1255 // CHECK9-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !5 1256 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !5 1257 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 1258 // CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 1259 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] 1260 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !5 1261 // CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 1262 // CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] 1263 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !5 1264 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1265 // CHECK9: omp.body.continue: 1266 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1267 // CHECK9: omp.inner.for.inc: 1268 // CHECK9-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1269 // CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 1270 // CHECK9-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1271 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 1272 // CHECK9: omp.inner.for.end: 1273 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1274 // CHECK9: omp.loop.exit: 1275 // CHECK9-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1276 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 1277 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) 1278 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1279 // CHECK9-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1280 // CHECK9-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1281 // CHECK9: .omp.final.then: 1282 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1283 // CHECK9-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP35]], 0 1284 // CHECK9-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 1285 // CHECK9-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 1286 // CHECK9-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 1287 // CHECK9-NEXT: store i32 [[ADD42]], i32* [[I11]], align 4 1288 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1289 // CHECK9-NEXT: [[SUB43:%.*]] = sub nsw i32 [[TMP36]], 0 1290 // CHECK9-NEXT: [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1 1291 // CHECK9-NEXT: [[MUL45:%.*]] = mul nsw i32 [[DIV44]], 1 1292 // CHECK9-NEXT: [[ADD46:%.*]] = add nsw i32 0, [[MUL45]] 1293 // CHECK9-NEXT: store i32 [[ADD46]], i32* [[J12]], align 4 1294 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1295 // CHECK9: .omp.final.done: 1296 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 1297 // CHECK9: omp.precond.end: 1298 // CHECK9-NEXT: ret void 1299 // 1300 // 1301 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1302 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 1303 // CHECK9-NEXT: entry: 1304 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1305 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1306 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1307 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1308 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1309 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1310 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1311 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1312 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1313 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1314 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 1315 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1316 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1317 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 1318 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1319 // CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 1320 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1321 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1322 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 1323 // CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1324 // CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1325 // CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1326 // CHECK9: omp_offload.failed: 1327 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 1328 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1329 // CHECK9: omp_offload.cont: 1330 // CHECK9-NEXT: ret i32 0 1331 // 1332 // 1333 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 1334 // CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1335 // CHECK9-NEXT: entry: 1336 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1337 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1338 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1339 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1340 // CHECK9-NEXT: ret void 1341 // 1342 // 1343 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 1344 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1345 // CHECK9-NEXT: entry: 1346 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1347 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1348 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1349 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1350 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1351 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1352 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1353 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1354 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1355 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1356 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1357 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1358 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1359 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1360 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1361 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1362 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1363 // CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1364 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1365 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1366 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1367 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1368 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1369 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1370 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1371 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1372 // CHECK9: cond.true: 1373 // CHECK9-NEXT: br label [[COND_END:%.*]] 1374 // CHECK9: cond.false: 1375 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1376 // CHECK9-NEXT: br label [[COND_END]] 1377 // CHECK9: cond.end: 1378 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1379 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1380 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1381 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1382 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1383 // CHECK9: omp.inner.for.cond: 1384 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1385 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 1386 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1387 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1388 // CHECK9: omp.inner.for.body: 1389 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1390 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1391 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1392 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1393 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 1394 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1395 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1396 // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1397 // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1398 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1399 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1400 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1401 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 1402 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1403 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1404 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 1405 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 1406 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 1407 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 1408 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 1409 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1410 // CHECK9: omp.body.continue: 1411 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1412 // CHECK9: omp.inner.for.inc: 1413 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1414 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 1415 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1416 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1417 // CHECK9: omp.inner.for.end: 1418 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1419 // CHECK9: omp.loop.exit: 1420 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1421 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1422 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1423 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1424 // CHECK9: .omp.final.then: 1425 // CHECK9-NEXT: store i32 10, i32* [[I]], align 4 1426 // CHECK9-NEXT: store i32 2, i32* [[J]], align 4 1427 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1428 // CHECK9: .omp.final.done: 1429 // CHECK9-NEXT: ret void 1430 // 1431 // 1432 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1433 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { 1434 // CHECK9-NEXT: entry: 1435 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1436 // CHECK9-NEXT: ret void 1437 // 1438 // 1439 // CHECK10-LABEL: define {{[^@]+}}@main 1440 // CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1441 // CHECK10-NEXT: entry: 1442 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1443 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1444 // CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 1445 // CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 1446 // CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 1447 // CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1448 // CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1449 // CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1450 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1451 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 1452 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1453 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1454 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1455 // CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1456 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1457 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1458 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1459 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 1460 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 1461 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1462 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1463 // CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 1464 // CHECK10-NEXT: store i32 100, i32* [[N]], align 4 1465 // CHECK10-NEXT: store i32 2, i32* [[M]], align 4 1466 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1467 // CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1468 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 1469 // CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1470 // CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 1471 // CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 1472 // CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1473 // CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 1474 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1475 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 1476 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 1477 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1478 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 1479 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 1480 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 1481 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 1482 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 1483 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 1484 // CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1485 // CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 1486 // CHECK10-NEXT: [[TMP12:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1487 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP12]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes to i8*), i64 40, i1 false) 1488 // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1489 // CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 1490 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP14]], align 8 1491 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1492 // CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 1493 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP16]], align 8 1494 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1495 // CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 1496 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1497 // CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1498 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 1499 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1500 // CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 1501 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 1502 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1503 // CHECK10-NEXT: store i8* null, i8** [[TMP22]], align 8 1504 // CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1505 // CHECK10-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1506 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8 1507 // CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1508 // CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 1509 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP26]], align 8 1510 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1511 // CHECK10-NEXT: store i8* null, i8** [[TMP27]], align 8 1512 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1513 // CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1514 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8 1515 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1516 // CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 1517 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 1518 // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1519 // CHECK10-NEXT: store i8* null, i8** [[TMP32]], align 8 1520 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1521 // CHECK10-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32** 1522 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP34]], align 8 1523 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1524 // CHECK10-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 1525 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 8 1526 // CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1527 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP37]], align 8 1528 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1529 // CHECK10-NEXT: store i8* null, i8** [[TMP38]], align 8 1530 // CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1531 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1532 // CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1533 // CHECK10-NEXT: [[TMP42:%.*]] = load i32, i32* [[N]], align 4 1534 // CHECK10-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 1535 // CHECK10-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 1536 // CHECK10-NEXT: store i32 [[TMP43]], i32* [[DOTCAPTURE_EXPR_3]], align 4 1537 // CHECK10-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1538 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP44]], 0 1539 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1540 // CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 1541 // CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 1542 // CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP45]], 0 1543 // CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1544 // CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1545 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 1546 // CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1547 // CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 1548 // CHECK10-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 1549 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP46]], 1 1550 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1551 // CHECK10-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP39]], i8** [[TMP40]], i64* [[TMP41]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1552 // CHECK10-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 1553 // CHECK10-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1554 // CHECK10: omp_offload.failed: 1555 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 1556 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1557 // CHECK10: omp_offload.cont: 1558 // CHECK10-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1559 // CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP49]]) 1560 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1561 // CHECK10-NEXT: [[TMP50:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1562 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP50]]) 1563 // CHECK10-NEXT: [[TMP51:%.*]] = load i32, i32* [[RETVAL]], align 4 1564 // CHECK10-NEXT: ret i32 [[TMP51]] 1565 // 1566 // 1567 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 1568 // CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1569 // CHECK10-NEXT: entry: 1570 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1571 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1572 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1573 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1574 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1575 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1576 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1577 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1578 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1579 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1580 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1581 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1582 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1583 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1584 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1585 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], i32* [[CONV3]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 1586 // CHECK10-NEXT: ret void 1587 // 1588 // 1589 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 1590 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 1591 // CHECK10-NEXT: entry: 1592 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1593 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1594 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 1595 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 8 1596 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1597 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1598 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1599 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1600 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1601 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1602 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1603 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1604 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1605 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1606 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 1607 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1608 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1609 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1610 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1611 // CHECK10-NEXT: [[I11:%.*]] = alloca i32, align 4 1612 // CHECK10-NEXT: [[J12:%.*]] = alloca i32, align 4 1613 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1614 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1615 // CHECK10-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 1616 // CHECK10-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 8 1617 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1618 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1619 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1620 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 1621 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 8 1622 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1623 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1624 // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1625 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 1626 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 1627 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 1628 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1629 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1630 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 1631 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1632 // CHECK10-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1633 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1634 // CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 1635 // CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1636 // CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1637 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1638 // CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1639 // CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 1640 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 1641 // CHECK10-NEXT: store i32 0, i32* [[J]], align 4 1642 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1643 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1644 // CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1645 // CHECK10: land.lhs.true: 1646 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1647 // CHECK10-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 1648 // CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1649 // CHECK10: omp.precond.then: 1650 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1651 // CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1652 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 1653 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1654 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1655 // CHECK10-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1656 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 1657 // CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1658 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1659 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1660 // CHECK10-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 1661 // CHECK10-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1662 // CHECK10: cond.true: 1663 // CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1664 // CHECK10-NEXT: br label [[COND_END:%.*]] 1665 // CHECK10: cond.false: 1666 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1667 // CHECK10-NEXT: br label [[COND_END]] 1668 // CHECK10: cond.end: 1669 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 1670 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1671 // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1672 // CHECK10-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 1673 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1674 // CHECK10: omp.inner.for.cond: 1675 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1676 // CHECK10-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 1677 // CHECK10-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 1678 // CHECK10-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1679 // CHECK10: omp.inner.for.body: 1680 // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1681 // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 1682 // CHECK10-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 1683 // CHECK10-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1684 // CHECK10-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 1685 // CHECK10-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 1686 // CHECK10-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] 1687 // CHECK10-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 1688 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 1689 // CHECK10-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 1690 // CHECK10-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !5 1691 // CHECK10-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1692 // CHECK10-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1693 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 1694 // CHECK10-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 1695 // CHECK10-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 1696 // CHECK10-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 1697 // CHECK10-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 1698 // CHECK10-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] 1699 // CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !5 1700 // CHECK10-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 1701 // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 1702 // CHECK10-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 1703 // CHECK10-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 1704 // CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 1705 // CHECK10-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] 1706 // CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 1707 // CHECK10-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 1708 // CHECK10-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 1709 // CHECK10-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !5 1710 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !5 1711 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 1712 // CHECK10-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 1713 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i64 [[TMP28]] 1714 // CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !5 1715 // CHECK10-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 1716 // CHECK10-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM36]] 1717 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX37]], align 4, !llvm.access.group !5 1718 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1719 // CHECK10: omp.body.continue: 1720 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1721 // CHECK10: omp.inner.for.inc: 1722 // CHECK10-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1723 // CHECK10-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 1724 // CHECK10-NEXT: store i64 [[ADD38]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1725 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 1726 // CHECK10: omp.inner.for.end: 1727 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1728 // CHECK10: omp.loop.exit: 1729 // CHECK10-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1730 // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 1731 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) 1732 // CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1733 // CHECK10-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1734 // CHECK10-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1735 // CHECK10: .omp.final.then: 1736 // CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1737 // CHECK10-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP35]], 0 1738 // CHECK10-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 1739 // CHECK10-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 1740 // CHECK10-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 1741 // CHECK10-NEXT: store i32 [[ADD42]], i32* [[I11]], align 4 1742 // CHECK10-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1743 // CHECK10-NEXT: [[SUB43:%.*]] = sub nsw i32 [[TMP36]], 0 1744 // CHECK10-NEXT: [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1 1745 // CHECK10-NEXT: [[MUL45:%.*]] = mul nsw i32 [[DIV44]], 1 1746 // CHECK10-NEXT: [[ADD46:%.*]] = add nsw i32 0, [[MUL45]] 1747 // CHECK10-NEXT: store i32 [[ADD46]], i32* [[J12]], align 4 1748 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] 1749 // CHECK10: .omp.final.done: 1750 // CHECK10-NEXT: br label [[OMP_PRECOND_END]] 1751 // CHECK10: omp.precond.end: 1752 // CHECK10-NEXT: ret void 1753 // 1754 // 1755 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1756 // CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 1757 // CHECK10-NEXT: entry: 1758 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1759 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1760 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1761 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1762 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1763 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1764 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1765 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1766 // CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1767 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1768 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 1769 // CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1770 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1771 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 1772 // CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1773 // CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 1774 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1775 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1776 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 1777 // CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1778 // CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1779 // CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1780 // CHECK10: omp_offload.failed: 1781 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 1782 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1783 // CHECK10: omp_offload.cont: 1784 // CHECK10-NEXT: ret i32 0 1785 // 1786 // 1787 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 1788 // CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1789 // CHECK10-NEXT: entry: 1790 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1791 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1792 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1793 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1794 // CHECK10-NEXT: ret void 1795 // 1796 // 1797 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 1798 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1799 // CHECK10-NEXT: entry: 1800 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1801 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1802 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1803 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1804 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1805 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1806 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1807 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1808 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1809 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1810 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1811 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 1812 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1813 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1814 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1815 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1816 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1817 // CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1818 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1819 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1820 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1821 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1822 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1823 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1824 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1825 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1826 // CHECK10: cond.true: 1827 // CHECK10-NEXT: br label [[COND_END:%.*]] 1828 // CHECK10: cond.false: 1829 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1830 // CHECK10-NEXT: br label [[COND_END]] 1831 // CHECK10: cond.end: 1832 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1833 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1834 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1835 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1836 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1837 // CHECK10: omp.inner.for.cond: 1838 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1839 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 1840 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1841 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1842 // CHECK10: omp.inner.for.body: 1843 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1844 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1845 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1846 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1847 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 1848 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1849 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1850 // CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1851 // CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1852 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1853 // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1854 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1855 // CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 1856 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1857 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1858 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 1859 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 1860 // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 1861 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 1862 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 1863 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1864 // CHECK10: omp.body.continue: 1865 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1866 // CHECK10: omp.inner.for.inc: 1867 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1868 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 1869 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1870 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1871 // CHECK10: omp.inner.for.end: 1872 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1873 // CHECK10: omp.loop.exit: 1874 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1875 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1876 // CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1877 // CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1878 // CHECK10: .omp.final.then: 1879 // CHECK10-NEXT: store i32 10, i32* [[I]], align 4 1880 // CHECK10-NEXT: store i32 2, i32* [[J]], align 4 1881 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] 1882 // CHECK10: .omp.final.done: 1883 // CHECK10-NEXT: ret void 1884 // 1885 // 1886 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1887 // CHECK10-SAME: () #[[ATTR6:[0-9]+]] { 1888 // CHECK10-NEXT: entry: 1889 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 1890 // CHECK10-NEXT: ret void 1891 // 1892 // 1893 // CHECK11-LABEL: define {{[^@]+}}@main 1894 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1895 // CHECK11-NEXT: entry: 1896 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1897 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1898 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 1899 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 1900 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 1901 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1902 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1903 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1904 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1905 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1906 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1907 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1908 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1909 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 1910 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1911 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1912 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1913 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1914 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1915 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1916 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1917 // CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 1918 // CHECK11-NEXT: store i32 100, i32* [[N]], align 4 1919 // CHECK11-NEXT: store i32 2, i32* [[M]], align 4 1920 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1921 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 1922 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1923 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1924 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1925 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 1926 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 1927 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 1928 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 1929 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 1930 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 1931 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 1932 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 1933 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 1934 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1935 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 1936 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 1937 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1938 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes to i8*), i32 40, i1 false) 1939 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1940 // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 1941 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP13]], align 4 1942 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1943 // CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1944 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP15]], align 4 1945 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1946 // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 1947 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1948 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 1949 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 1950 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1951 // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1952 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 1953 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1954 // CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 1955 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1956 // CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 1957 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP23]], align 4 1958 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1959 // CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1960 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP25]], align 4 1961 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1962 // CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 1963 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1964 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1965 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 1966 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1967 // CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1968 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 1969 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1970 // CHECK11-NEXT: store i8* null, i8** [[TMP31]], align 4 1971 // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1972 // CHECK11-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32** 1973 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP33]], align 4 1974 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1975 // CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32** 1976 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP35]], align 4 1977 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1978 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP36]], align 4 1979 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1980 // CHECK11-NEXT: store i8* null, i8** [[TMP37]], align 4 1981 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1982 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1983 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1984 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[N]], align 4 1985 // CHECK11-NEXT: store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR_]], align 4 1986 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, i32* [[M]], align 4 1987 // CHECK11-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1988 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1989 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP43]], 0 1990 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1991 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1992 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1993 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP44]], 0 1994 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1995 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1996 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1997 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1998 // CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 1999 // CHECK11-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 2000 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP45]], 1 2001 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 2002 // CHECK11-NEXT: [[TMP46:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP38]], i8** [[TMP39]], i64* [[TMP40]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2003 // CHECK11-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 2004 // CHECK11-NEXT: br i1 [[TMP47]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2005 // CHECK11: omp_offload.failed: 2006 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 2007 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2008 // CHECK11: omp_offload.cont: 2009 // CHECK11-NEXT: [[TMP48:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2010 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP48]]) 2011 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2012 // CHECK11-NEXT: [[TMP49:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2013 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP49]]) 2014 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, i32* [[RETVAL]], align 4 2015 // CHECK11-NEXT: ret i32 [[TMP50]] 2016 // 2017 // 2018 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 2019 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 2020 // CHECK11-NEXT: entry: 2021 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2022 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 2023 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2024 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2025 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2026 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2027 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 2028 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2029 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2030 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2031 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2032 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2033 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2034 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 2035 // CHECK11-NEXT: ret void 2036 // 2037 // 2038 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 2039 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 2040 // CHECK11-NEXT: entry: 2041 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2042 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2043 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 2044 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 2045 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2046 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2047 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2048 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2049 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 2050 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2051 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2052 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 2053 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 2054 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 2055 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 2056 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2057 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2058 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2059 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2060 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 2061 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 2062 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2063 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2064 // CHECK11-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 2065 // CHECK11-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 2066 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2067 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2068 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2069 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 2070 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 2071 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2072 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2073 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2074 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 2075 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 2076 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 2077 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 2078 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2079 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 2080 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2081 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2082 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2083 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 2084 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 2085 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 2086 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 2087 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 2088 // CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 2089 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 2090 // CHECK11-NEXT: store i32 0, i32* [[J]], align 4 2091 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2092 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 2093 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 2094 // CHECK11: land.lhs.true: 2095 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2096 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 2097 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 2098 // CHECK11: omp.precond.then: 2099 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2100 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2101 // CHECK11-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 2102 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2103 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2104 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2105 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 2106 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2107 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2108 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2109 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 2110 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2111 // CHECK11: cond.true: 2112 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2113 // CHECK11-NEXT: br label [[COND_END:%.*]] 2114 // CHECK11: cond.false: 2115 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2116 // CHECK11-NEXT: br label [[COND_END]] 2117 // CHECK11: cond.end: 2118 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 2119 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2120 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2121 // CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 2122 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2123 // CHECK11: omp.inner.for.cond: 2124 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2125 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 2126 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 2127 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2128 // CHECK11: omp.inner.for.body: 2129 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2130 // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2131 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 2132 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 2133 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 2134 // CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 2135 // CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] 2136 // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 2137 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 2138 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 2139 // CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 2140 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2141 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2142 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2143 // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 2144 // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 2145 // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 2146 // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 2147 // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] 2148 // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2149 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 2150 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 2151 // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 2152 // CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 2153 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 2154 // CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] 2155 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 2156 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 2157 // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 2158 // CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 2159 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 2160 // CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] 2161 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] 2162 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 2163 // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] 2164 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 2165 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2166 // CHECK11: omp.body.continue: 2167 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2168 // CHECK11: omp.inner.for.inc: 2169 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2170 // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 2171 // CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2172 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2173 // CHECK11: omp.inner.for.end: 2174 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2175 // CHECK11: omp.loop.exit: 2176 // CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2177 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 2178 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) 2179 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2180 // CHECK11-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 2181 // CHECK11-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2182 // CHECK11: .omp.final.then: 2183 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2184 // CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i32 [[TMP35]], 0 2185 // CHECK11-NEXT: [[DIV39:%.*]] = sdiv i32 [[SUB38]], 1 2186 // CHECK11-NEXT: [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 1 2187 // CHECK11-NEXT: [[ADD41:%.*]] = add nsw i32 0, [[MUL40]] 2188 // CHECK11-NEXT: store i32 [[ADD41]], i32* [[I11]], align 4 2189 // CHECK11-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2190 // CHECK11-NEXT: [[SUB42:%.*]] = sub nsw i32 [[TMP36]], 0 2191 // CHECK11-NEXT: [[DIV43:%.*]] = sdiv i32 [[SUB42]], 1 2192 // CHECK11-NEXT: [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 1 2193 // CHECK11-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 2194 // CHECK11-NEXT: store i32 [[ADD45]], i32* [[J12]], align 4 2195 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 2196 // CHECK11: .omp.final.done: 2197 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 2198 // CHECK11: omp.precond.end: 2199 // CHECK11-NEXT: ret void 2200 // 2201 // 2202 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2203 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 2204 // CHECK11-NEXT: entry: 2205 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2206 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2207 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2208 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2209 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2210 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 2211 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2212 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2213 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2214 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 2215 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 2216 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2217 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 2218 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 2219 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2220 // CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 2221 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2222 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2223 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 2224 // CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2225 // CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2226 // CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2227 // CHECK11: omp_offload.failed: 2228 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 2229 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2230 // CHECK11: omp_offload.cont: 2231 // CHECK11-NEXT: ret i32 0 2232 // 2233 // 2234 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 2235 // CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2236 // CHECK11-NEXT: entry: 2237 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2238 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2239 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2240 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 2241 // CHECK11-NEXT: ret void 2242 // 2243 // 2244 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2245 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2246 // CHECK11-NEXT: entry: 2247 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2248 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2249 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2250 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2251 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 2252 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2253 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2254 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2255 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2256 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2257 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 2258 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 2259 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2260 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2261 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2262 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2263 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2264 // CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 2265 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2266 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2267 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2268 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2269 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2270 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2271 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 2272 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2273 // CHECK11: cond.true: 2274 // CHECK11-NEXT: br label [[COND_END:%.*]] 2275 // CHECK11: cond.false: 2276 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2277 // CHECK11-NEXT: br label [[COND_END]] 2278 // CHECK11: cond.end: 2279 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2280 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2281 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2282 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2283 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2284 // CHECK11: omp.inner.for.cond: 2285 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2286 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 2287 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2288 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2289 // CHECK11: omp.inner.for.body: 2290 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2291 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 2292 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2293 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2294 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 2295 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2296 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2297 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 2298 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 2299 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 2300 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2301 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 2302 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 2303 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2304 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 2305 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 2306 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 2307 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 2308 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2309 // CHECK11: omp.body.continue: 2310 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2311 // CHECK11: omp.inner.for.inc: 2312 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2313 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 2314 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2315 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 2316 // CHECK11: omp.inner.for.end: 2317 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2318 // CHECK11: omp.loop.exit: 2319 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2320 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2321 // CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2322 // CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2323 // CHECK11: .omp.final.then: 2324 // CHECK11-NEXT: store i32 10, i32* [[I]], align 4 2325 // CHECK11-NEXT: store i32 2, i32* [[J]], align 4 2326 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 2327 // CHECK11: .omp.final.done: 2328 // CHECK11-NEXT: ret void 2329 // 2330 // 2331 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2332 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] { 2333 // CHECK11-NEXT: entry: 2334 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 2335 // CHECK11-NEXT: ret void 2336 // 2337 // 2338 // CHECK12-LABEL: define {{[^@]+}}@main 2339 // CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2340 // CHECK12-NEXT: entry: 2341 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2342 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2343 // CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 2344 // CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 2345 // CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 2346 // CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2347 // CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2348 // CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2349 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2350 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 2351 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2352 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2353 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2354 // CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2355 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2356 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2357 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2358 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2359 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 2360 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2361 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2362 // CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 2363 // CHECK12-NEXT: store i32 100, i32* [[N]], align 4 2364 // CHECK12-NEXT: store i32 2, i32* [[M]], align 4 2365 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 2366 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 2367 // CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2368 // CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2369 // CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2370 // CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 2371 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 2372 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 2373 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 2374 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 2375 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 2376 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 2377 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 2378 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 2379 // CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2380 // CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 2381 // CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 2382 // CHECK12-NEXT: [[TMP11:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2383 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes to i8*), i32 40, i1 false) 2384 // CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2385 // CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2386 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP13]], align 4 2387 // CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2388 // CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 2389 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP15]], align 4 2390 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2391 // CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 2392 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2393 // CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2394 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 2395 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2396 // CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 2397 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 2398 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2399 // CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 2400 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2401 // CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 2402 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP23]], align 4 2403 // CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2404 // CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2405 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP25]], align 4 2406 // CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2407 // CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 2408 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2409 // CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 2410 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 2411 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2412 // CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 2413 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 2414 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2415 // CHECK12-NEXT: store i8* null, i8** [[TMP31]], align 4 2416 // CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2417 // CHECK12-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32** 2418 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP33]], align 4 2419 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2420 // CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32** 2421 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP35]], align 4 2422 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2423 // CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP36]], align 4 2424 // CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2425 // CHECK12-NEXT: store i8* null, i8** [[TMP37]], align 4 2426 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2427 // CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2428 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2429 // CHECK12-NEXT: [[TMP41:%.*]] = load i32, i32* [[N]], align 4 2430 // CHECK12-NEXT: store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR_]], align 4 2431 // CHECK12-NEXT: [[TMP42:%.*]] = load i32, i32* [[M]], align 4 2432 // CHECK12-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2433 // CHECK12-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2434 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP43]], 0 2435 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2436 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2437 // CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2438 // CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP44]], 0 2439 // CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 2440 // CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 2441 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 2442 // CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 2443 // CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 2444 // CHECK12-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 2445 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP45]], 1 2446 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 2447 // CHECK12-NEXT: [[TMP46:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, i32 5, i8** [[TMP38]], i8** [[TMP39]], i64* [[TMP40]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2448 // CHECK12-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 2449 // CHECK12-NEXT: br i1 [[TMP47]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2450 // CHECK12: omp_offload.failed: 2451 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR3:[0-9]+]] 2452 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2453 // CHECK12: omp_offload.cont: 2454 // CHECK12-NEXT: [[TMP48:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2455 // CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP48]]) 2456 // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2457 // CHECK12-NEXT: [[TMP49:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2458 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP49]]) 2459 // CHECK12-NEXT: [[TMP50:%.*]] = load i32, i32* [[RETVAL]], align 4 2460 // CHECK12-NEXT: ret i32 [[TMP50]] 2461 // 2462 // 2463 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 2464 // CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 2465 // CHECK12-NEXT: entry: 2466 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2467 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 2468 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2469 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2470 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2471 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2472 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 2473 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2474 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2475 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2476 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2477 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2478 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2479 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[N_ADDR]], i32* [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 2480 // CHECK12-NEXT: ret void 2481 // 2482 // 2483 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 2484 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { 2485 // CHECK12-NEXT: entry: 2486 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2487 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2488 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 2489 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32*, align 4 2490 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2491 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2492 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2493 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2494 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2495 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2496 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2497 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 2498 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 2499 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 2500 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 2501 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2502 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2503 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2504 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2505 // CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 2506 // CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4 2507 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2508 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2509 // CHECK12-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 2510 // CHECK12-NEXT: store i32* [[M]], i32** [[M_ADDR]], align 4 2511 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2512 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2513 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2514 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 2515 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[M_ADDR]], align 4 2516 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2517 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2518 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2519 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 2520 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 2521 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4 2522 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 2523 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2524 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 2525 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2526 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2527 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2528 // CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 2529 // CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 2530 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 2531 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 2532 // CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 2533 // CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 2534 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 2535 // CHECK12-NEXT: store i32 0, i32* [[J]], align 4 2536 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2537 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 2538 // CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 2539 // CHECK12: land.lhs.true: 2540 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2541 // CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] 2542 // CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 2543 // CHECK12: omp.precond.then: 2544 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2545 // CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2546 // CHECK12-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 2547 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2548 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2549 // CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2550 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 2551 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP13]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2552 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2553 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2554 // CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 2555 // CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2556 // CHECK12: cond.true: 2557 // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2558 // CHECK12-NEXT: br label [[COND_END:%.*]] 2559 // CHECK12: cond.false: 2560 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2561 // CHECK12-NEXT: br label [[COND_END]] 2562 // CHECK12: cond.end: 2563 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 2564 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2565 // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2566 // CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 2567 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2568 // CHECK12: omp.inner.for.cond: 2569 // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2570 // CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 2571 // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 2572 // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2573 // CHECK12: omp.inner.for.body: 2574 // CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2575 // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2576 // CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 2577 // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 2578 // CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 2579 // CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 2580 // CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] 2581 // CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 2582 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 2583 // CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 2584 // CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 2585 // CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2586 // CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2587 // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2588 // CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 2589 // CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 2590 // CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 2591 // CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 2592 // CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] 2593 // CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2594 // CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 2595 // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 2596 // CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 2597 // CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 2598 // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 2599 // CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] 2600 // CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 2601 // CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 2602 // CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 2603 // CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 2604 // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 2605 // CHECK12-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] 2606 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32 [[TMP28]] 2607 // CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 2608 // CHECK12-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP29]] 2609 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 2610 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2611 // CHECK12: omp.body.continue: 2612 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2613 // CHECK12: omp.inner.for.inc: 2614 // CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2615 // CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 2616 // CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2617 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2618 // CHECK12: omp.inner.for.end: 2619 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2620 // CHECK12: omp.loop.exit: 2621 // CHECK12-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2622 // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[TMP31]], align 4 2623 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP32]]) 2624 // CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2625 // CHECK12-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 2626 // CHECK12-NEXT: br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2627 // CHECK12: .omp.final.then: 2628 // CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2629 // CHECK12-NEXT: [[SUB38:%.*]] = sub nsw i32 [[TMP35]], 0 2630 // CHECK12-NEXT: [[DIV39:%.*]] = sdiv i32 [[SUB38]], 1 2631 // CHECK12-NEXT: [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 1 2632 // CHECK12-NEXT: [[ADD41:%.*]] = add nsw i32 0, [[MUL40]] 2633 // CHECK12-NEXT: store i32 [[ADD41]], i32* [[I11]], align 4 2634 // CHECK12-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2635 // CHECK12-NEXT: [[SUB42:%.*]] = sub nsw i32 [[TMP36]], 0 2636 // CHECK12-NEXT: [[DIV43:%.*]] = sdiv i32 [[SUB42]], 1 2637 // CHECK12-NEXT: [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 1 2638 // CHECK12-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 2639 // CHECK12-NEXT: store i32 [[ADD45]], i32* [[J12]], align 4 2640 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] 2641 // CHECK12: .omp.final.done: 2642 // CHECK12-NEXT: br label [[OMP_PRECOND_END]] 2643 // CHECK12: omp.precond.end: 2644 // CHECK12-NEXT: ret void 2645 // 2646 // 2647 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2648 // CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat { 2649 // CHECK12-NEXT: entry: 2650 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2651 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2652 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2653 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2654 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2655 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2656 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2657 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2658 // CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2659 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 2660 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 2661 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2662 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 2663 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 2664 // CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2665 // CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 2666 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2667 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2668 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 2669 // CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2670 // CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2671 // CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2672 // CHECK12: omp_offload.failed: 2673 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69([10 x [2 x i32]]* [[A]]) #[[ATTR3]] 2674 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2675 // CHECK12: omp_offload.cont: 2676 // CHECK12-NEXT: ret i32 0 2677 // 2678 // 2679 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69 2680 // CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2681 // CHECK12-NEXT: entry: 2682 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2683 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2684 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2685 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 2686 // CHECK12-NEXT: ret void 2687 // 2688 // 2689 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 2690 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2691 // CHECK12-NEXT: entry: 2692 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2693 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2694 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2695 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2696 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2697 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2698 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2699 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2700 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2701 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2702 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 2703 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 2704 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2705 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2706 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2707 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2708 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2709 // CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 2710 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2711 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2712 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2713 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2714 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2715 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2716 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 2717 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2718 // CHECK12: cond.true: 2719 // CHECK12-NEXT: br label [[COND_END:%.*]] 2720 // CHECK12: cond.false: 2721 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2722 // CHECK12-NEXT: br label [[COND_END]] 2723 // CHECK12: cond.end: 2724 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2725 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2726 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2727 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2728 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2729 // CHECK12: omp.inner.for.cond: 2730 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2731 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 2732 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2733 // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2734 // CHECK12: omp.inner.for.body: 2735 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2736 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 2737 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2738 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2739 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 2740 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2741 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2742 // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 2743 // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 2744 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 2745 // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2746 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 2747 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 2748 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2749 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 2750 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 2751 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 2752 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 2753 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2754 // CHECK12: omp.body.continue: 2755 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2756 // CHECK12: omp.inner.for.inc: 2757 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2758 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 2759 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2760 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 2761 // CHECK12: omp.inner.for.end: 2762 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2763 // CHECK12: omp.loop.exit: 2764 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2765 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2766 // CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2767 // CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2768 // CHECK12: .omp.final.then: 2769 // CHECK12-NEXT: store i32 10, i32* [[I]], align 4 2770 // CHECK12-NEXT: store i32 2, i32* [[J]], align 4 2771 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] 2772 // CHECK12: .omp.final.done: 2773 // CHECK12-NEXT: ret void 2774 // 2775 // 2776 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2777 // CHECK12-SAME: () #[[ATTR6:[0-9]+]] { 2778 // CHECK12-NEXT: entry: 2779 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) 2780 // CHECK12-NEXT: ret void 2781 // 2782 // 2783 // CHECK13-LABEL: define {{[^@]+}}@main 2784 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2785 // CHECK13-NEXT: entry: 2786 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2787 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2788 // CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 2789 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 2790 // CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 2791 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2792 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2793 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2794 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 2795 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2796 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2797 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2798 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 2799 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2800 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2801 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2802 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 2803 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2804 // CHECK13-NEXT: [[I9:%.*]] = alloca i32, align 4 2805 // CHECK13-NEXT: [[J10:%.*]] = alloca i32, align 4 2806 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 2807 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2808 // CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 2809 // CHECK13-NEXT: store i32 100, i32* [[N]], align 4 2810 // CHECK13-NEXT: store i32 2, i32* [[M]], align 4 2811 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 2812 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2813 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 2814 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 2815 // CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 2816 // CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 2817 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 2818 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 2819 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 2820 // CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 2821 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 2822 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 2823 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 2824 // CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2825 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2826 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0 2827 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2828 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2829 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2830 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0 2831 // CHECK13-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 2832 // CHECK13-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 2833 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 2834 // CHECK13-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 2835 // CHECK13-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 2836 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2837 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 2838 // CHECK13-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_UB]], align 8 2839 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 2840 // CHECK13-NEXT: store i32 0, i32* [[J]], align 4 2841 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2842 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]] 2843 // CHECK13-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 2844 // CHECK13: land.lhs.true: 2845 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2846 // CHECK13-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]] 2847 // CHECK13-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 2848 // CHECK13: simd.if.then: 2849 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2850 // CHECK13-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_IV]], align 8 2851 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2852 // CHECK13: omp.inner.for.cond: 2853 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2854 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !2 2855 // CHECK13-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]] 2856 // CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2857 // CHECK13: omp.inner.for.body: 2858 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2859 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 2860 // CHECK13-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0 2861 // CHECK13-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 2862 // CHECK13-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 2863 // CHECK13-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 2864 // CHECK13-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]] 2865 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 2866 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 2867 // CHECK13-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 2868 // CHECK13-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !2 2869 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2870 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2871 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 2872 // CHECK13-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0 2873 // CHECK13-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 2874 // CHECK13-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 2875 // CHECK13-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 2876 // CHECK13-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]] 2877 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 2878 // CHECK13-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0 2879 // CHECK13-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 2880 // CHECK13-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 2881 // CHECK13-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 2882 // CHECK13-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 2883 // CHECK13-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]] 2884 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 2885 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 2886 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 2887 // CHECK13-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !2 2888 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !2 2889 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 2890 // CHECK13-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 2891 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP23]] 2892 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !2 2893 // CHECK13-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64 2894 // CHECK13-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM33]] 2895 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !2 2896 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2897 // CHECK13: omp.body.continue: 2898 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2899 // CHECK13: omp.inner.for.inc: 2900 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2901 // CHECK13-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1 2902 // CHECK13-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2903 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2904 // CHECK13: omp.inner.for.end: 2905 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2906 // CHECK13-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0 2907 // CHECK13-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 2908 // CHECK13-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1 2909 // CHECK13-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]] 2910 // CHECK13-NEXT: store i32 [[ADD39]], i32* [[I9]], align 4 2911 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2912 // CHECK13-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0 2913 // CHECK13-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 2914 // CHECK13-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 2915 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] 2916 // CHECK13-NEXT: store i32 [[ADD43]], i32* [[J10]], align 4 2917 // CHECK13-NEXT: br label [[SIMD_IF_END]] 2918 // CHECK13: simd.if.end: 2919 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2920 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) 2921 // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2922 // CHECK13-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2923 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 2924 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 2925 // CHECK13-NEXT: ret i32 [[TMP30]] 2926 // 2927 // 2928 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2929 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 2930 // CHECK13-NEXT: entry: 2931 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2932 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2933 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 2934 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2935 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2936 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2937 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2938 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2939 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 2940 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2941 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2942 // CHECK13-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 2943 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2944 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 2945 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2946 // CHECK13: omp.inner.for.cond: 2947 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2948 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 2949 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2950 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2951 // CHECK13: omp.inner.for.body: 2952 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2953 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 2954 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2955 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2956 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 2957 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2958 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2959 // CHECK13-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 2960 // CHECK13-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 2961 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 2962 // CHECK13-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 2963 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 2964 // CHECK13-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !6 2965 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 2966 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 2967 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 2968 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !6 2969 // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 2970 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] 2971 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !6 2972 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2973 // CHECK13: omp.body.continue: 2974 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2975 // CHECK13: omp.inner.for.inc: 2976 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2977 // CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 2978 // CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2979 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2980 // CHECK13: omp.inner.for.end: 2981 // CHECK13-NEXT: store i32 10, i32* [[I]], align 4 2982 // CHECK13-NEXT: store i32 2, i32* [[J]], align 4 2983 // CHECK13-NEXT: ret i32 0 2984 // 2985 // 2986 // CHECK14-LABEL: define {{[^@]+}}@main 2987 // CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2988 // CHECK14-NEXT: entry: 2989 // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2990 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2991 // CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 2992 // CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 2993 // CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 2994 // CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2995 // CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2996 // CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2997 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 2998 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2999 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3000 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3001 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 3002 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3003 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3004 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 3005 // CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 3006 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3007 // CHECK14-NEXT: [[I9:%.*]] = alloca i32, align 4 3008 // CHECK14-NEXT: [[J10:%.*]] = alloca i32, align 4 3009 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 3010 // CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3011 // CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 3012 // CHECK14-NEXT: store i32 100, i32* [[N]], align 4 3013 // CHECK14-NEXT: store i32 2, i32* [[M]], align 4 3014 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 3015 // CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 3016 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 3017 // CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 3018 // CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 3019 // CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 3020 // CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 3021 // CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 3022 // CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 3023 // CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 3024 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 3025 // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 3026 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 3027 // CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3028 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3029 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0 3030 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 3031 // CHECK14-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 3032 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3033 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0 3034 // CHECK14-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 3035 // CHECK14-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 3036 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 3037 // CHECK14-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 3038 // CHECK14-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 3039 // CHECK14-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3040 // CHECK14-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 3041 // CHECK14-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_UB]], align 8 3042 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4 3043 // CHECK14-NEXT: store i32 0, i32* [[J]], align 4 3044 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3045 // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]] 3046 // CHECK14-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 3047 // CHECK14: land.lhs.true: 3048 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3049 // CHECK14-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]] 3050 // CHECK14-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 3051 // CHECK14: simd.if.then: 3052 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3053 // CHECK14-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_IV]], align 8 3054 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3055 // CHECK14: omp.inner.for.cond: 3056 // CHECK14-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3057 // CHECK14-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !2 3058 // CHECK14-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]] 3059 // CHECK14-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3060 // CHECK14: omp.inner.for.body: 3061 // CHECK14-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3062 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 3063 // CHECK14-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0 3064 // CHECK14-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 3065 // CHECK14-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 3066 // CHECK14-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 3067 // CHECK14-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]] 3068 // CHECK14-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 3069 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 3070 // CHECK14-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 3071 // CHECK14-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !2 3072 // CHECK14-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3073 // CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3074 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 3075 // CHECK14-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0 3076 // CHECK14-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 3077 // CHECK14-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 3078 // CHECK14-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 3079 // CHECK14-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]] 3080 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 3081 // CHECK14-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0 3082 // CHECK14-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 3083 // CHECK14-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 3084 // CHECK14-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 3085 // CHECK14-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 3086 // CHECK14-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]] 3087 // CHECK14-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 3088 // CHECK14-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 3089 // CHECK14-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 3090 // CHECK14-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !2 3091 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !2 3092 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 3093 // CHECK14-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 3094 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP23]] 3095 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !2 3096 // CHECK14-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64 3097 // CHECK14-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM33]] 3098 // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !2 3099 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3100 // CHECK14: omp.body.continue: 3101 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3102 // CHECK14: omp.inner.for.inc: 3103 // CHECK14-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3104 // CHECK14-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1 3105 // CHECK14-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3106 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 3107 // CHECK14: omp.inner.for.end: 3108 // CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3109 // CHECK14-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0 3110 // CHECK14-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 3111 // CHECK14-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1 3112 // CHECK14-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]] 3113 // CHECK14-NEXT: store i32 [[ADD39]], i32* [[I9]], align 4 3114 // CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3115 // CHECK14-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0 3116 // CHECK14-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 3117 // CHECK14-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 3118 // CHECK14-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] 3119 // CHECK14-NEXT: store i32 [[ADD43]], i32* [[J10]], align 4 3120 // CHECK14-NEXT: br label [[SIMD_IF_END]] 3121 // CHECK14: simd.if.end: 3122 // CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 3123 // CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) 3124 // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3125 // CHECK14-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3126 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 3127 // CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 3128 // CHECK14-NEXT: ret i32 [[TMP30]] 3129 // 3130 // 3131 // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 3132 // CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 3133 // CHECK14-NEXT: entry: 3134 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3135 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 3136 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 3137 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3138 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3139 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3140 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3141 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 3142 // CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 3143 // CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3144 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3145 // CHECK14-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 3146 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3147 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3148 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3149 // CHECK14: omp.inner.for.cond: 3150 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3151 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 3152 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3153 // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3154 // CHECK14: omp.inner.for.body: 3155 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3156 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 3157 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 3158 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3159 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 3160 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3161 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3162 // CHECK14-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 3163 // CHECK14-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 3164 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 3165 // CHECK14-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 3166 // CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 3167 // CHECK14-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !6 3168 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 3169 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 3170 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 3171 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !6 3172 // CHECK14-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 3173 // CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] 3174 // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !6 3175 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3176 // CHECK14: omp.body.continue: 3177 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3178 // CHECK14: omp.inner.for.inc: 3179 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3180 // CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 3181 // CHECK14-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3182 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3183 // CHECK14: omp.inner.for.end: 3184 // CHECK14-NEXT: store i32 10, i32* [[I]], align 4 3185 // CHECK14-NEXT: store i32 2, i32* [[J]], align 4 3186 // CHECK14-NEXT: ret i32 0 3187 // 3188 // 3189 // CHECK15-LABEL: define {{[^@]+}}@main 3190 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 3191 // CHECK15-NEXT: entry: 3192 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3193 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3194 // CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 3195 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 3196 // CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 3197 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3198 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3199 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3200 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3201 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3202 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3203 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3204 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 3205 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3206 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3207 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3208 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 3209 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3210 // CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 3211 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4 3212 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 3213 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3214 // CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 3215 // CHECK15-NEXT: store i32 100, i32* [[N]], align 4 3216 // CHECK15-NEXT: store i32 2, i32* [[M]], align 4 3217 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 3218 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 3219 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3220 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3221 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 3222 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 3223 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 3224 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 3225 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 3226 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 3227 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[M]], align 4 3228 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3229 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3230 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 3231 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 3232 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 3233 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3234 // CHECK15-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0 3235 // CHECK15-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 3236 // CHECK15-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 3237 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 3238 // CHECK15-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 3239 // CHECK15-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 3240 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3241 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 3242 // CHECK15-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_UB]], align 8 3243 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4 3244 // CHECK15-NEXT: store i32 0, i32* [[J]], align 4 3245 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3246 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 3247 // CHECK15-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 3248 // CHECK15: land.lhs.true: 3249 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3250 // CHECK15-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]] 3251 // CHECK15-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 3252 // CHECK15: simd.if.then: 3253 // CHECK15-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3254 // CHECK15-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 3255 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3256 // CHECK15: omp.inner.for.cond: 3257 // CHECK15-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3258 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !3 3259 // CHECK15-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]] 3260 // CHECK15-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3261 // CHECK15: omp.inner.for.body: 3262 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3263 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3264 // CHECK15-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0 3265 // CHECK15-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 3266 // CHECK15-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 3267 // CHECK15-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 3268 // CHECK15-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]] 3269 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 3270 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 3271 // CHECK15-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 3272 // CHECK15-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !3 3273 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3274 // CHECK15-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3275 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3276 // CHECK15-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0 3277 // CHECK15-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 3278 // CHECK15-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 3279 // CHECK15-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 3280 // CHECK15-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]] 3281 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3282 // CHECK15-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0 3283 // CHECK15-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 3284 // CHECK15-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 3285 // CHECK15-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 3286 // CHECK15-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 3287 // CHECK15-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]] 3288 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 3289 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 3290 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 3291 // CHECK15-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !3 3292 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !3 3293 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]] 3294 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP21]] 3295 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !3 3296 // CHECK15-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP22]] 3297 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !3 3298 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3299 // CHECK15: omp.body.continue: 3300 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3301 // CHECK15: omp.inner.for.inc: 3302 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3303 // CHECK15-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1 3304 // CHECK15-NEXT: store i64 [[ADD34]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3305 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3306 // CHECK15: omp.inner.for.end: 3307 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3308 // CHECK15-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0 3309 // CHECK15-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1 3310 // CHECK15-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1 3311 // CHECK15-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]] 3312 // CHECK15-NEXT: store i32 [[ADD38]], i32* [[I9]], align 4 3313 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3314 // CHECK15-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0 3315 // CHECK15-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 3316 // CHECK15-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 3317 // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 3318 // CHECK15-NEXT: store i32 [[ADD42]], i32* [[J10]], align 4 3319 // CHECK15-NEXT: br label [[SIMD_IF_END]] 3320 // CHECK15: simd.if.end: 3321 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 3322 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) 3323 // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3324 // CHECK15-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3325 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) 3326 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 3327 // CHECK15-NEXT: ret i32 [[TMP28]] 3328 // 3329 // 3330 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 3331 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 3332 // CHECK15-NEXT: entry: 3333 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3334 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 3335 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3336 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3337 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3338 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3339 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3340 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3341 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 3342 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3343 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3344 // CHECK15-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 3345 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3346 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3347 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3348 // CHECK15: omp.inner.for.cond: 3349 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3350 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 3351 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3352 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3353 // CHECK15: omp.inner.for.body: 3354 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3355 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 3356 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 3357 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3358 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 3359 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3360 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3361 // CHECK15-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 3362 // CHECK15-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 3363 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 3364 // CHECK15-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 3365 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 3366 // CHECK15-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !7 3367 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 3368 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP6]] 3369 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !7 3370 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 3371 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !7 3372 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3373 // CHECK15: omp.body.continue: 3374 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3375 // CHECK15: omp.inner.for.inc: 3376 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3377 // CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1 3378 // CHECK15-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3379 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3380 // CHECK15: omp.inner.for.end: 3381 // CHECK15-NEXT: store i32 10, i32* [[I]], align 4 3382 // CHECK15-NEXT: store i32 2, i32* [[J]], align 4 3383 // CHECK15-NEXT: ret i32 0 3384 // 3385 // 3386 // CHECK16-LABEL: define {{[^@]+}}@main 3387 // CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 3388 // CHECK16-NEXT: entry: 3389 // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3390 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3391 // CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 3392 // CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 3393 // CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 3394 // CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3395 // CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3396 // CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3397 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 3398 // CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3399 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3400 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3401 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 3402 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3403 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3404 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 3405 // CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 3406 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3407 // CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 3408 // CHECK16-NEXT: [[J10:%.*]] = alloca i32, align 4 3409 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 3410 // CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3411 // CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 3412 // CHECK16-NEXT: store i32 100, i32* [[N]], align 4 3413 // CHECK16-NEXT: store i32 2, i32* [[M]], align 4 3414 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 3415 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 3416 // CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3417 // CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3418 // CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 3419 // CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 3420 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 3421 // CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 3422 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 3423 // CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 3424 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[M]], align 4 3425 // CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3426 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3427 // CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 3428 // CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 3429 // CHECK16-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 3430 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3431 // CHECK16-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0 3432 // CHECK16-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 3433 // CHECK16-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 3434 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 3435 // CHECK16-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 3436 // CHECK16-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 3437 // CHECK16-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3438 // CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 3439 // CHECK16-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_UB]], align 8 3440 // CHECK16-NEXT: store i32 0, i32* [[I]], align 4 3441 // CHECK16-NEXT: store i32 0, i32* [[J]], align 4 3442 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3443 // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 3444 // CHECK16-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 3445 // CHECK16: land.lhs.true: 3446 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3447 // CHECK16-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]] 3448 // CHECK16-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 3449 // CHECK16: simd.if.then: 3450 // CHECK16-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3451 // CHECK16-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 3452 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3453 // CHECK16: omp.inner.for.cond: 3454 // CHECK16-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3455 // CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !3 3456 // CHECK16-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]] 3457 // CHECK16-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3458 // CHECK16: omp.inner.for.body: 3459 // CHECK16-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3460 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3461 // CHECK16-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0 3462 // CHECK16-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 3463 // CHECK16-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 3464 // CHECK16-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 3465 // CHECK16-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]] 3466 // CHECK16-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 3467 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 3468 // CHECK16-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 3469 // CHECK16-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !3 3470 // CHECK16-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3471 // CHECK16-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3472 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3473 // CHECK16-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0 3474 // CHECK16-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 3475 // CHECK16-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 3476 // CHECK16-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 3477 // CHECK16-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]] 3478 // CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3479 // CHECK16-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0 3480 // CHECK16-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 3481 // CHECK16-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 3482 // CHECK16-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 3483 // CHECK16-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 3484 // CHECK16-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]] 3485 // CHECK16-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 3486 // CHECK16-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 3487 // CHECK16-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 3488 // CHECK16-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !3 3489 // CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !3 3490 // CHECK16-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]] 3491 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP21]] 3492 // CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !3 3493 // CHECK16-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP22]] 3494 // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !3 3495 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3496 // CHECK16: omp.body.continue: 3497 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3498 // CHECK16: omp.inner.for.inc: 3499 // CHECK16-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3500 // CHECK16-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1 3501 // CHECK16-NEXT: store i64 [[ADD34]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3502 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3503 // CHECK16: omp.inner.for.end: 3504 // CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3505 // CHECK16-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0 3506 // CHECK16-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1 3507 // CHECK16-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1 3508 // CHECK16-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]] 3509 // CHECK16-NEXT: store i32 [[ADD38]], i32* [[I9]], align 4 3510 // CHECK16-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3511 // CHECK16-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0 3512 // CHECK16-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 3513 // CHECK16-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 3514 // CHECK16-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 3515 // CHECK16-NEXT: store i32 [[ADD42]], i32* [[J10]], align 4 3516 // CHECK16-NEXT: br label [[SIMD_IF_END]] 3517 // CHECK16: simd.if.end: 3518 // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 3519 // CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) 3520 // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3521 // CHECK16-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3522 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) 3523 // CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 3524 // CHECK16-NEXT: ret i32 [[TMP28]] 3525 // 3526 // 3527 // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 3528 // CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 3529 // CHECK16-NEXT: entry: 3530 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3531 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 3532 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 3533 // CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3534 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3535 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3536 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3537 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 3538 // CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 3539 // CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3540 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3541 // CHECK16-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 3542 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3543 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3544 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3545 // CHECK16: omp.inner.for.cond: 3546 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3547 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 3548 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3549 // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3550 // CHECK16: omp.inner.for.body: 3551 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3552 // CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 3553 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 3554 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3555 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 3556 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3557 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3558 // CHECK16-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 3559 // CHECK16-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 3560 // CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 3561 // CHECK16-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 3562 // CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 3563 // CHECK16-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !7 3564 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 3565 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP6]] 3566 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !7 3567 // CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 3568 // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !7 3569 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3570 // CHECK16: omp.body.continue: 3571 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3572 // CHECK16: omp.inner.for.inc: 3573 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3574 // CHECK16-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1 3575 // CHECK16-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3576 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3577 // CHECK16: omp.inner.for.end: 3578 // CHECK16-NEXT: store i32 10, i32* [[I]], align 4 3579 // CHECK16-NEXT: store i32 2, i32* [[J]], align 4 3580 // CHECK16-NEXT: ret i32 0 3581 // 3582