1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute private(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute private(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global, bound tid and loop vars 80 g = 1; 81 g1 = 1; 82 sivar = 2; 83 [&]() { 84 g = 2; 85 g1 = 2; 86 sivar = 4; 87 88 }(); 89 } 90 }(); 91 return 0; 92 #else 93 #pragma omp target 94 #pragma omp teams distribute private(t_var, vec, s_arr, var, sivar) 95 for (int i = 0; i < 2; ++i) { 96 vec[i] = t_var; 97 s_arr[i] = var; 98 sivar += i; 99 } 100 return tmain<int>(); 101 #endif 102 } 103 104 105 106 // Skip global, bound tid and loop vars 107 108 // private(s_arr) 109 110 // private(var) 111 112 113 114 115 116 // Skip global, bound tid and loop vars 117 118 // private(s_arr) 119 120 121 // private(var) 122 123 124 #endif 125 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 126 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 127 // CHECK1-NEXT: entry: 128 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 129 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 130 // CHECK1-NEXT: ret void 131 // 132 // 133 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 134 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 135 // CHECK1-NEXT: entry: 136 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 137 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 138 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 139 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 140 // CHECK1-NEXT: ret void 141 // 142 // 143 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 144 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 145 // CHECK1-NEXT: entry: 146 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 147 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 148 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 149 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 154 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 157 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 160 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 161 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 162 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 163 // CHECK1-NEXT: ret void 164 // 165 // 166 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 167 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 168 // CHECK1-NEXT: entry: 169 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 170 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 171 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 172 // CHECK1-NEXT: ret void 173 // 174 // 175 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 176 // CHECK1-SAME: () #[[ATTR0]] { 177 // CHECK1-NEXT: entry: 178 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 179 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 180 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 181 // CHECK1-NEXT: ret void 182 // 183 // 184 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 185 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 186 // CHECK1-NEXT: entry: 187 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 188 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 189 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 190 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 191 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 193 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 194 // CHECK1-NEXT: ret void 195 // 196 // 197 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 198 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 199 // CHECK1-NEXT: entry: 200 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 201 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 202 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 203 // CHECK1: arraydestroy.body: 204 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 205 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 206 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 207 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 208 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 209 // CHECK1: arraydestroy.done1: 210 // CHECK1-NEXT: ret void 211 // 212 // 213 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 214 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 215 // CHECK1-NEXT: entry: 216 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 217 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 218 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 219 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 220 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 221 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 222 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 223 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 224 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 225 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 226 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 227 // CHECK1-NEXT: ret void 228 // 229 // 230 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 231 // CHECK1-SAME: () #[[ATTR0]] { 232 // CHECK1-NEXT: entry: 233 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 234 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 235 // CHECK1-NEXT: ret void 236 // 237 // 238 // CHECK1-LABEL: define {{[^@]+}}@main 239 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 240 // CHECK1-NEXT: entry: 241 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 242 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 243 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 244 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 245 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 246 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 247 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 248 // CHECK1: omp_offload.failed: 249 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] 250 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 251 // CHECK1: omp_offload.cont: 252 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 253 // CHECK1-NEXT: ret i32 [[CALL]] 254 // 255 // 256 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 257 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 258 // CHECK1-NEXT: entry: 259 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 260 // CHECK1-NEXT: ret void 261 // 262 // 263 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 264 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 265 // CHECK1-NEXT: entry: 266 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 267 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 268 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 269 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 273 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 274 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 275 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 276 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 277 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 278 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 279 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 280 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 281 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 282 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 283 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 284 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 285 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 286 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 287 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 288 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 289 // CHECK1: arrayctor.loop: 290 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 291 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) 292 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 293 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 294 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 295 // CHECK1: arrayctor.cont: 296 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) 297 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 298 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 299 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 300 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 301 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 302 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 303 // CHECK1: cond.true: 304 // CHECK1-NEXT: br label [[COND_END:%.*]] 305 // CHECK1: cond.false: 306 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 307 // CHECK1-NEXT: br label [[COND_END]] 308 // CHECK1: cond.end: 309 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 310 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 311 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 312 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 313 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 314 // CHECK1: omp.inner.for.cond: 315 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 316 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 317 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 318 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 319 // CHECK1: omp.inner.for.cond.cleanup: 320 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 321 // CHECK1: omp.inner.for.body: 322 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 323 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 324 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 325 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 326 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 327 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 328 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 329 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 330 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 331 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 332 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 333 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 334 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 335 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 336 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) 337 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 338 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 339 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 340 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4 341 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 342 // CHECK1: omp.body.continue: 343 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 344 // CHECK1: omp.inner.for.inc: 345 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 346 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 347 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 348 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 349 // CHECK1: omp.inner.for.end: 350 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 351 // CHECK1: omp.loop.exit: 352 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 353 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 354 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 355 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] 356 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 357 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 358 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 359 // CHECK1: arraydestroy.body: 360 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 361 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 362 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 363 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 364 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 365 // CHECK1: arraydestroy.done7: 366 // CHECK1-NEXT: ret void 367 // 368 // 369 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 370 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 371 // CHECK1-NEXT: entry: 372 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 373 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 374 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 375 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 376 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 377 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 378 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 379 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 380 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 381 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 382 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 383 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 384 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 385 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 386 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 387 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 388 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 389 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 390 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 391 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 392 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 393 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 394 // CHECK1: omp_offload.failed: 395 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 396 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 397 // CHECK1: omp_offload.cont: 398 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 399 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 400 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 401 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 402 // CHECK1: arraydestroy.body: 403 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 404 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 405 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 406 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 407 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 408 // CHECK1: arraydestroy.done2: 409 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 410 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 411 // CHECK1-NEXT: ret i32 [[TMP4]] 412 // 413 // 414 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 415 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 416 // CHECK1-NEXT: entry: 417 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 418 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 419 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 420 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 421 // CHECK1-NEXT: ret void 422 // 423 // 424 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 425 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 426 // CHECK1-NEXT: entry: 427 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 428 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 429 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 430 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 431 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 432 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 433 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) 434 // CHECK1-NEXT: ret void 435 // 436 // 437 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 438 // CHECK1-SAME: () #[[ATTR4]] { 439 // CHECK1-NEXT: entry: 440 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 441 // CHECK1-NEXT: ret void 442 // 443 // 444 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 445 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 446 // CHECK1-NEXT: entry: 447 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 448 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 449 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 450 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 451 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 452 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 453 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 454 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 455 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 456 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 457 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 458 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 459 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 460 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 461 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 462 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 463 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 464 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 465 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 466 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 467 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 468 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 469 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 470 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 471 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 472 // CHECK1: arrayctor.loop: 473 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 474 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) 475 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 476 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 477 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 478 // CHECK1: arrayctor.cont: 479 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) 480 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 481 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 482 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 483 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 484 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 485 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 486 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 487 // CHECK1: cond.true: 488 // CHECK1-NEXT: br label [[COND_END:%.*]] 489 // CHECK1: cond.false: 490 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 491 // CHECK1-NEXT: br label [[COND_END]] 492 // CHECK1: cond.end: 493 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 494 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 495 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 496 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 497 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 498 // CHECK1: omp.inner.for.cond: 499 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 500 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 501 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 502 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 503 // CHECK1: omp.inner.for.cond.cleanup: 504 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 505 // CHECK1: omp.inner.for.body: 506 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 507 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 508 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 509 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 510 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 511 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 512 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 513 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 514 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 515 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 516 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 517 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 518 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] 519 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 520 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 521 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) 522 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 523 // CHECK1: omp.body.continue: 524 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 525 // CHECK1: omp.inner.for.inc: 526 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 527 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 528 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 529 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 530 // CHECK1: omp.inner.for.end: 531 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 532 // CHECK1: omp.loop.exit: 533 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 534 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 535 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 536 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] 537 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 538 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 539 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 540 // CHECK1: arraydestroy.body: 541 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 542 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 543 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 544 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 545 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 546 // CHECK1: arraydestroy.done8: 547 // CHECK1-NEXT: ret void 548 // 549 // 550 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 551 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 552 // CHECK1-NEXT: entry: 553 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 554 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 555 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 556 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 557 // CHECK1-NEXT: ret void 558 // 559 // 560 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 561 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 562 // CHECK1-NEXT: entry: 563 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 564 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 565 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 566 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 567 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 568 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 569 // CHECK1-NEXT: ret void 570 // 571 // 572 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 573 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 574 // CHECK1-NEXT: entry: 575 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 576 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 577 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 578 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 579 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 580 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 581 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 582 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 583 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 584 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 585 // CHECK1-NEXT: ret void 586 // 587 // 588 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 589 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 590 // CHECK1-NEXT: entry: 591 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 592 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 593 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 594 // CHECK1-NEXT: ret void 595 // 596 // 597 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp 598 // CHECK1-SAME: () #[[ATTR0]] { 599 // CHECK1-NEXT: entry: 600 // CHECK1-NEXT: call void @__cxx_global_var_init() 601 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 602 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 603 // CHECK1-NEXT: ret void 604 // 605 // 606 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 607 // CHECK1-SAME: () #[[ATTR0]] { 608 // CHECK1-NEXT: entry: 609 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 610 // CHECK1-NEXT: ret void 611 // 612 // 613 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 614 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 615 // CHECK2-NEXT: entry: 616 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 617 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 618 // CHECK2-NEXT: ret void 619 // 620 // 621 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 622 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 623 // CHECK2-NEXT: entry: 624 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 625 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 626 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 627 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 628 // CHECK2-NEXT: ret void 629 // 630 // 631 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 632 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 633 // CHECK2-NEXT: entry: 634 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 635 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 636 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 637 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 638 // CHECK2-NEXT: ret void 639 // 640 // 641 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 642 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 643 // CHECK2-NEXT: entry: 644 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 645 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 646 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 647 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 648 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 649 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 650 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 651 // CHECK2-NEXT: ret void 652 // 653 // 654 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 655 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 656 // CHECK2-NEXT: entry: 657 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 658 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 659 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 660 // CHECK2-NEXT: ret void 661 // 662 // 663 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 664 // CHECK2-SAME: () #[[ATTR0]] { 665 // CHECK2-NEXT: entry: 666 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 667 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 668 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 669 // CHECK2-NEXT: ret void 670 // 671 // 672 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 673 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 674 // CHECK2-NEXT: entry: 675 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 676 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 677 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 678 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 679 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 680 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 681 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 682 // CHECK2-NEXT: ret void 683 // 684 // 685 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 686 // CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 687 // CHECK2-NEXT: entry: 688 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 689 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 690 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 691 // CHECK2: arraydestroy.body: 692 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 693 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 694 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 695 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 696 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 697 // CHECK2: arraydestroy.done1: 698 // CHECK2-NEXT: ret void 699 // 700 // 701 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 702 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 703 // CHECK2-NEXT: entry: 704 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 705 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 706 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 707 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 708 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 709 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 710 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 711 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 712 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 713 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 714 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 715 // CHECK2-NEXT: ret void 716 // 717 // 718 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 719 // CHECK2-SAME: () #[[ATTR0]] { 720 // CHECK2-NEXT: entry: 721 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 722 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 723 // CHECK2-NEXT: ret void 724 // 725 // 726 // CHECK2-LABEL: define {{[^@]+}}@main 727 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 728 // CHECK2-NEXT: entry: 729 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 730 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 731 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 732 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 733 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 734 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 735 // CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 736 // CHECK2: omp_offload.failed: 737 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] 738 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 739 // CHECK2: omp_offload.cont: 740 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 741 // CHECK2-NEXT: ret i32 [[CALL]] 742 // 743 // 744 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 745 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { 746 // CHECK2-NEXT: entry: 747 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 748 // CHECK2-NEXT: ret void 749 // 750 // 751 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 752 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 753 // CHECK2-NEXT: entry: 754 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 755 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 756 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 757 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 758 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 759 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 760 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 761 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 762 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 763 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 764 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 765 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 766 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 767 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 768 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 769 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 770 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 771 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 772 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 773 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 774 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 775 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 776 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 777 // CHECK2: arrayctor.loop: 778 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 779 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) 780 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 781 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 782 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 783 // CHECK2: arrayctor.cont: 784 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) 785 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 786 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 787 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 788 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 789 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 790 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 791 // CHECK2: cond.true: 792 // CHECK2-NEXT: br label [[COND_END:%.*]] 793 // CHECK2: cond.false: 794 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 795 // CHECK2-NEXT: br label [[COND_END]] 796 // CHECK2: cond.end: 797 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 798 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 799 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 800 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 801 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 802 // CHECK2: omp.inner.for.cond: 803 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 804 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 805 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 806 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 807 // CHECK2: omp.inner.for.cond.cleanup: 808 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 809 // CHECK2: omp.inner.for.body: 810 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 811 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 812 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 813 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 814 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 815 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 816 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 817 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 818 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 819 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 820 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 821 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 822 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 823 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 824 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) 825 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 826 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 827 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 828 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4 829 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 830 // CHECK2: omp.body.continue: 831 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 832 // CHECK2: omp.inner.for.inc: 833 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 834 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 835 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 836 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 837 // CHECK2: omp.inner.for.end: 838 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 839 // CHECK2: omp.loop.exit: 840 // CHECK2-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 841 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 842 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 843 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] 844 // CHECK2-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 845 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2 846 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 847 // CHECK2: arraydestroy.body: 848 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 849 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 850 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 851 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 852 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 853 // CHECK2: arraydestroy.done7: 854 // CHECK2-NEXT: ret void 855 // 856 // 857 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 858 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat { 859 // CHECK2-NEXT: entry: 860 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 861 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 862 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 863 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 864 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 865 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 866 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 867 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 868 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 869 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 870 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 871 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 872 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 873 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 874 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 875 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 876 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 877 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 878 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 879 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 880 // CHECK2-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 881 // CHECK2-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 882 // CHECK2: omp_offload.failed: 883 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 884 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 885 // CHECK2: omp_offload.cont: 886 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 887 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 888 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 889 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 890 // CHECK2: arraydestroy.body: 891 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 892 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 893 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 894 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 895 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 896 // CHECK2: arraydestroy.done2: 897 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 898 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 899 // CHECK2-NEXT: ret i32 [[TMP4]] 900 // 901 // 902 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 903 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 904 // CHECK2-NEXT: entry: 905 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 906 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 907 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 908 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 909 // CHECK2-NEXT: ret void 910 // 911 // 912 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 913 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 914 // CHECK2-NEXT: entry: 915 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 916 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 917 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 918 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 919 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 920 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 921 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) 922 // CHECK2-NEXT: ret void 923 // 924 // 925 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 926 // CHECK2-SAME: () #[[ATTR4]] { 927 // CHECK2-NEXT: entry: 928 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 929 // CHECK2-NEXT: ret void 930 // 931 // 932 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 933 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 934 // CHECK2-NEXT: entry: 935 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 936 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 937 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 938 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 939 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 940 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 941 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 942 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 943 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 944 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 945 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 946 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 947 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 948 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 949 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 950 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 951 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 952 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 953 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 954 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 955 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 956 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 957 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 958 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 959 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 960 // CHECK2: arrayctor.loop: 961 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 962 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) 963 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 964 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 965 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 966 // CHECK2: arrayctor.cont: 967 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) 968 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 969 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 970 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 971 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 972 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 973 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 974 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 975 // CHECK2: cond.true: 976 // CHECK2-NEXT: br label [[COND_END:%.*]] 977 // CHECK2: cond.false: 978 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 979 // CHECK2-NEXT: br label [[COND_END]] 980 // CHECK2: cond.end: 981 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 982 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 983 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 984 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 985 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 986 // CHECK2: omp.inner.for.cond: 987 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 988 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 989 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 990 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 991 // CHECK2: omp.inner.for.cond.cleanup: 992 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 993 // CHECK2: omp.inner.for.body: 994 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 995 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 996 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 997 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 998 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 999 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1000 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 1001 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 1002 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1003 // CHECK2-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8 1004 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1005 // CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 1006 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]] 1007 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 1008 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1009 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false) 1010 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1011 // CHECK2: omp.body.continue: 1012 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1013 // CHECK2: omp.inner.for.inc: 1014 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1015 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 1016 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 1017 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1018 // CHECK2: omp.inner.for.end: 1019 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1020 // CHECK2: omp.loop.exit: 1021 // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1022 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 1023 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 1024 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] 1025 // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1026 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 1027 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1028 // CHECK2: arraydestroy.body: 1029 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1030 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1031 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1032 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1033 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1034 // CHECK2: arraydestroy.done8: 1035 // CHECK2-NEXT: ret void 1036 // 1037 // 1038 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1039 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1040 // CHECK2-NEXT: entry: 1041 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1042 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1043 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1044 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 1045 // CHECK2-NEXT: ret void 1046 // 1047 // 1048 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1049 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1050 // CHECK2-NEXT: entry: 1051 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1052 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1053 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1054 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1055 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1056 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1057 // CHECK2-NEXT: ret void 1058 // 1059 // 1060 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1061 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1062 // CHECK2-NEXT: entry: 1063 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1064 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1065 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1066 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1067 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1068 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1069 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1070 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1071 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1072 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1073 // CHECK2-NEXT: ret void 1074 // 1075 // 1076 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1077 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1078 // CHECK2-NEXT: entry: 1079 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1080 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1081 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1082 // CHECK2-NEXT: ret void 1083 // 1084 // 1085 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp 1086 // CHECK2-SAME: () #[[ATTR0]] { 1087 // CHECK2-NEXT: entry: 1088 // CHECK2-NEXT: call void @__cxx_global_var_init() 1089 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 1090 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 1091 // CHECK2-NEXT: ret void 1092 // 1093 // 1094 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1095 // CHECK2-SAME: () #[[ATTR0]] { 1096 // CHECK2-NEXT: entry: 1097 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1098 // CHECK2-NEXT: ret void 1099 // 1100 // 1101 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1102 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1103 // CHECK3-NEXT: entry: 1104 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 1105 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1106 // CHECK3-NEXT: ret void 1107 // 1108 // 1109 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1110 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1111 // CHECK3-NEXT: entry: 1112 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1113 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1114 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1115 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 1116 // CHECK3-NEXT: ret void 1117 // 1118 // 1119 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1120 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1121 // CHECK3-NEXT: entry: 1122 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1123 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1124 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1125 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 1126 // CHECK3-NEXT: ret void 1127 // 1128 // 1129 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1130 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1131 // CHECK3-NEXT: entry: 1132 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1133 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1134 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1135 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1136 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1137 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1138 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 1139 // CHECK3-NEXT: ret void 1140 // 1141 // 1142 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1143 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1144 // CHECK3-NEXT: entry: 1145 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1146 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1147 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1148 // CHECK3-NEXT: ret void 1149 // 1150 // 1151 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1152 // CHECK3-SAME: () #[[ATTR0]] { 1153 // CHECK3-NEXT: entry: 1154 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 1155 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 1156 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1157 // CHECK3-NEXT: ret void 1158 // 1159 // 1160 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1161 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1162 // CHECK3-NEXT: entry: 1163 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1164 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1165 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1166 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1167 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1168 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1169 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 1170 // CHECK3-NEXT: ret void 1171 // 1172 // 1173 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1174 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1175 // CHECK3-NEXT: entry: 1176 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1177 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1178 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1179 // CHECK3: arraydestroy.body: 1180 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1181 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1182 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1183 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1184 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1185 // CHECK3: arraydestroy.done1: 1186 // CHECK3-NEXT: ret void 1187 // 1188 // 1189 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1190 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1191 // CHECK3-NEXT: entry: 1192 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1193 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1194 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1195 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1196 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1197 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1198 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1199 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1200 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1201 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1202 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1203 // CHECK3-NEXT: ret void 1204 // 1205 // 1206 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1207 // CHECK3-SAME: () #[[ATTR0]] { 1208 // CHECK3-NEXT: entry: 1209 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 1210 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1211 // CHECK3-NEXT: ret void 1212 // 1213 // 1214 // CHECK3-LABEL: define {{[^@]+}}@main 1215 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1216 // CHECK3-NEXT: entry: 1217 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1218 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1219 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1220 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1221 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1222 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 1223 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1224 // CHECK3: omp_offload.failed: 1225 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] 1226 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1227 // CHECK3: omp_offload.cont: 1228 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1229 // CHECK3-NEXT: ret i32 [[CALL]] 1230 // 1231 // 1232 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 1233 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 1234 // CHECK3-NEXT: entry: 1235 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1236 // CHECK3-NEXT: ret void 1237 // 1238 // 1239 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1240 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1241 // CHECK3-NEXT: entry: 1242 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1243 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1244 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1245 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1246 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1247 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1248 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1249 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1250 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1251 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1252 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1253 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1254 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1255 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1256 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1257 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1258 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1259 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1260 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1261 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1262 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1263 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1264 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1265 // CHECK3: arrayctor.loop: 1266 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1267 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) 1268 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1269 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1270 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1271 // CHECK3: arrayctor.cont: 1272 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) 1273 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1274 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1275 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1276 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1277 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1278 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1279 // CHECK3: cond.true: 1280 // CHECK3-NEXT: br label [[COND_END:%.*]] 1281 // CHECK3: cond.false: 1282 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1283 // CHECK3-NEXT: br label [[COND_END]] 1284 // CHECK3: cond.end: 1285 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1286 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1287 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1288 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1289 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1290 // CHECK3: omp.inner.for.cond: 1291 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1292 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1293 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1294 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1295 // CHECK3: omp.inner.for.cond.cleanup: 1296 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1297 // CHECK3: omp.inner.for.body: 1298 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1299 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1300 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1301 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1302 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1303 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1304 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1305 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1306 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 1307 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]] 1308 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1309 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1310 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) 1311 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1312 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 1313 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 1314 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 1315 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1316 // CHECK3: omp.body.continue: 1317 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1318 // CHECK3: omp.inner.for.inc: 1319 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1320 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 1321 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1322 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1323 // CHECK3: omp.inner.for.end: 1324 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1325 // CHECK3: omp.loop.exit: 1326 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1327 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 1328 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 1329 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] 1330 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1331 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 1332 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1333 // CHECK3: arraydestroy.body: 1334 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1335 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1336 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1337 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1338 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1339 // CHECK3: arraydestroy.done6: 1340 // CHECK3-NEXT: ret void 1341 // 1342 // 1343 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1344 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 1345 // CHECK3-NEXT: entry: 1346 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1347 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1348 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1349 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1350 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1351 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1352 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1353 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1354 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 1355 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 1356 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1357 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1358 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1359 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) 1360 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1361 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1362 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1363 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1364 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 1365 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1366 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1367 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1368 // CHECK3: omp_offload.failed: 1369 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1370 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1371 // CHECK3: omp_offload.cont: 1372 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1373 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1374 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1375 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1376 // CHECK3: arraydestroy.body: 1377 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1378 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1379 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1380 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1381 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1382 // CHECK3: arraydestroy.done2: 1383 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 1384 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1385 // CHECK3-NEXT: ret i32 [[TMP4]] 1386 // 1387 // 1388 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1389 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1390 // CHECK3-NEXT: entry: 1391 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1392 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1393 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1394 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 1395 // CHECK3-NEXT: ret void 1396 // 1397 // 1398 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1399 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1400 // CHECK3-NEXT: entry: 1401 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1402 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1403 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1404 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1405 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1406 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1407 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) 1408 // CHECK3-NEXT: ret void 1409 // 1410 // 1411 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1412 // CHECK3-SAME: () #[[ATTR4]] { 1413 // CHECK3-NEXT: entry: 1414 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 1415 // CHECK3-NEXT: ret void 1416 // 1417 // 1418 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 1419 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1420 // CHECK3-NEXT: entry: 1421 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1422 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1423 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1424 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1425 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1426 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1427 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1428 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1429 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1430 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1431 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1432 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1433 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1434 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 1435 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1436 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1437 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1438 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1439 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1440 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1441 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1442 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1443 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1444 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1445 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1446 // CHECK3: arrayctor.loop: 1447 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1448 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) 1449 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 1450 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1451 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1452 // CHECK3: arrayctor.cont: 1453 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) 1454 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 1455 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1456 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1457 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1458 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1459 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1460 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1461 // CHECK3: cond.true: 1462 // CHECK3-NEXT: br label [[COND_END:%.*]] 1463 // CHECK3: cond.false: 1464 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1465 // CHECK3-NEXT: br label [[COND_END]] 1466 // CHECK3: cond.end: 1467 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1468 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1469 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1470 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1471 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1472 // CHECK3: omp.inner.for.cond: 1473 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1474 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1475 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1476 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1477 // CHECK3: omp.inner.for.cond.cleanup: 1478 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1479 // CHECK3: omp.inner.for.body: 1480 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1481 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1482 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1483 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1484 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1485 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1486 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1487 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1488 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 1489 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1490 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 1491 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1492 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1493 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) 1494 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1495 // CHECK3: omp.body.continue: 1496 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1497 // CHECK3: omp.inner.for.inc: 1498 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1499 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1500 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 1501 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1502 // CHECK3: omp.inner.for.end: 1503 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1504 // CHECK3: omp.loop.exit: 1505 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1506 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 1507 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 1508 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] 1509 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1510 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 1511 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1512 // CHECK3: arraydestroy.body: 1513 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1514 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1515 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1516 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1517 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1518 // CHECK3: arraydestroy.done7: 1519 // CHECK3-NEXT: ret void 1520 // 1521 // 1522 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1523 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1524 // CHECK3-NEXT: entry: 1525 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1526 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1527 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1528 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 1529 // CHECK3-NEXT: ret void 1530 // 1531 // 1532 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1533 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1534 // CHECK3-NEXT: entry: 1535 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1536 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1537 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1538 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1539 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1540 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1541 // CHECK3-NEXT: ret void 1542 // 1543 // 1544 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1545 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1546 // CHECK3-NEXT: entry: 1547 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1548 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1549 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1550 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1551 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1552 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1553 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1554 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1555 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1556 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1557 // CHECK3-NEXT: ret void 1558 // 1559 // 1560 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1561 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1562 // CHECK3-NEXT: entry: 1563 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1564 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1565 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1566 // CHECK3-NEXT: ret void 1567 // 1568 // 1569 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp 1570 // CHECK3-SAME: () #[[ATTR0]] { 1571 // CHECK3-NEXT: entry: 1572 // CHECK3-NEXT: call void @__cxx_global_var_init() 1573 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1574 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1575 // CHECK3-NEXT: ret void 1576 // 1577 // 1578 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1579 // CHECK3-SAME: () #[[ATTR0]] { 1580 // CHECK3-NEXT: entry: 1581 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1582 // CHECK3-NEXT: ret void 1583 // 1584 // 1585 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 1586 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 1587 // CHECK4-NEXT: entry: 1588 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 1589 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1590 // CHECK4-NEXT: ret void 1591 // 1592 // 1593 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1594 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1595 // CHECK4-NEXT: entry: 1596 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1597 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1598 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1599 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 1600 // CHECK4-NEXT: ret void 1601 // 1602 // 1603 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1604 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1605 // CHECK4-NEXT: entry: 1606 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1607 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1608 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1609 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 1610 // CHECK4-NEXT: ret void 1611 // 1612 // 1613 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1614 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1615 // CHECK4-NEXT: entry: 1616 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1617 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1618 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1619 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1620 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1621 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1622 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4 1623 // CHECK4-NEXT: ret void 1624 // 1625 // 1626 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1627 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1628 // CHECK4-NEXT: entry: 1629 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1630 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1631 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1632 // CHECK4-NEXT: ret void 1633 // 1634 // 1635 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1636 // CHECK4-SAME: () #[[ATTR0]] { 1637 // CHECK4-NEXT: entry: 1638 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 1639 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 1640 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1641 // CHECK4-NEXT: ret void 1642 // 1643 // 1644 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1645 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1646 // CHECK4-NEXT: entry: 1647 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1648 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1649 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1650 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1651 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1652 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1653 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 1654 // CHECK4-NEXT: ret void 1655 // 1656 // 1657 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1658 // CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1659 // CHECK4-NEXT: entry: 1660 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1661 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1662 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1663 // CHECK4: arraydestroy.body: 1664 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1665 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1666 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1667 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1668 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1669 // CHECK4: arraydestroy.done1: 1670 // CHECK4-NEXT: ret void 1671 // 1672 // 1673 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1674 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1675 // CHECK4-NEXT: entry: 1676 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1677 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1678 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1679 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1680 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1681 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1682 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1683 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1684 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1685 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1686 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 1687 // CHECK4-NEXT: ret void 1688 // 1689 // 1690 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1691 // CHECK4-SAME: () #[[ATTR0]] { 1692 // CHECK4-NEXT: entry: 1693 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 1694 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1695 // CHECK4-NEXT: ret void 1696 // 1697 // 1698 // CHECK4-LABEL: define {{[^@]+}}@main 1699 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 1700 // CHECK4-NEXT: entry: 1701 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1702 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1703 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 1704 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1705 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1706 // CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 1707 // CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1708 // CHECK4: omp_offload.failed: 1709 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93() #[[ATTR2]] 1710 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1711 // CHECK4: omp_offload.cont: 1712 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1713 // CHECK4-NEXT: ret i32 [[CALL]] 1714 // 1715 // 1716 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l93 1717 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] { 1718 // CHECK4-NEXT: entry: 1719 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1720 // CHECK4-NEXT: ret void 1721 // 1722 // 1723 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 1724 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1725 // CHECK4-NEXT: entry: 1726 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1727 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1728 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1729 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1730 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1731 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1732 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1733 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1734 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1735 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1736 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1737 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1738 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1739 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1740 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1741 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1742 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1743 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1744 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1745 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1746 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1747 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1748 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1749 // CHECK4: arrayctor.loop: 1750 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1751 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[ARRAYCTOR_CUR]]) 1752 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1753 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1754 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1755 // CHECK4: arrayctor.cont: 1756 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef [[VAR]]) 1757 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1758 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1759 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1760 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1761 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1762 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1763 // CHECK4: cond.true: 1764 // CHECK4-NEXT: br label [[COND_END:%.*]] 1765 // CHECK4: cond.false: 1766 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1767 // CHECK4-NEXT: br label [[COND_END]] 1768 // CHECK4: cond.end: 1769 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1770 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1771 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1772 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1773 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1774 // CHECK4: omp.inner.for.cond: 1775 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1776 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1777 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1778 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1779 // CHECK4: omp.inner.for.cond.cleanup: 1780 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1781 // CHECK4: omp.inner.for.body: 1782 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1783 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1784 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1785 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1786 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1787 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1788 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1789 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1790 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4 1791 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]] 1792 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1793 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1794 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) 1795 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1796 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4 1797 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] 1798 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 1799 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1800 // CHECK4: omp.body.continue: 1801 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1802 // CHECK4: omp.inner.for.inc: 1803 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1804 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 1805 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1806 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 1807 // CHECK4: omp.inner.for.end: 1808 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1809 // CHECK4: omp.loop.exit: 1810 // CHECK4-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1811 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 1812 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]]) 1813 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR]]) #[[ATTR2]] 1814 // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1815 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 1816 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1817 // CHECK4: arraydestroy.body: 1818 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1819 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1820 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1821 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1822 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1823 // CHECK4: arraydestroy.done6: 1824 // CHECK4-NEXT: ret void 1825 // 1826 // 1827 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1828 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat { 1829 // CHECK4-NEXT: entry: 1830 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1831 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1832 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1833 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1834 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1835 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1836 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1837 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1838 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 1839 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 1840 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1841 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1842 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1843 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) 1844 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1845 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1846 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1847 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1848 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 1849 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1850 // CHECK4-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1851 // CHECK4-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1852 // CHECK4: omp_offload.failed: 1853 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1854 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1855 // CHECK4: omp_offload.cont: 1856 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 1857 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1858 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1859 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1860 // CHECK4: arraydestroy.body: 1861 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1862 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1863 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1864 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1865 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1866 // CHECK4: arraydestroy.done2: 1867 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 1868 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1869 // CHECK4-NEXT: ret i32 [[TMP4]] 1870 // 1871 // 1872 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1873 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1874 // CHECK4-NEXT: entry: 1875 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1876 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1877 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1878 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 1879 // CHECK4-NEXT: ret void 1880 // 1881 // 1882 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1883 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1884 // CHECK4-NEXT: entry: 1885 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1886 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1887 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1888 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1889 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1890 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1891 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) 1892 // CHECK4-NEXT: ret void 1893 // 1894 // 1895 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1896 // CHECK4-SAME: () #[[ATTR4]] { 1897 // CHECK4-NEXT: entry: 1898 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*)) 1899 // CHECK4-NEXT: ret void 1900 // 1901 // 1902 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 1903 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1904 // CHECK4-NEXT: entry: 1905 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1906 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1907 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1908 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1909 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1910 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1911 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1912 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1913 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1914 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1915 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1916 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1917 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1918 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 1919 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1920 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1921 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1922 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1923 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1924 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1925 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1926 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1927 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1928 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1929 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1930 // CHECK4: arrayctor.loop: 1931 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1932 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[ARRAYCTOR_CUR]]) 1933 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 1934 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1935 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1936 // CHECK4: arrayctor.cont: 1937 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[VAR]]) 1938 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 1939 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1940 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1941 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1942 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1943 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1944 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1945 // CHECK4: cond.true: 1946 // CHECK4-NEXT: br label [[COND_END:%.*]] 1947 // CHECK4: cond.false: 1948 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1949 // CHECK4-NEXT: br label [[COND_END]] 1950 // CHECK4: cond.end: 1951 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1952 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1953 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1954 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1955 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1956 // CHECK4: omp.inner.for.cond: 1957 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1958 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1959 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1960 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1961 // CHECK4: omp.inner.for.cond.cleanup: 1962 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1963 // CHECK4: omp.inner.for.body: 1964 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1965 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1966 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1967 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1968 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1969 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 1970 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 1971 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4 1972 // CHECK4-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 1973 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1974 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 1975 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1976 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1977 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false) 1978 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1979 // CHECK4: omp.body.continue: 1980 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1981 // CHECK4: omp.inner.for.inc: 1982 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1983 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 1984 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 1985 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 1986 // CHECK4: omp.inner.for.end: 1987 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1988 // CHECK4: omp.loop.exit: 1989 // CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1990 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 1991 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]]) 1992 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR]]) #[[ATTR2]] 1993 // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1994 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 1995 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1996 // CHECK4: arraydestroy.body: 1997 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1998 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1999 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2000 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 2001 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 2002 // CHECK4: arraydestroy.done7: 2003 // CHECK4-NEXT: ret void 2004 // 2005 // 2006 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2007 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2008 // CHECK4-NEXT: entry: 2009 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2010 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2011 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2012 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 2013 // CHECK4-NEXT: ret void 2014 // 2015 // 2016 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2017 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2018 // CHECK4-NEXT: entry: 2019 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2020 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2021 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2022 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2023 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2024 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2025 // CHECK4-NEXT: ret void 2026 // 2027 // 2028 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2029 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2030 // CHECK4-NEXT: entry: 2031 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2032 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2033 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2034 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2035 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2036 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2037 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2038 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2039 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2040 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2041 // CHECK4-NEXT: ret void 2042 // 2043 // 2044 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2045 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2046 // CHECK4-NEXT: entry: 2047 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2048 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2049 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2050 // CHECK4-NEXT: ret void 2051 // 2052 // 2053 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp 2054 // CHECK4-SAME: () #[[ATTR0]] { 2055 // CHECK4-NEXT: entry: 2056 // CHECK4-NEXT: call void @__cxx_global_var_init() 2057 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 2058 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 2059 // CHECK4-NEXT: ret void 2060 // 2061 // 2062 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2063 // CHECK4-SAME: () #[[ATTR0]] { 2064 // CHECK4-NEXT: entry: 2065 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 2066 // CHECK4-NEXT: ret void 2067 // 2068 // 2069 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 2070 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2071 // CHECK9-NEXT: entry: 2072 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 2073 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2074 // CHECK9-NEXT: ret void 2075 // 2076 // 2077 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2078 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2079 // CHECK9-NEXT: entry: 2080 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2081 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2082 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2083 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 2084 // CHECK9-NEXT: ret void 2085 // 2086 // 2087 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2088 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2089 // CHECK9-NEXT: entry: 2090 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2091 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2092 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2093 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 2094 // CHECK9-NEXT: ret void 2095 // 2096 // 2097 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2098 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2099 // CHECK9-NEXT: entry: 2100 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2101 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2102 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2103 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2104 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2105 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2106 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 2107 // CHECK9-NEXT: ret void 2108 // 2109 // 2110 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2111 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2112 // CHECK9-NEXT: entry: 2113 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2114 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2115 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2116 // CHECK9-NEXT: ret void 2117 // 2118 // 2119 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2120 // CHECK9-SAME: () #[[ATTR0]] { 2121 // CHECK9-NEXT: entry: 2122 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 2123 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 2124 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2125 // CHECK9-NEXT: ret void 2126 // 2127 // 2128 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2129 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2130 // CHECK9-NEXT: entry: 2131 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2132 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2133 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2134 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2135 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2136 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2137 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 2138 // CHECK9-NEXT: ret void 2139 // 2140 // 2141 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2142 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2143 // CHECK9-NEXT: entry: 2144 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2145 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2146 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2147 // CHECK9: arraydestroy.body: 2148 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2149 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2150 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2151 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2152 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2153 // CHECK9: arraydestroy.done1: 2154 // CHECK9-NEXT: ret void 2155 // 2156 // 2157 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2158 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2159 // CHECK9-NEXT: entry: 2160 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2161 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2162 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2163 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2164 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2165 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2166 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2167 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2168 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2169 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2170 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 2171 // CHECK9-NEXT: ret void 2172 // 2173 // 2174 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2175 // CHECK9-SAME: () #[[ATTR0]] { 2176 // CHECK9-NEXT: entry: 2177 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 2178 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2179 // CHECK9-NEXT: ret void 2180 // 2181 // 2182 // CHECK9-LABEL: define {{[^@]+}}@main 2183 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2184 // CHECK9-NEXT: entry: 2185 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2186 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2187 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 2188 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 2189 // CHECK9-NEXT: ret i32 0 2190 // 2191 // 2192 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 2193 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 2194 // CHECK9-NEXT: entry: 2195 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2196 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2197 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 2198 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 2199 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 2200 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2201 // CHECK9-NEXT: ret void 2202 // 2203 // 2204 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2205 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 2206 // CHECK9-NEXT: entry: 2207 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2208 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2209 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2210 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 2211 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 2212 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2213 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2214 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2215 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2216 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 2217 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 2218 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 2219 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2220 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2221 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2222 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2223 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2224 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 2225 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2226 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2227 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2228 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2229 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 2230 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2231 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2232 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2233 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2234 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2235 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2236 // CHECK9: cond.true: 2237 // CHECK9-NEXT: br label [[COND_END:%.*]] 2238 // CHECK9: cond.false: 2239 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2240 // CHECK9-NEXT: br label [[COND_END]] 2241 // CHECK9: cond.end: 2242 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2243 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2244 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2245 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2246 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2247 // CHECK9: omp.inner.for.cond: 2248 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2249 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2250 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2251 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2252 // CHECK9: omp.inner.for.body: 2253 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2254 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2255 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2256 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2257 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4 2258 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 2259 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 2260 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 2261 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 2262 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 2263 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 2264 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 2265 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 2266 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 2267 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 2268 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) 2269 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2270 // CHECK9: omp.body.continue: 2271 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2272 // CHECK9: omp.inner.for.inc: 2273 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2274 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 2275 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 2276 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 2277 // CHECK9: omp.inner.for.end: 2278 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2279 // CHECK9: omp.loop.exit: 2280 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2281 // CHECK9-NEXT: ret void 2282 // 2283 // 2284 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp 2285 // CHECK9-SAME: () #[[ATTR0]] { 2286 // CHECK9-NEXT: entry: 2287 // CHECK9-NEXT: call void @__cxx_global_var_init() 2288 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2289 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2290 // CHECK9-NEXT: ret void 2291 // 2292 // 2293 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2294 // CHECK9-SAME: () #[[ATTR0]] { 2295 // CHECK9-NEXT: entry: 2296 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 2297 // CHECK9-NEXT: ret void 2298 // 2299 // 2300 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init 2301 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 2302 // CHECK10-NEXT: entry: 2303 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 2304 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2305 // CHECK10-NEXT: ret void 2306 // 2307 // 2308 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2309 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2310 // CHECK10-NEXT: entry: 2311 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2312 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2313 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2314 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 2315 // CHECK10-NEXT: ret void 2316 // 2317 // 2318 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2319 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2320 // CHECK10-NEXT: entry: 2321 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2322 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2323 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2324 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 2325 // CHECK10-NEXT: ret void 2326 // 2327 // 2328 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2329 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2330 // CHECK10-NEXT: entry: 2331 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2332 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2333 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2334 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2335 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2336 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2337 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 2338 // CHECK10-NEXT: ret void 2339 // 2340 // 2341 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2342 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2343 // CHECK10-NEXT: entry: 2344 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2345 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2346 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2347 // CHECK10-NEXT: ret void 2348 // 2349 // 2350 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2351 // CHECK10-SAME: () #[[ATTR0]] { 2352 // CHECK10-NEXT: entry: 2353 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 2354 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 2355 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2356 // CHECK10-NEXT: ret void 2357 // 2358 // 2359 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2360 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2361 // CHECK10-NEXT: entry: 2362 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2363 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2364 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2365 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2366 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2367 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2368 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 2369 // CHECK10-NEXT: ret void 2370 // 2371 // 2372 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2373 // CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2374 // CHECK10-NEXT: entry: 2375 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2376 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2377 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2378 // CHECK10: arraydestroy.body: 2379 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2380 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2381 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2382 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2383 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2384 // CHECK10: arraydestroy.done1: 2385 // CHECK10-NEXT: ret void 2386 // 2387 // 2388 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2389 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2390 // CHECK10-NEXT: entry: 2391 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2392 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2393 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2394 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2395 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2396 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2397 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2398 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2399 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2400 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2401 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 2402 // CHECK10-NEXT: ret void 2403 // 2404 // 2405 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2406 // CHECK10-SAME: () #[[ATTR0]] { 2407 // CHECK10-NEXT: entry: 2408 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 2409 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2410 // CHECK10-NEXT: ret void 2411 // 2412 // 2413 // CHECK10-LABEL: define {{[^@]+}}@main 2414 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 2415 // CHECK10-NEXT: entry: 2416 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2417 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2418 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 2419 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 2420 // CHECK10-NEXT: ret i32 0 2421 // 2422 // 2423 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 2424 // CHECK10-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 2425 // CHECK10-NEXT: entry: 2426 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2427 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2428 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 2429 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 2430 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 2431 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2432 // CHECK10-NEXT: ret void 2433 // 2434 // 2435 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 2436 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 2437 // CHECK10-NEXT: entry: 2438 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2439 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2440 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2441 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 2442 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 2443 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2444 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2445 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2446 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2447 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4 2448 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4 2449 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 2450 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2451 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 2452 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2453 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2454 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2455 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8 2456 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2457 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2458 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2459 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2460 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 2461 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2462 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2463 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2464 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2465 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2466 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2467 // CHECK10: cond.true: 2468 // CHECK10-NEXT: br label [[COND_END:%.*]] 2469 // CHECK10: cond.false: 2470 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2471 // CHECK10-NEXT: br label [[COND_END]] 2472 // CHECK10: cond.end: 2473 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2474 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2475 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2476 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2477 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2478 // CHECK10: omp.inner.for.cond: 2479 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2480 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2481 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2482 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2483 // CHECK10: omp.inner.for.body: 2484 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2485 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2486 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2487 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2488 // CHECK10-NEXT: store i32 1, i32* [[G]], align 4 2489 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8 2490 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 2491 // CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4 2492 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 2493 // CHECK10-NEXT: store i32* [[G]], i32** [[TMP9]], align 8 2494 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 2495 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8 2496 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 2497 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 2498 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8 2499 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]) 2500 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2501 // CHECK10: omp.body.continue: 2502 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2503 // CHECK10: omp.inner.for.inc: 2504 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2505 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 2506 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 2507 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 2508 // CHECK10: omp.inner.for.end: 2509 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2510 // CHECK10: omp.loop.exit: 2511 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2512 // CHECK10-NEXT: ret void 2513 // 2514 // 2515 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_private_codegen.cpp 2516 // CHECK10-SAME: () #[[ATTR0]] { 2517 // CHECK10-NEXT: entry: 2518 // CHECK10-NEXT: call void @__cxx_global_var_init() 2519 // CHECK10-NEXT: call void @__cxx_global_var_init.1() 2520 // CHECK10-NEXT: call void @__cxx_global_var_init.2() 2521 // CHECK10-NEXT: ret void 2522 // 2523 // 2524 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2525 // CHECK10-SAME: () #[[ATTR0]] { 2526 // CHECK10-NEXT: entry: 2527 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 2528 // CHECK10-NEXT: ret void 2529 // 2530