1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute parallel for private(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute parallel for private(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global, bound tid and loop vars 80 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 85 // Skip global, bound tid and loop vars 86 [&]() { 87 g = 2; 88 g1 = 2; 89 sivar = 4; 90 91 }(); 92 } 93 }(); 94 return 0; 95 #else 96 #pragma omp target 97 #pragma omp teams distribute parallel for private(t_var, vec, s_arr, var, sivar) 98 for (int i = 0; i < 2; ++i) { 99 vec[i] = t_var; 100 s_arr[i] = var; 101 sivar += i; 102 } 103 return tmain<int>(); 104 #endif 105 } 106 107 108 109 // Skip global, bound tid and loop vars 110 111 // private(s_arr) 112 113 // private(var) 114 115 116 // Skip global, bound tid and loop vars 117 118 // private(s_arr) 119 120 // private(var) 121 122 123 124 125 // Skip global, bound tid and loop vars 126 127 // private(s_arr) 128 129 130 // private(var) 131 132 133 // Skip global, bound tid and loop vars 134 // prev lb and ub 135 // iter variables 136 137 // private(s_arr) 138 139 140 // private(var) 141 142 143 144 #endif 145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 147 // CHECK1-NEXT: entry: 148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 154 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 157 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 164 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 170 // CHECK1-NEXT: ret void 171 // 172 // 173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 174 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 175 // CHECK1-NEXT: entry: 176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 177 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 178 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 182 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 183 // CHECK1-NEXT: ret void 184 // 185 // 186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 187 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 188 // CHECK1-NEXT: entry: 189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 190 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 196 // CHECK1-SAME: () #[[ATTR0]] { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 201 // CHECK1-NEXT: ret void 202 // 203 // 204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 205 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 206 // CHECK1-NEXT: entry: 207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 209 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 210 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 211 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 214 // CHECK1-NEXT: ret void 215 // 216 // 217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 218 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 219 // CHECK1-NEXT: entry: 220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 221 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 223 // CHECK1: arraydestroy.body: 224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 229 // CHECK1: arraydestroy.done1: 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 234 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 238 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 239 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 246 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 247 // CHECK1-NEXT: ret void 248 // 249 // 250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 251 // CHECK1-SAME: () #[[ATTR0]] { 252 // CHECK1-NEXT: entry: 253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK1-LABEL: define {{[^@]+}}@main 259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 260 // CHECK1-NEXT: entry: 261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 262 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 263 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 264 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 265 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 266 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 267 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 268 // CHECK1: omp_offload.failed: 269 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 270 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 271 // CHECK1: omp_offload.cont: 272 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 273 // CHECK1-NEXT: ret i32 [[CALL]] 274 // 275 // 276 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 277 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 278 // CHECK1-NEXT: entry: 279 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 280 // CHECK1-NEXT: ret void 281 // 282 // 283 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 284 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 285 // CHECK1-NEXT: entry: 286 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 287 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 288 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 289 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 290 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 291 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 292 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 293 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 294 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 295 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 296 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 297 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 298 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 301 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 302 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 303 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 304 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 305 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 306 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 307 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 308 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 309 // CHECK1: arrayctor.loop: 310 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 311 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 312 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 313 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 314 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 315 // CHECK1: arrayctor.cont: 316 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 317 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 318 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 319 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 320 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 321 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 322 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 323 // CHECK1: cond.true: 324 // CHECK1-NEXT: br label [[COND_END:%.*]] 325 // CHECK1: cond.false: 326 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 327 // CHECK1-NEXT: br label [[COND_END]] 328 // CHECK1: cond.end: 329 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 330 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 331 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 332 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 333 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 334 // CHECK1: omp.inner.for.cond: 335 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 336 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 337 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 338 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 339 // CHECK1: omp.inner.for.cond.cleanup: 340 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 341 // CHECK1: omp.inner.for.body: 342 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 343 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 344 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 345 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 346 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) 347 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 348 // CHECK1: omp.inner.for.inc: 349 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 350 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 351 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 352 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 353 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 354 // CHECK1: omp.inner.for.end: 355 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 356 // CHECK1: omp.loop.exit: 357 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 358 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 359 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) 360 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 361 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 362 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 363 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 364 // CHECK1: arraydestroy.body: 365 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 366 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 367 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 368 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 369 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 370 // CHECK1: arraydestroy.done3: 371 // CHECK1-NEXT: ret void 372 // 373 // 374 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 375 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 376 // CHECK1-NEXT: entry: 377 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 378 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 379 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 380 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 381 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 383 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 384 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 385 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 386 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 387 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 388 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 389 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 390 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 391 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 392 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 393 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 394 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 395 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 396 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 398 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 399 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 400 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 401 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 402 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 403 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 404 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 405 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 406 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 407 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 408 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 409 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 410 // CHECK1: arrayctor.loop: 411 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 412 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 413 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 414 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 415 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 416 // CHECK1: arrayctor.cont: 417 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 418 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 419 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 420 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 421 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 422 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 423 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 424 // CHECK1: cond.true: 425 // CHECK1-NEXT: br label [[COND_END:%.*]] 426 // CHECK1: cond.false: 427 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 428 // CHECK1-NEXT: br label [[COND_END]] 429 // CHECK1: cond.end: 430 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 431 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 432 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 433 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 434 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 435 // CHECK1: omp.inner.for.cond: 436 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 437 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 438 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 439 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 440 // CHECK1: omp.inner.for.cond.cleanup: 441 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 442 // CHECK1: omp.inner.for.body: 443 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 444 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 445 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 446 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 447 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 448 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 449 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 450 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 451 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 452 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 453 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 454 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] 455 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* 456 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 457 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) 458 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 459 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 460 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 461 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 462 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 463 // CHECK1: omp.body.continue: 464 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 465 // CHECK1: omp.inner.for.inc: 466 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 467 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 468 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 470 // CHECK1: omp.inner.for.end: 471 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 472 // CHECK1: omp.loop.exit: 473 // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 474 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 475 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 476 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 477 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 478 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 479 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 480 // CHECK1: arraydestroy.body: 481 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 482 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 483 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 484 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 485 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 486 // CHECK1: arraydestroy.done8: 487 // CHECK1-NEXT: ret void 488 // 489 // 490 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 491 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 492 // CHECK1-NEXT: entry: 493 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 494 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 495 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 496 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 497 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 498 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 499 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 500 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 501 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 502 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 503 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 504 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 505 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 506 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 507 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 508 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 509 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 510 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 511 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 512 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 513 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 514 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 515 // CHECK1: omp_offload.failed: 516 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 517 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 518 // CHECK1: omp_offload.cont: 519 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 520 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 521 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 522 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 523 // CHECK1: arraydestroy.body: 524 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 525 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 526 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 527 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 528 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 529 // CHECK1: arraydestroy.done2: 530 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 531 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 532 // CHECK1-NEXT: ret i32 [[TMP4]] 533 // 534 // 535 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 536 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 537 // CHECK1-NEXT: entry: 538 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 539 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 540 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 541 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 542 // CHECK1-NEXT: ret void 543 // 544 // 545 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 546 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 547 // CHECK1-NEXT: entry: 548 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 549 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 550 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 551 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 552 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 553 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 554 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 555 // CHECK1-NEXT: ret void 556 // 557 // 558 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 559 // CHECK1-SAME: () #[[ATTR4]] { 560 // CHECK1-NEXT: entry: 561 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 562 // CHECK1-NEXT: ret void 563 // 564 // 565 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 566 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 567 // CHECK1-NEXT: entry: 568 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 569 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 570 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 571 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 572 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 573 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 574 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 575 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 576 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 577 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 578 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 579 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 580 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 581 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 582 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 583 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 584 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 585 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 586 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 587 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 588 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 589 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 590 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 591 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 592 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 593 // CHECK1: arrayctor.loop: 594 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 595 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 596 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 597 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 598 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 599 // CHECK1: arrayctor.cont: 600 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 601 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 602 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 603 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 604 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 605 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 606 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 607 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 608 // CHECK1: cond.true: 609 // CHECK1-NEXT: br label [[COND_END:%.*]] 610 // CHECK1: cond.false: 611 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 612 // CHECK1-NEXT: br label [[COND_END]] 613 // CHECK1: cond.end: 614 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 615 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 616 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 617 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 618 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 619 // CHECK1: omp.inner.for.cond: 620 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 621 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 622 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 623 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 624 // CHECK1: omp.inner.for.cond.cleanup: 625 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 626 // CHECK1: omp.inner.for.body: 627 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 628 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 629 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 630 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 631 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) 632 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 633 // CHECK1: omp.inner.for.inc: 634 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 635 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 636 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 637 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 638 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 639 // CHECK1: omp.inner.for.end: 640 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 641 // CHECK1: omp.loop.exit: 642 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 643 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 644 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) 645 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 646 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 647 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 648 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 649 // CHECK1: arraydestroy.body: 650 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 651 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 652 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 653 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 654 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 655 // CHECK1: arraydestroy.done5: 656 // CHECK1-NEXT: ret void 657 // 658 // 659 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 660 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 661 // CHECK1-NEXT: entry: 662 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 663 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 664 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 665 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 666 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 667 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 668 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 669 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 670 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 671 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 672 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 673 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 674 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 675 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 676 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 677 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 678 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 679 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 680 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 681 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 682 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 683 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 684 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 685 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 686 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 687 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 688 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 689 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 690 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 691 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 692 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 693 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 694 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 695 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 696 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 697 // CHECK1: arrayctor.loop: 698 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 699 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 700 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 701 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 702 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 703 // CHECK1: arrayctor.cont: 704 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 705 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 706 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 707 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 708 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 709 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 710 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 711 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 712 // CHECK1: cond.true: 713 // CHECK1-NEXT: br label [[COND_END:%.*]] 714 // CHECK1: cond.false: 715 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 716 // CHECK1-NEXT: br label [[COND_END]] 717 // CHECK1: cond.end: 718 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 719 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 720 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 721 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 722 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 723 // CHECK1: omp.inner.for.cond: 724 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 725 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 726 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 727 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 728 // CHECK1: omp.inner.for.cond.cleanup: 729 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 730 // CHECK1: omp.inner.for.body: 731 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 732 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 733 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 734 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 735 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 736 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 737 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 738 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 739 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 740 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 741 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 742 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 743 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] 744 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* 745 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* 746 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) 747 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 748 // CHECK1: omp.body.continue: 749 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 750 // CHECK1: omp.inner.for.inc: 751 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 752 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 753 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 754 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 755 // CHECK1: omp.inner.for.end: 756 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 757 // CHECK1: omp.loop.exit: 758 // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 759 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 760 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) 761 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 762 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 763 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 764 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 765 // CHECK1: arraydestroy.body: 766 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 767 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 768 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 769 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 770 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 771 // CHECK1: arraydestroy.done9: 772 // CHECK1-NEXT: ret void 773 // 774 // 775 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 776 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 777 // CHECK1-NEXT: entry: 778 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 779 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 780 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 781 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 782 // CHECK1-NEXT: ret void 783 // 784 // 785 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 786 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 787 // CHECK1-NEXT: entry: 788 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 789 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 790 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 791 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 792 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 793 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 794 // CHECK1-NEXT: ret void 795 // 796 // 797 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 798 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 799 // CHECK1-NEXT: entry: 800 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 801 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 802 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 803 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 804 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 805 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 806 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 807 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 808 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 809 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 810 // CHECK1-NEXT: ret void 811 // 812 // 813 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 814 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 815 // CHECK1-NEXT: entry: 816 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 817 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 818 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 819 // CHECK1-NEXT: ret void 820 // 821 // 822 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 823 // CHECK1-SAME: () #[[ATTR0]] { 824 // CHECK1-NEXT: entry: 825 // CHECK1-NEXT: call void @__cxx_global_var_init() 826 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 827 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 828 // CHECK1-NEXT: ret void 829 // 830 // 831 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 832 // CHECK1-SAME: () #[[ATTR0]] { 833 // CHECK1-NEXT: entry: 834 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 835 // CHECK1-NEXT: ret void 836 // 837 // 838 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 839 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 840 // CHECK2-NEXT: entry: 841 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 842 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 843 // CHECK2-NEXT: ret void 844 // 845 // 846 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 847 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 848 // CHECK2-NEXT: entry: 849 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 850 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 851 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 852 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 853 // CHECK2-NEXT: ret void 854 // 855 // 856 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 857 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 858 // CHECK2-NEXT: entry: 859 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 860 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 861 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 862 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 863 // CHECK2-NEXT: ret void 864 // 865 // 866 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 867 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 868 // CHECK2-NEXT: entry: 869 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 870 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 871 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 872 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 873 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 874 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 875 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 876 // CHECK2-NEXT: ret void 877 // 878 // 879 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 880 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 881 // CHECK2-NEXT: entry: 882 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 883 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 884 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 885 // CHECK2-NEXT: ret void 886 // 887 // 888 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 889 // CHECK2-SAME: () #[[ATTR0]] { 890 // CHECK2-NEXT: entry: 891 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 892 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 893 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 894 // CHECK2-NEXT: ret void 895 // 896 // 897 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 898 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 899 // CHECK2-NEXT: entry: 900 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 901 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 902 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 903 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 904 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 905 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 906 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 907 // CHECK2-NEXT: ret void 908 // 909 // 910 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 911 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 912 // CHECK2-NEXT: entry: 913 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 914 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 915 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 916 // CHECK2: arraydestroy.body: 917 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 918 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 919 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 920 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 921 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 922 // CHECK2: arraydestroy.done1: 923 // CHECK2-NEXT: ret void 924 // 925 // 926 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 927 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 928 // CHECK2-NEXT: entry: 929 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 930 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 931 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 932 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 933 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 934 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 935 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 936 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 937 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 938 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 939 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 940 // CHECK2-NEXT: ret void 941 // 942 // 943 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 944 // CHECK2-SAME: () #[[ATTR0]] { 945 // CHECK2-NEXT: entry: 946 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 947 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 948 // CHECK2-NEXT: ret void 949 // 950 // 951 // CHECK2-LABEL: define {{[^@]+}}@main 952 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 953 // CHECK2-NEXT: entry: 954 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 955 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 956 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 957 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 958 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 959 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 960 // CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 961 // CHECK2: omp_offload.failed: 962 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 963 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 964 // CHECK2: omp_offload.cont: 965 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 966 // CHECK2-NEXT: ret i32 [[CALL]] 967 // 968 // 969 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 970 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { 971 // CHECK2-NEXT: entry: 972 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 973 // CHECK2-NEXT: ret void 974 // 975 // 976 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 977 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 978 // CHECK2-NEXT: entry: 979 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 980 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 981 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 982 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 983 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 984 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 985 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 986 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 987 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 988 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 989 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 990 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 991 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 992 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 993 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 994 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 995 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 996 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 997 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 998 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 999 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1000 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1001 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1002 // CHECK2: arrayctor.loop: 1003 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1004 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1005 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 1006 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1007 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1008 // CHECK2: arrayctor.cont: 1009 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 1010 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1011 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1012 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1013 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1014 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1015 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1016 // CHECK2: cond.true: 1017 // CHECK2-NEXT: br label [[COND_END:%.*]] 1018 // CHECK2: cond.false: 1019 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1020 // CHECK2-NEXT: br label [[COND_END]] 1021 // CHECK2: cond.end: 1022 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1023 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 1024 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1025 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1026 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1027 // CHECK2: omp.inner.for.cond: 1028 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1029 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1030 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1031 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1032 // CHECK2: omp.inner.for.cond.cleanup: 1033 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1034 // CHECK2: omp.inner.for.body: 1035 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1036 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1037 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1038 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1039 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) 1040 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1041 // CHECK2: omp.inner.for.inc: 1042 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1043 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1044 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1045 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1046 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1047 // CHECK2: omp.inner.for.end: 1048 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1049 // CHECK2: omp.loop.exit: 1050 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1051 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 1052 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) 1053 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1054 // CHECK2-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1055 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 1056 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1057 // CHECK2: arraydestroy.body: 1058 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1059 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1060 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1061 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1062 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1063 // CHECK2: arraydestroy.done3: 1064 // CHECK2-NEXT: ret void 1065 // 1066 // 1067 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1068 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1069 // CHECK2-NEXT: entry: 1070 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1071 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1072 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1073 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1074 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1075 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1076 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1077 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1078 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1079 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1080 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1081 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1082 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1083 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1084 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1085 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1086 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1087 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1088 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1089 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1090 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1091 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1092 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1093 // CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1094 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1095 // CHECK2-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 1096 // CHECK2-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 1097 // CHECK2-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 1098 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1099 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1100 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1101 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1102 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1103 // CHECK2: arrayctor.loop: 1104 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1105 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1106 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 1107 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1108 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1109 // CHECK2: arrayctor.cont: 1110 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 1111 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1112 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1113 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1114 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1115 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1116 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1117 // CHECK2: cond.true: 1118 // CHECK2-NEXT: br label [[COND_END:%.*]] 1119 // CHECK2: cond.false: 1120 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1121 // CHECK2-NEXT: br label [[COND_END]] 1122 // CHECK2: cond.end: 1123 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1124 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1125 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1126 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1127 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1128 // CHECK2: omp.inner.for.cond: 1129 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1130 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1131 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1132 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1133 // CHECK2: omp.inner.for.cond.cleanup: 1134 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1135 // CHECK2: omp.inner.for.body: 1136 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1137 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1138 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1139 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1140 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 1141 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1142 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1143 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 1144 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 1145 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 1146 // CHECK2-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 1147 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] 1148 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* 1149 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1150 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) 1151 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 1152 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 1153 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 1154 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 1155 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1156 // CHECK2: omp.body.continue: 1157 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1158 // CHECK2: omp.inner.for.inc: 1159 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1160 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 1161 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 1162 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1163 // CHECK2: omp.inner.for.end: 1164 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1165 // CHECK2: omp.loop.exit: 1166 // CHECK2-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1167 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 1168 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 1169 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1170 // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1171 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 1172 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1173 // CHECK2: arraydestroy.body: 1174 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1175 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1176 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1177 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1178 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1179 // CHECK2: arraydestroy.done8: 1180 // CHECK2-NEXT: ret void 1181 // 1182 // 1183 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1184 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat { 1185 // CHECK2-NEXT: entry: 1186 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1187 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1188 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1189 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1190 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1191 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 1192 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1193 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 1194 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1195 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 1196 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1197 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1198 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1199 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 1200 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1201 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 1202 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 1203 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 1204 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 1205 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1206 // CHECK2-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1207 // CHECK2-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1208 // CHECK2: omp_offload.failed: 1209 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1210 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1211 // CHECK2: omp_offload.cont: 1212 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1213 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1214 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1215 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1216 // CHECK2: arraydestroy.body: 1217 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1218 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1219 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1220 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1221 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1222 // CHECK2: arraydestroy.done2: 1223 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1224 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1225 // CHECK2-NEXT: ret i32 [[TMP4]] 1226 // 1227 // 1228 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1229 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1230 // CHECK2-NEXT: entry: 1231 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1232 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1233 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1234 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1235 // CHECK2-NEXT: ret void 1236 // 1237 // 1238 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1239 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1240 // CHECK2-NEXT: entry: 1241 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1242 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1243 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1244 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1245 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1246 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1247 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 1248 // CHECK2-NEXT: ret void 1249 // 1250 // 1251 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1252 // CHECK2-SAME: () #[[ATTR4]] { 1253 // CHECK2-NEXT: entry: 1254 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 1255 // CHECK2-NEXT: ret void 1256 // 1257 // 1258 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1259 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1260 // CHECK2-NEXT: entry: 1261 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1262 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1263 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1264 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1265 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 1266 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1267 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1268 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1269 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1270 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1271 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1272 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1273 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1274 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 1275 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1276 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1277 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1278 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 1279 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 1280 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 1281 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1282 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1283 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1284 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1285 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1286 // CHECK2: arrayctor.loop: 1287 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1288 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1289 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 1290 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1291 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1292 // CHECK2: arrayctor.cont: 1293 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 1294 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 1295 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1296 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1297 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1298 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1299 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1300 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1301 // CHECK2: cond.true: 1302 // CHECK2-NEXT: br label [[COND_END:%.*]] 1303 // CHECK2: cond.false: 1304 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1305 // CHECK2-NEXT: br label [[COND_END]] 1306 // CHECK2: cond.end: 1307 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1308 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 1309 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1310 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1311 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1312 // CHECK2: omp.inner.for.cond: 1313 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1314 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1315 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1316 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1317 // CHECK2: omp.inner.for.cond.cleanup: 1318 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1319 // CHECK2: omp.inner.for.body: 1320 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1321 // CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1322 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1323 // CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1324 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) 1325 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1326 // CHECK2: omp.inner.for.inc: 1327 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1328 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1329 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1330 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1331 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1332 // CHECK2: omp.inner.for.end: 1333 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1334 // CHECK2: omp.loop.exit: 1335 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1336 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 1337 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) 1338 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1339 // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1340 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 1341 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1342 // CHECK2: arraydestroy.body: 1343 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1344 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1345 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1346 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 1347 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1348 // CHECK2: arraydestroy.done5: 1349 // CHECK2-NEXT: ret void 1350 // 1351 // 1352 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 1353 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1354 // CHECK2-NEXT: entry: 1355 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1356 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1357 // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1358 // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1359 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1360 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1361 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 1362 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1363 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1364 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1365 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1366 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1367 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1368 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1369 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1370 // CHECK2-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 1371 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1372 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1373 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1374 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1375 // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1376 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 1377 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1378 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1379 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1380 // CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1381 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1382 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 1383 // CHECK2-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 1384 // CHECK2-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 1385 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1386 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1387 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1388 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1389 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1390 // CHECK2: arrayctor.loop: 1391 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1392 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1393 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 1394 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1395 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1396 // CHECK2: arrayctor.cont: 1397 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 1398 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 1399 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1400 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1401 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1402 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1403 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1404 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1405 // CHECK2: cond.true: 1406 // CHECK2-NEXT: br label [[COND_END:%.*]] 1407 // CHECK2: cond.false: 1408 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1409 // CHECK2-NEXT: br label [[COND_END]] 1410 // CHECK2: cond.end: 1411 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1412 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1413 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1414 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1415 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1416 // CHECK2: omp.inner.for.cond: 1417 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1418 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1419 // CHECK2-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1420 // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1421 // CHECK2: omp.inner.for.cond.cleanup: 1422 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1423 // CHECK2: omp.inner.for.body: 1424 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1425 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1426 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1427 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1428 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 1429 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1430 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1431 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 1432 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 1433 // CHECK2-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 1434 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1435 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 1436 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] 1437 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* 1438 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* 1439 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) 1440 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1441 // CHECK2: omp.body.continue: 1442 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1443 // CHECK2: omp.inner.for.inc: 1444 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1445 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 1446 // CHECK2-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 1447 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1448 // CHECK2: omp.inner.for.end: 1449 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1450 // CHECK2: omp.loop.exit: 1451 // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1452 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 1453 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) 1454 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1455 // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1456 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 1457 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1458 // CHECK2: arraydestroy.body: 1459 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1460 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1461 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1462 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1463 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1464 // CHECK2: arraydestroy.done9: 1465 // CHECK2-NEXT: ret void 1466 // 1467 // 1468 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1469 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1470 // CHECK2-NEXT: entry: 1471 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1472 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1473 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1474 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1475 // CHECK2-NEXT: ret void 1476 // 1477 // 1478 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1479 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1480 // CHECK2-NEXT: entry: 1481 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1482 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1483 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1484 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1485 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1486 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1487 // CHECK2-NEXT: ret void 1488 // 1489 // 1490 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1491 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1492 // CHECK2-NEXT: entry: 1493 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1494 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1495 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1496 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1497 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1498 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1499 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1500 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1501 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1502 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1503 // CHECK2-NEXT: ret void 1504 // 1505 // 1506 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1507 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1508 // CHECK2-NEXT: entry: 1509 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1510 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1511 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1512 // CHECK2-NEXT: ret void 1513 // 1514 // 1515 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 1516 // CHECK2-SAME: () #[[ATTR0]] { 1517 // CHECK2-NEXT: entry: 1518 // CHECK2-NEXT: call void @__cxx_global_var_init() 1519 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 1520 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 1521 // CHECK2-NEXT: ret void 1522 // 1523 // 1524 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1525 // CHECK2-SAME: () #[[ATTR0]] { 1526 // CHECK2-NEXT: entry: 1527 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1528 // CHECK2-NEXT: ret void 1529 // 1530 // 1531 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1532 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1533 // CHECK3-NEXT: entry: 1534 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 1535 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1536 // CHECK3-NEXT: ret void 1537 // 1538 // 1539 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1540 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1541 // CHECK3-NEXT: entry: 1542 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1543 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1544 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1545 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1546 // CHECK3-NEXT: ret void 1547 // 1548 // 1549 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1550 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1551 // CHECK3-NEXT: entry: 1552 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1553 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1554 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1555 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1556 // CHECK3-NEXT: ret void 1557 // 1558 // 1559 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1560 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1561 // CHECK3-NEXT: entry: 1562 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1563 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1564 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1565 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1566 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1567 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1568 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 1569 // CHECK3-NEXT: ret void 1570 // 1571 // 1572 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1573 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1574 // CHECK3-NEXT: entry: 1575 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1576 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1577 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1578 // CHECK3-NEXT: ret void 1579 // 1580 // 1581 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1582 // CHECK3-SAME: () #[[ATTR0]] { 1583 // CHECK3-NEXT: entry: 1584 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 1585 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 1586 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1587 // CHECK3-NEXT: ret void 1588 // 1589 // 1590 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1591 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1592 // CHECK3-NEXT: entry: 1593 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1594 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1595 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1596 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1597 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1598 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1599 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1600 // CHECK3-NEXT: ret void 1601 // 1602 // 1603 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1604 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 1605 // CHECK3-NEXT: entry: 1606 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1607 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1608 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1609 // CHECK3: arraydestroy.body: 1610 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1611 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1612 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1613 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1614 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1615 // CHECK3: arraydestroy.done1: 1616 // CHECK3-NEXT: ret void 1617 // 1618 // 1619 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1620 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1621 // CHECK3-NEXT: entry: 1622 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1623 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1624 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1625 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1626 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1627 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1628 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1629 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1630 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1631 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1632 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1633 // CHECK3-NEXT: ret void 1634 // 1635 // 1636 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1637 // CHECK3-SAME: () #[[ATTR0]] { 1638 // CHECK3-NEXT: entry: 1639 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1640 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1641 // CHECK3-NEXT: ret void 1642 // 1643 // 1644 // CHECK3-LABEL: define {{[^@]+}}@main 1645 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1646 // CHECK3-NEXT: entry: 1647 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1648 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1649 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1650 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 1651 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1652 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 1653 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1654 // CHECK3: omp_offload.failed: 1655 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 1656 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1657 // CHECK3: omp_offload.cont: 1658 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1659 // CHECK3-NEXT: ret i32 [[CALL]] 1660 // 1661 // 1662 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 1663 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 1664 // CHECK3-NEXT: entry: 1665 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1666 // CHECK3-NEXT: ret void 1667 // 1668 // 1669 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1670 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1671 // CHECK3-NEXT: entry: 1672 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1673 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1674 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1675 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1676 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1677 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1678 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1679 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1680 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1681 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1682 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1683 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1684 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1685 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1686 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1687 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1688 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 1689 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 1690 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1691 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1692 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1693 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1694 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1695 // CHECK3: arrayctor.loop: 1696 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1697 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1698 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1699 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1700 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1701 // CHECK3: arrayctor.cont: 1702 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 1703 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1704 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1705 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1706 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1707 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1708 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1709 // CHECK3: cond.true: 1710 // CHECK3-NEXT: br label [[COND_END:%.*]] 1711 // CHECK3: cond.false: 1712 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1713 // CHECK3-NEXT: br label [[COND_END]] 1714 // CHECK3: cond.end: 1715 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1716 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 1717 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1718 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1719 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1720 // CHECK3: omp.inner.for.cond: 1721 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1722 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1723 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1724 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1725 // CHECK3: omp.inner.for.cond.cleanup: 1726 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1727 // CHECK3: omp.inner.for.body: 1728 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1729 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1730 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) 1731 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1732 // CHECK3: omp.inner.for.inc: 1733 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1734 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1735 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 1736 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1737 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1738 // CHECK3: omp.inner.for.end: 1739 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1740 // CHECK3: omp.loop.exit: 1741 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1742 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1743 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) 1744 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1745 // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1746 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 1747 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1748 // CHECK3: arraydestroy.body: 1749 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1750 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1751 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1752 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1753 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1754 // CHECK3: arraydestroy.done3: 1755 // CHECK3-NEXT: ret void 1756 // 1757 // 1758 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 1759 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1760 // CHECK3-NEXT: entry: 1761 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1762 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1763 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1764 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1765 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1766 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1767 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1768 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1769 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1770 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1771 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1772 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1773 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1774 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1775 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1776 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1777 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1778 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1779 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 1780 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 1781 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1782 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1783 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 1784 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 1785 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 1786 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 1787 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1788 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1789 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1790 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1791 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1792 // CHECK3: arrayctor.loop: 1793 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1794 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1795 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1796 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1797 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1798 // CHECK3: arrayctor.cont: 1799 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 1800 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1801 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1802 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1803 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1804 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1805 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1806 // CHECK3: cond.true: 1807 // CHECK3-NEXT: br label [[COND_END:%.*]] 1808 // CHECK3: cond.false: 1809 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1810 // CHECK3-NEXT: br label [[COND_END]] 1811 // CHECK3: cond.end: 1812 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1813 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1814 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1815 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1816 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1817 // CHECK3: omp.inner.for.cond: 1818 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1819 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1820 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1821 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1822 // CHECK3: omp.inner.for.cond.cleanup: 1823 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1824 // CHECK3: omp.inner.for.body: 1825 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1826 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1827 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1828 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1829 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 1830 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1831 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] 1832 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 1833 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 1834 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] 1835 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1836 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1837 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) 1838 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 1839 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 1840 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 1841 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 1842 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1843 // CHECK3: omp.body.continue: 1844 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1845 // CHECK3: omp.inner.for.inc: 1846 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1847 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 1848 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1849 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1850 // CHECK3: omp.inner.for.end: 1851 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1852 // CHECK3: omp.loop.exit: 1853 // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1854 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 1855 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 1856 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1857 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1858 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 1859 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1860 // CHECK3: arraydestroy.body: 1861 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1862 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1863 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1864 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1865 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1866 // CHECK3: arraydestroy.done6: 1867 // CHECK3-NEXT: ret void 1868 // 1869 // 1870 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1871 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 1872 // CHECK3-NEXT: entry: 1873 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1874 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1875 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1876 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1877 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1878 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1879 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1880 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1881 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1882 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 1883 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1884 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1885 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1886 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 1887 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1888 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 1889 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1890 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1891 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 1892 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1893 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1894 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1895 // CHECK3: omp_offload.failed: 1896 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1897 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1898 // CHECK3: omp_offload.cont: 1899 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1900 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1901 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1902 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1903 // CHECK3: arraydestroy.body: 1904 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1905 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1906 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1907 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1908 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1909 // CHECK3: arraydestroy.done2: 1910 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1911 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1912 // CHECK3-NEXT: ret i32 [[TMP4]] 1913 // 1914 // 1915 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1916 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1917 // CHECK3-NEXT: entry: 1918 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1919 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1920 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1921 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1922 // CHECK3-NEXT: ret void 1923 // 1924 // 1925 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1926 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1927 // CHECK3-NEXT: entry: 1928 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1929 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1930 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1931 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1932 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1933 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1934 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1935 // CHECK3-NEXT: ret void 1936 // 1937 // 1938 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1939 // CHECK3-SAME: () #[[ATTR4]] { 1940 // CHECK3-NEXT: entry: 1941 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 1942 // CHECK3-NEXT: ret void 1943 // 1944 // 1945 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1946 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1947 // CHECK3-NEXT: entry: 1948 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1949 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1950 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1951 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1952 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1953 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1954 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1955 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1956 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1957 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1958 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1959 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1960 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1961 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 1962 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1963 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1964 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1965 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1966 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 1967 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 1968 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1969 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1970 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1971 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1972 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1973 // CHECK3: arrayctor.loop: 1974 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1975 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1976 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 1977 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1978 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1979 // CHECK3: arrayctor.cont: 1980 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 1981 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 1982 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1983 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1984 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1985 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1986 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1987 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1988 // CHECK3: cond.true: 1989 // CHECK3-NEXT: br label [[COND_END:%.*]] 1990 // CHECK3: cond.false: 1991 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1992 // CHECK3-NEXT: br label [[COND_END]] 1993 // CHECK3: cond.end: 1994 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1995 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 1996 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1997 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1998 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1999 // CHECK3: omp.inner.for.cond: 2000 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2001 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2002 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2003 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2004 // CHECK3: omp.inner.for.cond.cleanup: 2005 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2006 // CHECK3: omp.inner.for.body: 2007 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 2008 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2009 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) 2010 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2011 // CHECK3: omp.inner.for.inc: 2012 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2013 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2014 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 2015 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2016 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2017 // CHECK3: omp.inner.for.end: 2018 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2019 // CHECK3: omp.loop.exit: 2020 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2021 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 2022 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) 2023 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2024 // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2025 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 2026 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2027 // CHECK3: arraydestroy.body: 2028 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2029 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2030 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2031 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 2032 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 2033 // CHECK3: arraydestroy.done5: 2034 // CHECK3-NEXT: ret void 2035 // 2036 // 2037 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 2038 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 2039 // CHECK3-NEXT: entry: 2040 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2041 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2042 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2043 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2044 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2045 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2046 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 2047 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2048 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2049 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2050 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2051 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2052 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2053 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2054 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2055 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 2056 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2057 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2058 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2059 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 2060 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 2061 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 2062 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2063 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2064 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 2065 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 2066 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 2067 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 2068 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2069 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2070 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2071 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2072 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2073 // CHECK3: arrayctor.loop: 2074 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2075 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2076 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 2077 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2078 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2079 // CHECK3: arrayctor.cont: 2080 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 2081 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 2082 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2083 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2084 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2085 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2086 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 2087 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2088 // CHECK3: cond.true: 2089 // CHECK3-NEXT: br label [[COND_END:%.*]] 2090 // CHECK3: cond.false: 2091 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2092 // CHECK3-NEXT: br label [[COND_END]] 2093 // CHECK3: cond.end: 2094 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2095 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2096 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2097 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 2098 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2099 // CHECK3: omp.inner.for.cond: 2100 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2101 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2102 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2103 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2104 // CHECK3: omp.inner.for.cond.cleanup: 2105 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2106 // CHECK3: omp.inner.for.body: 2107 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2108 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2109 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2110 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2111 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 2112 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 2113 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] 2114 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 2115 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 2116 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2117 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] 2118 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 2119 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* 2120 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) 2121 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2122 // CHECK3: omp.body.continue: 2123 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2124 // CHECK3: omp.inner.for.inc: 2125 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2126 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 2127 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 2128 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2129 // CHECK3: omp.inner.for.end: 2130 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2131 // CHECK3: omp.loop.exit: 2132 // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2133 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 2134 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) 2135 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2136 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2137 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 2138 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2139 // CHECK3: arraydestroy.body: 2140 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2141 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2142 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2143 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 2144 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 2145 // CHECK3: arraydestroy.done7: 2146 // CHECK3-NEXT: ret void 2147 // 2148 // 2149 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2150 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2151 // CHECK3-NEXT: entry: 2152 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2153 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2154 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2155 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2156 // CHECK3-NEXT: ret void 2157 // 2158 // 2159 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2160 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2161 // CHECK3-NEXT: entry: 2162 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2163 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2164 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2165 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2166 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2167 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2168 // CHECK3-NEXT: ret void 2169 // 2170 // 2171 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2172 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2173 // CHECK3-NEXT: entry: 2174 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2175 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2176 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2177 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2178 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2179 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2180 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2181 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2182 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2183 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2184 // CHECK3-NEXT: ret void 2185 // 2186 // 2187 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2188 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2189 // CHECK3-NEXT: entry: 2190 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2191 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2192 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2193 // CHECK3-NEXT: ret void 2194 // 2195 // 2196 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 2197 // CHECK3-SAME: () #[[ATTR0]] { 2198 // CHECK3-NEXT: entry: 2199 // CHECK3-NEXT: call void @__cxx_global_var_init() 2200 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 2201 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 2202 // CHECK3-NEXT: ret void 2203 // 2204 // 2205 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2206 // CHECK3-SAME: () #[[ATTR0]] { 2207 // CHECK3-NEXT: entry: 2208 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 2209 // CHECK3-NEXT: ret void 2210 // 2211 // 2212 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 2213 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 2214 // CHECK4-NEXT: entry: 2215 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 2216 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2217 // CHECK4-NEXT: ret void 2218 // 2219 // 2220 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2221 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2222 // CHECK4-NEXT: entry: 2223 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2224 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2225 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2226 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2227 // CHECK4-NEXT: ret void 2228 // 2229 // 2230 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2231 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2232 // CHECK4-NEXT: entry: 2233 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2234 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2235 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2236 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2237 // CHECK4-NEXT: ret void 2238 // 2239 // 2240 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2241 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2242 // CHECK4-NEXT: entry: 2243 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2244 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2245 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2246 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2247 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2248 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2249 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4 2250 // CHECK4-NEXT: ret void 2251 // 2252 // 2253 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2254 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2255 // CHECK4-NEXT: entry: 2256 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2257 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2258 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2259 // CHECK4-NEXT: ret void 2260 // 2261 // 2262 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2263 // CHECK4-SAME: () #[[ATTR0]] { 2264 // CHECK4-NEXT: entry: 2265 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 2266 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 2267 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2268 // CHECK4-NEXT: ret void 2269 // 2270 // 2271 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2272 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2273 // CHECK4-NEXT: entry: 2274 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2275 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2276 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2277 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2278 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2279 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2280 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2281 // CHECK4-NEXT: ret void 2282 // 2283 // 2284 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2285 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 2286 // CHECK4-NEXT: entry: 2287 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 2288 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 2289 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2290 // CHECK4: arraydestroy.body: 2291 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2292 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2293 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2294 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2295 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2296 // CHECK4: arraydestroy.done1: 2297 // CHECK4-NEXT: ret void 2298 // 2299 // 2300 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2301 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2302 // CHECK4-NEXT: entry: 2303 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2304 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2305 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2306 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2307 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2308 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2309 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2310 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2311 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2312 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2313 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 2314 // CHECK4-NEXT: ret void 2315 // 2316 // 2317 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2318 // CHECK4-SAME: () #[[ATTR0]] { 2319 // CHECK4-NEXT: entry: 2320 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 2321 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2322 // CHECK4-NEXT: ret void 2323 // 2324 // 2325 // CHECK4-LABEL: define {{[^@]+}}@main 2326 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 2327 // CHECK4-NEXT: entry: 2328 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2329 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2330 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 2331 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 2332 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 2333 // CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 2334 // CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2335 // CHECK4: omp_offload.failed: 2336 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 2337 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2338 // CHECK4: omp_offload.cont: 2339 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2340 // CHECK4-NEXT: ret i32 [[CALL]] 2341 // 2342 // 2343 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 2344 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] { 2345 // CHECK4-NEXT: entry: 2346 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2347 // CHECK4-NEXT: ret void 2348 // 2349 // 2350 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 2351 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 2352 // CHECK4-NEXT: entry: 2353 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2354 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2355 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2356 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2357 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2358 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2359 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2360 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2361 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2362 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2363 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2364 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2365 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2366 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2367 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2368 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2369 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 2370 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 2371 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2372 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2373 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2374 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2375 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2376 // CHECK4: arrayctor.loop: 2377 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2378 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2379 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 2380 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2381 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2382 // CHECK4: arrayctor.cont: 2383 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 2384 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2385 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2386 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2387 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2388 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2389 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2390 // CHECK4: cond.true: 2391 // CHECK4-NEXT: br label [[COND_END:%.*]] 2392 // CHECK4: cond.false: 2393 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2394 // CHECK4-NEXT: br label [[COND_END]] 2395 // CHECK4: cond.end: 2396 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2397 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 2398 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 2399 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2400 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2401 // CHECK4: omp.inner.for.cond: 2402 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2403 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2404 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2405 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2406 // CHECK4: omp.inner.for.cond.cleanup: 2407 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2408 // CHECK4: omp.inner.for.body: 2409 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 2410 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2411 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) 2412 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2413 // CHECK4: omp.inner.for.inc: 2414 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2415 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2416 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 2417 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2418 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2419 // CHECK4: omp.inner.for.end: 2420 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2421 // CHECK4: omp.loop.exit: 2422 // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2423 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 2424 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) 2425 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2426 // CHECK4-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2427 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 2428 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2429 // CHECK4: arraydestroy.body: 2430 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2431 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2432 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2433 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 2434 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 2435 // CHECK4: arraydestroy.done3: 2436 // CHECK4-NEXT: ret void 2437 // 2438 // 2439 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 2440 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 2441 // CHECK4-NEXT: entry: 2442 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2443 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2444 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2445 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2446 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2447 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2448 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2449 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2450 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2451 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2452 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2453 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2454 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2455 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2456 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2457 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2458 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2459 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2460 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 2461 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 2462 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2463 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2464 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 2465 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 2466 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 2467 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 2468 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2469 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2470 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2471 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2472 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2473 // CHECK4: arrayctor.loop: 2474 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2475 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2476 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 2477 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2478 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2479 // CHECK4: arrayctor.cont: 2480 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 2481 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2482 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2483 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2484 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2485 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 2486 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2487 // CHECK4: cond.true: 2488 // CHECK4-NEXT: br label [[COND_END:%.*]] 2489 // CHECK4: cond.false: 2490 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2491 // CHECK4-NEXT: br label [[COND_END]] 2492 // CHECK4: cond.end: 2493 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2494 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2495 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2496 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 2497 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2498 // CHECK4: omp.inner.for.cond: 2499 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2500 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2501 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2502 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2503 // CHECK4: omp.inner.for.cond.cleanup: 2504 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2505 // CHECK4: omp.inner.for.body: 2506 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2507 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2508 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2509 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2510 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 2511 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 2512 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] 2513 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 2514 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 2515 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] 2516 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 2517 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 2518 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) 2519 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 2520 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 2521 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 2522 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 2523 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2524 // CHECK4: omp.body.continue: 2525 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2526 // CHECK4: omp.inner.for.inc: 2527 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2528 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 2529 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 2530 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2531 // CHECK4: omp.inner.for.end: 2532 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2533 // CHECK4: omp.loop.exit: 2534 // CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2535 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 2536 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 2537 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2538 // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2539 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 2540 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2541 // CHECK4: arraydestroy.body: 2542 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2543 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2544 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2545 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 2546 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 2547 // CHECK4: arraydestroy.done6: 2548 // CHECK4-NEXT: ret void 2549 // 2550 // 2551 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2552 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat { 2553 // CHECK4-NEXT: entry: 2554 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2555 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2556 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2557 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2558 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2559 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2560 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2561 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 2562 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2563 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 2564 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2565 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2566 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2567 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2568 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2569 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2570 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2571 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 2572 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 2573 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 2574 // CHECK4-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 2575 // CHECK4-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2576 // CHECK4: omp_offload.failed: 2577 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 2578 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2579 // CHECK4: omp_offload.cont: 2580 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 2581 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2582 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2583 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2584 // CHECK4: arraydestroy.body: 2585 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2586 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2587 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2588 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2589 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2590 // CHECK4: arraydestroy.done2: 2591 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2592 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 2593 // CHECK4-NEXT: ret i32 [[TMP4]] 2594 // 2595 // 2596 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2597 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2598 // CHECK4-NEXT: entry: 2599 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2600 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2601 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2602 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2603 // CHECK4-NEXT: ret void 2604 // 2605 // 2606 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2607 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2608 // CHECK4-NEXT: entry: 2609 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2610 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2611 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2612 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2613 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2614 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2615 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 2616 // CHECK4-NEXT: ret void 2617 // 2618 // 2619 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 2620 // CHECK4-SAME: () #[[ATTR4]] { 2621 // CHECK4-NEXT: entry: 2622 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 2623 // CHECK4-NEXT: ret void 2624 // 2625 // 2626 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 2627 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 2628 // CHECK4-NEXT: entry: 2629 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2630 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2631 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2632 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2633 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 2634 // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 2635 // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 2636 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2637 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2638 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2639 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2640 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2641 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2642 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 2643 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2644 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2645 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2646 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 2647 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 2648 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 2649 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2650 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2651 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2652 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2653 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2654 // CHECK4: arrayctor.loop: 2655 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2656 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2657 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 2658 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2659 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2660 // CHECK4: arrayctor.cont: 2661 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 2662 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 2663 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2664 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2665 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2666 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2667 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2668 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2669 // CHECK4: cond.true: 2670 // CHECK4-NEXT: br label [[COND_END:%.*]] 2671 // CHECK4: cond.false: 2672 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2673 // CHECK4-NEXT: br label [[COND_END]] 2674 // CHECK4: cond.end: 2675 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2676 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 2677 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 2678 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2679 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2680 // CHECK4: omp.inner.for.cond: 2681 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2682 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2683 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2684 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2685 // CHECK4: omp.inner.for.cond.cleanup: 2686 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2687 // CHECK4: omp.inner.for.body: 2688 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 2689 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 2690 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) 2691 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2692 // CHECK4: omp.inner.for.inc: 2693 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2694 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2695 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 2696 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2697 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2698 // CHECK4: omp.inner.for.end: 2699 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2700 // CHECK4: omp.loop.exit: 2701 // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2702 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 2703 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) 2704 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2705 // CHECK4-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2706 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 2707 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2708 // CHECK4: arraydestroy.body: 2709 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2710 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2711 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2712 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 2713 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 2714 // CHECK4: arraydestroy.done5: 2715 // CHECK4-NEXT: ret void 2716 // 2717 // 2718 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 2719 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 2720 // CHECK4-NEXT: entry: 2721 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2722 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2723 // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 2724 // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 2725 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2726 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2727 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 2728 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2729 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2730 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2731 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2732 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2733 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2734 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2735 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2736 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 2737 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2738 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2739 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2740 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 2741 // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 2742 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 2743 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2744 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2745 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 2746 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 2747 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 2748 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 2749 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2750 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2751 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2752 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2753 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2754 // CHECK4: arrayctor.loop: 2755 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2756 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2757 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 2758 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2759 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2760 // CHECK4: arrayctor.cont: 2761 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) 2762 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 2763 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2764 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2765 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2766 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2767 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 2768 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2769 // CHECK4: cond.true: 2770 // CHECK4-NEXT: br label [[COND_END:%.*]] 2771 // CHECK4: cond.false: 2772 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2773 // CHECK4-NEXT: br label [[COND_END]] 2774 // CHECK4: cond.end: 2775 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2776 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2777 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2778 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 2779 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2780 // CHECK4: omp.inner.for.cond: 2781 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2782 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2783 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 2784 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2785 // CHECK4: omp.inner.for.cond.cleanup: 2786 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2787 // CHECK4: omp.inner.for.body: 2788 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2789 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 2790 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2791 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2792 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 2793 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 2794 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] 2795 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 2796 // CHECK4-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 2797 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2798 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] 2799 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 2800 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* 2801 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) 2802 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2803 // CHECK4: omp.body.continue: 2804 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2805 // CHECK4: omp.inner.for.inc: 2806 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2807 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 2808 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 2809 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2810 // CHECK4: omp.inner.for.end: 2811 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2812 // CHECK4: omp.loop.exit: 2813 // CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2814 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 2815 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) 2816 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 2817 // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2818 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 2819 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2820 // CHECK4: arraydestroy.body: 2821 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2822 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2823 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2824 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 2825 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 2826 // CHECK4: arraydestroy.done7: 2827 // CHECK4-NEXT: ret void 2828 // 2829 // 2830 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2831 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2832 // CHECK4-NEXT: entry: 2833 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2834 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2835 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2836 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2837 // CHECK4-NEXT: ret void 2838 // 2839 // 2840 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2841 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2842 // CHECK4-NEXT: entry: 2843 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2844 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2845 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2846 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2847 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2848 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2849 // CHECK4-NEXT: ret void 2850 // 2851 // 2852 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2853 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2854 // CHECK4-NEXT: entry: 2855 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2856 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2857 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2858 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2859 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2860 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2861 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2862 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2863 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2864 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2865 // CHECK4-NEXT: ret void 2866 // 2867 // 2868 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2869 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2870 // CHECK4-NEXT: entry: 2871 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2872 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2873 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2874 // CHECK4-NEXT: ret void 2875 // 2876 // 2877 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 2878 // CHECK4-SAME: () #[[ATTR0]] { 2879 // CHECK4-NEXT: entry: 2880 // CHECK4-NEXT: call void @__cxx_global_var_init() 2881 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 2882 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 2883 // CHECK4-NEXT: ret void 2884 // 2885 // 2886 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2887 // CHECK4-SAME: () #[[ATTR0]] { 2888 // CHECK4-NEXT: entry: 2889 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 2890 // CHECK4-NEXT: ret void 2891 // 2892 // 2893 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 2894 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 2895 // CHECK5-NEXT: entry: 2896 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 2897 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2898 // CHECK5-NEXT: ret void 2899 // 2900 // 2901 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2902 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2903 // CHECK5-NEXT: entry: 2904 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2905 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2906 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2907 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2908 // CHECK5-NEXT: ret void 2909 // 2910 // 2911 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2912 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2913 // CHECK5-NEXT: entry: 2914 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2915 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2916 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2917 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2918 // CHECK5-NEXT: ret void 2919 // 2920 // 2921 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2922 // CHECK5-SAME: () #[[ATTR0]] { 2923 // CHECK5-NEXT: entry: 2924 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 2925 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 2926 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2927 // CHECK5-NEXT: ret void 2928 // 2929 // 2930 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2931 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2932 // CHECK5-NEXT: entry: 2933 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2934 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2935 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2936 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2937 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2938 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2939 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2940 // CHECK5-NEXT: ret void 2941 // 2942 // 2943 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2944 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 2945 // CHECK5-NEXT: entry: 2946 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2947 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2948 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2949 // CHECK5: arraydestroy.body: 2950 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2951 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2952 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2953 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2954 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2955 // CHECK5: arraydestroy.done1: 2956 // CHECK5-NEXT: ret void 2957 // 2958 // 2959 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2960 // CHECK5-SAME: () #[[ATTR0]] { 2961 // CHECK5-NEXT: entry: 2962 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 2963 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2964 // CHECK5-NEXT: ret void 2965 // 2966 // 2967 // CHECK5-LABEL: define {{[^@]+}}@main 2968 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 2969 // CHECK5-NEXT: entry: 2970 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2971 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2972 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2973 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2974 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2975 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2976 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2977 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 2978 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2979 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 2980 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 2981 // CHECK5: arrayctor.loop: 2982 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 2983 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 2984 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 2985 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 2986 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 2987 // CHECK5: arrayctor.cont: 2988 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 2989 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 2990 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 2991 // CHECK5: for.cond: 2992 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 2993 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 2994 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 2995 // CHECK5: for.body: 2996 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 2997 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 2998 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 2999 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 3000 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3001 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3002 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 3003 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] 3004 // CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 3005 // CHECK5-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* 3006 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) 3007 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 3008 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 3009 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 3010 // CHECK5-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 3011 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 3012 // CHECK5: for.inc: 3013 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3014 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 3015 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 3016 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 3017 // CHECK5: for.end: 3018 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3019 // CHECK5-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3020 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 3021 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3022 // CHECK5: arraydestroy.body: 3023 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3024 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3025 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3026 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] 3027 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 3028 // CHECK5: arraydestroy.done4: 3029 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 3030 // CHECK5-NEXT: ret i32 [[CALL]] 3031 // 3032 // 3033 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3034 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 3035 // CHECK5-NEXT: entry: 3036 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3037 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3038 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3039 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3040 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3041 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 3042 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 3043 // CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3044 // CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3045 // CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 3046 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 3047 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3048 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3049 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 3050 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3051 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3052 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3053 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 3054 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3055 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 3056 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 3057 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3058 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3059 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3060 // CHECK5: arrayctor.loop: 3061 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3062 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3063 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 3064 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3065 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3066 // CHECK5: arrayctor.cont: 3067 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) 3068 // CHECK5-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 3069 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 3070 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 3071 // CHECK5: for.cond: 3072 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 3073 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 3074 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3075 // CHECK5: for.body: 3076 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 3077 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3078 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 3079 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 3080 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 3081 // CHECK5-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 3082 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3083 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 3084 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] 3085 // CHECK5-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* 3086 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 3087 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) 3088 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 3089 // CHECK5: for.inc: 3090 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3091 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 3092 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 3093 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3094 // CHECK5: for.end: 3095 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 3096 // CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3097 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 3098 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3099 // CHECK5: arraydestroy.body: 3100 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3101 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3102 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3103 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 3104 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 3105 // CHECK5: arraydestroy.done8: 3106 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 3107 // CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3108 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 3109 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] 3110 // CHECK5: arraydestroy.body10: 3111 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] 3112 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 3113 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] 3114 // CHECK5-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] 3115 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] 3116 // CHECK5: arraydestroy.done14: 3117 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3118 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 3119 // CHECK5-NEXT: ret i32 [[TMP11]] 3120 // 3121 // 3122 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3123 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3124 // CHECK5-NEXT: entry: 3125 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3126 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3127 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3128 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3129 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3130 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3131 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 3132 // CHECK5-NEXT: ret void 3133 // 3134 // 3135 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3136 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3137 // CHECK5-NEXT: entry: 3138 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3139 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3140 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3141 // CHECK5-NEXT: ret void 3142 // 3143 // 3144 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3145 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3146 // CHECK5-NEXT: entry: 3147 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3148 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3149 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3150 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3151 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3152 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3153 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3154 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3155 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3156 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3157 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 3158 // CHECK5-NEXT: ret void 3159 // 3160 // 3161 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3162 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3163 // CHECK5-NEXT: entry: 3164 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3165 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3166 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3167 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3168 // CHECK5-NEXT: ret void 3169 // 3170 // 3171 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3172 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3173 // CHECK5-NEXT: entry: 3174 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3175 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3176 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3177 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3178 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3179 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3180 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 3181 // CHECK5-NEXT: ret void 3182 // 3183 // 3184 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3185 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3186 // CHECK5-NEXT: entry: 3187 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3188 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3189 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3190 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3191 // CHECK5-NEXT: ret void 3192 // 3193 // 3194 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3195 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3196 // CHECK5-NEXT: entry: 3197 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3198 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3199 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3200 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3201 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3202 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3203 // CHECK5-NEXT: ret void 3204 // 3205 // 3206 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3207 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3208 // CHECK5-NEXT: entry: 3209 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3210 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3211 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3212 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3213 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3214 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3215 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3216 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3217 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3218 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3219 // CHECK5-NEXT: ret void 3220 // 3221 // 3222 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3223 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3224 // CHECK5-NEXT: entry: 3225 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3226 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3227 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3228 // CHECK5-NEXT: ret void 3229 // 3230 // 3231 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 3232 // CHECK5-SAME: () #[[ATTR0]] { 3233 // CHECK5-NEXT: entry: 3234 // CHECK5-NEXT: call void @__cxx_global_var_init() 3235 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 3236 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 3237 // CHECK5-NEXT: ret void 3238 // 3239 // 3240 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init 3241 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 3242 // CHECK6-NEXT: entry: 3243 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3244 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3245 // CHECK6-NEXT: ret void 3246 // 3247 // 3248 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3249 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3250 // CHECK6-NEXT: entry: 3251 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3252 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3253 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3254 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3255 // CHECK6-NEXT: ret void 3256 // 3257 // 3258 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3259 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3260 // CHECK6-NEXT: entry: 3261 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3262 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3263 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3264 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3265 // CHECK6-NEXT: ret void 3266 // 3267 // 3268 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3269 // CHECK6-SAME: () #[[ATTR0]] { 3270 // CHECK6-NEXT: entry: 3271 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 3272 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 3273 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3274 // CHECK6-NEXT: ret void 3275 // 3276 // 3277 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3278 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3279 // CHECK6-NEXT: entry: 3280 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3281 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3282 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3283 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3284 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3285 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3286 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3287 // CHECK6-NEXT: ret void 3288 // 3289 // 3290 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3291 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3292 // CHECK6-NEXT: entry: 3293 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3294 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3295 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3296 // CHECK6: arraydestroy.body: 3297 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3298 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3299 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3300 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3301 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3302 // CHECK6: arraydestroy.done1: 3303 // CHECK6-NEXT: ret void 3304 // 3305 // 3306 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3307 // CHECK6-SAME: () #[[ATTR0]] { 3308 // CHECK6-NEXT: entry: 3309 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3310 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3311 // CHECK6-NEXT: ret void 3312 // 3313 // 3314 // CHECK6-LABEL: define {{[^@]+}}@main 3315 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] { 3316 // CHECK6-NEXT: entry: 3317 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3318 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3319 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3320 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3321 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3322 // CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 3323 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3324 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 3325 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3326 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 3327 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3328 // CHECK6: arrayctor.loop: 3329 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3330 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3331 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 3332 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3333 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3334 // CHECK6: arrayctor.cont: 3335 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 3336 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 3337 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3338 // CHECK6: for.cond: 3339 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3340 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 3341 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3342 // CHECK6: for.body: 3343 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 3344 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3345 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 3346 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 3347 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3348 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3349 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 3350 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]] 3351 // CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 3352 // CHECK6-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* 3353 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i64 4, i1 false) 3354 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 3355 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 3356 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 3357 // CHECK6-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 3358 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3359 // CHECK6: for.inc: 3360 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3361 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 3362 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 3363 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 3364 // CHECK6: for.end: 3365 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3366 // CHECK6-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3367 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN3]], i64 2 3368 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3369 // CHECK6: arraydestroy.body: 3370 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3371 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3372 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3373 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] 3374 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 3375 // CHECK6: arraydestroy.done4: 3376 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 3377 // CHECK6-NEXT: ret i32 [[CALL]] 3378 // 3379 // 3380 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3381 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { 3382 // CHECK6-NEXT: entry: 3383 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3384 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3385 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3386 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3387 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3388 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 3389 // CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 3390 // CHECK6-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3391 // CHECK6-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3392 // CHECK6-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 3393 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 3394 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3395 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3396 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 3397 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3398 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3399 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3400 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 3401 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3402 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 3403 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 3404 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3405 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3406 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3407 // CHECK6: arrayctor.loop: 3408 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3409 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3410 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 3411 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3412 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3413 // CHECK6: arrayctor.cont: 3414 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) 3415 // CHECK6-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 8 3416 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 3417 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3418 // CHECK6: for.cond: 3419 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 3420 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 3421 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3422 // CHECK6: for.body: 3423 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 3424 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3425 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64 3426 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 3427 // CHECK6-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 3428 // CHECK6-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 3429 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3430 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP5]] to i64 3431 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM5]] 3432 // CHECK6-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* 3433 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 3434 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false) 3435 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3436 // CHECK6: for.inc: 3437 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3438 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 3439 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 3440 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3441 // CHECK6: for.end: 3442 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 3443 // CHECK6-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3444 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2 3445 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3446 // CHECK6: arraydestroy.body: 3447 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3448 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3449 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3450 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 3451 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 3452 // CHECK6: arraydestroy.done8: 3453 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 3454 // CHECK6-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3455 // CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 3456 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY10:%.*]] 3457 // CHECK6: arraydestroy.body10: 3458 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST11:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE8]] ], [ [[ARRAYDESTROY_ELEMENT12:%.*]], [[ARRAYDESTROY_BODY10]] ] 3459 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT12]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST11]], i64 -1 3460 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT12]]) #[[ATTR2]] 3461 // CHECK6-NEXT: [[ARRAYDESTROY_DONE13:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT12]], [[ARRAY_BEGIN9]] 3462 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE13]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY10]] 3463 // CHECK6: arraydestroy.done14: 3464 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3465 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 3466 // CHECK6-NEXT: ret i32 [[TMP11]] 3467 // 3468 // 3469 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3470 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3471 // CHECK6-NEXT: entry: 3472 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3473 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3474 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3475 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3476 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3477 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3478 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 3479 // CHECK6-NEXT: ret void 3480 // 3481 // 3482 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3483 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3484 // CHECK6-NEXT: entry: 3485 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3486 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3487 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3488 // CHECK6-NEXT: ret void 3489 // 3490 // 3491 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3492 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3493 // CHECK6-NEXT: entry: 3494 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3495 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3496 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3497 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3498 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3499 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3500 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3501 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3502 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3503 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3504 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 3505 // CHECK6-NEXT: ret void 3506 // 3507 // 3508 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3509 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3510 // CHECK6-NEXT: entry: 3511 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3512 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3513 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3514 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3515 // CHECK6-NEXT: ret void 3516 // 3517 // 3518 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3519 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3520 // CHECK6-NEXT: entry: 3521 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3522 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3523 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3524 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3525 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3526 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3527 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 3528 // CHECK6-NEXT: ret void 3529 // 3530 // 3531 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3532 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3533 // CHECK6-NEXT: entry: 3534 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3535 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3536 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3537 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3538 // CHECK6-NEXT: ret void 3539 // 3540 // 3541 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3542 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3543 // CHECK6-NEXT: entry: 3544 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3545 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3546 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3547 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3548 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3549 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3550 // CHECK6-NEXT: ret void 3551 // 3552 // 3553 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3554 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3555 // CHECK6-NEXT: entry: 3556 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3557 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3558 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3559 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3560 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3561 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3562 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3563 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3564 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3565 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3566 // CHECK6-NEXT: ret void 3567 // 3568 // 3569 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3570 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3571 // CHECK6-NEXT: entry: 3572 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3573 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3574 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3575 // CHECK6-NEXT: ret void 3576 // 3577 // 3578 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 3579 // CHECK6-SAME: () #[[ATTR0]] { 3580 // CHECK6-NEXT: entry: 3581 // CHECK6-NEXT: call void @__cxx_global_var_init() 3582 // CHECK6-NEXT: call void @__cxx_global_var_init.1() 3583 // CHECK6-NEXT: call void @__cxx_global_var_init.2() 3584 // CHECK6-NEXT: ret void 3585 // 3586 // 3587 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 3588 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 3589 // CHECK7-NEXT: entry: 3590 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3591 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3592 // CHECK7-NEXT: ret void 3593 // 3594 // 3595 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3596 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3597 // CHECK7-NEXT: entry: 3598 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3599 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3600 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3601 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3602 // CHECK7-NEXT: ret void 3603 // 3604 // 3605 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3606 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3607 // CHECK7-NEXT: entry: 3608 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3609 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3610 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3611 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3612 // CHECK7-NEXT: ret void 3613 // 3614 // 3615 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3616 // CHECK7-SAME: () #[[ATTR0]] { 3617 // CHECK7-NEXT: entry: 3618 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 3619 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 3620 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3621 // CHECK7-NEXT: ret void 3622 // 3623 // 3624 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3625 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3626 // CHECK7-NEXT: entry: 3627 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3628 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3629 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3630 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3631 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3632 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3633 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3634 // CHECK7-NEXT: ret void 3635 // 3636 // 3637 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3638 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3639 // CHECK7-NEXT: entry: 3640 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 3641 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 3642 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3643 // CHECK7: arraydestroy.body: 3644 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3645 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3646 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3647 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3648 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3649 // CHECK7: arraydestroy.done1: 3650 // CHECK7-NEXT: ret void 3651 // 3652 // 3653 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3654 // CHECK7-SAME: () #[[ATTR0]] { 3655 // CHECK7-NEXT: entry: 3656 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3657 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3658 // CHECK7-NEXT: ret void 3659 // 3660 // 3661 // CHECK7-LABEL: define {{[^@]+}}@main 3662 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 3663 // CHECK7-NEXT: entry: 3664 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3665 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3666 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3667 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 3668 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 3669 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 3670 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3671 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 3672 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3673 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 3674 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3675 // CHECK7: arrayctor.loop: 3676 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3677 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3678 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 3679 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3680 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3681 // CHECK7: arrayctor.cont: 3682 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 3683 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 3684 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 3685 // CHECK7: for.cond: 3686 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3687 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 3688 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3689 // CHECK7: for.body: 3690 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 3691 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3692 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] 3693 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3694 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3695 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] 3696 // CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 3697 // CHECK7-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* 3698 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) 3699 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 3700 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 3701 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 3702 // CHECK7-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 3703 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 3704 // CHECK7: for.inc: 3705 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3706 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 3707 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 3708 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 3709 // CHECK7: for.end: 3710 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 3711 // CHECK7-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 3712 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 3713 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3714 // CHECK7: arraydestroy.body: 3715 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3716 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3717 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3718 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 3719 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 3720 // CHECK7: arraydestroy.done3: 3721 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 3722 // CHECK7-NEXT: ret i32 [[CALL]] 3723 // 3724 // 3725 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3726 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 3727 // CHECK7-NEXT: entry: 3728 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3729 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3730 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3731 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3732 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3733 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 3734 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 3735 // CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3736 // CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3737 // CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 3738 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3739 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3740 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3741 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 3742 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3743 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 3744 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3745 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 3746 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 3747 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 3748 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 3749 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3750 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3751 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 3752 // CHECK7: arrayctor.loop: 3753 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 3754 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 3755 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 3756 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 3757 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 3758 // CHECK7: arrayctor.cont: 3759 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) 3760 // CHECK7-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 3761 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 3762 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 3763 // CHECK7: for.cond: 3764 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 3765 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 3766 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3767 // CHECK7: for.body: 3768 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 3769 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3770 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] 3771 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 3772 // CHECK7-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3773 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3774 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] 3775 // CHECK7-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 3776 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 3777 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) 3778 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 3779 // CHECK7: for.inc: 3780 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3781 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 3782 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 3783 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 3784 // CHECK7: for.end: 3785 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 3786 // CHECK7-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3787 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 3788 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3789 // CHECK7: arraydestroy.body: 3790 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3791 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3792 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3793 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 3794 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 3795 // CHECK7: arraydestroy.done7: 3796 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 3797 // CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3798 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 3799 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] 3800 // CHECK7: arraydestroy.body9: 3801 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] 3802 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 3803 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] 3804 // CHECK7-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] 3805 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] 3806 // CHECK7: arraydestroy.done13: 3807 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3808 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 3809 // CHECK7-NEXT: ret i32 [[TMP11]] 3810 // 3811 // 3812 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3813 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3814 // CHECK7-NEXT: entry: 3815 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3816 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3817 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3818 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3819 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3820 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3821 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 3822 // CHECK7-NEXT: ret void 3823 // 3824 // 3825 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3826 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3827 // CHECK7-NEXT: entry: 3828 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3829 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3830 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3831 // CHECK7-NEXT: ret void 3832 // 3833 // 3834 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3835 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3836 // CHECK7-NEXT: entry: 3837 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3838 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3839 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3840 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3841 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3842 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3843 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3844 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3845 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3846 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3847 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 3848 // CHECK7-NEXT: ret void 3849 // 3850 // 3851 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3852 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3853 // CHECK7-NEXT: entry: 3854 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3855 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3856 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3857 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3858 // CHECK7-NEXT: ret void 3859 // 3860 // 3861 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3862 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3863 // CHECK7-NEXT: entry: 3864 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3865 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3866 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3867 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3868 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3869 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3870 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3871 // CHECK7-NEXT: ret void 3872 // 3873 // 3874 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3875 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3876 // CHECK7-NEXT: entry: 3877 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3878 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3879 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3880 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3881 // CHECK7-NEXT: ret void 3882 // 3883 // 3884 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3885 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3886 // CHECK7-NEXT: entry: 3887 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3888 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3889 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3890 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3891 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3892 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3893 // CHECK7-NEXT: ret void 3894 // 3895 // 3896 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3897 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3898 // CHECK7-NEXT: entry: 3899 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3900 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3901 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3902 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3903 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3904 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3905 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3906 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3907 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3908 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3909 // CHECK7-NEXT: ret void 3910 // 3911 // 3912 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3913 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3914 // CHECK7-NEXT: entry: 3915 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3916 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3917 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3918 // CHECK7-NEXT: ret void 3919 // 3920 // 3921 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 3922 // CHECK7-SAME: () #[[ATTR0]] { 3923 // CHECK7-NEXT: entry: 3924 // CHECK7-NEXT: call void @__cxx_global_var_init() 3925 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 3926 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 3927 // CHECK7-NEXT: ret void 3928 // 3929 // 3930 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init 3931 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 3932 // CHECK8-NEXT: entry: 3933 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3934 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3935 // CHECK8-NEXT: ret void 3936 // 3937 // 3938 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3939 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3940 // CHECK8-NEXT: entry: 3941 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3942 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3943 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3944 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3945 // CHECK8-NEXT: ret void 3946 // 3947 // 3948 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3949 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3950 // CHECK8-NEXT: entry: 3951 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3952 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3953 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3954 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3955 // CHECK8-NEXT: ret void 3956 // 3957 // 3958 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3959 // CHECK8-SAME: () #[[ATTR0]] { 3960 // CHECK8-NEXT: entry: 3961 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 3962 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 3963 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3964 // CHECK8-NEXT: ret void 3965 // 3966 // 3967 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3968 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3969 // CHECK8-NEXT: entry: 3970 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3971 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3972 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3973 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3974 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3975 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3976 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3977 // CHECK8-NEXT: ret void 3978 // 3979 // 3980 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3981 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3982 // CHECK8-NEXT: entry: 3983 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 3984 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 3985 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3986 // CHECK8: arraydestroy.body: 3987 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3988 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3989 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3990 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3991 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3992 // CHECK8: arraydestroy.done1: 3993 // CHECK8-NEXT: ret void 3994 // 3995 // 3996 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3997 // CHECK8-SAME: () #[[ATTR0]] { 3998 // CHECK8-NEXT: entry: 3999 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4000 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4001 // CHECK8-NEXT: ret void 4002 // 4003 // 4004 // CHECK8-LABEL: define {{[^@]+}}@main 4005 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] { 4006 // CHECK8-NEXT: entry: 4007 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4008 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 4009 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4010 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 4011 // CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 4012 // CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 4013 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 4014 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 4015 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 4016 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 4017 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 4018 // CHECK8: arrayctor.loop: 4019 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 4020 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 4021 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 4022 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 4023 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 4024 // CHECK8: arrayctor.cont: 4025 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) 4026 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 4027 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 4028 // CHECK8: for.cond: 4029 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 4030 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 4031 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4032 // CHECK8: for.body: 4033 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 4034 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 4035 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP2]] 4036 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 4037 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 4038 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP3]] 4039 // CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 4040 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast %struct.S* [[VAR]] to i8* 4041 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 [[TMP5]], i32 4, i1 false) 4042 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 4043 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[SIVAR]], align 4 4044 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP6]] 4045 // CHECK8-NEXT: store i32 [[ADD]], i32* [[SIVAR]], align 4 4046 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 4047 // CHECK8: for.inc: 4048 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 4049 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 4050 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 4051 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 4052 // CHECK8: for.end: 4053 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 4054 // CHECK8-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 4055 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 4056 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4057 // CHECK8: arraydestroy.body: 4058 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4059 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4060 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4061 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 4062 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 4063 // CHECK8: arraydestroy.done3: 4064 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 4065 // CHECK8-NEXT: ret i32 [[CALL]] 4066 // 4067 // 4068 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4069 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { 4070 // CHECK8-NEXT: entry: 4071 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4072 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4073 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 4074 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4075 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 4076 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 4077 // CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 4078 // CHECK8-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 4079 // CHECK8-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 4080 // CHECK8-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 4081 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 4082 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 4083 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 4084 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 4085 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4086 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 4087 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4088 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 4089 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 4090 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 4091 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 4092 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 4093 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4094 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 4095 // CHECK8: arrayctor.loop: 4096 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 4097 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 4098 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 4099 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 4100 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 4101 // CHECK8: arrayctor.cont: 4102 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) 4103 // CHECK8-NEXT: store %struct.S.0* [[VAR4]], %struct.S.0** [[TMP]], align 4 4104 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 4105 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 4106 // CHECK8: for.cond: 4107 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 4108 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 2 4109 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4110 // CHECK8: for.body: 4111 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR1]], align 4 4112 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 4113 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP3]] 4114 // CHECK8-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 4115 // CHECK8-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 4116 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4117 // CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP5]] 4118 // CHECK8-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8* 4119 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[TMP4]] to i8* 4120 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 4, i1 false) 4121 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 4122 // CHECK8: for.inc: 4123 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 4124 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 4125 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 4126 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 4127 // CHECK8: for.end: 4128 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 4129 // CHECK8-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 4130 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 4131 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4132 // CHECK8: arraydestroy.body: 4133 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4134 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4135 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4136 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 4137 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 4138 // CHECK8: arraydestroy.done7: 4139 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 4140 // CHECK8-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4141 // CHECK8-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 4142 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY9:%.*]] 4143 // CHECK8: arraydestroy.body9: 4144 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST10:%.*]] = phi %struct.S.0* [ [[TMP10]], [[ARRAYDESTROY_DONE7]] ], [ [[ARRAYDESTROY_ELEMENT11:%.*]], [[ARRAYDESTROY_BODY9]] ] 4145 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT11]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST10]], i32 -1 4146 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT11]]) #[[ATTR2]] 4147 // CHECK8-NEXT: [[ARRAYDESTROY_DONE12:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT11]], [[ARRAY_BEGIN8]] 4148 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE12]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY9]] 4149 // CHECK8: arraydestroy.done13: 4150 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 4151 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[RETVAL]], align 4 4152 // CHECK8-NEXT: ret i32 [[TMP11]] 4153 // 4154 // 4155 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4156 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4157 // CHECK8-NEXT: entry: 4158 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4159 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4160 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4161 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4162 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4163 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4164 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 4165 // CHECK8-NEXT: ret void 4166 // 4167 // 4168 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4169 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4170 // CHECK8-NEXT: entry: 4171 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4172 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4173 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4174 // CHECK8-NEXT: ret void 4175 // 4176 // 4177 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4178 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4179 // CHECK8-NEXT: entry: 4180 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4181 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4182 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4183 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4184 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4185 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4186 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4187 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4188 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4189 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4190 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 4191 // CHECK8-NEXT: ret void 4192 // 4193 // 4194 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4195 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4196 // CHECK8-NEXT: entry: 4197 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4198 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4199 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4200 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 4201 // CHECK8-NEXT: ret void 4202 // 4203 // 4204 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4205 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4206 // CHECK8-NEXT: entry: 4207 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4208 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4209 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4210 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4211 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4212 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4213 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 4214 // CHECK8-NEXT: ret void 4215 // 4216 // 4217 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4218 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4219 // CHECK8-NEXT: entry: 4220 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4221 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4222 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4223 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4224 // CHECK8-NEXT: ret void 4225 // 4226 // 4227 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4228 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4229 // CHECK8-NEXT: entry: 4230 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4231 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4232 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4233 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4234 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4235 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4236 // CHECK8-NEXT: ret void 4237 // 4238 // 4239 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4240 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4241 // CHECK8-NEXT: entry: 4242 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4243 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4244 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4245 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4246 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4247 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4248 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4249 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4250 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4251 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4252 // CHECK8-NEXT: ret void 4253 // 4254 // 4255 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4256 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4257 // CHECK8-NEXT: entry: 4258 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4259 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4260 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4261 // CHECK8-NEXT: ret void 4262 // 4263 // 4264 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 4265 // CHECK8-SAME: () #[[ATTR0]] { 4266 // CHECK8-NEXT: entry: 4267 // CHECK8-NEXT: call void @__cxx_global_var_init() 4268 // CHECK8-NEXT: call void @__cxx_global_var_init.1() 4269 // CHECK8-NEXT: call void @__cxx_global_var_init.2() 4270 // CHECK8-NEXT: ret void 4271 // 4272 // 4273 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 4274 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 4275 // CHECK9-NEXT: entry: 4276 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4277 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4278 // CHECK9-NEXT: ret void 4279 // 4280 // 4281 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4282 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4283 // CHECK9-NEXT: entry: 4284 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4285 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4286 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4287 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4288 // CHECK9-NEXT: ret void 4289 // 4290 // 4291 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4292 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4293 // CHECK9-NEXT: entry: 4294 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4295 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4296 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4297 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4298 // CHECK9-NEXT: ret void 4299 // 4300 // 4301 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4302 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4303 // CHECK9-NEXT: entry: 4304 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4305 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4306 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4307 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4308 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4309 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4310 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 4311 // CHECK9-NEXT: ret void 4312 // 4313 // 4314 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4315 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4316 // CHECK9-NEXT: entry: 4317 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4318 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4319 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4320 // CHECK9-NEXT: ret void 4321 // 4322 // 4323 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4324 // CHECK9-SAME: () #[[ATTR0]] { 4325 // CHECK9-NEXT: entry: 4326 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4327 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4328 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4329 // CHECK9-NEXT: ret void 4330 // 4331 // 4332 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4333 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4334 // CHECK9-NEXT: entry: 4335 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4336 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4337 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4338 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4339 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4340 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4341 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4342 // CHECK9-NEXT: ret void 4343 // 4344 // 4345 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4346 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4347 // CHECK9-NEXT: entry: 4348 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4349 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4350 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4351 // CHECK9: arraydestroy.body: 4352 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4353 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4354 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4355 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4356 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4357 // CHECK9: arraydestroy.done1: 4358 // CHECK9-NEXT: ret void 4359 // 4360 // 4361 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4362 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4363 // CHECK9-NEXT: entry: 4364 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4365 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4366 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4367 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4368 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4369 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4370 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4371 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4372 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4373 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4374 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 4375 // CHECK9-NEXT: ret void 4376 // 4377 // 4378 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4379 // CHECK9-SAME: () #[[ATTR0]] { 4380 // CHECK9-NEXT: entry: 4381 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4382 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4383 // CHECK9-NEXT: ret void 4384 // 4385 // 4386 // CHECK9-LABEL: define {{[^@]+}}@main 4387 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 4388 // CHECK9-NEXT: entry: 4389 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4390 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 4391 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 4392 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 4393 // CHECK9-NEXT: ret i32 0 4394 // 4395 // 4396 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 4397 // CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 4398 // CHECK9-NEXT: entry: 4399 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4400 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4401 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4402 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4403 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 4404 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4405 // CHECK9-NEXT: ret void 4406 // 4407 // 4408 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 4409 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 4410 // CHECK9-NEXT: entry: 4411 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4412 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4413 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4414 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4415 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 4416 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 4417 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 4418 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4419 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4420 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 4421 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 4422 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 4423 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 4424 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4425 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4426 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4427 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 4428 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 4429 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 4430 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4431 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4432 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 4433 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4434 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4435 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4436 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4437 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 4438 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4439 // CHECK9: cond.true: 4440 // CHECK9-NEXT: br label [[COND_END:%.*]] 4441 // CHECK9: cond.false: 4442 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4443 // CHECK9-NEXT: br label [[COND_END]] 4444 // CHECK9: cond.end: 4445 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4446 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 4447 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 4448 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4449 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4450 // CHECK9: omp.inner.for.cond: 4451 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4452 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4453 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4454 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4455 // CHECK9: omp.inner.for.body: 4456 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 4457 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 4458 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4459 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 4460 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) 4461 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4462 // CHECK9: omp.inner.for.inc: 4463 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4464 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4465 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 4466 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4467 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4468 // CHECK9: omp.inner.for.end: 4469 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4470 // CHECK9: omp.loop.exit: 4471 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4472 // CHECK9-NEXT: ret void 4473 // 4474 // 4475 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 4476 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { 4477 // CHECK9-NEXT: entry: 4478 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4479 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4480 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 4481 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 4482 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4483 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4484 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 4485 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4486 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4487 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4488 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4489 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 4490 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 4491 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 4492 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 4493 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4494 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 4495 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4496 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4497 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 4498 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 4499 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 4500 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4501 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4502 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 4503 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 4504 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 4505 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 4506 // CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 4507 // CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 4508 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4509 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4510 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8 4511 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4512 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 4513 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4514 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4515 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 4516 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4517 // CHECK9: cond.true: 4518 // CHECK9-NEXT: br label [[COND_END:%.*]] 4519 // CHECK9: cond.false: 4520 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4521 // CHECK9-NEXT: br label [[COND_END]] 4522 // CHECK9: cond.end: 4523 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4524 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4525 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4526 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 4527 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4528 // CHECK9: omp.inner.for.cond: 4529 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4530 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4531 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4532 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4533 // CHECK9: omp.inner.for.body: 4534 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4535 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 4536 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4537 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4538 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4 4539 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 4540 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 4541 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 4542 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 4543 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 4544 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 4545 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 4546 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 4547 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 4548 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 4549 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 4550 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4551 // CHECK9: omp.body.continue: 4552 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4553 // CHECK9: omp.inner.for.inc: 4554 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4555 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 4556 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 4557 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4558 // CHECK9: omp.inner.for.end: 4559 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4560 // CHECK9: omp.loop.exit: 4561 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 4562 // CHECK9-NEXT: ret void 4563 // 4564 // 4565 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 4566 // CHECK9-SAME: () #[[ATTR0]] { 4567 // CHECK9-NEXT: entry: 4568 // CHECK9-NEXT: call void @__cxx_global_var_init() 4569 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 4570 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 4571 // CHECK9-NEXT: ret void 4572 // 4573 // 4574 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4575 // CHECK9-SAME: () #[[ATTR0]] { 4576 // CHECK9-NEXT: entry: 4577 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 4578 // CHECK9-NEXT: ret void 4579 // 4580 // 4581 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init 4582 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 4583 // CHECK10-NEXT: entry: 4584 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4585 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4586 // CHECK10-NEXT: ret void 4587 // 4588 // 4589 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4590 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4591 // CHECK10-NEXT: entry: 4592 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4593 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4594 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4595 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4596 // CHECK10-NEXT: ret void 4597 // 4598 // 4599 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4600 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4601 // CHECK10-NEXT: entry: 4602 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4603 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4604 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4605 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4606 // CHECK10-NEXT: ret void 4607 // 4608 // 4609 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4610 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4611 // CHECK10-NEXT: entry: 4612 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4613 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4614 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4615 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4616 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4617 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4618 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 4619 // CHECK10-NEXT: ret void 4620 // 4621 // 4622 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4623 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4624 // CHECK10-NEXT: entry: 4625 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4626 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4627 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4628 // CHECK10-NEXT: ret void 4629 // 4630 // 4631 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4632 // CHECK10-SAME: () #[[ATTR0]] { 4633 // CHECK10-NEXT: entry: 4634 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4635 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4636 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4637 // CHECK10-NEXT: ret void 4638 // 4639 // 4640 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4641 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4642 // CHECK10-NEXT: entry: 4643 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4644 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4645 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4646 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4647 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4648 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4649 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4650 // CHECK10-NEXT: ret void 4651 // 4652 // 4653 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4654 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4655 // CHECK10-NEXT: entry: 4656 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4657 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4658 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4659 // CHECK10: arraydestroy.body: 4660 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4661 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4662 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4663 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4664 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4665 // CHECK10: arraydestroy.done1: 4666 // CHECK10-NEXT: ret void 4667 // 4668 // 4669 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4670 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4671 // CHECK10-NEXT: entry: 4672 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4673 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4674 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4675 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4676 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4677 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4678 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4679 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4680 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4681 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4682 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 4683 // CHECK10-NEXT: ret void 4684 // 4685 // 4686 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4687 // CHECK10-SAME: () #[[ATTR0]] { 4688 // CHECK10-NEXT: entry: 4689 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4690 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4691 // CHECK10-NEXT: ret void 4692 // 4693 // 4694 // CHECK10-LABEL: define {{[^@]+}}@main 4695 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 4696 // CHECK10-NEXT: entry: 4697 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4698 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 4699 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 4700 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 4701 // CHECK10-NEXT: ret i32 0 4702 // 4703 // 4704 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 4705 // CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 4706 // CHECK10-NEXT: entry: 4707 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4708 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4709 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4710 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4711 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 4712 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4713 // CHECK10-NEXT: ret void 4714 // 4715 // 4716 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 4717 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 4718 // CHECK10-NEXT: entry: 4719 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4720 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4721 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4722 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 4723 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 4724 // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 4725 // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 4726 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4727 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4728 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4 4729 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4 4730 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 4731 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 4732 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 4733 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4734 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4735 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8 4736 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 4737 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 4738 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4739 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4740 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 4741 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4742 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4743 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4744 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4745 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 4746 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4747 // CHECK10: cond.true: 4748 // CHECK10-NEXT: br label [[COND_END:%.*]] 4749 // CHECK10: cond.false: 4750 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4751 // CHECK10-NEXT: br label [[COND_END]] 4752 // CHECK10: cond.end: 4753 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4754 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 4755 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 4756 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4757 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4758 // CHECK10: omp.inner.for.cond: 4759 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4760 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4761 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4762 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4763 // CHECK10: omp.inner.for.body: 4764 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 4765 // CHECK10-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 4766 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 4767 // CHECK10-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 4768 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) 4769 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4770 // CHECK10: omp.inner.for.inc: 4771 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4772 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4773 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 4774 // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4775 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 4776 // CHECK10: omp.inner.for.end: 4777 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4778 // CHECK10: omp.loop.exit: 4779 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4780 // CHECK10-NEXT: ret void 4781 // 4782 // 4783 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 4784 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { 4785 // CHECK10-NEXT: entry: 4786 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4787 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4788 // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 4789 // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 4790 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4791 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 4792 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 4793 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4794 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4795 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4796 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4797 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4 4798 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4 4799 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 4800 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 4801 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 4802 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 4803 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4804 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4805 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 4806 // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 4807 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8 4808 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4809 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4810 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 4811 // CHECK10-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 4812 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 4813 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 4814 // CHECK10-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 4815 // CHECK10-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 4816 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4817 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4818 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8 4819 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4820 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 4821 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4822 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4823 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 4824 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4825 // CHECK10: cond.true: 4826 // CHECK10-NEXT: br label [[COND_END:%.*]] 4827 // CHECK10: cond.false: 4828 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4829 // CHECK10-NEXT: br label [[COND_END]] 4830 // CHECK10: cond.end: 4831 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4832 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4833 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4834 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 4835 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4836 // CHECK10: omp.inner.for.cond: 4837 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4838 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4839 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 4840 // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4841 // CHECK10: omp.inner.for.body: 4842 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4843 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 4844 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4845 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4846 // CHECK10-NEXT: store i32 1, i32* [[G]], align 4 4847 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 4848 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 4849 // CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4 4850 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 4851 // CHECK10-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 4852 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 4853 // CHECK10-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 4854 // CHECK10-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 4855 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 4856 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 4857 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 4858 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4859 // CHECK10: omp.body.continue: 4860 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4861 // CHECK10: omp.inner.for.inc: 4862 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4863 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 4864 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 4865 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 4866 // CHECK10: omp.inner.for.end: 4867 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4868 // CHECK10: omp.loop.exit: 4869 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 4870 // CHECK10-NEXT: ret void 4871 // 4872 // 4873 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 4874 // CHECK10-SAME: () #[[ATTR0]] { 4875 // CHECK10-NEXT: entry: 4876 // CHECK10-NEXT: call void @__cxx_global_var_init() 4877 // CHECK10-NEXT: call void @__cxx_global_var_init.1() 4878 // CHECK10-NEXT: call void @__cxx_global_var_init.2() 4879 // CHECK10-NEXT: ret void 4880 // 4881 // 4882 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4883 // CHECK10-SAME: () #[[ATTR0]] { 4884 // CHECK10-NEXT: entry: 4885 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 4886 // CHECK10-NEXT: ret void 4887 // 4888 // 4889 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 4890 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 4891 // CHECK11-NEXT: entry: 4892 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4893 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4894 // CHECK11-NEXT: ret void 4895 // 4896 // 4897 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4898 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4899 // CHECK11-NEXT: entry: 4900 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4901 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4902 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4903 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4904 // CHECK11-NEXT: ret void 4905 // 4906 // 4907 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4908 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4909 // CHECK11-NEXT: entry: 4910 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4911 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4912 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4913 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4914 // CHECK11-NEXT: ret void 4915 // 4916 // 4917 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4918 // CHECK11-SAME: () #[[ATTR0]] { 4919 // CHECK11-NEXT: entry: 4920 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4921 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4922 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4923 // CHECK11-NEXT: ret void 4924 // 4925 // 4926 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4927 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4928 // CHECK11-NEXT: entry: 4929 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4930 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4931 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4932 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4933 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4934 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4935 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4936 // CHECK11-NEXT: ret void 4937 // 4938 // 4939 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4940 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4941 // CHECK11-NEXT: entry: 4942 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4943 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4944 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4945 // CHECK11: arraydestroy.body: 4946 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4947 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4948 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4949 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4950 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4951 // CHECK11: arraydestroy.done1: 4952 // CHECK11-NEXT: ret void 4953 // 4954 // 4955 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4956 // CHECK11-SAME: () #[[ATTR0]] { 4957 // CHECK11-NEXT: entry: 4958 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4959 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4960 // CHECK11-NEXT: ret void 4961 // 4962 // 4963 // CHECK11-LABEL: define {{[^@]+}}@main 4964 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 4965 // CHECK11-NEXT: entry: 4966 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4967 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 4968 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 4969 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 4970 // CHECK11-NEXT: ret i32 0 4971 // 4972 // 4973 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4974 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4975 // CHECK11-NEXT: entry: 4976 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4977 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4978 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4979 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4980 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4981 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4982 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 4983 // CHECK11-NEXT: ret void 4984 // 4985 // 4986 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4987 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4988 // CHECK11-NEXT: entry: 4989 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4990 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4991 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4992 // CHECK11-NEXT: ret void 4993 // 4994 // 4995 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4996 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4997 // CHECK11-NEXT: entry: 4998 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4999 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5000 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5001 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5002 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5003 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5004 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5005 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5006 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5007 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5008 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 5009 // CHECK11-NEXT: ret void 5010 // 5011 // 5012 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 5013 // CHECK11-SAME: () #[[ATTR0]] { 5014 // CHECK11-NEXT: entry: 5015 // CHECK11-NEXT: call void @__cxx_global_var_init() 5016 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 5017 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 5018 // CHECK11-NEXT: ret void 5019 // 5020 // 5021 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init 5022 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 5023 // CHECK12-NEXT: entry: 5024 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 5025 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 5026 // CHECK12-NEXT: ret void 5027 // 5028 // 5029 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 5030 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 5031 // CHECK12-NEXT: entry: 5032 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5033 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5034 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5035 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 5036 // CHECK12-NEXT: ret void 5037 // 5038 // 5039 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 5040 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5041 // CHECK12-NEXT: entry: 5042 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5043 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5044 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5045 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 5046 // CHECK12-NEXT: ret void 5047 // 5048 // 5049 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5050 // CHECK12-SAME: () #[[ATTR0]] { 5051 // CHECK12-NEXT: entry: 5052 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 5053 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 5054 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5055 // CHECK12-NEXT: ret void 5056 // 5057 // 5058 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5059 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5060 // CHECK12-NEXT: entry: 5061 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5062 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5063 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5064 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5065 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5066 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5067 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 5068 // CHECK12-NEXT: ret void 5069 // 5070 // 5071 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5072 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 5073 // CHECK12-NEXT: entry: 5074 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 5075 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 5076 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5077 // CHECK12: arraydestroy.body: 5078 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5079 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5080 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5081 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5082 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5083 // CHECK12: arraydestroy.done1: 5084 // CHECK12-NEXT: ret void 5085 // 5086 // 5087 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5088 // CHECK12-SAME: () #[[ATTR0]] { 5089 // CHECK12-NEXT: entry: 5090 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 5091 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5092 // CHECK12-NEXT: ret void 5093 // 5094 // 5095 // CHECK12-LABEL: define {{[^@]+}}@main 5096 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 5097 // CHECK12-NEXT: entry: 5098 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5099 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5100 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 5101 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 5102 // CHECK12-NEXT: ret i32 0 5103 // 5104 // 5105 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5106 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5107 // CHECK12-NEXT: entry: 5108 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5109 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5110 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5111 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5112 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5113 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5114 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 5115 // CHECK12-NEXT: ret void 5116 // 5117 // 5118 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5119 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5120 // CHECK12-NEXT: entry: 5121 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5122 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5123 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5124 // CHECK12-NEXT: ret void 5125 // 5126 // 5127 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5128 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5129 // CHECK12-NEXT: entry: 5130 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5131 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5132 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5133 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5134 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5135 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5136 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5137 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5138 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5139 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5140 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 5141 // CHECK12-NEXT: ret void 5142 // 5143 // 5144 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 5145 // CHECK12-SAME: () #[[ATTR0]] { 5146 // CHECK12-NEXT: entry: 5147 // CHECK12-NEXT: call void @__cxx_global_var_init() 5148 // CHECK12-NEXT: call void @__cxx_global_var_init.1() 5149 // CHECK12-NEXT: call void @__cxx_global_var_init.2() 5150 // CHECK12-NEXT: ret void 5151 // 5152