1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute parallel for private(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute parallel for private(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global, bound tid and loop vars 80 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 85 // Skip global, bound tid and loop vars 86 [&]() { 87 g = 2; 88 g1 = 2; 89 sivar = 4; 90 91 }(); 92 } 93 }(); 94 return 0; 95 #else 96 #pragma omp target 97 #pragma omp teams distribute parallel for private(t_var, vec, s_arr, var, sivar) 98 for (int i = 0; i < 2; ++i) { 99 vec[i] = t_var; 100 s_arr[i] = var; 101 sivar += i; 102 } 103 return tmain<int>(); 104 #endif 105 } 106 107 108 109 // Skip global, bound tid and loop vars 110 111 // private(s_arr) 112 113 // private(var) 114 115 116 // Skip global, bound tid and loop vars 117 118 // private(s_arr) 119 120 // private(var) 121 122 123 124 125 // Skip global, bound tid and loop vars 126 127 // private(s_arr) 128 129 130 // private(var) 131 132 133 // Skip global, bound tid and loop vars 134 // prev lb and ub 135 // iter variables 136 137 // private(s_arr) 138 139 140 // private(var) 141 142 143 144 #endif 145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 147 // CHECK1-NEXT: entry: 148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 154 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 157 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 164 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 170 // CHECK1-NEXT: ret void 171 // 172 // 173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 174 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 175 // CHECK1-NEXT: entry: 176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 177 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 178 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 182 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 183 // CHECK1-NEXT: ret void 184 // 185 // 186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 187 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 188 // CHECK1-NEXT: entry: 189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 190 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 196 // CHECK1-SAME: () #[[ATTR0]] { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 201 // CHECK1-NEXT: ret void 202 // 203 // 204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 205 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 206 // CHECK1-NEXT: entry: 207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 209 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 210 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 211 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 214 // CHECK1-NEXT: ret void 215 // 216 // 217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 218 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 219 // CHECK1-NEXT: entry: 220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 221 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 223 // CHECK1: arraydestroy.body: 224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 229 // CHECK1: arraydestroy.done1: 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 234 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 238 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 239 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 246 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 247 // CHECK1-NEXT: ret void 248 // 249 // 250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 251 // CHECK1-SAME: () #[[ATTR0]] { 252 // CHECK1-NEXT: entry: 253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK1-LABEL: define {{[^@]+}}@main 259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 260 // CHECK1-NEXT: entry: 261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 262 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 263 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 264 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 265 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 266 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 267 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 268 // CHECK1: omp_offload.failed: 269 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 270 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 271 // CHECK1: omp_offload.cont: 272 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 273 // CHECK1-NEXT: ret i32 [[CALL]] 274 // 275 // 276 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 277 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 278 // CHECK1-NEXT: entry: 279 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 280 // CHECK1-NEXT: ret void 281 // 282 // 283 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 284 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 285 // CHECK1-NEXT: entry: 286 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 287 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 288 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 289 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 290 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 291 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 292 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 293 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 294 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 295 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 296 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 297 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 298 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 301 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 302 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 303 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 304 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 305 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 306 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 307 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 308 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 309 // CHECK1: arrayctor.loop: 310 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 311 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 312 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 313 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 314 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 315 // CHECK1: arrayctor.cont: 316 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 317 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 318 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 319 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 320 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 321 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 322 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 323 // CHECK1: cond.true: 324 // CHECK1-NEXT: br label [[COND_END:%.*]] 325 // CHECK1: cond.false: 326 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 327 // CHECK1-NEXT: br label [[COND_END]] 328 // CHECK1: cond.end: 329 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 330 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 331 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 332 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 333 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 334 // CHECK1: omp.inner.for.cond: 335 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 336 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 337 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 338 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 339 // CHECK1: omp.inner.for.cond.cleanup: 340 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 341 // CHECK1: omp.inner.for.body: 342 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 343 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 344 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 345 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 346 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) 347 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 348 // CHECK1: omp.inner.for.inc: 349 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 350 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 351 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 352 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 353 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 354 // CHECK1: omp.inner.for.end: 355 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 356 // CHECK1: omp.loop.exit: 357 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 358 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 359 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) 360 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 361 // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 362 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i64 2 363 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 364 // CHECK1: arraydestroy.body: 365 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 366 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 367 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 368 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 369 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 370 // CHECK1: arraydestroy.done3: 371 // CHECK1-NEXT: ret void 372 // 373 // 374 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 375 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 376 // CHECK1-NEXT: entry: 377 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 378 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 379 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 380 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 381 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 383 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 384 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 385 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 386 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 387 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 388 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 389 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 390 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 391 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 392 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 393 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 394 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 395 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 396 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 398 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 399 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 400 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 401 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 402 // CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 403 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 404 // CHECK1-NEXT: store i32 [[CONV1]], i32* [[DOTOMP_UB]], align 4 405 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 406 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 407 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 408 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 409 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 410 // CHECK1: arrayctor.loop: 411 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 412 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 413 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1 414 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 415 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 416 // CHECK1: arrayctor.cont: 417 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 418 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 419 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 420 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 421 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 422 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 423 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 424 // CHECK1: cond.true: 425 // CHECK1-NEXT: br label [[COND_END:%.*]] 426 // CHECK1: cond.false: 427 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 428 // CHECK1-NEXT: br label [[COND_END]] 429 // CHECK1: cond.end: 430 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 431 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 432 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 433 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 434 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 435 // CHECK1: omp.inner.for.cond: 436 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 437 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 438 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 439 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 440 // CHECK1: omp.inner.for.cond.cleanup: 441 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 442 // CHECK1: omp.inner.for.body: 443 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 444 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 445 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 446 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 447 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 448 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 449 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 450 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 451 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 452 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 453 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 454 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM3]] 455 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX4]] to i8* 456 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 457 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) 458 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 459 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 460 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 461 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[SIVAR]], align 4 462 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 463 // CHECK1: omp.body.continue: 464 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 465 // CHECK1: omp.inner.for.inc: 466 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 467 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 468 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 470 // CHECK1: omp.inner.for.end: 471 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 472 // CHECK1: omp.loop.exit: 473 // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 474 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 475 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 476 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 477 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 478 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i64 2 479 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 480 // CHECK1: arraydestroy.body: 481 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 482 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 483 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 484 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 485 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 486 // CHECK1: arraydestroy.done8: 487 // CHECK1-NEXT: ret void 488 // 489 // 490 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 491 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 492 // CHECK1-NEXT: entry: 493 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 494 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 495 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 496 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 497 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 498 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 499 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 500 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 501 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 502 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 503 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 504 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 505 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 506 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 507 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 508 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 509 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 510 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 511 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 512 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 513 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 514 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 515 // CHECK1: omp_offload.failed: 516 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 517 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 518 // CHECK1: omp_offload.cont: 519 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 520 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 521 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 522 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 523 // CHECK1: arraydestroy.body: 524 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 525 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 526 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 527 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 528 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 529 // CHECK1: arraydestroy.done2: 530 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 531 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 532 // CHECK1-NEXT: ret i32 [[TMP4]] 533 // 534 // 535 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 536 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 537 // CHECK1-NEXT: entry: 538 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 539 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 540 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 541 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 542 // CHECK1-NEXT: ret void 543 // 544 // 545 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 546 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 547 // CHECK1-NEXT: entry: 548 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 549 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 550 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 551 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 552 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 553 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 554 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 555 // CHECK1-NEXT: ret void 556 // 557 // 558 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 559 // CHECK1-SAME: () #[[ATTR4]] { 560 // CHECK1-NEXT: entry: 561 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 562 // CHECK1-NEXT: ret void 563 // 564 // 565 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 566 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 567 // CHECK1-NEXT: entry: 568 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 569 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 570 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 571 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 572 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 573 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 574 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 575 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 576 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 577 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 578 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 579 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 580 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 581 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8 582 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 583 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 584 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 585 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 586 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 587 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 588 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 589 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 590 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 591 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 592 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 593 // CHECK1: arrayctor.loop: 594 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 595 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 596 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 597 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 598 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 599 // CHECK1: arrayctor.cont: 600 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 601 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8 602 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 603 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 604 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 605 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 606 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 607 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 608 // CHECK1: cond.true: 609 // CHECK1-NEXT: br label [[COND_END:%.*]] 610 // CHECK1: cond.false: 611 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 612 // CHECK1-NEXT: br label [[COND_END]] 613 // CHECK1: cond.end: 614 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 615 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 616 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 617 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 618 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 619 // CHECK1: omp.inner.for.cond: 620 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 621 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 622 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 623 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 624 // CHECK1: omp.inner.for.cond.cleanup: 625 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 626 // CHECK1: omp.inner.for.body: 627 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 628 // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 629 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 630 // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 631 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) 632 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 633 // CHECK1: omp.inner.for.inc: 634 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 635 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 636 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 637 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 638 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 639 // CHECK1: omp.inner.for.end: 640 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 641 // CHECK1: omp.loop.exit: 642 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 643 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 644 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP14]]) 645 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 646 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 647 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i64 2 648 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 649 // CHECK1: arraydestroy.body: 650 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 651 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 652 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 653 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 654 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 655 // CHECK1: arraydestroy.done5: 656 // CHECK1-NEXT: ret void 657 // 658 // 659 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 660 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 661 // CHECK1-NEXT: entry: 662 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 663 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 664 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 665 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 666 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 667 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 668 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 669 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 670 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 671 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 672 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 673 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 674 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 675 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 676 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 677 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca %struct.S.0*, align 8 678 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 679 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 680 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 681 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 682 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 683 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8 684 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 685 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 686 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 687 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 688 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 689 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 690 // CHECK1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 691 // CHECK1-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 692 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 693 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 694 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 695 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 696 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 697 // CHECK1: arrayctor.loop: 698 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 699 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 700 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1 701 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 702 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 703 // CHECK1: arrayctor.cont: 704 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 705 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP3]], align 8 706 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 707 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 708 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 709 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 710 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 711 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 712 // CHECK1: cond.true: 713 // CHECK1-NEXT: br label [[COND_END:%.*]] 714 // CHECK1: cond.false: 715 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 716 // CHECK1-NEXT: br label [[COND_END]] 717 // CHECK1: cond.end: 718 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 719 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 720 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 721 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 722 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 723 // CHECK1: omp.inner.for.cond: 724 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 725 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 726 // CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 727 // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 728 // CHECK1: omp.inner.for.cond.cleanup: 729 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 730 // CHECK1: omp.inner.for.body: 731 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 732 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 733 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 734 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 735 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 736 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 737 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 738 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 739 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 740 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP3]], align 8 741 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 742 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 743 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM5]] 744 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX6]] to i8* 745 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* 746 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) 747 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 748 // CHECK1: omp.body.continue: 749 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 750 // CHECK1: omp.inner.for.inc: 751 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 752 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], 1 753 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 754 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 755 // CHECK1: omp.inner.for.end: 756 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 757 // CHECK1: omp.loop.exit: 758 // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 759 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 760 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) 761 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 762 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 763 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 764 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 765 // CHECK1: arraydestroy.body: 766 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 767 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 768 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 769 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 770 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 771 // CHECK1: arraydestroy.done9: 772 // CHECK1-NEXT: ret void 773 // 774 // 775 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 776 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 777 // CHECK1-NEXT: entry: 778 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 779 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 780 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 781 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 782 // CHECK1-NEXT: ret void 783 // 784 // 785 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 786 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 787 // CHECK1-NEXT: entry: 788 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 789 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 790 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 791 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 792 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 793 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 794 // CHECK1-NEXT: ret void 795 // 796 // 797 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 798 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 799 // CHECK1-NEXT: entry: 800 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 801 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 802 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 803 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 804 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 805 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 806 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 807 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 808 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 809 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 810 // CHECK1-NEXT: ret void 811 // 812 // 813 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 814 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 815 // CHECK1-NEXT: entry: 816 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 817 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 818 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 819 // CHECK1-NEXT: ret void 820 // 821 // 822 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 823 // CHECK1-SAME: () #[[ATTR0]] { 824 // CHECK1-NEXT: entry: 825 // CHECK1-NEXT: call void @__cxx_global_var_init() 826 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 827 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 828 // CHECK1-NEXT: ret void 829 // 830 // 831 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 832 // CHECK1-SAME: () #[[ATTR0]] { 833 // CHECK1-NEXT: entry: 834 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 835 // CHECK1-NEXT: ret void 836 // 837 // 838 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 839 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 840 // CHECK3-NEXT: entry: 841 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 842 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 843 // CHECK3-NEXT: ret void 844 // 845 // 846 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 847 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 848 // CHECK3-NEXT: entry: 849 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 850 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 851 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 852 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 853 // CHECK3-NEXT: ret void 854 // 855 // 856 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 857 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 858 // CHECK3-NEXT: entry: 859 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 860 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 861 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 862 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 863 // CHECK3-NEXT: ret void 864 // 865 // 866 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 867 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 868 // CHECK3-NEXT: entry: 869 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 870 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 871 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 872 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 873 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 874 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 875 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 876 // CHECK3-NEXT: ret void 877 // 878 // 879 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 880 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 881 // CHECK3-NEXT: entry: 882 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 883 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 884 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 885 // CHECK3-NEXT: ret void 886 // 887 // 888 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 889 // CHECK3-SAME: () #[[ATTR0]] { 890 // CHECK3-NEXT: entry: 891 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 892 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 893 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 894 // CHECK3-NEXT: ret void 895 // 896 // 897 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 898 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 899 // CHECK3-NEXT: entry: 900 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 901 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 902 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 903 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 904 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 905 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 906 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 907 // CHECK3-NEXT: ret void 908 // 909 // 910 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 911 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 912 // CHECK3-NEXT: entry: 913 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 914 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 915 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 916 // CHECK3: arraydestroy.body: 917 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 918 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 919 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 920 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 921 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 922 // CHECK3: arraydestroy.done1: 923 // CHECK3-NEXT: ret void 924 // 925 // 926 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 927 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 928 // CHECK3-NEXT: entry: 929 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 930 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 931 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 932 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 933 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 934 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 935 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 936 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 937 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 938 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 939 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 940 // CHECK3-NEXT: ret void 941 // 942 // 943 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 944 // CHECK3-SAME: () #[[ATTR0]] { 945 // CHECK3-NEXT: entry: 946 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 947 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 948 // CHECK3-NEXT: ret void 949 // 950 // 951 // CHECK3-LABEL: define {{[^@]+}}@main 952 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 953 // CHECK3-NEXT: entry: 954 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 955 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 956 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 957 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 958 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 959 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 960 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 961 // CHECK3: omp_offload.failed: 962 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96() #[[ATTR2]] 963 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 964 // CHECK3: omp_offload.cont: 965 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 966 // CHECK3-NEXT: ret i32 [[CALL]] 967 // 968 // 969 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 970 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 971 // CHECK3-NEXT: entry: 972 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 973 // CHECK3-NEXT: ret void 974 // 975 // 976 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 977 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 978 // CHECK3-NEXT: entry: 979 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 980 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 981 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 982 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 983 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 984 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 985 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 986 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 987 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 988 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 989 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 990 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 991 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 992 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 993 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 994 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 995 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 996 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 997 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 998 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 999 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1000 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1001 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1002 // CHECK3: arrayctor.loop: 1003 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1004 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1005 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1006 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1007 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1008 // CHECK3: arrayctor.cont: 1009 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1010 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1011 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1012 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1013 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1014 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1015 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1016 // CHECK3: cond.true: 1017 // CHECK3-NEXT: br label [[COND_END:%.*]] 1018 // CHECK3: cond.false: 1019 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1020 // CHECK3-NEXT: br label [[COND_END]] 1021 // CHECK3: cond.end: 1022 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1023 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 1024 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1025 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1026 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1027 // CHECK3: omp.inner.for.cond: 1028 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1029 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1030 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1031 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1032 // CHECK3: omp.inner.for.cond.cleanup: 1033 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1034 // CHECK3: omp.inner.for.body: 1035 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1036 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1037 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) 1038 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1039 // CHECK3: omp.inner.for.inc: 1040 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1041 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1042 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 1043 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1044 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1045 // CHECK3: omp.inner.for.end: 1046 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1047 // CHECK3: omp.loop.exit: 1048 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1049 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1050 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) 1051 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1052 // CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1053 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN2]], i32 2 1054 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1055 // CHECK3: arraydestroy.body: 1056 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1057 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1058 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1059 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] 1060 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 1061 // CHECK3: arraydestroy.done3: 1062 // CHECK3-NEXT: ret void 1063 // 1064 // 1065 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 1066 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1067 // CHECK3-NEXT: entry: 1068 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1069 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1070 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1071 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1072 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1073 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1074 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1075 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1076 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1077 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1078 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1079 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1080 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1081 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1082 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1083 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1084 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1085 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1086 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 1087 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 1088 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1089 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1090 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 1091 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 1092 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 1093 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 1094 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1095 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1096 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1097 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1098 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1099 // CHECK3: arrayctor.loop: 1100 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1101 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1102 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1 1103 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1104 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1105 // CHECK3: arrayctor.cont: 1106 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1107 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1108 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1109 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1110 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1111 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1112 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1113 // CHECK3: cond.true: 1114 // CHECK3-NEXT: br label [[COND_END:%.*]] 1115 // CHECK3: cond.false: 1116 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1117 // CHECK3-NEXT: br label [[COND_END]] 1118 // CHECK3: cond.end: 1119 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1120 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1121 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1122 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1123 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1124 // CHECK3: omp.inner.for.cond: 1125 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1126 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1127 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1128 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1129 // CHECK3: omp.inner.for.cond.cleanup: 1130 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1131 // CHECK3: omp.inner.for.body: 1132 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1133 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1134 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1135 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1136 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 1137 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1138 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] 1139 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 1140 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 1141 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP12]] 1142 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1143 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 1144 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) 1145 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 1146 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[SIVAR]], align 4 1147 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] 1148 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4 1149 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1150 // CHECK3: omp.body.continue: 1151 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1152 // CHECK3: omp.inner.for.inc: 1153 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1154 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP17]], 1 1155 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4 1156 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1157 // CHECK3: omp.inner.for.end: 1158 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1159 // CHECK3: omp.loop.exit: 1160 // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1161 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 1162 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]]) 1163 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1164 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1165 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2 1166 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1167 // CHECK3: arraydestroy.body: 1168 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1169 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1170 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1171 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1172 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1173 // CHECK3: arraydestroy.done6: 1174 // CHECK3-NEXT: ret void 1175 // 1176 // 1177 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1178 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 1179 // CHECK3-NEXT: entry: 1180 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1181 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1182 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1183 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1184 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1185 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1186 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1187 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1188 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1189 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 1190 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1191 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1192 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1193 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 1194 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1195 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1196 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1197 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1198 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 1199 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 0) 1200 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 1201 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1202 // CHECK3: omp_offload.failed: 1203 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1204 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1205 // CHECK3: omp_offload.cont: 1206 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1207 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1208 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1209 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1210 // CHECK3: arraydestroy.body: 1211 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1212 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1213 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1214 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1215 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1216 // CHECK3: arraydestroy.done2: 1217 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1218 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4 1219 // CHECK3-NEXT: ret i32 [[TMP4]] 1220 // 1221 // 1222 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1223 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1224 // CHECK3-NEXT: entry: 1225 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1226 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1227 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1228 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1229 // CHECK3-NEXT: ret void 1230 // 1231 // 1232 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1233 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1234 // CHECK3-NEXT: entry: 1235 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1236 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1237 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1238 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1239 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1240 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1241 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1242 // CHECK3-NEXT: ret void 1243 // 1244 // 1245 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1246 // CHECK3-SAME: () #[[ATTR4]] { 1247 // CHECK3-NEXT: entry: 1248 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 1249 // CHECK3-NEXT: ret void 1250 // 1251 // 1252 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1253 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1254 // CHECK3-NEXT: entry: 1255 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1256 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1257 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1258 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1259 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1260 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1261 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1262 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1263 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1264 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1265 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1266 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1267 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1268 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 1269 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1270 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1271 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1272 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1273 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 1274 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 1275 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1276 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1277 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1278 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1279 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1280 // CHECK3: arrayctor.loop: 1281 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1282 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1283 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 1284 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1285 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1286 // CHECK3: arrayctor.cont: 1287 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1288 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 1289 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1290 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1291 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1292 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1293 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1294 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1295 // CHECK3: cond.true: 1296 // CHECK3-NEXT: br label [[COND_END:%.*]] 1297 // CHECK3: cond.false: 1298 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1299 // CHECK3-NEXT: br label [[COND_END]] 1300 // CHECK3: cond.end: 1301 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1302 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 1303 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1304 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1305 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1306 // CHECK3: omp.inner.for.cond: 1307 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1308 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1309 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1310 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1311 // CHECK3: omp.inner.for.cond.cleanup: 1312 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1313 // CHECK3: omp.inner.for.body: 1314 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1315 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1316 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP7]], i32 [[TMP8]]) 1317 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1318 // CHECK3: omp.inner.for.inc: 1319 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1320 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1321 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] 1322 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1323 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1324 // CHECK3: omp.inner.for.end: 1325 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1326 // CHECK3: omp.loop.exit: 1327 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1328 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1329 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP12]]) 1330 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1331 // CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1332 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN4]], i32 2 1333 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1334 // CHECK3: arraydestroy.body: 1335 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1336 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1337 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1338 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 1339 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1340 // CHECK3: arraydestroy.done5: 1341 // CHECK3-NEXT: ret void 1342 // 1343 // 1344 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 1345 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { 1346 // CHECK3-NEXT: entry: 1347 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1348 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1349 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 1350 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 1351 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1352 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1353 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 1354 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1355 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1356 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1357 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1358 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1359 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1360 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1361 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1362 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4 1363 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1364 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1365 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1366 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 1367 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 1368 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4 1369 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1370 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1371 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 1372 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 1373 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_LB]], align 4 1374 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_UB]], align 4 1375 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1376 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1377 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1378 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1379 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1380 // CHECK3: arrayctor.loop: 1381 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1382 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1383 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1 1384 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1385 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1386 // CHECK3: arrayctor.cont: 1387 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1388 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4 1389 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1390 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1391 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1392 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1393 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1394 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1395 // CHECK3: cond.true: 1396 // CHECK3-NEXT: br label [[COND_END:%.*]] 1397 // CHECK3: cond.false: 1398 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1399 // CHECK3-NEXT: br label [[COND_END]] 1400 // CHECK3: cond.end: 1401 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1402 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1403 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1404 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1405 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1406 // CHECK3: omp.inner.for.cond: 1407 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1408 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1409 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1410 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1411 // CHECK3: omp.inner.for.cond.cleanup: 1412 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1413 // CHECK3: omp.inner.for.body: 1414 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1415 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1416 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1417 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1418 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR]], align 4 1419 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 1420 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP11]] 1421 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[ARRAYIDX]], align 4 1422 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4 1423 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1424 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP13]] 1425 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1426 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* 1427 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) 1428 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1429 // CHECK3: omp.body.continue: 1430 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1431 // CHECK3: omp.inner.for.inc: 1432 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1433 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], 1 1434 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 1435 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1436 // CHECK3: omp.inner.for.end: 1437 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1438 // CHECK3: omp.loop.exit: 1439 // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1440 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 1441 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]]) 1442 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1443 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1444 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2 1445 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1446 // CHECK3: arraydestroy.body: 1447 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1448 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1449 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1450 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1451 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1452 // CHECK3: arraydestroy.done7: 1453 // CHECK3-NEXT: ret void 1454 // 1455 // 1456 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1457 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1458 // CHECK3-NEXT: entry: 1459 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1460 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1461 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1462 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1463 // CHECK3-NEXT: ret void 1464 // 1465 // 1466 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1467 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1468 // CHECK3-NEXT: entry: 1469 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1470 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1471 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1472 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1473 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1474 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1475 // CHECK3-NEXT: ret void 1476 // 1477 // 1478 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1479 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1480 // CHECK3-NEXT: entry: 1481 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1482 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1483 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1484 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1485 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1486 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1487 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1488 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1489 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1490 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1491 // CHECK3-NEXT: ret void 1492 // 1493 // 1494 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1495 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1496 // CHECK3-NEXT: entry: 1497 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1498 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1499 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1500 // CHECK3-NEXT: ret void 1501 // 1502 // 1503 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 1504 // CHECK3-SAME: () #[[ATTR0]] { 1505 // CHECK3-NEXT: entry: 1506 // CHECK3-NEXT: call void @__cxx_global_var_init() 1507 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1508 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1509 // CHECK3-NEXT: ret void 1510 // 1511 // 1512 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1513 // CHECK3-SAME: () #[[ATTR0]] { 1514 // CHECK3-NEXT: entry: 1515 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1516 // CHECK3-NEXT: ret void 1517 // 1518 // 1519 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1520 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1521 // CHECK9-NEXT: entry: 1522 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1523 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1524 // CHECK9-NEXT: ret void 1525 // 1526 // 1527 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1528 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1529 // CHECK9-NEXT: entry: 1530 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1531 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1532 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1533 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1534 // CHECK9-NEXT: ret void 1535 // 1536 // 1537 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1538 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1539 // CHECK9-NEXT: entry: 1540 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1541 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1542 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1543 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1544 // CHECK9-NEXT: ret void 1545 // 1546 // 1547 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1548 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1549 // CHECK9-NEXT: entry: 1550 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1551 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1552 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1553 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1554 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1555 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1556 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 1557 // CHECK9-NEXT: ret void 1558 // 1559 // 1560 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1561 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1562 // CHECK9-NEXT: entry: 1563 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1564 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1565 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1566 // CHECK9-NEXT: ret void 1567 // 1568 // 1569 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1570 // CHECK9-SAME: () #[[ATTR0]] { 1571 // CHECK9-NEXT: entry: 1572 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 1573 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 1574 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1575 // CHECK9-NEXT: ret void 1576 // 1577 // 1578 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1579 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1580 // CHECK9-NEXT: entry: 1581 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1582 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1583 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1584 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1585 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1586 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1587 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1588 // CHECK9-NEXT: ret void 1589 // 1590 // 1591 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1592 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1593 // CHECK9-NEXT: entry: 1594 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1595 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1596 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1597 // CHECK9: arraydestroy.body: 1598 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1599 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1600 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1601 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1602 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1603 // CHECK9: arraydestroy.done1: 1604 // CHECK9-NEXT: ret void 1605 // 1606 // 1607 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1608 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1609 // CHECK9-NEXT: entry: 1610 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1611 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1612 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1613 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1614 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1615 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1616 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1617 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1618 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1619 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1620 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 1621 // CHECK9-NEXT: ret void 1622 // 1623 // 1624 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1625 // CHECK9-SAME: () #[[ATTR0]] { 1626 // CHECK9-NEXT: entry: 1627 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1628 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1629 // CHECK9-NEXT: ret void 1630 // 1631 // 1632 // CHECK9-LABEL: define {{[^@]+}}@main 1633 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 1634 // CHECK9-NEXT: entry: 1635 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1636 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1637 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 1638 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1639 // CHECK9-NEXT: ret i32 0 1640 // 1641 // 1642 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 1643 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 1644 // CHECK9-NEXT: entry: 1645 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 1646 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 1647 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 1648 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 1649 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 1650 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1651 // CHECK9-NEXT: ret void 1652 // 1653 // 1654 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 1655 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 1656 // CHECK9-NEXT: entry: 1657 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1658 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1659 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1660 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1661 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 1662 // CHECK9-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 1663 // CHECK9-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 1664 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1665 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1666 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 1667 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 1668 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8 1669 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1670 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1671 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1672 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1673 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 1674 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 1675 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_COMB_UB]], align 4 1676 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1677 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1678 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8 1679 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1680 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1681 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1682 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1683 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1684 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1685 // CHECK9: cond.true: 1686 // CHECK9-NEXT: br label [[COND_END:%.*]] 1687 // CHECK9: cond.false: 1688 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1689 // CHECK9-NEXT: br label [[COND_END]] 1690 // CHECK9: cond.end: 1691 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1692 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 1693 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1694 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1695 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1696 // CHECK9: omp.inner.for.cond: 1697 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1698 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1699 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1700 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1701 // CHECK9: omp.inner.for.body: 1702 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 1703 // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 1704 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 1705 // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 1706 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP8]], i64 [[TMP10]]) 1707 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1708 // CHECK9: omp.inner.for.inc: 1709 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1710 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1711 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] 1712 // CHECK9-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1713 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1714 // CHECK9: omp.inner.for.end: 1715 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1716 // CHECK9: omp.loop.exit: 1717 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 1718 // CHECK9-NEXT: ret void 1719 // 1720 // 1721 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 1722 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] { 1723 // CHECK9-NEXT: entry: 1724 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1725 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1726 // CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 1727 // CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 1728 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1729 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1730 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 1731 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1732 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1733 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1734 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1735 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 1736 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 1737 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 1738 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1739 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1740 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1741 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1742 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1743 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1744 // CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1745 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8 1746 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1747 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1748 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 1749 // CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 1750 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 1751 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 1752 // CHECK9-NEXT: store i32 [[CONV]], i32* [[DOTOMP_LB]], align 4 1753 // CHECK9-NEXT: store i32 [[CONV2]], i32* [[DOTOMP_UB]], align 4 1754 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1755 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1756 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP3]], align 8 1757 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1758 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1759 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1760 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1761 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 1762 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1763 // CHECK9: cond.true: 1764 // CHECK9-NEXT: br label [[COND_END:%.*]] 1765 // CHECK9: cond.false: 1766 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1767 // CHECK9-NEXT: br label [[COND_END]] 1768 // CHECK9: cond.end: 1769 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 1770 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1771 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1772 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 1773 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1774 // CHECK9: omp.inner.for.cond: 1775 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1776 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1777 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 1778 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1779 // CHECK9: omp.inner.for.body: 1780 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1781 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 1782 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1783 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1784 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4 1785 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 1786 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP10]], align 4 1787 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4 1788 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 1789 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP11]], align 8 1790 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 1791 // CHECK9-NEXT: [[TMP13:%.*]] = load i32*, i32** [[_TMP3]], align 8 1792 // CHECK9-NEXT: store i32* [[TMP13]], i32** [[TMP12]], align 8 1793 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 1794 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP14]], align 8 1795 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) 1796 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1797 // CHECK9: omp.body.continue: 1798 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1799 // CHECK9: omp.inner.for.inc: 1800 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1801 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 1802 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 1803 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 1804 // CHECK9: omp.inner.for.end: 1805 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1806 // CHECK9: omp.loop.exit: 1807 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 1808 // CHECK9-NEXT: ret void 1809 // 1810 // 1811 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_private_codegen.cpp 1812 // CHECK9-SAME: () #[[ATTR0]] { 1813 // CHECK9-NEXT: entry: 1814 // CHECK9-NEXT: call void @__cxx_global_var_init() 1815 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 1816 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 1817 // CHECK9-NEXT: ret void 1818 // 1819 // 1820 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1821 // CHECK9-SAME: () #[[ATTR0]] { 1822 // CHECK9-NEXT: entry: 1823 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1824 // CHECK9-NEXT: ret void 1825 // 1826