1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute firstprivate(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute firstprivate(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global and bound tid vars 80 // skip loop vars 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 [&]() { 85 g = 2; 86 g1 = 2; 87 sivar = 4; 88 89 }(); 90 } 91 }(); 92 return 0; 93 #else 94 #pragma omp target 95 #pragma omp teams distribute firstprivate(t_var, vec, s_arr, var, sivar) 96 for (int i = 0; i < 2; ++i) { 97 vec[i] = t_var; 98 s_arr[i] = var; 99 sivar += i; 100 } 101 return tmain<int>(); 102 #endif 103 } 104 105 106 107 108 109 // Skip global and bound tid vars 110 // Skip temp vars for loop 111 112 // param copy 113 114 // T_VAR and SIVAR 115 116 // preparation vars 117 118 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 119 120 // firstprivate(s_arr) 121 122 // firstprivate(var) 123 124 125 126 127 128 129 // Skip global and bound tid vars 130 // Skip temp vars for loop 131 132 // param copy 133 134 135 // T_VAR and preparation variables 136 137 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 138 139 // firstprivate(s_arr) 140 141 // firstprivate(var) 142 143 144 #endif 145 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 146 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 147 // CHECK1-NEXT: entry: 148 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 149 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 150 // CHECK1-NEXT: ret void 151 // 152 // 153 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 154 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 155 // CHECK1-NEXT: entry: 156 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 157 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 158 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 164 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 167 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 168 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 170 // CHECK1-NEXT: ret void 171 // 172 // 173 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 174 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 175 // CHECK1-NEXT: entry: 176 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 177 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 178 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 179 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 180 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 181 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 182 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 183 // CHECK1-NEXT: ret void 184 // 185 // 186 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 187 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 188 // CHECK1-NEXT: entry: 189 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 190 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 196 // CHECK1-SAME: () #[[ATTR0]] { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 199 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 200 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 201 // CHECK1-NEXT: ret void 202 // 203 // 204 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 205 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 206 // CHECK1-NEXT: entry: 207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 209 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 210 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 211 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 212 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 213 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 214 // CHECK1-NEXT: ret void 215 // 216 // 217 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 218 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 219 // CHECK1-NEXT: entry: 220 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 221 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 222 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 223 // CHECK1: arraydestroy.body: 224 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 225 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 226 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 227 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 228 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 229 // CHECK1: arraydestroy.done1: 230 // CHECK1-NEXT: ret void 231 // 232 // 233 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 234 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 235 // CHECK1-NEXT: entry: 236 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 237 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 238 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 239 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 241 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 242 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 243 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 244 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 245 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 246 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 247 // CHECK1-NEXT: ret void 248 // 249 // 250 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 251 // CHECK1-SAME: () #[[ATTR0]] { 252 // CHECK1-NEXT: entry: 253 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 254 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 255 // CHECK1-NEXT: ret void 256 // 257 // 258 // CHECK1-LABEL: define {{[^@]+}}@main 259 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 260 // CHECK1-NEXT: entry: 261 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 262 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 263 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 264 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 265 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 266 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 267 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 269 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 270 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 271 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 272 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 273 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 274 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 275 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 276 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 277 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 278 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 279 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 280 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 281 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* 282 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 283 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 284 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 285 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 286 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 287 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8 288 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 289 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 290 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8 291 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 292 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 293 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 294 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 295 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 296 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 297 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 298 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 299 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 300 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 301 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 302 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 303 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 304 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 305 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 306 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 307 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 308 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 309 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 310 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 311 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 312 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 313 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 314 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 315 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 316 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 317 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 318 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 319 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 320 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 321 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 322 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 323 // CHECK1: omp_offload.failed: 324 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 325 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 326 // CHECK1: omp_offload.cont: 327 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 328 // CHECK1-NEXT: ret i32 [[CALL]] 329 // 330 // 331 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 332 // CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 333 // CHECK1-NEXT: entry: 334 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 335 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 336 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 337 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 338 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 339 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 340 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 341 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 342 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 343 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 344 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 345 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 346 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 347 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 348 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 349 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 350 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 351 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 352 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 353 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 354 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 355 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 356 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 357 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 358 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 359 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 360 // CHECK1-NEXT: ret void 361 // 362 // 363 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 364 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { 365 // CHECK1-NEXT: entry: 366 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 367 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 368 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 369 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 370 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 371 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 372 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 373 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 374 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 375 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 376 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 377 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 378 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 379 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 380 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 381 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 382 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 383 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 384 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 385 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 386 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 387 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 388 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 389 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 390 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 391 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 392 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 393 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 394 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 395 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 396 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 398 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 399 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 400 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 401 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 402 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 403 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 404 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 405 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 406 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 407 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 408 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 409 // CHECK1: omp.arraycpy.body: 410 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 411 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 412 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 413 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 414 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 415 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 416 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 417 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 418 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 419 // CHECK1: omp.arraycpy.done4: 420 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 421 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 422 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 423 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 424 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 425 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 426 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 427 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 428 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 429 // CHECK1: cond.true: 430 // CHECK1-NEXT: br label [[COND_END:%.*]] 431 // CHECK1: cond.false: 432 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 433 // CHECK1-NEXT: br label [[COND_END]] 434 // CHECK1: cond.end: 435 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 436 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 437 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 438 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 439 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 440 // CHECK1: omp.inner.for.cond: 441 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 442 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 443 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 444 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 445 // CHECK1: omp.inner.for.cond.cleanup: 446 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 447 // CHECK1: omp.inner.for.body: 448 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 449 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 450 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 451 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 452 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 453 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 454 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 455 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 456 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 457 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 458 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 459 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 460 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* 461 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 462 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) 463 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 464 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 465 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 466 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 467 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 468 // CHECK1: omp.body.continue: 469 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 470 // CHECK1: omp.inner.for.inc: 471 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 472 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 473 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 474 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 475 // CHECK1: omp.inner.for.end: 476 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 477 // CHECK1: omp.loop.exit: 478 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 479 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 480 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 481 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 482 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 483 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 484 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 485 // CHECK1: arraydestroy.body: 486 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 487 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 488 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 489 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 490 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 491 // CHECK1: arraydestroy.done13: 492 // CHECK1-NEXT: ret void 493 // 494 // 495 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 496 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 497 // CHECK1-NEXT: entry: 498 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 499 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 500 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 501 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 502 // CHECK1-NEXT: ret void 503 // 504 // 505 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 506 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 507 // CHECK1-NEXT: entry: 508 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 509 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 510 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 511 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 512 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 513 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 514 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 515 // CHECK1-NEXT: ret void 516 // 517 // 518 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 519 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 520 // CHECK1-NEXT: entry: 521 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 522 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 523 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 524 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 525 // CHECK1-NEXT: ret void 526 // 527 // 528 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 529 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 530 // CHECK1-NEXT: entry: 531 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 532 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 533 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 534 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 535 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 536 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 537 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 538 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 539 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 540 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 541 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 542 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 543 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 544 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 545 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 546 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 547 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 548 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 549 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 550 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 551 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 552 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 553 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 554 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 555 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 556 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 557 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 558 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 559 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 560 // CHECK1-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 561 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 562 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 563 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 564 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 565 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 566 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 567 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 568 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 569 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 570 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 571 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 572 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 573 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 574 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 575 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 576 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 577 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 578 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 579 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 580 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 581 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 582 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 583 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 584 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 585 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 586 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 587 // CHECK1-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 588 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 589 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 590 // CHECK1-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 591 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 592 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 593 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 594 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 595 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 596 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 597 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 598 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 599 // CHECK1: omp_offload.failed: 600 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 601 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 602 // CHECK1: omp_offload.cont: 603 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 604 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 605 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 606 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 607 // CHECK1: arraydestroy.body: 608 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 609 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 610 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 611 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 612 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 613 // CHECK1: arraydestroy.done2: 614 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 615 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 616 // CHECK1-NEXT: ret i32 [[TMP32]] 617 // 618 // 619 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 620 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 621 // CHECK1-NEXT: entry: 622 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 623 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 624 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 625 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 626 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 627 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 628 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4 629 // CHECK1-NEXT: ret void 630 // 631 // 632 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 633 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 634 // CHECK1-NEXT: entry: 635 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 636 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 637 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 638 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 639 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 640 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 641 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 642 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 643 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 644 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 645 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 646 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 647 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 648 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 649 // CHECK1-NEXT: ret void 650 // 651 // 652 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 653 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 654 // CHECK1-NEXT: entry: 655 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 656 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 657 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 658 // CHECK1-NEXT: ret void 659 // 660 // 661 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 662 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 663 // CHECK1-NEXT: entry: 664 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 665 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 666 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 667 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 668 // CHECK1-NEXT: ret void 669 // 670 // 671 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 672 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 673 // CHECK1-NEXT: entry: 674 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 675 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 676 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 677 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 678 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 679 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 680 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 681 // CHECK1-NEXT: ret void 682 // 683 // 684 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 685 // CHECK1-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 686 // CHECK1-NEXT: entry: 687 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 688 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 689 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 690 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 691 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 692 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 693 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 694 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 695 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 696 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 697 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 698 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 699 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 700 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 701 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 702 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 703 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 704 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 705 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 706 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 707 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 708 // CHECK1-NEXT: ret void 709 // 710 // 711 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 712 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 713 // CHECK1-NEXT: entry: 714 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 715 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 716 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 717 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 718 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 719 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 720 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 721 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 722 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 723 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 724 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 725 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 726 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 727 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 728 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 729 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 730 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 731 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 732 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 733 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 734 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 735 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 736 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 737 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 738 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 739 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 740 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 741 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 742 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 743 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 744 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 745 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 746 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 747 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 748 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 749 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 750 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 751 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 752 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 753 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 754 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 755 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 756 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 757 // CHECK1: omp.arraycpy.body: 758 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 759 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 760 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 761 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 762 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 763 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 764 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 765 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 766 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 767 // CHECK1: omp.arraycpy.done4: 768 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 769 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 770 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 771 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 772 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 773 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 774 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 775 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 776 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 777 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 778 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 779 // CHECK1: cond.true: 780 // CHECK1-NEXT: br label [[COND_END:%.*]] 781 // CHECK1: cond.false: 782 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 783 // CHECK1-NEXT: br label [[COND_END]] 784 // CHECK1: cond.end: 785 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 786 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 787 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 788 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 789 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 790 // CHECK1: omp.inner.for.cond: 791 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 792 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 793 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 794 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 795 // CHECK1: omp.inner.for.cond.cleanup: 796 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 797 // CHECK1: omp.inner.for.body: 798 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 799 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 800 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 801 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 802 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 803 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 804 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 805 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 806 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 807 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 808 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 809 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 810 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 811 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* 812 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 813 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) 814 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 815 // CHECK1: omp.body.continue: 816 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 817 // CHECK1: omp.inner.for.inc: 818 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 819 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 820 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 821 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 822 // CHECK1: omp.inner.for.end: 823 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 824 // CHECK1: omp.loop.exit: 825 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 826 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 827 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 828 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 829 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 830 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 831 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 832 // CHECK1: arraydestroy.body: 833 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 834 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 835 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 836 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 837 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 838 // CHECK1: arraydestroy.done13: 839 // CHECK1-NEXT: ret void 840 // 841 // 842 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 843 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 844 // CHECK1-NEXT: entry: 845 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 846 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 847 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 848 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 849 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 850 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 851 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 852 // CHECK1-NEXT: ret void 853 // 854 // 855 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 856 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 857 // CHECK1-NEXT: entry: 858 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 859 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 860 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 861 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 862 // CHECK1-NEXT: ret void 863 // 864 // 865 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 866 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 867 // CHECK1-NEXT: entry: 868 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 869 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 870 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 871 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 872 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 873 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 874 // CHECK1-NEXT: ret void 875 // 876 // 877 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 878 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 879 // CHECK1-NEXT: entry: 880 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 881 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 882 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 883 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 884 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 885 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 886 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 887 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 888 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 889 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 890 // CHECK1-NEXT: ret void 891 // 892 // 893 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 894 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 895 // CHECK1-NEXT: entry: 896 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 897 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 898 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 899 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 900 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 901 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 902 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 903 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 904 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 905 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 906 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 907 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 908 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 909 // CHECK1-NEXT: ret void 910 // 911 // 912 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 913 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 914 // CHECK1-NEXT: entry: 915 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 916 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 917 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 918 // CHECK1-NEXT: ret void 919 // 920 // 921 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 922 // CHECK1-SAME: () #[[ATTR0]] { 923 // CHECK1-NEXT: entry: 924 // CHECK1-NEXT: call void @__cxx_global_var_init() 925 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 926 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 927 // CHECK1-NEXT: ret void 928 // 929 // 930 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 931 // CHECK1-SAME: () #[[ATTR0]] { 932 // CHECK1-NEXT: entry: 933 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 934 // CHECK1-NEXT: ret void 935 // 936 // 937 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 938 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 939 // CHECK2-NEXT: entry: 940 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 941 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 942 // CHECK2-NEXT: ret void 943 // 944 // 945 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 946 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 947 // CHECK2-NEXT: entry: 948 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 949 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 950 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 951 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 952 // CHECK2-NEXT: ret void 953 // 954 // 955 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 956 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 957 // CHECK2-NEXT: entry: 958 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 959 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 960 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 961 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 962 // CHECK2-NEXT: ret void 963 // 964 // 965 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 966 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 967 // CHECK2-NEXT: entry: 968 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 969 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 970 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 971 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 972 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 973 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 974 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 975 // CHECK2-NEXT: ret void 976 // 977 // 978 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 979 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 980 // CHECK2-NEXT: entry: 981 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 982 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 983 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 984 // CHECK2-NEXT: ret void 985 // 986 // 987 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 988 // CHECK2-SAME: () #[[ATTR0]] { 989 // CHECK2-NEXT: entry: 990 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 991 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 992 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 993 // CHECK2-NEXT: ret void 994 // 995 // 996 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 997 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 998 // CHECK2-NEXT: entry: 999 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1000 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1001 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1002 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1003 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1004 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1005 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1006 // CHECK2-NEXT: ret void 1007 // 1008 // 1009 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1010 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 1011 // CHECK2-NEXT: entry: 1012 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1013 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1014 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1015 // CHECK2: arraydestroy.body: 1016 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1017 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1018 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1019 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1020 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1021 // CHECK2: arraydestroy.done1: 1022 // CHECK2-NEXT: ret void 1023 // 1024 // 1025 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1026 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1027 // CHECK2-NEXT: entry: 1028 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1029 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1030 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1031 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1032 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1033 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1034 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1035 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1036 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1037 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1038 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1039 // CHECK2-NEXT: ret void 1040 // 1041 // 1042 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1043 // CHECK2-SAME: () #[[ATTR0]] { 1044 // CHECK2-NEXT: entry: 1045 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1046 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1047 // CHECK2-NEXT: ret void 1048 // 1049 // 1050 // CHECK2-LABEL: define {{[^@]+}}@main 1051 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 1052 // CHECK2-NEXT: entry: 1053 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1054 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1055 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1056 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1057 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1058 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1059 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1060 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1061 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1062 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1063 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1064 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1065 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1066 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1067 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 1068 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1069 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1070 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 1071 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 1072 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1073 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* 1074 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8 1075 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1076 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8 1077 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1078 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 1079 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 8 1080 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1081 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 1082 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 8 1083 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1084 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 1085 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1086 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 1087 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 1088 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1089 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 1090 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 1091 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1092 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 1093 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1094 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 1095 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 1096 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1097 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 1098 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 1099 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1100 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 1101 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1102 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1103 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 1104 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1105 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1106 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 1107 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1108 // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8 1109 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1110 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1111 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1112 // CHECK2-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1113 // CHECK2-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1114 // CHECK2-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1115 // CHECK2: omp_offload.failed: 1116 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i64 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 1117 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1118 // CHECK2: omp_offload.cont: 1119 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 1120 // CHECK2-NEXT: ret i32 [[CALL]] 1121 // 1122 // 1123 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 1124 // CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1125 // CHECK2-NEXT: entry: 1126 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1127 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1128 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1129 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1130 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1131 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1132 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1133 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1134 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1135 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1136 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1137 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1138 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1139 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1140 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1141 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1142 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1143 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1144 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1145 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 1146 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1147 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 1148 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1149 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 1150 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1151 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 1152 // CHECK2-NEXT: ret void 1153 // 1154 // 1155 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1156 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4]] { 1157 // CHECK2-NEXT: entry: 1158 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1159 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1160 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1161 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1162 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1163 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1164 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1165 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1166 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1167 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1168 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1169 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1170 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1171 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1172 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 1173 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1174 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1175 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1176 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1177 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1178 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1179 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1180 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1181 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1182 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1183 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1184 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1185 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1186 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1187 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1188 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1189 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1190 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1191 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1192 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1193 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1194 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1195 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1196 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1197 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1198 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1199 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1200 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1201 // CHECK2: omp.arraycpy.body: 1202 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1203 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1204 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1205 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1206 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1207 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1208 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1209 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1210 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1211 // CHECK2: omp.arraycpy.done4: 1212 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1213 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 1214 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1215 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1216 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1217 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1218 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1219 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1220 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1221 // CHECK2: cond.true: 1222 // CHECK2-NEXT: br label [[COND_END:%.*]] 1223 // CHECK2: cond.false: 1224 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1225 // CHECK2-NEXT: br label [[COND_END]] 1226 // CHECK2: cond.end: 1227 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1228 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1229 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1230 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 1231 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1232 // CHECK2: omp.inner.for.cond: 1233 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1234 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1235 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1236 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1237 // CHECK2: omp.inner.for.cond.cleanup: 1238 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1239 // CHECK2: omp.inner.for.body: 1240 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1241 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 1242 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1243 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1244 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 1245 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1246 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 1247 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 1248 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 1249 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 1250 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 1251 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 1252 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* 1253 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 1254 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false) 1255 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 1256 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 8 1257 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 1258 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 8 1259 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1260 // CHECK2: omp.body.continue: 1261 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1262 // CHECK2: omp.inner.for.inc: 1263 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1264 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 1265 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1266 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1267 // CHECK2: omp.inner.for.end: 1268 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1269 // CHECK2: omp.loop.exit: 1270 // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1271 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1272 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1273 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1274 // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1275 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 1276 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1277 // CHECK2: arraydestroy.body: 1278 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1279 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1280 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1281 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 1282 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 1283 // CHECK2: arraydestroy.done13: 1284 // CHECK2-NEXT: ret void 1285 // 1286 // 1287 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1288 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1289 // CHECK2-NEXT: entry: 1290 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1291 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1292 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1293 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 1294 // CHECK2-NEXT: ret void 1295 // 1296 // 1297 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1298 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1299 // CHECK2-NEXT: entry: 1300 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1301 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1302 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1303 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1304 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1305 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1306 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1307 // CHECK2-NEXT: ret void 1308 // 1309 // 1310 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1311 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1312 // CHECK2-NEXT: entry: 1313 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1314 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1315 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1316 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1317 // CHECK2-NEXT: ret void 1318 // 1319 // 1320 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1321 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat { 1322 // CHECK2-NEXT: entry: 1323 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1324 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1325 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1326 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1327 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1328 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 1329 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1330 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1331 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1332 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1333 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1334 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1335 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1336 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 1337 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1338 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1339 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1340 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 1341 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1342 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 1343 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 1344 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 1345 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 1346 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 1347 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1348 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 1349 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1350 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1351 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1352 // CHECK2-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1353 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1354 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1355 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 1356 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1357 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1358 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 1359 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1360 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8 1361 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1362 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 1363 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 1364 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1365 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 1366 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 1367 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1368 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8 1369 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1370 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 1371 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 1372 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1373 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 1374 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 1375 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1376 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 1377 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1378 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 1379 // CHECK2-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 1380 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1381 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 1382 // CHECK2-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 1383 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1384 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8 1385 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1386 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1387 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 1388 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1389 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1390 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1391 // CHECK2: omp_offload.failed: 1392 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 1393 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1394 // CHECK2: omp_offload.cont: 1395 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1396 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1397 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1398 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1399 // CHECK2: arraydestroy.body: 1400 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1401 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1402 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1403 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1404 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1405 // CHECK2: arraydestroy.done2: 1406 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1407 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 1408 // CHECK2-NEXT: ret i32 [[TMP32]] 1409 // 1410 // 1411 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1412 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1413 // CHECK2-NEXT: entry: 1414 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1415 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1416 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1417 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1418 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1419 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1420 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4 1421 // CHECK2-NEXT: ret void 1422 // 1423 // 1424 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1425 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1426 // CHECK2-NEXT: entry: 1427 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1428 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1429 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1430 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1431 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1432 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1433 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1434 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1435 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1436 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1437 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1438 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1439 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1440 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1441 // CHECK2-NEXT: ret void 1442 // 1443 // 1444 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1445 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1446 // CHECK2-NEXT: entry: 1447 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1448 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1449 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1450 // CHECK2-NEXT: ret void 1451 // 1452 // 1453 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1454 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1455 // CHECK2-NEXT: entry: 1456 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1457 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1458 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1459 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1460 // CHECK2-NEXT: ret void 1461 // 1462 // 1463 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1464 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1465 // CHECK2-NEXT: entry: 1466 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1467 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1468 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1469 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1470 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1471 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1472 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 1473 // CHECK2-NEXT: ret void 1474 // 1475 // 1476 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1477 // CHECK2-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1478 // CHECK2-NEXT: entry: 1479 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1480 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1481 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1482 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1483 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1484 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1485 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1486 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1487 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1488 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1489 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1490 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1491 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1492 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1493 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 1494 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1495 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1496 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 1497 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1498 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1499 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 1500 // CHECK2-NEXT: ret void 1501 // 1502 // 1503 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1504 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1505 // CHECK2-NEXT: entry: 1506 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1507 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1508 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1509 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1510 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1511 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1512 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1513 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1514 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1515 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1516 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1517 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1518 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1519 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1520 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1521 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1522 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1523 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1524 // CHECK2-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 1525 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1526 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1527 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1528 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1529 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1530 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1531 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1532 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1533 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1534 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1535 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1536 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 1537 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1538 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1539 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1540 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1541 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1542 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1543 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1544 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1545 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 1546 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1547 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 1548 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1549 // CHECK2: omp.arraycpy.body: 1550 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1551 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1552 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1553 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1554 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1555 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1556 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1557 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1558 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1559 // CHECK2: omp.arraycpy.done4: 1560 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1561 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1562 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 1563 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1564 // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 1565 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1566 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 1567 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1568 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1569 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 1570 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1571 // CHECK2: cond.true: 1572 // CHECK2-NEXT: br label [[COND_END:%.*]] 1573 // CHECK2: cond.false: 1574 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1575 // CHECK2-NEXT: br label [[COND_END]] 1576 // CHECK2: cond.end: 1577 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1578 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1579 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1580 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1581 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1582 // CHECK2: omp.inner.for.cond: 1583 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1584 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1585 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1586 // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1587 // CHECK2: omp.inner.for.cond.cleanup: 1588 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1589 // CHECK2: omp.inner.for.body: 1590 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1591 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 1592 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1593 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1594 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 8 1595 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 1596 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 1597 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 1598 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 1599 // CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8 1600 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1601 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 1602 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 1603 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* 1604 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 1605 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false) 1606 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1607 // CHECK2: omp.body.continue: 1608 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1609 // CHECK2: omp.inner.for.inc: 1610 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1611 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 1612 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1613 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1614 // CHECK2: omp.inner.for.end: 1615 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1616 // CHECK2: omp.loop.exit: 1617 // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1618 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1619 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1620 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1621 // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1622 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 1623 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1624 // CHECK2: arraydestroy.body: 1625 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1626 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1627 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1628 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 1629 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 1630 // CHECK2: arraydestroy.done13: 1631 // CHECK2-NEXT: ret void 1632 // 1633 // 1634 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1635 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1636 // CHECK2-NEXT: entry: 1637 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1638 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1639 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1640 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1641 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1642 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1643 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1644 // CHECK2-NEXT: ret void 1645 // 1646 // 1647 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1648 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1649 // CHECK2-NEXT: entry: 1650 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1651 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1652 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1653 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1654 // CHECK2-NEXT: ret void 1655 // 1656 // 1657 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1658 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1659 // CHECK2-NEXT: entry: 1660 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1661 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1662 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1663 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1664 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1665 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1666 // CHECK2-NEXT: ret void 1667 // 1668 // 1669 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1670 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1671 // CHECK2-NEXT: entry: 1672 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1673 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1674 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1675 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1676 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1677 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1678 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1679 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1680 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1681 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1682 // CHECK2-NEXT: ret void 1683 // 1684 // 1685 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1686 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1687 // CHECK2-NEXT: entry: 1688 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1689 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1690 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1691 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1692 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1693 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1694 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1695 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1696 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1697 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1698 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1699 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1700 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1701 // CHECK2-NEXT: ret void 1702 // 1703 // 1704 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1705 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1706 // CHECK2-NEXT: entry: 1707 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1708 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1709 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1710 // CHECK2-NEXT: ret void 1711 // 1712 // 1713 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 1714 // CHECK2-SAME: () #[[ATTR0]] { 1715 // CHECK2-NEXT: entry: 1716 // CHECK2-NEXT: call void @__cxx_global_var_init() 1717 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 1718 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 1719 // CHECK2-NEXT: ret void 1720 // 1721 // 1722 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1723 // CHECK2-SAME: () #[[ATTR0]] { 1724 // CHECK2-NEXT: entry: 1725 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1726 // CHECK2-NEXT: ret void 1727 // 1728 // 1729 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1730 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1731 // CHECK3-NEXT: entry: 1732 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 1733 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1734 // CHECK3-NEXT: ret void 1735 // 1736 // 1737 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1738 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1739 // CHECK3-NEXT: entry: 1740 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1741 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1742 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1743 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1744 // CHECK3-NEXT: ret void 1745 // 1746 // 1747 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1748 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1749 // CHECK3-NEXT: entry: 1750 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1751 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1752 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1753 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1754 // CHECK3-NEXT: ret void 1755 // 1756 // 1757 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1758 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1759 // CHECK3-NEXT: entry: 1760 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1761 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1762 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1763 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1764 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1765 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1766 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 1767 // CHECK3-NEXT: ret void 1768 // 1769 // 1770 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1771 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1772 // CHECK3-NEXT: entry: 1773 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1774 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1775 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1776 // CHECK3-NEXT: ret void 1777 // 1778 // 1779 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1780 // CHECK3-SAME: () #[[ATTR0]] { 1781 // CHECK3-NEXT: entry: 1782 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 1783 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 1784 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1785 // CHECK3-NEXT: ret void 1786 // 1787 // 1788 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1789 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1790 // CHECK3-NEXT: entry: 1791 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1792 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1793 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1794 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1795 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1796 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1797 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1798 // CHECK3-NEXT: ret void 1799 // 1800 // 1801 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1802 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 1803 // CHECK3-NEXT: entry: 1804 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1805 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1806 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1807 // CHECK3: arraydestroy.body: 1808 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1809 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1810 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1811 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1812 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1813 // CHECK3: arraydestroy.done1: 1814 // CHECK3-NEXT: ret void 1815 // 1816 // 1817 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1818 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1819 // CHECK3-NEXT: entry: 1820 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1821 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1822 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1823 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1824 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1825 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1826 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1827 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1828 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1829 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1830 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1831 // CHECK3-NEXT: ret void 1832 // 1833 // 1834 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1835 // CHECK3-SAME: () #[[ATTR0]] { 1836 // CHECK3-NEXT: entry: 1837 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1838 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1839 // CHECK3-NEXT: ret void 1840 // 1841 // 1842 // CHECK3-LABEL: define {{[^@]+}}@main 1843 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1844 // CHECK3-NEXT: entry: 1845 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1846 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1847 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1848 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1849 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1850 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1851 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1852 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1853 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1854 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 1855 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1856 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1857 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 1858 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1859 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1860 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1861 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1862 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1863 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* 1864 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 1865 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1866 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1867 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1868 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 1869 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4 1870 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1871 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 1872 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4 1873 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1874 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1875 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1876 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 1877 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 1878 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1879 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 1880 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 1881 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1882 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1883 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1884 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 1885 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 1886 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1887 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 1888 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 1889 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1890 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1891 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1892 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1893 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 1894 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1895 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 1896 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 1897 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1898 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 1899 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1900 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1901 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1902 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1903 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1904 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1905 // CHECK3: omp_offload.failed: 1906 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 1907 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1908 // CHECK3: omp_offload.cont: 1909 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1910 // CHECK3-NEXT: ret i32 [[CALL]] 1911 // 1912 // 1913 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 1914 // CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1915 // CHECK3-NEXT: entry: 1916 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1917 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1918 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1919 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1920 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1921 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1922 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1923 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1924 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1925 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1926 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1927 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1928 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1929 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1930 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1931 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1932 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 1933 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1934 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 1935 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 1936 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1937 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 1938 // CHECK3-NEXT: ret void 1939 // 1940 // 1941 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1942 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { 1943 // CHECK3-NEXT: entry: 1944 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1945 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1946 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1947 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1948 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1949 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1950 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1951 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1952 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1953 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1954 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1955 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1956 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1957 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1958 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1959 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1960 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1961 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1962 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1963 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1964 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1965 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1966 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1967 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1968 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1969 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1970 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1971 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1972 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1973 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1974 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1975 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1976 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1977 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 1978 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1979 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 1980 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1981 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1982 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1983 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1984 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1985 // CHECK3: omp.arraycpy.body: 1986 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1987 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1988 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1989 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1990 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1991 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1992 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1993 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1994 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1995 // CHECK3: omp.arraycpy.done3: 1996 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1997 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 1998 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1999 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2000 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 2001 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2002 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2003 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2004 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2005 // CHECK3: cond.true: 2006 // CHECK3-NEXT: br label [[COND_END:%.*]] 2007 // CHECK3: cond.false: 2008 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2009 // CHECK3-NEXT: br label [[COND_END]] 2010 // CHECK3: cond.end: 2011 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2012 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2013 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2014 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 2015 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2016 // CHECK3: omp.inner.for.cond: 2017 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2018 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2019 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2020 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2021 // CHECK3: omp.inner.for.cond.cleanup: 2022 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2023 // CHECK3: omp.inner.for.body: 2024 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2025 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2026 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2027 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2028 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2029 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2030 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] 2031 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 2032 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 2033 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] 2034 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 2035 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2036 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) 2037 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 2038 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2039 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 2040 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 2041 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2042 // CHECK3: omp.body.continue: 2043 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2044 // CHECK3: omp.inner.for.inc: 2045 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2046 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 2047 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 2048 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2049 // CHECK3: omp.inner.for.end: 2050 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2051 // CHECK3: omp.loop.exit: 2052 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2053 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 2054 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 2055 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 2056 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2057 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 2058 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2059 // CHECK3: arraydestroy.body: 2060 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2061 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2062 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2063 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2064 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2065 // CHECK3: arraydestroy.done11: 2066 // CHECK3-NEXT: ret void 2067 // 2068 // 2069 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2070 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2071 // CHECK3-NEXT: entry: 2072 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2073 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2074 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2075 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2076 // CHECK3-NEXT: ret void 2077 // 2078 // 2079 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2080 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2081 // CHECK3-NEXT: entry: 2082 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2083 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2084 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2085 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2086 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2087 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2088 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2089 // CHECK3-NEXT: ret void 2090 // 2091 // 2092 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2093 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2094 // CHECK3-NEXT: entry: 2095 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2096 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2097 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2098 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 2099 // CHECK3-NEXT: ret void 2100 // 2101 // 2102 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2103 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 2104 // CHECK3-NEXT: entry: 2105 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2106 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2107 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2108 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2109 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2110 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2111 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2112 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2113 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2114 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2115 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2116 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2117 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2118 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 2119 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2120 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2121 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2122 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2123 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2124 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2125 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2126 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2127 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 2128 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 2129 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 2130 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2131 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2132 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2133 // CHECK3-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2134 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2135 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2136 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 2137 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2138 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 2139 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 2140 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2141 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 2142 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2143 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 2144 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 2145 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2146 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 2147 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 2148 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2149 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 2150 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2151 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 2152 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 2153 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2154 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 2155 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 2156 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2157 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 2158 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2159 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 2160 // CHECK3-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 2161 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2162 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 2163 // CHECK3-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 2164 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2165 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 2166 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2167 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2168 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 2169 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2170 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2171 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2172 // CHECK3: omp_offload.failed: 2173 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 2174 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2175 // CHECK3: omp_offload.cont: 2176 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 2177 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2178 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2179 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2180 // CHECK3: arraydestroy.body: 2181 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2182 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2183 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2184 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2185 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2186 // CHECK3: arraydestroy.done2: 2187 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2188 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 2189 // CHECK3-NEXT: ret i32 [[TMP32]] 2190 // 2191 // 2192 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2193 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2194 // CHECK3-NEXT: entry: 2195 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2196 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2197 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2198 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 2199 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2200 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2201 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4 2202 // CHECK3-NEXT: ret void 2203 // 2204 // 2205 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 2206 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2207 // CHECK3-NEXT: entry: 2208 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2209 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2210 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2211 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2212 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2213 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2214 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2215 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 2216 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 2217 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2218 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2219 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 2220 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 2221 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 2222 // CHECK3-NEXT: ret void 2223 // 2224 // 2225 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 2226 // CHECK3-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2227 // CHECK3-NEXT: entry: 2228 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2229 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2230 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2231 // CHECK3-NEXT: ret void 2232 // 2233 // 2234 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2235 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2236 // CHECK3-NEXT: entry: 2237 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2238 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2239 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2240 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2241 // CHECK3-NEXT: ret void 2242 // 2243 // 2244 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2245 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2246 // CHECK3-NEXT: entry: 2247 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2248 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2249 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2250 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2251 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2252 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2253 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 2254 // CHECK3-NEXT: ret void 2255 // 2256 // 2257 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 2258 // CHECK3-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2259 // CHECK3-NEXT: entry: 2260 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2261 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2262 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2263 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2264 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2265 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2266 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2267 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2268 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2269 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2270 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2271 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2272 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2273 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 2274 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2275 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2276 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2277 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2278 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 2279 // CHECK3-NEXT: ret void 2280 // 2281 // 2282 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2283 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2284 // CHECK3-NEXT: entry: 2285 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2286 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2287 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2288 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2289 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2290 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2291 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2292 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2293 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2294 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2295 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2296 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2297 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2298 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2299 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2300 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2301 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2302 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2303 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 2304 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2305 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2306 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2307 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2308 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2309 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2310 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2311 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2312 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2313 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2314 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 2315 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2316 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2317 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2318 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2319 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 2320 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2321 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2322 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2323 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 2324 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2325 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 2326 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2327 // CHECK3: omp.arraycpy.body: 2328 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2329 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2330 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2331 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2332 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2333 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2334 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2335 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2336 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2337 // CHECK3: omp.arraycpy.done4: 2338 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2339 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2340 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 2341 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 2342 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 2343 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2344 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 2345 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2346 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2347 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 2348 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2349 // CHECK3: cond.true: 2350 // CHECK3-NEXT: br label [[COND_END:%.*]] 2351 // CHECK3: cond.false: 2352 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2353 // CHECK3-NEXT: br label [[COND_END]] 2354 // CHECK3: cond.end: 2355 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2356 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2357 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2358 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2359 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2360 // CHECK3: omp.inner.for.cond: 2361 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2362 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2363 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2364 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2365 // CHECK3: omp.inner.for.cond.cleanup: 2366 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2367 // CHECK3: omp.inner.for.body: 2368 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2369 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 2370 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2371 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2372 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2373 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 2374 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] 2375 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 2376 // CHECK3-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 2377 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2378 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] 2379 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 2380 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 2381 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) 2382 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2383 // CHECK3: omp.body.continue: 2384 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2385 // CHECK3: omp.inner.for.inc: 2386 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2387 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 2388 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 2389 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2390 // CHECK3: omp.inner.for.end: 2391 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2392 // CHECK3: omp.loop.exit: 2393 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2394 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 2395 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 2396 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 2397 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2398 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 2399 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2400 // CHECK3: arraydestroy.body: 2401 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2402 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2403 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2404 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 2405 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 2406 // CHECK3: arraydestroy.done12: 2407 // CHECK3-NEXT: ret void 2408 // 2409 // 2410 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 2411 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2412 // CHECK3-NEXT: entry: 2413 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2414 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2415 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2416 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2417 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2418 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2419 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2420 // CHECK3-NEXT: ret void 2421 // 2422 // 2423 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2424 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2425 // CHECK3-NEXT: entry: 2426 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2427 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2428 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2429 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2430 // CHECK3-NEXT: ret void 2431 // 2432 // 2433 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2434 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2435 // CHECK3-NEXT: entry: 2436 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2437 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2438 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2439 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2440 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2441 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2442 // CHECK3-NEXT: ret void 2443 // 2444 // 2445 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2446 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2447 // CHECK3-NEXT: entry: 2448 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2449 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2450 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2451 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2452 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2453 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2454 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2455 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2456 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2457 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2458 // CHECK3-NEXT: ret void 2459 // 2460 // 2461 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 2462 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2463 // CHECK3-NEXT: entry: 2464 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2465 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2466 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2467 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2468 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2469 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2470 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2471 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 2472 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 2473 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2474 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2475 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 2476 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2477 // CHECK3-NEXT: ret void 2478 // 2479 // 2480 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2481 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2482 // CHECK3-NEXT: entry: 2483 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2484 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2485 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2486 // CHECK3-NEXT: ret void 2487 // 2488 // 2489 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 2490 // CHECK3-SAME: () #[[ATTR0]] { 2491 // CHECK3-NEXT: entry: 2492 // CHECK3-NEXT: call void @__cxx_global_var_init() 2493 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 2494 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 2495 // CHECK3-NEXT: ret void 2496 // 2497 // 2498 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2499 // CHECK3-SAME: () #[[ATTR0]] { 2500 // CHECK3-NEXT: entry: 2501 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 2502 // CHECK3-NEXT: ret void 2503 // 2504 // 2505 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 2506 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 2507 // CHECK4-NEXT: entry: 2508 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 2509 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2510 // CHECK4-NEXT: ret void 2511 // 2512 // 2513 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2514 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2515 // CHECK4-NEXT: entry: 2516 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2517 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2518 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2519 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2520 // CHECK4-NEXT: ret void 2521 // 2522 // 2523 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2524 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2525 // CHECK4-NEXT: entry: 2526 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2527 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2528 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2529 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2530 // CHECK4-NEXT: ret void 2531 // 2532 // 2533 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2534 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2535 // CHECK4-NEXT: entry: 2536 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2537 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2538 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2539 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2540 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2541 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2542 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4 2543 // CHECK4-NEXT: ret void 2544 // 2545 // 2546 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2547 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2548 // CHECK4-NEXT: entry: 2549 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2550 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2551 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2552 // CHECK4-NEXT: ret void 2553 // 2554 // 2555 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2556 // CHECK4-SAME: () #[[ATTR0]] { 2557 // CHECK4-NEXT: entry: 2558 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 2559 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 2560 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2561 // CHECK4-NEXT: ret void 2562 // 2563 // 2564 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2565 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2566 // CHECK4-NEXT: entry: 2567 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2568 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2569 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2570 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2571 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2572 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2573 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2574 // CHECK4-NEXT: ret void 2575 // 2576 // 2577 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2578 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 2579 // CHECK4-NEXT: entry: 2580 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 2581 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 2582 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2583 // CHECK4: arraydestroy.body: 2584 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2585 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2586 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2587 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2588 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2589 // CHECK4: arraydestroy.done1: 2590 // CHECK4-NEXT: ret void 2591 // 2592 // 2593 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2594 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2595 // CHECK4-NEXT: entry: 2596 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2597 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2598 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2599 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2600 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2601 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2602 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2603 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2604 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2605 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2606 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 2607 // CHECK4-NEXT: ret void 2608 // 2609 // 2610 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2611 // CHECK4-SAME: () #[[ATTR0]] { 2612 // CHECK4-NEXT: entry: 2613 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 2614 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2615 // CHECK4-NEXT: ret void 2616 // 2617 // 2618 // CHECK4-LABEL: define {{[^@]+}}@main 2619 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 2620 // CHECK4-NEXT: entry: 2621 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2622 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2623 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2624 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2625 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2626 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2627 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2628 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 2629 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 2630 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 2631 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2632 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 2633 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 2634 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2635 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2636 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 2637 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 2638 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2639 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* 2640 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 2641 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2642 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4 2643 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2644 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [2 x i32]** 2645 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP10]], align 4 2646 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2647 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x i32]** 2648 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP12]], align 4 2649 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2650 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 2651 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2652 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 2653 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 2654 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2655 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 2656 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 2657 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2658 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 2659 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2660 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 2661 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 2662 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2663 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 2664 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 2665 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2666 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 2667 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2668 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2669 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 2670 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2671 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2672 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 2673 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2674 // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4 2675 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2676 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2677 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 2678 // CHECK4-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2679 // CHECK4-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2680 // CHECK4-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2681 // CHECK4: omp_offload.failed: 2682 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94(i32 [[TMP1]], [2 x i32]* @vec, [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 2683 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2684 // CHECK4: omp_offload.cont: 2685 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2686 // CHECK4-NEXT: ret i32 [[CALL]] 2687 // 2688 // 2689 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 2690 // CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 2691 // CHECK4-NEXT: entry: 2692 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2693 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2694 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2695 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2696 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2697 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2698 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2699 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2700 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2701 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2702 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2703 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2704 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2705 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2706 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2707 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2708 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2709 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2710 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2711 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 2712 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2713 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 2714 // CHECK4-NEXT: ret void 2715 // 2716 // 2717 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 2718 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4]] { 2719 // CHECK4-NEXT: entry: 2720 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2721 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2722 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2723 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2724 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2725 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2726 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2727 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2728 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2729 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2730 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2731 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2732 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2733 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2734 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2735 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2736 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2737 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2738 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2739 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2740 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2741 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2742 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2743 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2744 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2745 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2746 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2747 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2748 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2749 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2750 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2751 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2752 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2753 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 2754 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2755 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2756 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2757 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2758 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2759 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2760 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2761 // CHECK4: omp.arraycpy.body: 2762 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2763 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2764 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2765 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2766 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 2767 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2768 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2769 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2770 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2771 // CHECK4: omp.arraycpy.done3: 2772 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 2773 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 2774 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 2775 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2776 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 2777 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2778 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2779 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2780 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2781 // CHECK4: cond.true: 2782 // CHECK4-NEXT: br label [[COND_END:%.*]] 2783 // CHECK4: cond.false: 2784 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2785 // CHECK4-NEXT: br label [[COND_END]] 2786 // CHECK4: cond.end: 2787 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2788 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2789 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2790 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 2791 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2792 // CHECK4: omp.inner.for.cond: 2793 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2794 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2795 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2796 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2797 // CHECK4: omp.inner.for.cond.cleanup: 2798 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2799 // CHECK4: omp.inner.for.body: 2800 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2801 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2802 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2803 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2804 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2805 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2806 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] 2807 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4 2808 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 2809 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] 2810 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 2811 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2812 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false) 2813 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 2814 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2815 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 2816 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4 2817 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2818 // CHECK4: omp.body.continue: 2819 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2820 // CHECK4: omp.inner.for.inc: 2821 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2822 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 2823 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 2824 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 2825 // CHECK4: omp.inner.for.end: 2826 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2827 // CHECK4: omp.loop.exit: 2828 // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2829 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 2830 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 2831 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 2832 // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2833 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 2834 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2835 // CHECK4: arraydestroy.body: 2836 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2837 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2838 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2839 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2840 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2841 // CHECK4: arraydestroy.done11: 2842 // CHECK4-NEXT: ret void 2843 // 2844 // 2845 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2846 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2847 // CHECK4-NEXT: entry: 2848 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2849 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2850 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2851 // CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2852 // CHECK4-NEXT: ret void 2853 // 2854 // 2855 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2856 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2857 // CHECK4-NEXT: entry: 2858 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2859 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2860 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2861 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2862 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2863 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2864 // CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2865 // CHECK4-NEXT: ret void 2866 // 2867 // 2868 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2869 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2870 // CHECK4-NEXT: entry: 2871 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2872 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2873 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2874 // CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 2875 // CHECK4-NEXT: ret void 2876 // 2877 // 2878 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2879 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat { 2880 // CHECK4-NEXT: entry: 2881 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2882 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2883 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2884 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2885 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2886 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2887 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2888 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2889 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2890 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2891 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2892 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2893 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2894 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 2895 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2896 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2897 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2898 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2899 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2900 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2901 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2902 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2903 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 2904 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 2905 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 2906 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2907 // CHECK4-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2908 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2909 // CHECK4-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2910 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2911 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2912 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 2913 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2914 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 2915 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 2916 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2917 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4 2918 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2919 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 2920 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 2921 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2922 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** 2923 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 2924 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2925 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4 2926 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2927 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 2928 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 2929 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2930 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** 2931 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 2932 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2933 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 2934 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2935 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 2936 // CHECK4-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 2937 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2938 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** 2939 // CHECK4-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 2940 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2941 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4 2942 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2943 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2944 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 2945 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2946 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2947 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2948 // CHECK4: omp_offload.failed: 2949 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 2950 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2951 // CHECK4: omp_offload.cont: 2952 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 2953 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2954 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2955 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2956 // CHECK4: arraydestroy.body: 2957 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2958 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2959 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2960 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2961 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2962 // CHECK4: arraydestroy.done2: 2963 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2964 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 2965 // CHECK4-NEXT: ret i32 [[TMP32]] 2966 // 2967 // 2968 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2969 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2970 // CHECK4-NEXT: entry: 2971 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2972 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2973 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2974 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 2975 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 2976 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2977 // CHECK4-NEXT: store i32 0, i32* [[B]], align 4 2978 // CHECK4-NEXT: ret void 2979 // 2980 // 2981 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 2982 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2983 // CHECK4-NEXT: entry: 2984 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2985 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2986 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2987 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2988 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2989 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2990 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2991 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 2992 // CHECK4-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 2993 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2994 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2995 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 2996 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 2997 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 2998 // CHECK4-NEXT: ret void 2999 // 3000 // 3001 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev 3002 // CHECK4-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3003 // CHECK4-NEXT: entry: 3004 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3005 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3006 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3007 // CHECK4-NEXT: ret void 3008 // 3009 // 3010 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3011 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3012 // CHECK4-NEXT: entry: 3013 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3014 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3015 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3016 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3017 // CHECK4-NEXT: ret void 3018 // 3019 // 3020 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3021 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3022 // CHECK4-NEXT: entry: 3023 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3024 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3025 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3026 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3027 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3028 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3029 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3030 // CHECK4-NEXT: ret void 3031 // 3032 // 3033 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 3034 // CHECK4-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 3035 // CHECK4-NEXT: entry: 3036 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3037 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3038 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3039 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3040 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3041 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3042 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3043 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3044 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3045 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3046 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3047 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3048 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3049 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 3050 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3051 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 3052 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 3053 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3054 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 3055 // CHECK4-NEXT: ret void 3056 // 3057 // 3058 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 3059 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 3060 // CHECK4-NEXT: entry: 3061 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3062 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3063 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3064 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3065 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3066 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3067 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3068 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3069 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3070 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3071 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3072 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3073 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3074 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3075 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3076 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3077 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3078 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3079 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 3080 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3081 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3082 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3083 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3084 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3085 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3086 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3087 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3088 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3089 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3090 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 3091 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3092 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3093 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3094 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3095 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 3096 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3097 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 3098 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3099 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 3100 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3101 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 3102 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3103 // CHECK4: omp.arraycpy.body: 3104 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3105 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3106 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3107 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 3108 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 3109 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3110 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3111 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 3112 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3113 // CHECK4: omp.arraycpy.done4: 3114 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3115 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3116 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* [[AGG_TMP6]]) 3117 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 3118 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 3119 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3120 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 3121 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3122 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3123 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 3124 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3125 // CHECK4: cond.true: 3126 // CHECK4-NEXT: br label [[COND_END:%.*]] 3127 // CHECK4: cond.false: 3128 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3129 // CHECK4-NEXT: br label [[COND_END]] 3130 // CHECK4: cond.end: 3131 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 3132 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3133 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3134 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 3135 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3136 // CHECK4: omp.inner.for.cond: 3137 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3138 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3139 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 3140 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3141 // CHECK4: omp.inner.for.cond.cleanup: 3142 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3143 // CHECK4: omp.inner.for.body: 3144 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3145 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 3146 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3147 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3148 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3149 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 3150 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] 3151 // CHECK4-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4 3152 // CHECK4-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4 3153 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3154 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] 3155 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 3156 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 3157 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false) 3158 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3159 // CHECK4: omp.body.continue: 3160 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3161 // CHECK4: omp.inner.for.inc: 3162 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3163 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 3164 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 3165 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3166 // CHECK4: omp.inner.for.end: 3167 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3168 // CHECK4: omp.loop.exit: 3169 // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3170 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 3171 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 3172 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 3173 // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3174 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 3175 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3176 // CHECK4: arraydestroy.body: 3177 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3178 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3179 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3180 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 3181 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 3182 // CHECK4: arraydestroy.done12: 3183 // CHECK4-NEXT: ret void 3184 // 3185 // 3186 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3187 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3188 // CHECK4-NEXT: entry: 3189 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3190 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3191 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3192 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3193 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3194 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3195 // CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 3196 // CHECK4-NEXT: ret void 3197 // 3198 // 3199 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3200 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3201 // CHECK4-NEXT: entry: 3202 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3203 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3204 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3205 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3206 // CHECK4-NEXT: ret void 3207 // 3208 // 3209 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3210 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3211 // CHECK4-NEXT: entry: 3212 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3213 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3214 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3215 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3216 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3217 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3218 // CHECK4-NEXT: ret void 3219 // 3220 // 3221 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3222 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3223 // CHECK4-NEXT: entry: 3224 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3225 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3226 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3227 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3228 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3229 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3230 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3231 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3232 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3233 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3234 // CHECK4-NEXT: ret void 3235 // 3236 // 3237 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 3238 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3239 // CHECK4-NEXT: entry: 3240 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3241 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3242 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3243 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3244 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3245 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3246 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3247 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 3248 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 3249 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3250 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3251 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 3252 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3253 // CHECK4-NEXT: ret void 3254 // 3255 // 3256 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3257 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3258 // CHECK4-NEXT: entry: 3259 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3260 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3261 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3262 // CHECK4-NEXT: ret void 3263 // 3264 // 3265 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 3266 // CHECK4-SAME: () #[[ATTR0]] { 3267 // CHECK4-NEXT: entry: 3268 // CHECK4-NEXT: call void @__cxx_global_var_init() 3269 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 3270 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 3271 // CHECK4-NEXT: ret void 3272 // 3273 // 3274 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3275 // CHECK4-SAME: () #[[ATTR0]] { 3276 // CHECK4-NEXT: entry: 3277 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 3278 // CHECK4-NEXT: ret void 3279 // 3280 // 3281 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 3282 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 3283 // CHECK5-NEXT: entry: 3284 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3285 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3286 // CHECK5-NEXT: ret void 3287 // 3288 // 3289 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3290 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3291 // CHECK5-NEXT: entry: 3292 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3293 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3294 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3295 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3296 // CHECK5-NEXT: ret void 3297 // 3298 // 3299 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3300 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3301 // CHECK5-NEXT: entry: 3302 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3303 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3304 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3305 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3306 // CHECK5-NEXT: ret void 3307 // 3308 // 3309 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3310 // CHECK5-SAME: () #[[ATTR0]] { 3311 // CHECK5-NEXT: entry: 3312 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 3313 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 3314 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3315 // CHECK5-NEXT: ret void 3316 // 3317 // 3318 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3319 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3320 // CHECK5-NEXT: entry: 3321 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3322 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3323 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3324 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3325 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3326 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3327 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3328 // CHECK5-NEXT: ret void 3329 // 3330 // 3331 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3332 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3333 // CHECK5-NEXT: entry: 3334 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3335 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3336 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3337 // CHECK5: arraydestroy.body: 3338 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3339 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3340 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3341 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3342 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3343 // CHECK5: arraydestroy.done1: 3344 // CHECK5-NEXT: ret void 3345 // 3346 // 3347 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3348 // CHECK5-SAME: () #[[ATTR0]] { 3349 // CHECK5-NEXT: entry: 3350 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3351 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3352 // CHECK5-NEXT: ret void 3353 // 3354 // 3355 // CHECK5-LABEL: define {{[^@]+}}@main 3356 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 3357 // CHECK5-NEXT: entry: 3358 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3359 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3360 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 3361 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 3362 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 3363 // CHECK5: for.cond: 3364 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3365 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 3366 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3367 // CHECK5: for.body: 3368 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 3369 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3370 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 3371 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 3372 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3373 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3374 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 3375 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 3376 // CHECK5-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 3377 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) 3378 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3379 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 3380 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 3381 // CHECK5-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 3382 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 3383 // CHECK5: for.inc: 3384 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 3385 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 3386 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 3387 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 3388 // CHECK5: for.end: 3389 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 3390 // CHECK5-NEXT: ret i32 [[CALL]] 3391 // 3392 // 3393 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3394 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 3395 // CHECK5-NEXT: entry: 3396 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3397 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3398 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3399 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3400 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3401 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 3402 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 3403 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 3404 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3405 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3406 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 3407 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3408 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3409 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3410 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 3411 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3412 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 3413 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 3414 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3415 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 3416 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3417 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 3418 // CHECK5-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 3419 // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 3420 // CHECK5-NEXT: br label [[FOR_COND:%.*]] 3421 // CHECK5: for.cond: 3422 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 3423 // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 3424 // CHECK5-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3425 // CHECK5: for.body: 3426 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 3427 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 3428 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 3429 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 3430 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 3431 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 3432 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3433 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 3434 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 3435 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* 3436 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 3437 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) 3438 // CHECK5-NEXT: br label [[FOR_INC:%.*]] 3439 // CHECK5: for.inc: 3440 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 3441 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 3442 // CHECK5-NEXT: store i32 [[INC]], i32* [[I]], align 4 3443 // CHECK5-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3444 // CHECK5: for.end: 3445 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 3446 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3447 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3448 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3449 // CHECK5: arraydestroy.body: 3450 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3451 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3452 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3453 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3454 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 3455 // CHECK5: arraydestroy.done4: 3456 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3457 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 3458 // CHECK5-NEXT: ret i32 [[TMP13]] 3459 // 3460 // 3461 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3462 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3463 // CHECK5-NEXT: entry: 3464 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3465 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3466 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3467 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3468 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3469 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3470 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 3471 // CHECK5-NEXT: ret void 3472 // 3473 // 3474 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3475 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3476 // CHECK5-NEXT: entry: 3477 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3478 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3479 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3480 // CHECK5-NEXT: ret void 3481 // 3482 // 3483 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3484 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3485 // CHECK5-NEXT: entry: 3486 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3487 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3488 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3489 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3490 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3491 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3492 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3493 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3494 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3495 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3496 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 3497 // CHECK5-NEXT: ret void 3498 // 3499 // 3500 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3501 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3502 // CHECK5-NEXT: entry: 3503 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3504 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3505 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3506 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3507 // CHECK5-NEXT: ret void 3508 // 3509 // 3510 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3511 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3512 // CHECK5-NEXT: entry: 3513 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3514 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3515 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3516 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3517 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3518 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3519 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 3520 // CHECK5-NEXT: ret void 3521 // 3522 // 3523 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3524 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3525 // CHECK5-NEXT: entry: 3526 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3527 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3528 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3529 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3530 // CHECK5-NEXT: ret void 3531 // 3532 // 3533 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3534 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3535 // CHECK5-NEXT: entry: 3536 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3537 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3538 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3539 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3540 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3541 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3542 // CHECK5-NEXT: ret void 3543 // 3544 // 3545 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3546 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3547 // CHECK5-NEXT: entry: 3548 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3549 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3550 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3551 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3552 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3553 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3554 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3555 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3556 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3557 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3558 // CHECK5-NEXT: ret void 3559 // 3560 // 3561 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3562 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3563 // CHECK5-NEXT: entry: 3564 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3565 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3566 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3567 // CHECK5-NEXT: ret void 3568 // 3569 // 3570 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 3571 // CHECK5-SAME: () #[[ATTR0]] { 3572 // CHECK5-NEXT: entry: 3573 // CHECK5-NEXT: call void @__cxx_global_var_init() 3574 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 3575 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 3576 // CHECK5-NEXT: ret void 3577 // 3578 // 3579 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init 3580 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 3581 // CHECK6-NEXT: entry: 3582 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3583 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3584 // CHECK6-NEXT: ret void 3585 // 3586 // 3587 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3588 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3589 // CHECK6-NEXT: entry: 3590 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3591 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3592 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3593 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3594 // CHECK6-NEXT: ret void 3595 // 3596 // 3597 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3598 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3599 // CHECK6-NEXT: entry: 3600 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3601 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3602 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3603 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3604 // CHECK6-NEXT: ret void 3605 // 3606 // 3607 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3608 // CHECK6-SAME: () #[[ATTR0]] { 3609 // CHECK6-NEXT: entry: 3610 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 3611 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 3612 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3613 // CHECK6-NEXT: ret void 3614 // 3615 // 3616 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3617 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3618 // CHECK6-NEXT: entry: 3619 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3620 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3621 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3622 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3623 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3624 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3625 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3626 // CHECK6-NEXT: ret void 3627 // 3628 // 3629 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3630 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3631 // CHECK6-NEXT: entry: 3632 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3633 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3634 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3635 // CHECK6: arraydestroy.body: 3636 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3637 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3638 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3639 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3640 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3641 // CHECK6: arraydestroy.done1: 3642 // CHECK6-NEXT: ret void 3643 // 3644 // 3645 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3646 // CHECK6-SAME: () #[[ATTR0]] { 3647 // CHECK6-NEXT: entry: 3648 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3649 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3650 // CHECK6-NEXT: ret void 3651 // 3652 // 3653 // CHECK6-LABEL: define {{[^@]+}}@main 3654 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] { 3655 // CHECK6-NEXT: entry: 3656 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3657 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3658 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 3659 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 3660 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3661 // CHECK6: for.cond: 3662 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3663 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 3664 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3665 // CHECK6: for.body: 3666 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 3667 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3668 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 3669 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 3670 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3671 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3672 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP3]] to i64 3673 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 3674 // CHECK6-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 3675 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) 3676 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3677 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 3678 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 3679 // CHECK6-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 3680 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3681 // CHECK6: for.inc: 3682 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 3683 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 3684 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 3685 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 3686 // CHECK6: for.end: 3687 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 3688 // CHECK6-NEXT: ret i32 [[CALL]] 3689 // 3690 // 3691 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3692 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { 3693 // CHECK6-NEXT: entry: 3694 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3695 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3696 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3697 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3698 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3699 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 3700 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 3701 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 3702 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3703 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3704 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 3705 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3706 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3707 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3708 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 3709 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3710 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 3711 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 3712 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3713 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 3714 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3715 // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 3716 // CHECK6-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 8 3717 // CHECK6-NEXT: store i32 0, i32* [[I]], align 4 3718 // CHECK6-NEXT: br label [[FOR_COND:%.*]] 3719 // CHECK6: for.cond: 3720 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 3721 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 3722 // CHECK6-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3723 // CHECK6: for.body: 3724 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 3725 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 3726 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 3727 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 3728 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 3729 // CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 3730 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 3731 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP8]] to i64 3732 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 3733 // CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* 3734 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 3735 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false) 3736 // CHECK6-NEXT: br label [[FOR_INC:%.*]] 3737 // CHECK6: for.inc: 3738 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 3739 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 3740 // CHECK6-NEXT: store i32 [[INC]], i32* [[I]], align 4 3741 // CHECK6-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3742 // CHECK6: for.end: 3743 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 3744 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3745 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3746 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3747 // CHECK6: arraydestroy.body: 3748 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3749 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3750 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3751 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3752 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 3753 // CHECK6: arraydestroy.done4: 3754 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 3755 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 3756 // CHECK6-NEXT: ret i32 [[TMP13]] 3757 // 3758 // 3759 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3760 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3761 // CHECK6-NEXT: entry: 3762 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3763 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3764 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3765 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3766 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3767 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3768 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 3769 // CHECK6-NEXT: ret void 3770 // 3771 // 3772 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3773 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3774 // CHECK6-NEXT: entry: 3775 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3776 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3777 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3778 // CHECK6-NEXT: ret void 3779 // 3780 // 3781 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3782 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3783 // CHECK6-NEXT: entry: 3784 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3785 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3786 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3787 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3788 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3789 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3790 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3791 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3792 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3793 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3794 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 3795 // CHECK6-NEXT: ret void 3796 // 3797 // 3798 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3799 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3800 // CHECK6-NEXT: entry: 3801 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3802 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3803 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3804 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3805 // CHECK6-NEXT: ret void 3806 // 3807 // 3808 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3809 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3810 // CHECK6-NEXT: entry: 3811 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3812 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3813 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3814 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3815 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3816 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3817 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 3818 // CHECK6-NEXT: ret void 3819 // 3820 // 3821 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3822 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3823 // CHECK6-NEXT: entry: 3824 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3825 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3826 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3827 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3828 // CHECK6-NEXT: ret void 3829 // 3830 // 3831 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3832 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3833 // CHECK6-NEXT: entry: 3834 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3835 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3836 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3837 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3838 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3839 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3840 // CHECK6-NEXT: ret void 3841 // 3842 // 3843 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3844 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3845 // CHECK6-NEXT: entry: 3846 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3847 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3848 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3849 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3850 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3851 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3852 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3853 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3854 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3855 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3856 // CHECK6-NEXT: ret void 3857 // 3858 // 3859 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3860 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3861 // CHECK6-NEXT: entry: 3862 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3863 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3864 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3865 // CHECK6-NEXT: ret void 3866 // 3867 // 3868 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 3869 // CHECK6-SAME: () #[[ATTR0]] { 3870 // CHECK6-NEXT: entry: 3871 // CHECK6-NEXT: call void @__cxx_global_var_init() 3872 // CHECK6-NEXT: call void @__cxx_global_var_init.1() 3873 // CHECK6-NEXT: call void @__cxx_global_var_init.2() 3874 // CHECK6-NEXT: ret void 3875 // 3876 // 3877 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 3878 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 3879 // CHECK7-NEXT: entry: 3880 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 3881 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3882 // CHECK7-NEXT: ret void 3883 // 3884 // 3885 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3886 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3887 // CHECK7-NEXT: entry: 3888 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3889 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3890 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3891 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 3892 // CHECK7-NEXT: ret void 3893 // 3894 // 3895 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3896 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3897 // CHECK7-NEXT: entry: 3898 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3899 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3900 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3901 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 3902 // CHECK7-NEXT: ret void 3903 // 3904 // 3905 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3906 // CHECK7-SAME: () #[[ATTR0]] { 3907 // CHECK7-NEXT: entry: 3908 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 3909 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 3910 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3911 // CHECK7-NEXT: ret void 3912 // 3913 // 3914 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3915 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3916 // CHECK7-NEXT: entry: 3917 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3918 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3919 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3920 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3921 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3922 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3923 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 3924 // CHECK7-NEXT: ret void 3925 // 3926 // 3927 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3928 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 3929 // CHECK7-NEXT: entry: 3930 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 3931 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 3932 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3933 // CHECK7: arraydestroy.body: 3934 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3935 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3936 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3937 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3938 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3939 // CHECK7: arraydestroy.done1: 3940 // CHECK7-NEXT: ret void 3941 // 3942 // 3943 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3944 // CHECK7-SAME: () #[[ATTR0]] { 3945 // CHECK7-NEXT: entry: 3946 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 3947 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3948 // CHECK7-NEXT: ret void 3949 // 3950 // 3951 // CHECK7-LABEL: define {{[^@]+}}@main 3952 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 3953 // CHECK7-NEXT: entry: 3954 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3955 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3956 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 3957 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 3958 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 3959 // CHECK7: for.cond: 3960 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 3961 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 3962 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 3963 // CHECK7: for.body: 3964 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 3965 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 3966 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] 3967 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 3968 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 3969 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] 3970 // CHECK7-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 3971 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) 3972 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 3973 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 3974 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 3975 // CHECK7-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 3976 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 3977 // CHECK7: for.inc: 3978 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 3979 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 3980 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 3981 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 3982 // CHECK7: for.end: 3983 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 3984 // CHECK7-NEXT: ret i32 [[CALL]] 3985 // 3986 // 3987 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3988 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 3989 // CHECK7-NEXT: entry: 3990 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3991 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3992 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3993 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3994 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3995 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 3996 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3997 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 3998 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 3999 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 4000 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 4001 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4002 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 4003 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4004 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 4005 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 4006 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 4007 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 4008 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4009 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 4010 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4011 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 4012 // CHECK7-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 4013 // CHECK7-NEXT: store i32 0, i32* [[I]], align 4 4014 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 4015 // CHECK7: for.cond: 4016 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 4017 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 4018 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4019 // CHECK7: for.body: 4020 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 4021 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 4022 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] 4023 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 4024 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 4025 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 4026 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] 4027 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* 4028 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 4029 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) 4030 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 4031 // CHECK7: for.inc: 4032 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 4033 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 4034 // CHECK7-NEXT: store i32 [[INC]], i32* [[I]], align 4 4035 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 4036 // CHECK7: for.end: 4037 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 4038 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4039 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4040 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4041 // CHECK7: arraydestroy.body: 4042 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4043 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4044 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4045 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4046 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 4047 // CHECK7: arraydestroy.done3: 4048 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 4049 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 4050 // CHECK7-NEXT: ret i32 [[TMP13]] 4051 // 4052 // 4053 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4054 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4055 // CHECK7-NEXT: entry: 4056 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4057 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4058 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4059 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4060 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4061 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4062 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 4063 // CHECK7-NEXT: ret void 4064 // 4065 // 4066 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4067 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4068 // CHECK7-NEXT: entry: 4069 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4070 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4071 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4072 // CHECK7-NEXT: ret void 4073 // 4074 // 4075 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4076 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4077 // CHECK7-NEXT: entry: 4078 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4079 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4080 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4081 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4082 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4083 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4084 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4085 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4086 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4087 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4088 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 4089 // CHECK7-NEXT: ret void 4090 // 4091 // 4092 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4093 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4094 // CHECK7-NEXT: entry: 4095 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4096 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4097 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4098 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 4099 // CHECK7-NEXT: ret void 4100 // 4101 // 4102 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4103 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4104 // CHECK7-NEXT: entry: 4105 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4106 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4107 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4108 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4109 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4110 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4111 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 4112 // CHECK7-NEXT: ret void 4113 // 4114 // 4115 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4116 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4117 // CHECK7-NEXT: entry: 4118 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4119 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4120 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4121 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4122 // CHECK7-NEXT: ret void 4123 // 4124 // 4125 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4126 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4127 // CHECK7-NEXT: entry: 4128 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4129 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4130 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4131 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4132 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4133 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4134 // CHECK7-NEXT: ret void 4135 // 4136 // 4137 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4138 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4139 // CHECK7-NEXT: entry: 4140 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4141 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4142 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4143 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4144 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4145 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4146 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4147 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4148 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4149 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4150 // CHECK7-NEXT: ret void 4151 // 4152 // 4153 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4154 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4155 // CHECK7-NEXT: entry: 4156 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4157 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4158 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4159 // CHECK7-NEXT: ret void 4160 // 4161 // 4162 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 4163 // CHECK7-SAME: () #[[ATTR0]] { 4164 // CHECK7-NEXT: entry: 4165 // CHECK7-NEXT: call void @__cxx_global_var_init() 4166 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 4167 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 4168 // CHECK7-NEXT: ret void 4169 // 4170 // 4171 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init 4172 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 4173 // CHECK8-NEXT: entry: 4174 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4175 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4176 // CHECK8-NEXT: ret void 4177 // 4178 // 4179 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4180 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4181 // CHECK8-NEXT: entry: 4182 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4183 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4184 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4185 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4186 // CHECK8-NEXT: ret void 4187 // 4188 // 4189 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4190 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4191 // CHECK8-NEXT: entry: 4192 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4193 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4194 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4195 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4196 // CHECK8-NEXT: ret void 4197 // 4198 // 4199 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4200 // CHECK8-SAME: () #[[ATTR0]] { 4201 // CHECK8-NEXT: entry: 4202 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00) 4203 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00) 4204 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4205 // CHECK8-NEXT: ret void 4206 // 4207 // 4208 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4209 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4210 // CHECK8-NEXT: entry: 4211 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4212 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4213 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4214 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4215 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4216 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4217 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4218 // CHECK8-NEXT: ret void 4219 // 4220 // 4221 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4222 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4223 // CHECK8-NEXT: entry: 4224 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 4225 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 4226 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4227 // CHECK8: arraydestroy.body: 4228 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4229 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4230 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4231 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4232 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4233 // CHECK8: arraydestroy.done1: 4234 // CHECK8-NEXT: ret void 4235 // 4236 // 4237 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4238 // CHECK8-SAME: () #[[ATTR0]] { 4239 // CHECK8-NEXT: entry: 4240 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4241 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4242 // CHECK8-NEXT: ret void 4243 // 4244 // 4245 // CHECK8-LABEL: define {{[^@]+}}@main 4246 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] { 4247 // CHECK8-NEXT: entry: 4248 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4249 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 4250 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 4251 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 4252 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 4253 // CHECK8: for.cond: 4254 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 4255 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 2 4256 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4257 // CHECK8: for.body: 4258 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 4259 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 4260 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP2]] 4261 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 4262 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4 4263 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP3]] 4264 // CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 4265 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP4]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false) 4266 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 4267 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 4268 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 4269 // CHECK8-NEXT: store i32 [[ADD]], i32* @_ZZ4mainE5sivar, align 4 4270 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 4271 // CHECK8: for.inc: 4272 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[I]], align 4 4273 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 4274 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 4275 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 4276 // CHECK8: for.end: 4277 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 4278 // CHECK8-NEXT: ret i32 [[CALL]] 4279 // 4280 // 4281 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4282 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { 4283 // CHECK8-NEXT: entry: 4284 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4285 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4286 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 4287 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4288 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 4289 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 4290 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 4291 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 4292 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 4293 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 4294 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 4295 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4296 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 4297 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4298 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 4299 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 4300 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 4301 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 4302 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4303 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 4304 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4305 // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 4306 // CHECK8-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[_TMP1]], align 4 4307 // CHECK8-NEXT: store i32 0, i32* [[I]], align 4 4308 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 4309 // CHECK8: for.cond: 4310 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 4311 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], 2 4312 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 4313 // CHECK8: for.body: 4314 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 4315 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4 4316 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP6]] 4317 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4 4318 // CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 4319 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 4320 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP8]] 4321 // CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* 4322 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8* 4323 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false) 4324 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 4325 // CHECK8: for.inc: 4326 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 4327 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 4328 // CHECK8-NEXT: store i32 [[INC]], i32* [[I]], align 4 4329 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 4330 // CHECK8: for.end: 4331 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 4332 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4333 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4334 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4335 // CHECK8: arraydestroy.body: 4336 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4337 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4338 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4339 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4340 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] 4341 // CHECK8: arraydestroy.done3: 4342 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 4343 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[RETVAL]], align 4 4344 // CHECK8-NEXT: ret i32 [[TMP13]] 4345 // 4346 // 4347 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4348 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4349 // CHECK8-NEXT: entry: 4350 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4351 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4352 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4353 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4354 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4355 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4356 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 4357 // CHECK8-NEXT: ret void 4358 // 4359 // 4360 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4361 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4362 // CHECK8-NEXT: entry: 4363 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4364 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4365 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4366 // CHECK8-NEXT: ret void 4367 // 4368 // 4369 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4370 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4371 // CHECK8-NEXT: entry: 4372 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4373 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4374 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4375 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4376 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4377 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4378 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4379 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4380 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4381 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4382 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 4383 // CHECK8-NEXT: ret void 4384 // 4385 // 4386 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4387 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4388 // CHECK8-NEXT: entry: 4389 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4390 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4391 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4392 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 4393 // CHECK8-NEXT: ret void 4394 // 4395 // 4396 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4397 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4398 // CHECK8-NEXT: entry: 4399 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4400 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4401 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4402 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4403 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4404 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4405 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 4406 // CHECK8-NEXT: ret void 4407 // 4408 // 4409 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4410 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4411 // CHECK8-NEXT: entry: 4412 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4413 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4414 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4415 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4416 // CHECK8-NEXT: ret void 4417 // 4418 // 4419 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4420 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4421 // CHECK8-NEXT: entry: 4422 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4423 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4424 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4425 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4426 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4427 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4428 // CHECK8-NEXT: ret void 4429 // 4430 // 4431 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4432 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4433 // CHECK8-NEXT: entry: 4434 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4435 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4436 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4437 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4438 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4439 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4440 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4441 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4442 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4443 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4444 // CHECK8-NEXT: ret void 4445 // 4446 // 4447 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4448 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4449 // CHECK8-NEXT: entry: 4450 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4451 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4452 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4453 // CHECK8-NEXT: ret void 4454 // 4455 // 4456 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 4457 // CHECK8-SAME: () #[[ATTR0]] { 4458 // CHECK8-NEXT: entry: 4459 // CHECK8-NEXT: call void @__cxx_global_var_init() 4460 // CHECK8-NEXT: call void @__cxx_global_var_init.1() 4461 // CHECK8-NEXT: call void @__cxx_global_var_init.2() 4462 // CHECK8-NEXT: ret void 4463 // 4464 // 4465 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 4466 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 4467 // CHECK9-NEXT: entry: 4468 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4469 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4470 // CHECK9-NEXT: ret void 4471 // 4472 // 4473 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4474 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4475 // CHECK9-NEXT: entry: 4476 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4477 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4478 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4479 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4480 // CHECK9-NEXT: ret void 4481 // 4482 // 4483 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4484 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4485 // CHECK9-NEXT: entry: 4486 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4487 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4488 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4489 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4490 // CHECK9-NEXT: ret void 4491 // 4492 // 4493 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4494 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4495 // CHECK9-NEXT: entry: 4496 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4497 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4498 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4499 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4500 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4501 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4502 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 4503 // CHECK9-NEXT: ret void 4504 // 4505 // 4506 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4507 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4508 // CHECK9-NEXT: entry: 4509 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4510 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4511 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4512 // CHECK9-NEXT: ret void 4513 // 4514 // 4515 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4516 // CHECK9-SAME: () #[[ATTR0]] { 4517 // CHECK9-NEXT: entry: 4518 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4519 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4520 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4521 // CHECK9-NEXT: ret void 4522 // 4523 // 4524 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4525 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4526 // CHECK9-NEXT: entry: 4527 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4528 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4529 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4530 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4531 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4532 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4533 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4534 // CHECK9-NEXT: ret void 4535 // 4536 // 4537 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4538 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4539 // CHECK9-NEXT: entry: 4540 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4541 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4542 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4543 // CHECK9: arraydestroy.body: 4544 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4545 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4546 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4547 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4548 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4549 // CHECK9: arraydestroy.done1: 4550 // CHECK9-NEXT: ret void 4551 // 4552 // 4553 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4554 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4555 // CHECK9-NEXT: entry: 4556 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4557 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4558 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4559 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4560 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4561 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4562 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4563 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4564 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4565 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4566 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 4567 // CHECK9-NEXT: ret void 4568 // 4569 // 4570 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4571 // CHECK9-SAME: () #[[ATTR0]] { 4572 // CHECK9-NEXT: entry: 4573 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4574 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4575 // CHECK9-NEXT: ret void 4576 // 4577 // 4578 // CHECK9-LABEL: define {{[^@]+}}@main 4579 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 4580 // CHECK9-NEXT: entry: 4581 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4582 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 4583 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 4584 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 4585 // CHECK9-NEXT: ret i32 0 4586 // 4587 // 4588 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 4589 // CHECK9-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 4590 // CHECK9-NEXT: entry: 4591 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4592 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4593 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4594 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4595 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 4596 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 4597 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 4598 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4599 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4600 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4601 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4602 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4603 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4604 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 4605 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 4606 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 4607 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 4608 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 4609 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 4610 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 4611 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 4612 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 4613 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 4614 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 4615 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 4616 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 4617 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 4618 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 4619 // CHECK9-NEXT: ret void 4620 // 4621 // 4622 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 4623 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { 4624 // CHECK9-NEXT: entry: 4625 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4626 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4627 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4628 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4629 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4630 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4631 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4632 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 4633 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4634 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4635 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4636 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4637 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4638 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 4639 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4640 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4641 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4642 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4643 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4644 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4645 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4646 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4647 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 4648 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4649 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4650 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4651 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4652 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4653 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4654 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4655 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4656 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 4657 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4658 // CHECK9: cond.true: 4659 // CHECK9-NEXT: br label [[COND_END:%.*]] 4660 // CHECK9: cond.false: 4661 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4662 // CHECK9-NEXT: br label [[COND_END]] 4663 // CHECK9: cond.end: 4664 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4665 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4666 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4667 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4668 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4669 // CHECK9: omp.inner.for.cond: 4670 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4671 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4672 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4673 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4674 // CHECK9: omp.inner.for.body: 4675 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4676 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4677 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4678 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4679 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 8 4680 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 4681 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 4682 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 8 4683 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 4684 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 4685 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 4686 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 4687 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 4688 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 4689 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 4690 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 4691 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4692 // CHECK9: omp.body.continue: 4693 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4694 // CHECK9: omp.inner.for.inc: 4695 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4696 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 4697 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 4698 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4699 // CHECK9: omp.inner.for.end: 4700 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4701 // CHECK9: omp.loop.exit: 4702 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4703 // CHECK9-NEXT: ret void 4704 // 4705 // 4706 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 4707 // CHECK9-SAME: () #[[ATTR0]] { 4708 // CHECK9-NEXT: entry: 4709 // CHECK9-NEXT: call void @__cxx_global_var_init() 4710 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 4711 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 4712 // CHECK9-NEXT: ret void 4713 // 4714 // 4715 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4716 // CHECK9-SAME: () #[[ATTR0]] { 4717 // CHECK9-NEXT: entry: 4718 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 4719 // CHECK9-NEXT: ret void 4720 // 4721 // 4722 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init 4723 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 4724 // CHECK10-NEXT: entry: 4725 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4726 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4727 // CHECK10-NEXT: ret void 4728 // 4729 // 4730 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4731 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4732 // CHECK10-NEXT: entry: 4733 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4734 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4735 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4736 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4737 // CHECK10-NEXT: ret void 4738 // 4739 // 4740 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4741 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4742 // CHECK10-NEXT: entry: 4743 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4744 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4745 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4746 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 4747 // CHECK10-NEXT: ret void 4748 // 4749 // 4750 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4751 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4752 // CHECK10-NEXT: entry: 4753 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4754 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4755 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4756 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4757 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4758 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4759 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 4760 // CHECK10-NEXT: ret void 4761 // 4762 // 4763 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4764 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4765 // CHECK10-NEXT: entry: 4766 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4767 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4768 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4769 // CHECK10-NEXT: ret void 4770 // 4771 // 4772 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4773 // CHECK10-SAME: () #[[ATTR0]] { 4774 // CHECK10-NEXT: entry: 4775 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 4776 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 4777 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4778 // CHECK10-NEXT: ret void 4779 // 4780 // 4781 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4782 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4783 // CHECK10-NEXT: entry: 4784 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4785 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4786 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4787 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4788 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4789 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4790 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 4791 // CHECK10-NEXT: ret void 4792 // 4793 // 4794 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4795 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 4796 // CHECK10-NEXT: entry: 4797 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4798 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4799 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4800 // CHECK10: arraydestroy.body: 4801 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4802 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4803 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4804 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4805 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4806 // CHECK10: arraydestroy.done1: 4807 // CHECK10-NEXT: ret void 4808 // 4809 // 4810 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4811 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4812 // CHECK10-NEXT: entry: 4813 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4814 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4815 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4816 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4817 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4818 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4819 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4820 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4821 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4822 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4823 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 4824 // CHECK10-NEXT: ret void 4825 // 4826 // 4827 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4828 // CHECK10-SAME: () #[[ATTR0]] { 4829 // CHECK10-NEXT: entry: 4830 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 4831 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4832 // CHECK10-NEXT: ret void 4833 // 4834 // 4835 // CHECK10-LABEL: define {{[^@]+}}@main 4836 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 4837 // CHECK10-NEXT: entry: 4838 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4839 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 4840 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 4841 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 4842 // CHECK10-NEXT: ret i32 0 4843 // 4844 // 4845 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 4846 // CHECK10-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]], i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 4847 // CHECK10-NEXT: entry: 4848 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4849 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4850 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4851 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4852 // CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 4853 // CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 4854 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 4855 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4856 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4857 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4858 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4859 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4860 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4861 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP]], align 8 4862 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 4863 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 4864 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 4865 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 4866 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 4867 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 4868 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 4869 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 4870 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 4871 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 4872 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 4873 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 4874 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 4875 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 4876 // CHECK10-NEXT: ret void 4877 // 4878 // 4879 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 4880 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR5]] { 4881 // CHECK10-NEXT: entry: 4882 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4883 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4884 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4885 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4886 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4887 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4888 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4889 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 4890 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4891 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4892 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4893 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4894 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 4895 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 4896 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4897 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4898 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4899 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4900 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4901 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4902 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4903 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4904 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 4905 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4906 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4907 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4908 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4909 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4910 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4911 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4912 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4913 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 4914 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4915 // CHECK10: cond.true: 4916 // CHECK10-NEXT: br label [[COND_END:%.*]] 4917 // CHECK10: cond.false: 4918 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4919 // CHECK10-NEXT: br label [[COND_END]] 4920 // CHECK10: cond.end: 4921 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4922 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4923 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4924 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4925 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4926 // CHECK10: omp.inner.for.cond: 4927 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4928 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4929 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4930 // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4931 // CHECK10: omp.inner.for.body: 4932 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4933 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4934 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4935 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4936 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 8 4937 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8 4938 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4 4939 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 8 4940 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 4941 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8 4942 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 4943 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8 4944 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8 4945 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 4946 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8 4947 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]]) 4948 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4949 // CHECK10: omp.body.continue: 4950 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4951 // CHECK10: omp.inner.for.inc: 4952 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4953 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 4954 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4 4955 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] 4956 // CHECK10: omp.inner.for.end: 4957 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4958 // CHECK10: omp.loop.exit: 4959 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4960 // CHECK10-NEXT: ret void 4961 // 4962 // 4963 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 4964 // CHECK10-SAME: () #[[ATTR0]] { 4965 // CHECK10-NEXT: entry: 4966 // CHECK10-NEXT: call void @__cxx_global_var_init() 4967 // CHECK10-NEXT: call void @__cxx_global_var_init.1() 4968 // CHECK10-NEXT: call void @__cxx_global_var_init.2() 4969 // CHECK10-NEXT: ret void 4970 // 4971 // 4972 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4973 // CHECK10-SAME: () #[[ATTR0]] { 4974 // CHECK10-NEXT: entry: 4975 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 4976 // CHECK10-NEXT: ret void 4977 // 4978 // 4979 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 4980 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 4981 // CHECK11-NEXT: entry: 4982 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 4983 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4984 // CHECK11-NEXT: ret void 4985 // 4986 // 4987 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4988 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4989 // CHECK11-NEXT: entry: 4990 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4991 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4992 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4993 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 4994 // CHECK11-NEXT: ret void 4995 // 4996 // 4997 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4998 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4999 // CHECK11-NEXT: entry: 5000 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5001 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5002 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5003 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 5004 // CHECK11-NEXT: ret void 5005 // 5006 // 5007 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5008 // CHECK11-SAME: () #[[ATTR0]] { 5009 // CHECK11-NEXT: entry: 5010 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 5011 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 5012 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5013 // CHECK11-NEXT: ret void 5014 // 5015 // 5016 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5017 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5018 // CHECK11-NEXT: entry: 5019 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5020 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5021 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5022 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5023 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5024 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5025 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 5026 // CHECK11-NEXT: ret void 5027 // 5028 // 5029 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5030 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 5031 // CHECK11-NEXT: entry: 5032 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 5033 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 5034 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5035 // CHECK11: arraydestroy.body: 5036 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5037 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5038 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5039 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5040 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5041 // CHECK11: arraydestroy.done1: 5042 // CHECK11-NEXT: ret void 5043 // 5044 // 5045 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5046 // CHECK11-SAME: () #[[ATTR0]] { 5047 // CHECK11-NEXT: entry: 5048 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 5049 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5050 // CHECK11-NEXT: ret void 5051 // 5052 // 5053 // CHECK11-LABEL: define {{[^@]+}}@main 5054 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 5055 // CHECK11-NEXT: entry: 5056 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5057 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5058 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 5059 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 5060 // CHECK11-NEXT: ret i32 0 5061 // 5062 // 5063 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5064 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5065 // CHECK11-NEXT: entry: 5066 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5067 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5068 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5069 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5070 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5071 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5072 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 5073 // CHECK11-NEXT: ret void 5074 // 5075 // 5076 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5077 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5078 // CHECK11-NEXT: entry: 5079 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5080 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5081 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5082 // CHECK11-NEXT: ret void 5083 // 5084 // 5085 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5086 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5087 // CHECK11-NEXT: entry: 5088 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5089 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5090 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5091 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5092 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5093 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5094 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5095 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5096 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5097 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5098 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 5099 // CHECK11-NEXT: ret void 5100 // 5101 // 5102 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 5103 // CHECK11-SAME: () #[[ATTR0]] { 5104 // CHECK11-NEXT: entry: 5105 // CHECK11-NEXT: call void @__cxx_global_var_init() 5106 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 5107 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 5108 // CHECK11-NEXT: ret void 5109 // 5110 // 5111 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init 5112 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 5113 // CHECK12-NEXT: entry: 5114 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 5115 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 5116 // CHECK12-NEXT: ret void 5117 // 5118 // 5119 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 5120 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 5121 // CHECK12-NEXT: entry: 5122 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5123 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5124 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5125 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 5126 // CHECK12-NEXT: ret void 5127 // 5128 // 5129 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 5130 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5131 // CHECK12-NEXT: entry: 5132 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5133 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5134 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5135 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 5136 // CHECK12-NEXT: ret void 5137 // 5138 // 5139 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5140 // CHECK12-SAME: () #[[ATTR0]] { 5141 // CHECK12-NEXT: entry: 5142 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 5143 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 5144 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5145 // CHECK12-NEXT: ret void 5146 // 5147 // 5148 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5149 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5150 // CHECK12-NEXT: entry: 5151 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5152 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5153 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5154 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5155 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5156 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5157 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 5158 // CHECK12-NEXT: ret void 5159 // 5160 // 5161 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5162 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] { 5163 // CHECK12-NEXT: entry: 5164 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 5165 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 5166 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5167 // CHECK12: arraydestroy.body: 5168 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5169 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5170 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5171 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5172 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5173 // CHECK12: arraydestroy.done1: 5174 // CHECK12-NEXT: ret void 5175 // 5176 // 5177 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5178 // CHECK12-SAME: () #[[ATTR0]] { 5179 // CHECK12-NEXT: entry: 5180 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 5181 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5182 // CHECK12-NEXT: ret void 5183 // 5184 // 5185 // CHECK12-LABEL: define {{[^@]+}}@main 5186 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 5187 // CHECK12-NEXT: entry: 5188 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5189 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5190 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 5191 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 5192 // CHECK12-NEXT: ret i32 0 5193 // 5194 // 5195 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5196 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5197 // CHECK12-NEXT: entry: 5198 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5199 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5200 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5201 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5202 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5203 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5204 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 5205 // CHECK12-NEXT: ret void 5206 // 5207 // 5208 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5209 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5210 // CHECK12-NEXT: entry: 5211 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5212 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5213 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5214 // CHECK12-NEXT: ret void 5215 // 5216 // 5217 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5218 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5219 // CHECK12-NEXT: entry: 5220 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5221 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5222 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5223 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5224 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5225 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5226 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5227 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5228 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5229 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5230 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 5231 // CHECK12-NEXT: ret void 5232 // 5233 // 5234 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_firstprivate_codegen.cpp 5235 // CHECK12-SAME: () #[[ATTR0]] { 5236 // CHECK12-NEXT: entry: 5237 // CHECK12-NEXT: call void @__cxx_global_var_init() 5238 // CHECK12-NEXT: call void @__cxx_global_var_init.1() 5239 // CHECK12-NEXT: call void @__cxx_global_var_init.2() 5240 // CHECK12-NEXT: ret void 5241 // 5242