1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // expected-no-diagnostics 3 #ifndef HEADER 4 #define HEADER 5 // Test host codegen. 6 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 7 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 9 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 10 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 12 13 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 14 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 16 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 17 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 19 #ifdef CK1 20 21 int Gbla; 22 long long Gblb; 23 int &Gblc = Gbla; 24 25 int teams_argument_global_local(int a){ 26 int comp = 1; 27 28 int la = 23; 29 float lc = 25.0; 30 31 #pragma omp target 32 #pragma omp teams 33 { 34 ++comp; 35 } 36 37 #pragma omp target 38 {{{ 39 #pragma omp teams 40 { 41 ++comp; 42 } 43 }}} 44 45 46 #pragma omp target 47 #pragma omp teams num_teams(la) 48 { 49 ++comp; 50 } 51 52 53 #pragma omp target 54 #pragma omp teams thread_limit(la) 55 { 56 ++comp; 57 } 58 59 60 61 62 #pragma omp target 63 #pragma omp teams num_teams(Gbla+a) thread_limit(Gblb+(long long)lc) 64 { 65 ++comp; 66 } 67 68 69 70 71 #pragma omp target 72 #pragma omp teams num_teams(Gblc+1) thread_limit(Gblc+2) 73 { 74 comp += Gblc; 75 } 76 77 return comp; 78 } 79 80 #endif // CK1 81 82 // Test host codegen. 83 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 84 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 85 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 86 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 87 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 88 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 89 90 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 91 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 92 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 93 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 94 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 95 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 96 #ifdef CK2 97 98 template <typename T> 99 struct SS{ 100 T a; 101 float b; 102 }; 103 104 SS<int> Gbla; 105 SS<long long> Gblb; 106 107 int teams_template_arg(void) { 108 int comp = 1; 109 110 SS<int> la; 111 SS<long long> lb; 112 113 114 115 116 #pragma omp target 117 #pragma omp teams num_teams(Gbla.a) thread_limit((long long)la.b) 118 { 119 ++comp; 120 } 121 122 123 124 125 #pragma omp target 126 #pragma omp teams num_teams((long long)lb.b) thread_limit(Gblb.a) 127 { 128 ++comp; 129 } 130 return comp; 131 } 132 #endif // CK2 133 134 // Test host codegen. 135 // RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 136 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 137 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 138 // RUN: %clang_cc1 -DCK3 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 139 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 140 // RUN: %clang_cc1 -DCK3 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 141 142 // RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 143 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 144 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 145 // RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 146 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 147 // RUN: %clang_cc1 -DCK3 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 148 #ifdef CK3 149 150 151 template <typename T, int X, long long Y> 152 struct SS{ 153 T a; 154 float b; 155 156 int foo(void) { 157 int comp = 1; 158 159 160 161 #pragma omp target 162 #pragma omp teams num_teams(a) thread_limit(X) 163 { 164 ++comp; 165 } 166 167 168 169 #pragma omp target 170 #pragma omp teams num_teams(Y) thread_limit((int)b+X) 171 { 172 ++comp; 173 } 174 return comp; 175 } 176 }; 177 178 int teams_template_struct(void) { 179 SS<int, 123, 456> V; 180 return V.foo(); 181 182 } 183 #endif // CK3 184 185 // Test target codegen - host bc file has to be created first. 186 // RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 187 // RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 188 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 189 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 190 // RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 191 // RUN: %clang_cc1 -DCK4 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 192 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 193 // RUN: %clang_cc1 -DCK4 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 194 195 // RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 196 // RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 197 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 198 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 199 // RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 200 // RUN: %clang_cc1 -DCK4 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 201 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 202 // RUN: %clang_cc1 -DCK4 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 203 204 #ifdef CK4 205 206 207 template <typename T> 208 int tmain(T argc) { 209 #pragma omp target 210 #pragma omp teams 211 argc = 0; 212 return 0; 213 } 214 215 int main (int argc, char **argv) { 216 #pragma omp target 217 #pragma omp teams 218 argc = 0; 219 return tmain(argv); 220 } 221 222 223 224 225 #endif // CK4 226 227 // Test target codegen - host bc file has to be created first. 228 // RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 229 // RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK33 230 // RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 231 // RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK34 232 // RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 233 // RUN: %clang_cc1 -DCK5 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK35 234 // RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 235 // RUN: %clang_cc1 -DCK5 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK36 236 237 // RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 238 // RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK37 239 // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 240 // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK38 241 // RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 242 // RUN: %clang_cc1 -DCK5 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK39 243 // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 244 // RUN: %clang_cc1 -DCK5 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK40 245 246 // expected-no-diagnostics 247 #ifdef CK5 248 249 250 template <typename T> 251 int tmain(T argc) { 252 int a = 10; 253 int b = 5; 254 #pragma omp target 255 #pragma omp teams num_teams(a) thread_limit(b) 256 { 257 argc = 0; 258 } 259 return 0; 260 } 261 262 int main (int argc, char **argv) { 263 int a = 20; 264 int b = 5; 265 #pragma omp target 266 #pragma omp teams num_teams(a) thread_limit(b) 267 { 268 argc = 0; 269 } 270 return tmain(argv); 271 } 272 273 274 275 #endif // CK5 276 277 // Test host codegen. 278 // RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK41 279 // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 280 // RUN: %clang_cc1 -DCK6 -fopenmp-version=50 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK42 281 // RUN: %clang_cc1 -DCK6 -verify -fopenmp -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK43 282 // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 283 // RUN: %clang_cc1 -DCK6 -fopenmp -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK44 284 285 // RUN: %clang_cc1 -DCK6 -verify -fopenmp-version=50 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK45 286 // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 287 // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK46 288 // RUN: %clang_cc1 -DCK6 -verify -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK47 289 // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 290 // RUN: %clang_cc1 -DCK6 -fopenmp-simd -fopenmp-version=50 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK48 291 #ifdef CK6 292 293 void foo() { 294 #pragma omp teams 295 ; 296 } 297 298 #endif // CK6 299 300 #endif 301 // CHECK1-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali 302 // CHECK1-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 303 // CHECK1-NEXT: entry: 304 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 305 // CHECK1-NEXT: [[COMP:%.*]] = alloca i32, align 4 306 // CHECK1-NEXT: [[LA:%.*]] = alloca i32, align 4 307 // CHECK1-NEXT: [[LC:%.*]] = alloca float, align 4 308 // CHECK1-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 309 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 310 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 311 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 312 // CHECK1-NEXT: [[COMP_CASTED1:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 8 314 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 8 315 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 8 316 // CHECK1-NEXT: [[LA_CASTED:%.*]] = alloca i64, align 8 317 // CHECK1-NEXT: [[COMP_CASTED9:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS11:%.*]] = alloca [2 x i8*], align 8 319 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS12:%.*]] = alloca [2 x i8*], align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS13:%.*]] = alloca [2 x i8*], align 8 321 // CHECK1-NEXT: [[LA_CASTED16:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[COMP_CASTED18:%.*]] = alloca i64, align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [2 x i8*], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [2 x i8*], align 8 325 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [2 x i8*], align 8 326 // CHECK1-NEXT: [[GBLA_CASTED:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 328 // CHECK1-NEXT: [[GBLB_CASTED:%.*]] = alloca i64, align 8 329 // CHECK1-NEXT: [[LC_CASTED:%.*]] = alloca i64, align 8 330 // CHECK1-NEXT: [[COMP_CASTED28:%.*]] = alloca i64, align 8 331 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [5 x i8*], align 8 332 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [5 x i8*], align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [5 x i8*], align 8 334 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 8 335 // CHECK1-NEXT: [[GBLC_CASTED:%.*]] = alloca i64, align 8 336 // CHECK1-NEXT: [[COMP_CASTED38:%.*]] = alloca i64, align 8 337 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [2 x i8*], align 8 338 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [2 x i8*], align 8 339 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [2 x i8*], align 8 340 // CHECK1-NEXT: [[_TMP43:%.*]] = alloca i32*, align 8 341 // CHECK1-NEXT: [[_TMP45:%.*]] = alloca i32*, align 8 342 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 343 // CHECK1-NEXT: store i32 1, i32* [[COMP]], align 4 344 // CHECK1-NEXT: store i32 23, i32* [[LA]], align 4 345 // CHECK1-NEXT: store float 2.500000e+01, float* [[LC]], align 4 346 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 347 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* 348 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 349 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 350 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 351 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 352 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 353 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 354 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 355 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 356 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 357 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 358 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 359 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 360 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 361 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 362 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 363 // CHECK1: omp_offload.failed: 364 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 365 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 366 // CHECK1: omp_offload.cont: 367 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[COMP]], align 4 368 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[COMP_CASTED1]] to i32* 369 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 370 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[COMP_CASTED1]], align 8 371 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 372 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 373 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP14]], align 8 374 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 375 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 376 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 377 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0 378 // CHECK1-NEXT: store i8* null, i8** [[TMP17]], align 8 379 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 380 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 381 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 382 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 383 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 384 // CHECK1: omp_offload.failed6: 385 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37(i64 [[TMP12]]) #[[ATTR2]] 386 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]] 387 // CHECK1: omp_offload.cont7: 388 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[LA]], align 4 389 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[LA_CASTED]] to i32* 390 // CHECK1-NEXT: store i32 [[TMP22]], i32* [[CONV8]], align 4 391 // CHECK1-NEXT: [[TMP23:%.*]] = load i64, i64* [[LA_CASTED]], align 8 392 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 393 // CHECK1-NEXT: [[CONV10:%.*]] = bitcast i64* [[COMP_CASTED9]] to i32* 394 // CHECK1-NEXT: store i32 [[TMP24]], i32* [[CONV10]], align 4 395 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED9]], align 8 396 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 398 // CHECK1-NEXT: store i64 [[TMP23]], i64* [[TMP27]], align 8 399 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0 400 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 401 // CHECK1-NEXT: store i64 [[TMP23]], i64* [[TMP29]], align 8 402 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 0 403 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 404 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 1 405 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 406 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 407 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 1 408 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64* 409 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP34]], align 8 410 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 1 411 // CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8 412 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0 413 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0 414 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[LA]], align 4 415 // CHECK1-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46.region_id, i32 2, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP38]], i32 0) 416 // CHECK1-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 417 // CHECK1-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] 418 // CHECK1: omp_offload.failed14: 419 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR2]] 420 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT15]] 421 // CHECK1: omp_offload.cont15: 422 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[LA]], align 4 423 // CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[LA_CASTED16]] to i32* 424 // CHECK1-NEXT: store i32 [[TMP41]], i32* [[CONV17]], align 4 425 // CHECK1-NEXT: [[TMP42:%.*]] = load i64, i64* [[LA_CASTED16]], align 8 426 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, i32* [[COMP]], align 4 427 // CHECK1-NEXT: [[CONV19:%.*]] = bitcast i64* [[COMP_CASTED18]] to i32* 428 // CHECK1-NEXT: store i32 [[TMP43]], i32* [[CONV19]], align 4 429 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, i64* [[COMP_CASTED18]], align 8 430 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 431 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 432 // CHECK1-NEXT: store i64 [[TMP42]], i64* [[TMP46]], align 8 433 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 434 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 435 // CHECK1-NEXT: store i64 [[TMP42]], i64* [[TMP48]], align 8 436 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 437 // CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8 438 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 439 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 440 // CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8 441 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 442 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 443 // CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8 444 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 445 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8 446 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 447 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 448 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, i32* [[LA]], align 4 449 // CHECK1-NEXT: [[TMP58:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP57]]) 450 // CHECK1-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0 451 // CHECK1-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 452 // CHECK1: omp_offload.failed23: 453 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53(i64 [[TMP42]], i64 [[TMP44]]) #[[ATTR2]] 454 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT24]] 455 // CHECK1: omp_offload.cont24: 456 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, i32* @Gbla, align 4 457 // CHECK1-NEXT: [[CONV25:%.*]] = bitcast i64* [[GBLA_CASTED]] to i32* 458 // CHECK1-NEXT: store i32 [[TMP60]], i32* [[CONV25]], align 4 459 // CHECK1-NEXT: [[TMP61:%.*]] = load i64, i64* [[GBLA_CASTED]], align 8 460 // CHECK1-NEXT: [[TMP62:%.*]] = load i32, i32* [[A_ADDR]], align 4 461 // CHECK1-NEXT: [[CONV26:%.*]] = bitcast i64* [[A_CASTED]] to i32* 462 // CHECK1-NEXT: store i32 [[TMP62]], i32* [[CONV26]], align 4 463 // CHECK1-NEXT: [[TMP63:%.*]] = load i64, i64* [[A_CASTED]], align 8 464 // CHECK1-NEXT: [[TMP64:%.*]] = load i64, i64* @Gblb, align 8 465 // CHECK1-NEXT: store i64 [[TMP64]], i64* [[GBLB_CASTED]], align 8 466 // CHECK1-NEXT: [[TMP65:%.*]] = load i64, i64* [[GBLB_CASTED]], align 8 467 // CHECK1-NEXT: [[TMP66:%.*]] = load float, float* [[LC]], align 4 468 // CHECK1-NEXT: [[CONV27:%.*]] = bitcast i64* [[LC_CASTED]] to float* 469 // CHECK1-NEXT: store float [[TMP66]], float* [[CONV27]], align 4 470 // CHECK1-NEXT: [[TMP67:%.*]] = load i64, i64* [[LC_CASTED]], align 8 471 // CHECK1-NEXT: [[TMP68:%.*]] = load i32, i32* [[COMP]], align 4 472 // CHECK1-NEXT: [[CONV29:%.*]] = bitcast i64* [[COMP_CASTED28]] to i32* 473 // CHECK1-NEXT: store i32 [[TMP68]], i32* [[CONV29]], align 4 474 // CHECK1-NEXT: [[TMP69:%.*]] = load i64, i64* [[COMP_CASTED28]], align 8 475 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 476 // CHECK1-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* 477 // CHECK1-NEXT: store i64 [[TMP61]], i64* [[TMP71]], align 8 478 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 479 // CHECK1-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64* 480 // CHECK1-NEXT: store i64 [[TMP61]], i64* [[TMP73]], align 8 481 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 0 482 // CHECK1-NEXT: store i8* null, i8** [[TMP74]], align 8 483 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 484 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 485 // CHECK1-NEXT: store i64 [[TMP63]], i64* [[TMP76]], align 8 486 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 487 // CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 488 // CHECK1-NEXT: store i64 [[TMP63]], i64* [[TMP78]], align 8 489 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 1 490 // CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8 491 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 492 // CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 493 // CHECK1-NEXT: store i64 [[TMP65]], i64* [[TMP81]], align 8 494 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 495 // CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 496 // CHECK1-NEXT: store i64 [[TMP65]], i64* [[TMP83]], align 8 497 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 2 498 // CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8 499 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 500 // CHECK1-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* 501 // CHECK1-NEXT: store i64 [[TMP67]], i64* [[TMP86]], align 8 502 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 503 // CHECK1-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* 504 // CHECK1-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 505 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 3 506 // CHECK1-NEXT: store i8* null, i8** [[TMP89]], align 8 507 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 4 508 // CHECK1-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64* 509 // CHECK1-NEXT: store i64 [[TMP69]], i64* [[TMP91]], align 8 510 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 4 511 // CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64* 512 // CHECK1-NEXT: store i64 [[TMP69]], i64* [[TMP93]], align 8 513 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 4 514 // CHECK1-NEXT: store i8* null, i8** [[TMP94]], align 8 515 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 516 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 517 // CHECK1-NEXT: [[TMP97:%.*]] = load i32, i32* @Gbla, align 4 518 // CHECK1-NEXT: [[TMP98:%.*]] = load i32, i32* [[A_ADDR]], align 4 519 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP97]], [[TMP98]] 520 // CHECK1-NEXT: [[TMP99:%.*]] = load i64, i64* @Gblb, align 8 521 // CHECK1-NEXT: [[TMP100:%.*]] = load float, float* [[LC]], align 4 522 // CHECK1-NEXT: [[CONV33:%.*]] = fptosi float [[TMP100]] to i64 523 // CHECK1-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP99]], [[CONV33]] 524 // CHECK1-NEXT: [[TMP101:%.*]] = trunc i64 [[ADD34]] to i32 525 // CHECK1-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62.region_id, i32 5, i8** [[TMP95]], i8** [[TMP96]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 [[ADD]], i32 [[TMP101]]) 526 // CHECK1-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 527 // CHECK1-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED35:%.*]], label [[OMP_OFFLOAD_CONT36:%.*]] 528 // CHECK1: omp_offload.failed35: 529 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62(i64 [[TMP61]], i64 [[TMP63]], i64 [[TMP65]], i64 [[TMP67]], i64 [[TMP69]]) #[[ATTR2]] 530 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT36]] 531 // CHECK1: omp_offload.cont36: 532 // CHECK1-NEXT: [[TMP104:%.*]] = load i32*, i32** @Gblc, align 8 533 // CHECK1-NEXT: store i32* [[TMP104]], i32** [[TMP]], align 8 534 // CHECK1-NEXT: [[TMP105:%.*]] = load i32, i32* @Gbla, align 4 535 // CHECK1-NEXT: [[CONV37:%.*]] = bitcast i64* [[GBLC_CASTED]] to i32* 536 // CHECK1-NEXT: store i32 [[TMP105]], i32* [[CONV37]], align 4 537 // CHECK1-NEXT: [[TMP106:%.*]] = load i64, i64* [[GBLC_CASTED]], align 8 538 // CHECK1-NEXT: [[TMP107:%.*]] = load i32, i32* [[COMP]], align 4 539 // CHECK1-NEXT: [[CONV39:%.*]] = bitcast i64* [[COMP_CASTED38]] to i32* 540 // CHECK1-NEXT: store i32 [[TMP107]], i32* [[CONV39]], align 4 541 // CHECK1-NEXT: [[TMP108:%.*]] = load i64, i64* [[COMP_CASTED38]], align 8 542 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 543 // CHECK1-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* 544 // CHECK1-NEXT: store i64 [[TMP106]], i64* [[TMP110]], align 8 545 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 546 // CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* 547 // CHECK1-NEXT: store i64 [[TMP106]], i64* [[TMP112]], align 8 548 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 549 // CHECK1-NEXT: store i8* null, i8** [[TMP113]], align 8 550 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 1 551 // CHECK1-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i64* 552 // CHECK1-NEXT: store i64 [[TMP108]], i64* [[TMP115]], align 8 553 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 1 554 // CHECK1-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 555 // CHECK1-NEXT: store i64 [[TMP108]], i64* [[TMP117]], align 8 556 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 1 557 // CHECK1-NEXT: store i8* null, i8** [[TMP118]], align 8 558 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 559 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 560 // CHECK1-NEXT: [[TMP121:%.*]] = load i32*, i32** @Gblc, align 8 561 // CHECK1-NEXT: store i32* [[TMP121]], i32** [[_TMP43]], align 8 562 // CHECK1-NEXT: [[TMP122:%.*]] = load i32, i32* @Gbla, align 4 563 // CHECK1-NEXT: [[ADD44:%.*]] = add nsw i32 [[TMP122]], 1 564 // CHECK1-NEXT: [[TMP123:%.*]] = load i32*, i32** @Gblc, align 8 565 // CHECK1-NEXT: store i32* [[TMP123]], i32** [[_TMP45]], align 8 566 // CHECK1-NEXT: [[TMP124:%.*]] = load i32, i32* @Gbla, align 4 567 // CHECK1-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP124]], 2 568 // CHECK1-NEXT: [[TMP125:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71.region_id, i32 2, i8** [[TMP119]], i8** [[TMP120]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 [[ADD44]], i32 [[ADD46]]) 569 // CHECK1-NEXT: [[TMP126:%.*]] = icmp ne i32 [[TMP125]], 0 570 // CHECK1-NEXT: br i1 [[TMP126]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]] 571 // CHECK1: omp_offload.failed47: 572 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71(i64 [[TMP106]], i64 [[TMP108]]) #[[ATTR2]] 573 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT48]] 574 // CHECK1: omp_offload.cont48: 575 // CHECK1-NEXT: [[TMP127:%.*]] = load i32, i32* [[COMP]], align 4 576 // CHECK1-NEXT: ret i32 [[TMP127]] 577 // 578 // 579 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31 580 // CHECK1-SAME: (i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 581 // CHECK1-NEXT: entry: 582 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 583 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 584 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 585 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 586 // CHECK1-NEXT: ret void 587 // 588 // 589 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 590 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 591 // CHECK1-NEXT: entry: 592 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 593 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 594 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 595 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 596 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 597 // CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 598 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 599 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 600 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 601 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 602 // CHECK1-NEXT: ret void 603 // 604 // 605 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37 606 // CHECK1-SAME: (i64 [[COMP:%.*]]) #[[ATTR1]] { 607 // CHECK1-NEXT: entry: 608 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 609 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 610 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 611 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 612 // CHECK1-NEXT: ret void 613 // 614 // 615 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 616 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 617 // CHECK1-NEXT: entry: 618 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 619 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 620 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 621 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 622 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 623 // CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 624 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 625 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 626 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 627 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 628 // CHECK1-NEXT: ret void 629 // 630 // 631 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46 632 // CHECK1-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 633 // CHECK1-NEXT: entry: 634 // CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 635 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 636 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 637 // CHECK1-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8 638 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 639 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32* 640 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 641 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 642 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 643 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]]) 644 // CHECK1-NEXT: ret void 645 // 646 // 647 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 648 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 649 // CHECK1-NEXT: entry: 650 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 651 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 652 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 653 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 654 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 655 // CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 656 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 657 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 658 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 659 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 660 // CHECK1-NEXT: ret void 661 // 662 // 663 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53 664 // CHECK1-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 665 // CHECK1-NEXT: entry: 666 // CHECK1-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 667 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 668 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 669 // CHECK1-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8 670 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 671 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32* 672 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 673 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 674 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) 675 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]]) 676 // CHECK1-NEXT: ret void 677 // 678 // 679 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 680 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 681 // CHECK1-NEXT: entry: 682 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 683 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 684 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 685 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 686 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 687 // CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 688 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 689 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 690 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 691 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 692 // CHECK1-NEXT: ret void 693 // 694 // 695 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62 696 // CHECK1-SAME: (i64 [[GBLA:%.*]], i64 [[A:%.*]], i64 [[GBLB:%.*]], i64 [[LC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 697 // CHECK1-NEXT: entry: 698 // CHECK1-NEXT: [[GBLA_ADDR:%.*]] = alloca i64, align 8 699 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 700 // CHECK1-NEXT: [[GBLB_ADDR:%.*]] = alloca i64, align 8 701 // CHECK1-NEXT: [[LC_ADDR:%.*]] = alloca i64, align 8 702 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 703 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 704 // CHECK1-NEXT: store i64 [[GBLA]], i64* [[GBLA_ADDR]], align 8 705 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 706 // CHECK1-NEXT: store i64 [[GBLB]], i64* [[GBLB_ADDR]], align 8 707 // CHECK1-NEXT: store i64 [[LC]], i64* [[LC_ADDR]], align 8 708 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 709 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLA_ADDR]] to i32* 710 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* 711 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float* 712 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 713 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 714 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 715 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 716 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8 717 // CHECK1-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 8 718 // CHECK1-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64 719 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]] 720 // CHECK1-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32 721 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP5]]) 722 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV3]]) 723 // CHECK1-NEXT: ret void 724 // 725 // 726 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 727 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 728 // CHECK1-NEXT: entry: 729 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 730 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 731 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 732 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 733 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 734 // CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 735 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 736 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 737 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 738 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 739 // CHECK1-NEXT: ret void 740 // 741 // 742 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71 743 // CHECK1-SAME: (i64 [[GBLC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 744 // CHECK1-NEXT: entry: 745 // CHECK1-NEXT: [[GBLC_ADDR:%.*]] = alloca i64, align 8 746 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 747 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 8 748 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 749 // CHECK1-NEXT: store i64 [[GBLC]], i64* [[GBLC_ADDR]], align 8 750 // CHECK1-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 751 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLC_ADDR]] to i32* 752 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 753 // CHECK1-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 754 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* @Gbla, align 4 755 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 756 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4 757 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 2 758 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[ADD2]]) 759 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 760 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32* [[CONV1]], i32* [[TMP3]]) 761 // CHECK1-NEXT: ret void 762 // 763 // 764 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 765 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { 766 // CHECK1-NEXT: entry: 767 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 768 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 769 // CHECK1-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 770 // CHECK1-NEXT: [[GBLC_ADDR:%.*]] = alloca i32*, align 8 771 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 8 772 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 773 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 774 // CHECK1-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 775 // CHECK1-NEXT: store i32* [[GBLC]], i32** [[GBLC_ADDR]], align 8 776 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 777 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[GBLC_ADDR]], align 8 778 // CHECK1-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 779 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4 780 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 781 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] 782 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 783 // CHECK1-NEXT: ret void 784 // 785 // 786 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 787 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 788 // CHECK1-NEXT: entry: 789 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 790 // CHECK1-NEXT: ret void 791 // 792 // 793 // CHECK2-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali 794 // CHECK2-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 795 // CHECK2-NEXT: entry: 796 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 797 // CHECK2-NEXT: [[COMP:%.*]] = alloca i32, align 4 798 // CHECK2-NEXT: [[LA:%.*]] = alloca i32, align 4 799 // CHECK2-NEXT: [[LC:%.*]] = alloca float, align 4 800 // CHECK2-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 801 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 802 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 803 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 804 // CHECK2-NEXT: [[COMP_CASTED1:%.*]] = alloca i64, align 8 805 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 8 806 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 8 807 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 8 808 // CHECK2-NEXT: [[LA_CASTED:%.*]] = alloca i64, align 8 809 // CHECK2-NEXT: [[COMP_CASTED9:%.*]] = alloca i64, align 8 810 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS11:%.*]] = alloca [2 x i8*], align 8 811 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS12:%.*]] = alloca [2 x i8*], align 8 812 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS13:%.*]] = alloca [2 x i8*], align 8 813 // CHECK2-NEXT: [[LA_CASTED16:%.*]] = alloca i64, align 8 814 // CHECK2-NEXT: [[COMP_CASTED18:%.*]] = alloca i64, align 8 815 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [2 x i8*], align 8 816 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [2 x i8*], align 8 817 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [2 x i8*], align 8 818 // CHECK2-NEXT: [[GBLA_CASTED:%.*]] = alloca i64, align 8 819 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 820 // CHECK2-NEXT: [[GBLB_CASTED:%.*]] = alloca i64, align 8 821 // CHECK2-NEXT: [[LC_CASTED:%.*]] = alloca i64, align 8 822 // CHECK2-NEXT: [[COMP_CASTED28:%.*]] = alloca i64, align 8 823 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS30:%.*]] = alloca [5 x i8*], align 8 824 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS31:%.*]] = alloca [5 x i8*], align 8 825 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS32:%.*]] = alloca [5 x i8*], align 8 826 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 8 827 // CHECK2-NEXT: [[GBLC_CASTED:%.*]] = alloca i64, align 8 828 // CHECK2-NEXT: [[COMP_CASTED38:%.*]] = alloca i64, align 8 829 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [2 x i8*], align 8 830 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [2 x i8*], align 8 831 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [2 x i8*], align 8 832 // CHECK2-NEXT: [[_TMP43:%.*]] = alloca i32*, align 8 833 // CHECK2-NEXT: [[_TMP45:%.*]] = alloca i32*, align 8 834 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 835 // CHECK2-NEXT: store i32 1, i32* [[COMP]], align 4 836 // CHECK2-NEXT: store i32 23, i32* [[LA]], align 4 837 // CHECK2-NEXT: store float 2.500000e+01, float* [[LC]], align 4 838 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 839 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* 840 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 841 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 842 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 843 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 844 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 845 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 846 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 847 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 848 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 849 // CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8 850 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 851 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 852 // CHECK2-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 853 // CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 854 // CHECK2-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 855 // CHECK2: omp_offload.failed: 856 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31(i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 857 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 858 // CHECK2: omp_offload.cont: 859 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[COMP]], align 4 860 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[COMP_CASTED1]] to i32* 861 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 862 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[COMP_CASTED1]], align 8 863 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 864 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 865 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP14]], align 8 866 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 867 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 868 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 869 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i64 0, i64 0 870 // CHECK2-NEXT: store i8* null, i8** [[TMP17]], align 8 871 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 872 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 873 // CHECK2-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 874 // CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 875 // CHECK2-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 876 // CHECK2: omp_offload.failed6: 877 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37(i64 [[TMP12]]) #[[ATTR2]] 878 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT7]] 879 // CHECK2: omp_offload.cont7: 880 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[LA]], align 4 881 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[LA_CASTED]] to i32* 882 // CHECK2-NEXT: store i32 [[TMP22]], i32* [[CONV8]], align 4 883 // CHECK2-NEXT: [[TMP23:%.*]] = load i64, i64* [[LA_CASTED]], align 8 884 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 885 // CHECK2-NEXT: [[CONV10:%.*]] = bitcast i64* [[COMP_CASTED9]] to i32* 886 // CHECK2-NEXT: store i32 [[TMP24]], i32* [[CONV10]], align 4 887 // CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED9]], align 8 888 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0 889 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 890 // CHECK2-NEXT: store i64 [[TMP23]], i64* [[TMP27]], align 8 891 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0 892 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 893 // CHECK2-NEXT: store i64 [[TMP23]], i64* [[TMP29]], align 8 894 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 0 895 // CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8 896 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 1 897 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 898 // CHECK2-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 899 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 1 900 // CHECK2-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64* 901 // CHECK2-NEXT: store i64 [[TMP25]], i64* [[TMP34]], align 8 902 // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 1 903 // CHECK2-NEXT: store i8* null, i8** [[TMP35]], align 8 904 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0 905 // CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0 906 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[LA]], align 4 907 // CHECK2-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46.region_id, i32 2, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP38]], i32 0) 908 // CHECK2-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 909 // CHECK2-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] 910 // CHECK2: omp_offload.failed14: 911 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR2]] 912 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT15]] 913 // CHECK2: omp_offload.cont15: 914 // CHECK2-NEXT: [[TMP41:%.*]] = load i32, i32* [[LA]], align 4 915 // CHECK2-NEXT: [[CONV17:%.*]] = bitcast i64* [[LA_CASTED16]] to i32* 916 // CHECK2-NEXT: store i32 [[TMP41]], i32* [[CONV17]], align 4 917 // CHECK2-NEXT: [[TMP42:%.*]] = load i64, i64* [[LA_CASTED16]], align 8 918 // CHECK2-NEXT: [[TMP43:%.*]] = load i32, i32* [[COMP]], align 4 919 // CHECK2-NEXT: [[CONV19:%.*]] = bitcast i64* [[COMP_CASTED18]] to i32* 920 // CHECK2-NEXT: store i32 [[TMP43]], i32* [[CONV19]], align 4 921 // CHECK2-NEXT: [[TMP44:%.*]] = load i64, i64* [[COMP_CASTED18]], align 8 922 // CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 923 // CHECK2-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 924 // CHECK2-NEXT: store i64 [[TMP42]], i64* [[TMP46]], align 8 925 // CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 926 // CHECK2-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 927 // CHECK2-NEXT: store i64 [[TMP42]], i64* [[TMP48]], align 8 928 // CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 929 // CHECK2-NEXT: store i8* null, i8** [[TMP49]], align 8 930 // CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 931 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 932 // CHECK2-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8 933 // CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 934 // CHECK2-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 935 // CHECK2-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8 936 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 937 // CHECK2-NEXT: store i8* null, i8** [[TMP54]], align 8 938 // CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 939 // CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 940 // CHECK2-NEXT: [[TMP57:%.*]] = load i32, i32* [[LA]], align 4 941 // CHECK2-NEXT: [[TMP58:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP57]]) 942 // CHECK2-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0 943 // CHECK2-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 944 // CHECK2: omp_offload.failed23: 945 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53(i64 [[TMP42]], i64 [[TMP44]]) #[[ATTR2]] 946 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT24]] 947 // CHECK2: omp_offload.cont24: 948 // CHECK2-NEXT: [[TMP60:%.*]] = load i32, i32* @Gbla, align 4 949 // CHECK2-NEXT: [[CONV25:%.*]] = bitcast i64* [[GBLA_CASTED]] to i32* 950 // CHECK2-NEXT: store i32 [[TMP60]], i32* [[CONV25]], align 4 951 // CHECK2-NEXT: [[TMP61:%.*]] = load i64, i64* [[GBLA_CASTED]], align 8 952 // CHECK2-NEXT: [[TMP62:%.*]] = load i32, i32* [[A_ADDR]], align 4 953 // CHECK2-NEXT: [[CONV26:%.*]] = bitcast i64* [[A_CASTED]] to i32* 954 // CHECK2-NEXT: store i32 [[TMP62]], i32* [[CONV26]], align 4 955 // CHECK2-NEXT: [[TMP63:%.*]] = load i64, i64* [[A_CASTED]], align 8 956 // CHECK2-NEXT: [[TMP64:%.*]] = load i64, i64* @Gblb, align 8 957 // CHECK2-NEXT: store i64 [[TMP64]], i64* [[GBLB_CASTED]], align 8 958 // CHECK2-NEXT: [[TMP65:%.*]] = load i64, i64* [[GBLB_CASTED]], align 8 959 // CHECK2-NEXT: [[TMP66:%.*]] = load float, float* [[LC]], align 4 960 // CHECK2-NEXT: [[CONV27:%.*]] = bitcast i64* [[LC_CASTED]] to float* 961 // CHECK2-NEXT: store float [[TMP66]], float* [[CONV27]], align 4 962 // CHECK2-NEXT: [[TMP67:%.*]] = load i64, i64* [[LC_CASTED]], align 8 963 // CHECK2-NEXT: [[TMP68:%.*]] = load i32, i32* [[COMP]], align 4 964 // CHECK2-NEXT: [[CONV29:%.*]] = bitcast i64* [[COMP_CASTED28]] to i32* 965 // CHECK2-NEXT: store i32 [[TMP68]], i32* [[CONV29]], align 4 966 // CHECK2-NEXT: [[TMP69:%.*]] = load i64, i64* [[COMP_CASTED28]], align 8 967 // CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 968 // CHECK2-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* 969 // CHECK2-NEXT: store i64 [[TMP61]], i64* [[TMP71]], align 8 970 // CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 971 // CHECK2-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i64* 972 // CHECK2-NEXT: store i64 [[TMP61]], i64* [[TMP73]], align 8 973 // CHECK2-NEXT: [[TMP74:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 0 974 // CHECK2-NEXT: store i8* null, i8** [[TMP74]], align 8 975 // CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 1 976 // CHECK2-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 977 // CHECK2-NEXT: store i64 [[TMP63]], i64* [[TMP76]], align 8 978 // CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 1 979 // CHECK2-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 980 // CHECK2-NEXT: store i64 [[TMP63]], i64* [[TMP78]], align 8 981 // CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 1 982 // CHECK2-NEXT: store i8* null, i8** [[TMP79]], align 8 983 // CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 2 984 // CHECK2-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 985 // CHECK2-NEXT: store i64 [[TMP65]], i64* [[TMP81]], align 8 986 // CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 2 987 // CHECK2-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 988 // CHECK2-NEXT: store i64 [[TMP65]], i64* [[TMP83]], align 8 989 // CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 2 990 // CHECK2-NEXT: store i8* null, i8** [[TMP84]], align 8 991 // CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 3 992 // CHECK2-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* 993 // CHECK2-NEXT: store i64 [[TMP67]], i64* [[TMP86]], align 8 994 // CHECK2-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 3 995 // CHECK2-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* 996 // CHECK2-NEXT: store i64 [[TMP67]], i64* [[TMP88]], align 8 997 // CHECK2-NEXT: [[TMP89:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 3 998 // CHECK2-NEXT: store i8* null, i8** [[TMP89]], align 8 999 // CHECK2-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 4 1000 // CHECK2-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64* 1001 // CHECK2-NEXT: store i64 [[TMP69]], i64* [[TMP91]], align 8 1002 // CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 4 1003 // CHECK2-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64* 1004 // CHECK2-NEXT: store i64 [[TMP69]], i64* [[TMP93]], align 8 1005 // CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS32]], i64 0, i64 4 1006 // CHECK2-NEXT: store i8* null, i8** [[TMP94]], align 8 1007 // CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS30]], i32 0, i32 0 1008 // CHECK2-NEXT: [[TMP96:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS31]], i32 0, i32 0 1009 // CHECK2-NEXT: [[TMP97:%.*]] = load i32, i32* @Gbla, align 4 1010 // CHECK2-NEXT: [[TMP98:%.*]] = load i32, i32* [[A_ADDR]], align 4 1011 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP97]], [[TMP98]] 1012 // CHECK2-NEXT: [[TMP99:%.*]] = load i64, i64* @Gblb, align 8 1013 // CHECK2-NEXT: [[TMP100:%.*]] = load float, float* [[LC]], align 4 1014 // CHECK2-NEXT: [[CONV33:%.*]] = fptosi float [[TMP100]] to i64 1015 // CHECK2-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP99]], [[CONV33]] 1016 // CHECK2-NEXT: [[TMP101:%.*]] = trunc i64 [[ADD34]] to i32 1017 // CHECK2-NEXT: [[TMP102:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62.region_id, i32 5, i8** [[TMP95]], i8** [[TMP96]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 [[ADD]], i32 [[TMP101]]) 1018 // CHECK2-NEXT: [[TMP103:%.*]] = icmp ne i32 [[TMP102]], 0 1019 // CHECK2-NEXT: br i1 [[TMP103]], label [[OMP_OFFLOAD_FAILED35:%.*]], label [[OMP_OFFLOAD_CONT36:%.*]] 1020 // CHECK2: omp_offload.failed35: 1021 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62(i64 [[TMP61]], i64 [[TMP63]], i64 [[TMP65]], i64 [[TMP67]], i64 [[TMP69]]) #[[ATTR2]] 1022 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT36]] 1023 // CHECK2: omp_offload.cont36: 1024 // CHECK2-NEXT: [[TMP104:%.*]] = load i32*, i32** @Gblc, align 8 1025 // CHECK2-NEXT: store i32* [[TMP104]], i32** [[TMP]], align 8 1026 // CHECK2-NEXT: [[TMP105:%.*]] = load i32, i32* @Gbla, align 4 1027 // CHECK2-NEXT: [[CONV37:%.*]] = bitcast i64* [[GBLC_CASTED]] to i32* 1028 // CHECK2-NEXT: store i32 [[TMP105]], i32* [[CONV37]], align 4 1029 // CHECK2-NEXT: [[TMP106:%.*]] = load i64, i64* [[GBLC_CASTED]], align 8 1030 // CHECK2-NEXT: [[TMP107:%.*]] = load i32, i32* [[COMP]], align 4 1031 // CHECK2-NEXT: [[CONV39:%.*]] = bitcast i64* [[COMP_CASTED38]] to i32* 1032 // CHECK2-NEXT: store i32 [[TMP107]], i32* [[CONV39]], align 4 1033 // CHECK2-NEXT: [[TMP108:%.*]] = load i64, i64* [[COMP_CASTED38]], align 8 1034 // CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 1035 // CHECK2-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i64* 1036 // CHECK2-NEXT: store i64 [[TMP106]], i64* [[TMP110]], align 8 1037 // CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 1038 // CHECK2-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i64* 1039 // CHECK2-NEXT: store i64 [[TMP106]], i64* [[TMP112]], align 8 1040 // CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 1041 // CHECK2-NEXT: store i8* null, i8** [[TMP113]], align 8 1042 // CHECK2-NEXT: [[TMP114:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 1 1043 // CHECK2-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i64* 1044 // CHECK2-NEXT: store i64 [[TMP108]], i64* [[TMP115]], align 8 1045 // CHECK2-NEXT: [[TMP116:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 1 1046 // CHECK2-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 1047 // CHECK2-NEXT: store i64 [[TMP108]], i64* [[TMP117]], align 8 1048 // CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 1 1049 // CHECK2-NEXT: store i8* null, i8** [[TMP118]], align 8 1050 // CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 1051 // CHECK2-NEXT: [[TMP120:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 1052 // CHECK2-NEXT: [[TMP121:%.*]] = load i32*, i32** @Gblc, align 8 1053 // CHECK2-NEXT: store i32* [[TMP121]], i32** [[_TMP43]], align 8 1054 // CHECK2-NEXT: [[TMP122:%.*]] = load i32, i32* @Gbla, align 4 1055 // CHECK2-NEXT: [[ADD44:%.*]] = add nsw i32 [[TMP122]], 1 1056 // CHECK2-NEXT: [[TMP123:%.*]] = load i32*, i32** @Gblc, align 8 1057 // CHECK2-NEXT: store i32* [[TMP123]], i32** [[_TMP45]], align 8 1058 // CHECK2-NEXT: [[TMP124:%.*]] = load i32, i32* @Gbla, align 4 1059 // CHECK2-NEXT: [[ADD46:%.*]] = add nsw i32 [[TMP124]], 2 1060 // CHECK2-NEXT: [[TMP125:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71.region_id, i32 2, i8** [[TMP119]], i8** [[TMP120]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 [[ADD44]], i32 [[ADD46]]) 1061 // CHECK2-NEXT: [[TMP126:%.*]] = icmp ne i32 [[TMP125]], 0 1062 // CHECK2-NEXT: br i1 [[TMP126]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]] 1063 // CHECK2: omp_offload.failed47: 1064 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71(i64 [[TMP106]], i64 [[TMP108]]) #[[ATTR2]] 1065 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT48]] 1066 // CHECK2: omp_offload.cont48: 1067 // CHECK2-NEXT: [[TMP127:%.*]] = load i32, i32* [[COMP]], align 4 1068 // CHECK2-NEXT: ret i32 [[TMP127]] 1069 // 1070 // 1071 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31 1072 // CHECK2-SAME: (i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 1073 // CHECK2-NEXT: entry: 1074 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 1075 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 1076 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 1077 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 1078 // CHECK2-NEXT: ret void 1079 // 1080 // 1081 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1082 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1083 // CHECK2-NEXT: entry: 1084 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1085 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1086 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 1087 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1088 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1089 // CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 1090 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 1091 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1092 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1093 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1094 // CHECK2-NEXT: ret void 1095 // 1096 // 1097 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37 1098 // CHECK2-SAME: (i64 [[COMP:%.*]]) #[[ATTR1]] { 1099 // CHECK2-NEXT: entry: 1100 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 1101 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 1102 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 1103 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 1104 // CHECK2-NEXT: ret void 1105 // 1106 // 1107 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 1108 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1109 // CHECK2-NEXT: entry: 1110 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1111 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1112 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 1113 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1114 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1115 // CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 1116 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 1117 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1118 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1119 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1120 // CHECK2-NEXT: ret void 1121 // 1122 // 1123 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46 1124 // CHECK2-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 1125 // CHECK2-NEXT: entry: 1126 // CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 1127 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 1128 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1129 // CHECK2-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8 1130 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 1131 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32* 1132 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 1133 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1134 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 1135 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[CONV1]]) 1136 // CHECK2-NEXT: ret void 1137 // 1138 // 1139 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1140 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1141 // CHECK2-NEXT: entry: 1142 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1143 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1144 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 1145 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1146 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1147 // CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 1148 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 1149 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1150 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1151 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1152 // CHECK2-NEXT: ret void 1153 // 1154 // 1155 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53 1156 // CHECK2-SAME: (i64 [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 1157 // CHECK2-NEXT: entry: 1158 // CHECK2-NEXT: [[LA_ADDR:%.*]] = alloca i64, align 8 1159 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 1160 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1161 // CHECK2-NEXT: store i64 [[LA]], i64* [[LA_ADDR]], align 8 1162 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 1163 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[LA_ADDR]] to i32* 1164 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 1165 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1166 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) 1167 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV1]]) 1168 // CHECK2-NEXT: ret void 1169 // 1170 // 1171 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 1172 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1173 // CHECK2-NEXT: entry: 1174 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1175 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1176 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 1177 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1178 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1179 // CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 1180 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 1181 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1182 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1183 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1184 // CHECK2-NEXT: ret void 1185 // 1186 // 1187 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62 1188 // CHECK2-SAME: (i64 [[GBLA:%.*]], i64 [[A:%.*]], i64 [[GBLB:%.*]], i64 [[LC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 1189 // CHECK2-NEXT: entry: 1190 // CHECK2-NEXT: [[GBLA_ADDR:%.*]] = alloca i64, align 8 1191 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1192 // CHECK2-NEXT: [[GBLB_ADDR:%.*]] = alloca i64, align 8 1193 // CHECK2-NEXT: [[LC_ADDR:%.*]] = alloca i64, align 8 1194 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 1195 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1196 // CHECK2-NEXT: store i64 [[GBLA]], i64* [[GBLA_ADDR]], align 8 1197 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1198 // CHECK2-NEXT: store i64 [[GBLB]], i64* [[GBLB_ADDR]], align 8 1199 // CHECK2-NEXT: store i64 [[LC]], i64* [[LC_ADDR]], align 8 1200 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 1201 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLA_ADDR]] to i32* 1202 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1203 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[LC_ADDR]] to float* 1204 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 1205 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1206 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 1207 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1208 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[GBLB_ADDR]], align 8 1209 // CHECK2-NEXT: [[TMP4:%.*]] = load float, float* [[CONV2]], align 8 1210 // CHECK2-NEXT: [[CONV4:%.*]] = fptosi float [[TMP4]] to i64 1211 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP3]], [[CONV4]] 1212 // CHECK2-NEXT: [[TMP5:%.*]] = trunc i64 [[ADD5]] to i32 1213 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP5]]) 1214 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[CONV3]]) 1215 // CHECK2-NEXT: ret void 1216 // 1217 // 1218 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 1219 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1220 // CHECK2-NEXT: entry: 1221 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1222 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1223 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 1224 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1225 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1226 // CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 1227 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 1228 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1229 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1230 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1231 // CHECK2-NEXT: ret void 1232 // 1233 // 1234 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71 1235 // CHECK2-SAME: (i64 [[GBLC:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 1236 // CHECK2-NEXT: entry: 1237 // CHECK2-NEXT: [[GBLC_ADDR:%.*]] = alloca i64, align 8 1238 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 1239 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 8 1240 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1241 // CHECK2-NEXT: store i64 [[GBLC]], i64* [[GBLC_ADDR]], align 8 1242 // CHECK2-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 1243 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[GBLC_ADDR]] to i32* 1244 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 1245 // CHECK2-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 1246 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* @Gbla, align 4 1247 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1248 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4 1249 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 2 1250 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[ADD2]]) 1251 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 8 1252 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32* [[CONV1]], i32* [[TMP3]]) 1253 // CHECK2-NEXT: ret void 1254 // 1255 // 1256 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 1257 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { 1258 // CHECK2-NEXT: entry: 1259 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1260 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1261 // CHECK2-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 1262 // CHECK2-NEXT: [[GBLC_ADDR:%.*]] = alloca i32*, align 8 1263 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 8 1264 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1265 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1266 // CHECK2-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 1267 // CHECK2-NEXT: store i32* [[GBLC]], i32** [[GBLC_ADDR]], align 8 1268 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 1269 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[GBLC_ADDR]], align 8 1270 // CHECK2-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 8 1271 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4 1272 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 1273 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] 1274 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 1275 // CHECK2-NEXT: ret void 1276 // 1277 // 1278 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1279 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 1280 // CHECK2-NEXT: entry: 1281 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1282 // CHECK2-NEXT: ret void 1283 // 1284 // 1285 // CHECK3-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali 1286 // CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { 1287 // CHECK3-NEXT: entry: 1288 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1289 // CHECK3-NEXT: [[COMP:%.*]] = alloca i32, align 4 1290 // CHECK3-NEXT: [[LA:%.*]] = alloca i32, align 4 1291 // CHECK3-NEXT: [[LC:%.*]] = alloca float, align 4 1292 // CHECK3-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 1293 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1294 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1295 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1296 // CHECK3-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4 1297 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 1298 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 1299 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 1300 // CHECK3-NEXT: [[LA_CASTED:%.*]] = alloca i32, align 4 1301 // CHECK3-NEXT: [[COMP_CASTED7:%.*]] = alloca i32, align 4 1302 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4 1303 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4 1304 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4 1305 // CHECK3-NEXT: [[LA_CASTED13:%.*]] = alloca i32, align 4 1306 // CHECK3-NEXT: [[COMP_CASTED14:%.*]] = alloca i32, align 4 1307 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS15:%.*]] = alloca [2 x i8*], align 4 1308 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS16:%.*]] = alloca [2 x i8*], align 4 1309 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS17:%.*]] = alloca [2 x i8*], align 4 1310 // CHECK3-NEXT: [[GBLA_CASTED:%.*]] = alloca i32, align 4 1311 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1312 // CHECK3-NEXT: [[LC_CASTED:%.*]] = alloca i32, align 4 1313 // CHECK3-NEXT: [[COMP_CASTED20:%.*]] = alloca i32, align 4 1314 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [5 x i8*], align 4 1315 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [5 x i8*], align 4 1316 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [5 x i8*], align 4 1317 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4 1318 // CHECK3-NEXT: [[GBLC_CASTED:%.*]] = alloca i32, align 4 1319 // CHECK3-NEXT: [[COMP_CASTED28:%.*]] = alloca i32, align 4 1320 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [2 x i8*], align 4 1321 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [2 x i8*], align 4 1322 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [2 x i8*], align 4 1323 // CHECK3-NEXT: [[_TMP32:%.*]] = alloca i32*, align 4 1324 // CHECK3-NEXT: [[_TMP34:%.*]] = alloca i32*, align 4 1325 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1326 // CHECK3-NEXT: store i32 1, i32* [[COMP]], align 4 1327 // CHECK3-NEXT: store i32 23, i32* [[LA]], align 4 1328 // CHECK3-NEXT: store float 2.500000e+01, float* [[LC]], align 4 1329 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 1330 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 1331 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 1332 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1333 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 1334 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 1335 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1336 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1337 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1338 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1339 // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 1340 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1341 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1342 // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1343 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 1344 // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1345 // CHECK3: omp_offload.failed: 1346 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 1347 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1348 // CHECK3: omp_offload.cont: 1349 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[COMP]], align 4 1350 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[COMP_CASTED1]], align 4 1351 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4 1352 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1353 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1354 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 1355 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1356 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 1357 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 1358 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 1359 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 1360 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1361 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1362 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1363 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1364 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] 1365 // CHECK3: omp_offload.failed5: 1366 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37(i32 [[TMP12]]) #[[ATTR2]] 1367 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT6]] 1368 // CHECK3: omp_offload.cont6: 1369 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[LA]], align 4 1370 // CHECK3-NEXT: store i32 [[TMP22]], i32* [[LA_CASTED]], align 4 1371 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[LA_CASTED]], align 4 1372 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 1373 // CHECK3-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED7]], align 4 1374 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED7]], align 4 1375 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 1376 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 1377 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP27]], align 4 1378 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 1379 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 1380 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP29]], align 4 1381 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0 1382 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 1383 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 1384 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* 1385 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP32]], align 4 1386 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 1387 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32* 1388 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP34]], align 4 1389 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1 1390 // CHECK3-NEXT: store i8* null, i8** [[TMP35]], align 4 1391 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 1392 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 1393 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, i32* [[LA]], align 4 1394 // CHECK3-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46.region_id, i32 2, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP38]], i32 0) 1395 // CHECK3-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 1396 // CHECK3-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] 1397 // CHECK3: omp_offload.failed11: 1398 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR2]] 1399 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT12]] 1400 // CHECK3: omp_offload.cont12: 1401 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[LA]], align 4 1402 // CHECK3-NEXT: store i32 [[TMP41]], i32* [[LA_CASTED13]], align 4 1403 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[LA_CASTED13]], align 4 1404 // CHECK3-NEXT: [[TMP43:%.*]] = load i32, i32* [[COMP]], align 4 1405 // CHECK3-NEXT: store i32 [[TMP43]], i32* [[COMP_CASTED14]], align 4 1406 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[COMP_CASTED14]], align 4 1407 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0 1408 // CHECK3-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* 1409 // CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP46]], align 4 1410 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0 1411 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32* 1412 // CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP48]], align 4 1413 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 0 1414 // CHECK3-NEXT: store i8* null, i8** [[TMP49]], align 4 1415 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 1 1416 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 1417 // CHECK3-NEXT: store i32 [[TMP44]], i32* [[TMP51]], align 4 1418 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 1 1419 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 1420 // CHECK3-NEXT: store i32 [[TMP44]], i32* [[TMP53]], align 4 1421 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 1 1422 // CHECK3-NEXT: store i8* null, i8** [[TMP54]], align 4 1423 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0 1424 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0 1425 // CHECK3-NEXT: [[TMP57:%.*]] = load i32, i32* [[LA]], align 4 1426 // CHECK3-NEXT: [[TMP58:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP57]]) 1427 // CHECK3-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0 1428 // CHECK3-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 1429 // CHECK3: omp_offload.failed18: 1430 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53(i32 [[TMP42]], i32 [[TMP44]]) #[[ATTR2]] 1431 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]] 1432 // CHECK3: omp_offload.cont19: 1433 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* @Gbla, align 4 1434 // CHECK3-NEXT: store i32 [[TMP60]], i32* [[GBLA_CASTED]], align 4 1435 // CHECK3-NEXT: [[TMP61:%.*]] = load i32, i32* [[GBLA_CASTED]], align 4 1436 // CHECK3-NEXT: [[TMP62:%.*]] = load i32, i32* [[A_ADDR]], align 4 1437 // CHECK3-NEXT: store i32 [[TMP62]], i32* [[A_CASTED]], align 4 1438 // CHECK3-NEXT: [[TMP63:%.*]] = load i32, i32* [[A_CASTED]], align 4 1439 // CHECK3-NEXT: [[TMP64:%.*]] = load float, float* [[LC]], align 4 1440 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[LC_CASTED]] to float* 1441 // CHECK3-NEXT: store float [[TMP64]], float* [[CONV]], align 4 1442 // CHECK3-NEXT: [[TMP65:%.*]] = load i32, i32* [[LC_CASTED]], align 4 1443 // CHECK3-NEXT: [[TMP66:%.*]] = load i32, i32* [[COMP]], align 4 1444 // CHECK3-NEXT: store i32 [[TMP66]], i32* [[COMP_CASTED20]], align 4 1445 // CHECK3-NEXT: [[TMP67:%.*]] = load i32, i32* [[COMP_CASTED20]], align 4 1446 // CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 1447 // CHECK3-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32* 1448 // CHECK3-NEXT: store i32 [[TMP61]], i32* [[TMP69]], align 4 1449 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 1450 // CHECK3-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* 1451 // CHECK3-NEXT: store i32 [[TMP61]], i32* [[TMP71]], align 4 1452 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0 1453 // CHECK3-NEXT: store i8* null, i8** [[TMP72]], align 4 1454 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 1455 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 1456 // CHECK3-NEXT: store i32 [[TMP63]], i32* [[TMP74]], align 4 1457 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 1458 // CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 1459 // CHECK3-NEXT: store i32 [[TMP63]], i32* [[TMP76]], align 4 1460 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1 1461 // CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4 1462 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 1463 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64** 1464 // CHECK3-NEXT: store i64* @Gblb, i64** [[TMP79]], align 4 1465 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 1466 // CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64** 1467 // CHECK3-NEXT: store i64* @Gblb, i64** [[TMP81]], align 4 1468 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2 1469 // CHECK3-NEXT: store i8* null, i8** [[TMP82]], align 4 1470 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 1471 // CHECK3-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32* 1472 // CHECK3-NEXT: store i32 [[TMP65]], i32* [[TMP84]], align 4 1473 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 1474 // CHECK3-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* 1475 // CHECK3-NEXT: store i32 [[TMP65]], i32* [[TMP86]], align 4 1476 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3 1477 // CHECK3-NEXT: store i8* null, i8** [[TMP87]], align 4 1478 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4 1479 // CHECK3-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32* 1480 // CHECK3-NEXT: store i32 [[TMP67]], i32* [[TMP89]], align 4 1481 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4 1482 // CHECK3-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32* 1483 // CHECK3-NEXT: store i32 [[TMP67]], i32* [[TMP91]], align 4 1484 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4 1485 // CHECK3-NEXT: store i8* null, i8** [[TMP92]], align 4 1486 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 1487 // CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 1488 // CHECK3-NEXT: [[TMP95:%.*]] = load i32, i32* @Gbla, align 4 1489 // CHECK3-NEXT: [[TMP96:%.*]] = load i32, i32* [[A_ADDR]], align 4 1490 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP95]], [[TMP96]] 1491 // CHECK3-NEXT: [[TMP97:%.*]] = load i64, i64* @Gblb, align 8 1492 // CHECK3-NEXT: [[TMP98:%.*]] = load float, float* [[LC]], align 4 1493 // CHECK3-NEXT: [[CONV24:%.*]] = fptosi float [[TMP98]] to i64 1494 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP97]], [[CONV24]] 1495 // CHECK3-NEXT: [[TMP99:%.*]] = trunc i64 [[ADD25]] to i32 1496 // CHECK3-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62.region_id, i32 5, i8** [[TMP93]], i8** [[TMP94]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 [[ADD]], i32 [[TMP99]]) 1497 // CHECK3-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 1498 // CHECK3-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED26:%.*]], label [[OMP_OFFLOAD_CONT27:%.*]] 1499 // CHECK3: omp_offload.failed26: 1500 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62(i32 [[TMP61]], i32 [[TMP63]], i64* @Gblb, i32 [[TMP65]], i32 [[TMP67]]) #[[ATTR2]] 1501 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT27]] 1502 // CHECK3: omp_offload.cont27: 1503 // CHECK3-NEXT: [[TMP102:%.*]] = load i32*, i32** @Gblc, align 4 1504 // CHECK3-NEXT: store i32* [[TMP102]], i32** [[TMP]], align 4 1505 // CHECK3-NEXT: [[TMP103:%.*]] = load i32, i32* @Gbla, align 4 1506 // CHECK3-NEXT: store i32 [[TMP103]], i32* [[GBLC_CASTED]], align 4 1507 // CHECK3-NEXT: [[TMP104:%.*]] = load i32, i32* [[GBLC_CASTED]], align 4 1508 // CHECK3-NEXT: [[TMP105:%.*]] = load i32, i32* [[COMP]], align 4 1509 // CHECK3-NEXT: store i32 [[TMP105]], i32* [[COMP_CASTED28]], align 4 1510 // CHECK3-NEXT: [[TMP106:%.*]] = load i32, i32* [[COMP_CASTED28]], align 4 1511 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 1512 // CHECK3-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* 1513 // CHECK3-NEXT: store i32 [[TMP104]], i32* [[TMP108]], align 4 1514 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 1515 // CHECK3-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* 1516 // CHECK3-NEXT: store i32 [[TMP104]], i32* [[TMP110]], align 4 1517 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i32 0, i32 0 1518 // CHECK3-NEXT: store i8* null, i8** [[TMP111]], align 4 1519 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1 1520 // CHECK3-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32* 1521 // CHECK3-NEXT: store i32 [[TMP106]], i32* [[TMP113]], align 4 1522 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1 1523 // CHECK3-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 1524 // CHECK3-NEXT: store i32 [[TMP106]], i32* [[TMP115]], align 4 1525 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i32 0, i32 1 1526 // CHECK3-NEXT: store i8* null, i8** [[TMP116]], align 4 1527 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 1528 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 1529 // CHECK3-NEXT: [[TMP119:%.*]] = load i32*, i32** @Gblc, align 4 1530 // CHECK3-NEXT: store i32* [[TMP119]], i32** [[_TMP32]], align 4 1531 // CHECK3-NEXT: [[TMP120:%.*]] = load i32, i32* @Gbla, align 4 1532 // CHECK3-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP120]], 1 1533 // CHECK3-NEXT: [[TMP121:%.*]] = load i32*, i32** @Gblc, align 4 1534 // CHECK3-NEXT: store i32* [[TMP121]], i32** [[_TMP34]], align 4 1535 // CHECK3-NEXT: [[TMP122:%.*]] = load i32, i32* @Gbla, align 4 1536 // CHECK3-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP122]], 2 1537 // CHECK3-NEXT: [[TMP123:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71.region_id, i32 2, i8** [[TMP117]], i8** [[TMP118]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 [[ADD33]], i32 [[ADD35]]) 1538 // CHECK3-NEXT: [[TMP124:%.*]] = icmp ne i32 [[TMP123]], 0 1539 // CHECK3-NEXT: br i1 [[TMP124]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 1540 // CHECK3: omp_offload.failed36: 1541 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71(i32 [[TMP104]], i32 [[TMP106]]) #[[ATTR2]] 1542 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT37]] 1543 // CHECK3: omp_offload.cont37: 1544 // CHECK3-NEXT: [[TMP125:%.*]] = load i32, i32* [[COMP]], align 4 1545 // CHECK3-NEXT: ret i32 [[TMP125]] 1546 // 1547 // 1548 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31 1549 // CHECK3-SAME: (i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 1550 // CHECK3-NEXT: entry: 1551 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 1552 // CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 1553 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 1554 // CHECK3-NEXT: ret void 1555 // 1556 // 1557 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1558 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1559 // CHECK3-NEXT: entry: 1560 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1561 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1562 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 1563 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1564 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1565 // CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 1566 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 1567 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1568 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1569 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1570 // CHECK3-NEXT: ret void 1571 // 1572 // 1573 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37 1574 // CHECK3-SAME: (i32 [[COMP:%.*]]) #[[ATTR1]] { 1575 // CHECK3-NEXT: entry: 1576 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 1577 // CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 1578 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 1579 // CHECK3-NEXT: ret void 1580 // 1581 // 1582 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 1583 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1584 // CHECK3-NEXT: entry: 1585 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1586 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1587 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 1588 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1589 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1590 // CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 1591 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 1592 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1593 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1594 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1595 // CHECK3-NEXT: ret void 1596 // 1597 // 1598 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46 1599 // CHECK3-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 1600 // CHECK3-NEXT: entry: 1601 // CHECK3-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4 1602 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 1603 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1604 // CHECK3-NEXT: store i32 [[LA]], i32* [[LA_ADDR]], align 4 1605 // CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 1606 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[LA_ADDR]], align 4 1607 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 1608 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 1609 // CHECK3-NEXT: ret void 1610 // 1611 // 1612 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1613 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1614 // CHECK3-NEXT: entry: 1615 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1616 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1617 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 1618 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1619 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1620 // CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 1621 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 1622 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1623 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1624 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1625 // CHECK3-NEXT: ret void 1626 // 1627 // 1628 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53 1629 // CHECK3-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 1630 // CHECK3-NEXT: entry: 1631 // CHECK3-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4 1632 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 1633 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1634 // CHECK3-NEXT: store i32 [[LA]], i32* [[LA_ADDR]], align 4 1635 // CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 1636 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[LA_ADDR]], align 4 1637 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) 1638 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 1639 // CHECK3-NEXT: ret void 1640 // 1641 // 1642 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 1643 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1644 // CHECK3-NEXT: entry: 1645 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1646 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1647 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 1648 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1649 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1650 // CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 1651 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 1652 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1653 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1654 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1655 // CHECK3-NEXT: ret void 1656 // 1657 // 1658 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62 1659 // CHECK3-SAME: (i32 [[GBLA:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[GBLB:%.*]], i32 [[LC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 1660 // CHECK3-NEXT: entry: 1661 // CHECK3-NEXT: [[GBLA_ADDR:%.*]] = alloca i32, align 4 1662 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1663 // CHECK3-NEXT: [[GBLB_ADDR:%.*]] = alloca i64*, align 4 1664 // CHECK3-NEXT: [[LC_ADDR:%.*]] = alloca i32, align 4 1665 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 1666 // CHECK3-NEXT: [[GBLB1:%.*]] = alloca i64, align 8 1667 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1668 // CHECK3-NEXT: store i32 [[GBLA]], i32* [[GBLA_ADDR]], align 4 1669 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1670 // CHECK3-NEXT: store i64* [[GBLB]], i64** [[GBLB_ADDR]], align 4 1671 // CHECK3-NEXT: store i32 [[LC]], i32* [[LC_ADDR]], align 4 1672 // CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 1673 // CHECK3-NEXT: [[TMP1:%.*]] = load i64*, i64** [[GBLB_ADDR]], align 4 1674 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[LC_ADDR]] to float* 1675 // CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[TMP1]], align 8 1676 // CHECK3-NEXT: store i64 [[TMP2]], i64* [[GBLB1]], align 8 1677 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[GBLA_ADDR]], align 4 1678 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 1679 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP4]] 1680 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[GBLB1]], align 8 1681 // CHECK3-NEXT: [[TMP6:%.*]] = load float, float* [[CONV]], align 4 1682 // CHECK3-NEXT: [[CONV2:%.*]] = fptosi float [[TMP6]] to i64 1683 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i64 [[TMP5]], [[CONV2]] 1684 // CHECK3-NEXT: [[TMP7:%.*]] = trunc i64 [[ADD3]] to i32 1685 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP7]]) 1686 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 1687 // CHECK3-NEXT: ret void 1688 // 1689 // 1690 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 1691 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 1692 // CHECK3-NEXT: entry: 1693 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1694 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1695 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 1696 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1697 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1698 // CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 1699 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 1700 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1701 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 1702 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 1703 // CHECK3-NEXT: ret void 1704 // 1705 // 1706 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71 1707 // CHECK3-SAME: (i32 [[GBLC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 1708 // CHECK3-NEXT: entry: 1709 // CHECK3-NEXT: [[GBLC_ADDR:%.*]] = alloca i32, align 4 1710 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 1711 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4 1712 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1713 // CHECK3-NEXT: store i32 [[GBLC]], i32* [[GBLC_ADDR]], align 4 1714 // CHECK3-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 1715 // CHECK3-NEXT: store i32* [[GBLC_ADDR]], i32** [[TMP]], align 4 1716 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* @Gbla, align 4 1717 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1718 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4 1719 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], 2 1720 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[ADD1]]) 1721 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4 1722 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]], i32* [[TMP3]]) 1723 // CHECK3-NEXT: ret void 1724 // 1725 // 1726 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 1727 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { 1728 // CHECK3-NEXT: entry: 1729 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1730 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1731 // CHECK3-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 1732 // CHECK3-NEXT: [[GBLC_ADDR:%.*]] = alloca i32*, align 4 1733 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4 1734 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1735 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1736 // CHECK3-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 1737 // CHECK3-NEXT: store i32* [[GBLC]], i32** [[GBLC_ADDR]], align 4 1738 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 1739 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[GBLC_ADDR]], align 4 1740 // CHECK3-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 4 1741 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4 1742 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 1743 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] 1744 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 1745 // CHECK3-NEXT: ret void 1746 // 1747 // 1748 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1749 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1750 // CHECK3-NEXT: entry: 1751 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1752 // CHECK3-NEXT: ret void 1753 // 1754 // 1755 // CHECK4-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali 1756 // CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { 1757 // CHECK4-NEXT: entry: 1758 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1759 // CHECK4-NEXT: [[COMP:%.*]] = alloca i32, align 4 1760 // CHECK4-NEXT: [[LA:%.*]] = alloca i32, align 4 1761 // CHECK4-NEXT: [[LC:%.*]] = alloca float, align 4 1762 // CHECK4-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 1763 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1764 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1765 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1766 // CHECK4-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4 1767 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 1768 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 1769 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 1770 // CHECK4-NEXT: [[LA_CASTED:%.*]] = alloca i32, align 4 1771 // CHECK4-NEXT: [[COMP_CASTED7:%.*]] = alloca i32, align 4 1772 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4 1773 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4 1774 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4 1775 // CHECK4-NEXT: [[LA_CASTED13:%.*]] = alloca i32, align 4 1776 // CHECK4-NEXT: [[COMP_CASTED14:%.*]] = alloca i32, align 4 1777 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS15:%.*]] = alloca [2 x i8*], align 4 1778 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS16:%.*]] = alloca [2 x i8*], align 4 1779 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS17:%.*]] = alloca [2 x i8*], align 4 1780 // CHECK4-NEXT: [[GBLA_CASTED:%.*]] = alloca i32, align 4 1781 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1782 // CHECK4-NEXT: [[LC_CASTED:%.*]] = alloca i32, align 4 1783 // CHECK4-NEXT: [[COMP_CASTED20:%.*]] = alloca i32, align 4 1784 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [5 x i8*], align 4 1785 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [5 x i8*], align 4 1786 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [5 x i8*], align 4 1787 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4 1788 // CHECK4-NEXT: [[GBLC_CASTED:%.*]] = alloca i32, align 4 1789 // CHECK4-NEXT: [[COMP_CASTED28:%.*]] = alloca i32, align 4 1790 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [2 x i8*], align 4 1791 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [2 x i8*], align 4 1792 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [2 x i8*], align 4 1793 // CHECK4-NEXT: [[_TMP32:%.*]] = alloca i32*, align 4 1794 // CHECK4-NEXT: [[_TMP34:%.*]] = alloca i32*, align 4 1795 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1796 // CHECK4-NEXT: store i32 1, i32* [[COMP]], align 4 1797 // CHECK4-NEXT: store i32 23, i32* [[LA]], align 4 1798 // CHECK4-NEXT: store float 2.500000e+01, float* [[LC]], align 4 1799 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 1800 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 1801 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 1802 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1803 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* 1804 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 1805 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1806 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* 1807 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 1808 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1809 // CHECK4-NEXT: store i8* null, i8** [[TMP6]], align 4 1810 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1811 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1812 // CHECK4-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1813 // CHECK4-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 1814 // CHECK4-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1815 // CHECK4: omp_offload.failed: 1816 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31(i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 1817 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1818 // CHECK4: omp_offload.cont: 1819 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[COMP]], align 4 1820 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[COMP_CASTED1]], align 4 1821 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4 1822 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1823 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1824 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 1825 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1826 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 1827 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 1828 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 1829 // CHECK4-NEXT: store i8* null, i8** [[TMP17]], align 4 1830 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1831 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1832 // CHECK4-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1833 // CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1834 // CHECK4-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] 1835 // CHECK4: omp_offload.failed5: 1836 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37(i32 [[TMP12]]) #[[ATTR2]] 1837 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT6]] 1838 // CHECK4: omp_offload.cont6: 1839 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[LA]], align 4 1840 // CHECK4-NEXT: store i32 [[TMP22]], i32* [[LA_CASTED]], align 4 1841 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[LA_CASTED]], align 4 1842 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 1843 // CHECK4-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED7]], align 4 1844 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED7]], align 4 1845 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 1846 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 1847 // CHECK4-NEXT: store i32 [[TMP23]], i32* [[TMP27]], align 4 1848 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 1849 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 1850 // CHECK4-NEXT: store i32 [[TMP23]], i32* [[TMP29]], align 4 1851 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0 1852 // CHECK4-NEXT: store i8* null, i8** [[TMP30]], align 4 1853 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 1854 // CHECK4-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* 1855 // CHECK4-NEXT: store i32 [[TMP25]], i32* [[TMP32]], align 4 1856 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 1857 // CHECK4-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32* 1858 // CHECK4-NEXT: store i32 [[TMP25]], i32* [[TMP34]], align 4 1859 // CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1 1860 // CHECK4-NEXT: store i8* null, i8** [[TMP35]], align 4 1861 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 1862 // CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 1863 // CHECK4-NEXT: [[TMP38:%.*]] = load i32, i32* [[LA]], align 4 1864 // CHECK4-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46.region_id, i32 2, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP38]], i32 0) 1865 // CHECK4-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 1866 // CHECK4-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] 1867 // CHECK4: omp_offload.failed11: 1868 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR2]] 1869 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT12]] 1870 // CHECK4: omp_offload.cont12: 1871 // CHECK4-NEXT: [[TMP41:%.*]] = load i32, i32* [[LA]], align 4 1872 // CHECK4-NEXT: store i32 [[TMP41]], i32* [[LA_CASTED13]], align 4 1873 // CHECK4-NEXT: [[TMP42:%.*]] = load i32, i32* [[LA_CASTED13]], align 4 1874 // CHECK4-NEXT: [[TMP43:%.*]] = load i32, i32* [[COMP]], align 4 1875 // CHECK4-NEXT: store i32 [[TMP43]], i32* [[COMP_CASTED14]], align 4 1876 // CHECK4-NEXT: [[TMP44:%.*]] = load i32, i32* [[COMP_CASTED14]], align 4 1877 // CHECK4-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0 1878 // CHECK4-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* 1879 // CHECK4-NEXT: store i32 [[TMP42]], i32* [[TMP46]], align 4 1880 // CHECK4-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0 1881 // CHECK4-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i32* 1882 // CHECK4-NEXT: store i32 [[TMP42]], i32* [[TMP48]], align 4 1883 // CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 0 1884 // CHECK4-NEXT: store i8* null, i8** [[TMP49]], align 4 1885 // CHECK4-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 1 1886 // CHECK4-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 1887 // CHECK4-NEXT: store i32 [[TMP44]], i32* [[TMP51]], align 4 1888 // CHECK4-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 1 1889 // CHECK4-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 1890 // CHECK4-NEXT: store i32 [[TMP44]], i32* [[TMP53]], align 4 1891 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 1 1892 // CHECK4-NEXT: store i8* null, i8** [[TMP54]], align 4 1893 // CHECK4-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0 1894 // CHECK4-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0 1895 // CHECK4-NEXT: [[TMP57:%.*]] = load i32, i32* [[LA]], align 4 1896 // CHECK4-NEXT: [[TMP58:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 [[TMP57]]) 1897 // CHECK4-NEXT: [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0 1898 // CHECK4-NEXT: br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 1899 // CHECK4: omp_offload.failed18: 1900 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53(i32 [[TMP42]], i32 [[TMP44]]) #[[ATTR2]] 1901 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT19]] 1902 // CHECK4: omp_offload.cont19: 1903 // CHECK4-NEXT: [[TMP60:%.*]] = load i32, i32* @Gbla, align 4 1904 // CHECK4-NEXT: store i32 [[TMP60]], i32* [[GBLA_CASTED]], align 4 1905 // CHECK4-NEXT: [[TMP61:%.*]] = load i32, i32* [[GBLA_CASTED]], align 4 1906 // CHECK4-NEXT: [[TMP62:%.*]] = load i32, i32* [[A_ADDR]], align 4 1907 // CHECK4-NEXT: store i32 [[TMP62]], i32* [[A_CASTED]], align 4 1908 // CHECK4-NEXT: [[TMP63:%.*]] = load i32, i32* [[A_CASTED]], align 4 1909 // CHECK4-NEXT: [[TMP64:%.*]] = load float, float* [[LC]], align 4 1910 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[LC_CASTED]] to float* 1911 // CHECK4-NEXT: store float [[TMP64]], float* [[CONV]], align 4 1912 // CHECK4-NEXT: [[TMP65:%.*]] = load i32, i32* [[LC_CASTED]], align 4 1913 // CHECK4-NEXT: [[TMP66:%.*]] = load i32, i32* [[COMP]], align 4 1914 // CHECK4-NEXT: store i32 [[TMP66]], i32* [[COMP_CASTED20]], align 4 1915 // CHECK4-NEXT: [[TMP67:%.*]] = load i32, i32* [[COMP_CASTED20]], align 4 1916 // CHECK4-NEXT: [[TMP68:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 1917 // CHECK4-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32* 1918 // CHECK4-NEXT: store i32 [[TMP61]], i32* [[TMP69]], align 4 1919 // CHECK4-NEXT: [[TMP70:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 1920 // CHECK4-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* 1921 // CHECK4-NEXT: store i32 [[TMP61]], i32* [[TMP71]], align 4 1922 // CHECK4-NEXT: [[TMP72:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0 1923 // CHECK4-NEXT: store i8* null, i8** [[TMP72]], align 4 1924 // CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 1925 // CHECK4-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 1926 // CHECK4-NEXT: store i32 [[TMP63]], i32* [[TMP74]], align 4 1927 // CHECK4-NEXT: [[TMP75:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 1928 // CHECK4-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 1929 // CHECK4-NEXT: store i32 [[TMP63]], i32* [[TMP76]], align 4 1930 // CHECK4-NEXT: [[TMP77:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1 1931 // CHECK4-NEXT: store i8* null, i8** [[TMP77]], align 4 1932 // CHECK4-NEXT: [[TMP78:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 1933 // CHECK4-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64** 1934 // CHECK4-NEXT: store i64* @Gblb, i64** [[TMP79]], align 4 1935 // CHECK4-NEXT: [[TMP80:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 1936 // CHECK4-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64** 1937 // CHECK4-NEXT: store i64* @Gblb, i64** [[TMP81]], align 4 1938 // CHECK4-NEXT: [[TMP82:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2 1939 // CHECK4-NEXT: store i8* null, i8** [[TMP82]], align 4 1940 // CHECK4-NEXT: [[TMP83:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 1941 // CHECK4-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32* 1942 // CHECK4-NEXT: store i32 [[TMP65]], i32* [[TMP84]], align 4 1943 // CHECK4-NEXT: [[TMP85:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 1944 // CHECK4-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* 1945 // CHECK4-NEXT: store i32 [[TMP65]], i32* [[TMP86]], align 4 1946 // CHECK4-NEXT: [[TMP87:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3 1947 // CHECK4-NEXT: store i8* null, i8** [[TMP87]], align 4 1948 // CHECK4-NEXT: [[TMP88:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4 1949 // CHECK4-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32* 1950 // CHECK4-NEXT: store i32 [[TMP67]], i32* [[TMP89]], align 4 1951 // CHECK4-NEXT: [[TMP90:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4 1952 // CHECK4-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32* 1953 // CHECK4-NEXT: store i32 [[TMP67]], i32* [[TMP91]], align 4 1954 // CHECK4-NEXT: [[TMP92:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4 1955 // CHECK4-NEXT: store i8* null, i8** [[TMP92]], align 4 1956 // CHECK4-NEXT: [[TMP93:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 1957 // CHECK4-NEXT: [[TMP94:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 1958 // CHECK4-NEXT: [[TMP95:%.*]] = load i32, i32* @Gbla, align 4 1959 // CHECK4-NEXT: [[TMP96:%.*]] = load i32, i32* [[A_ADDR]], align 4 1960 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP95]], [[TMP96]] 1961 // CHECK4-NEXT: [[TMP97:%.*]] = load i64, i64* @Gblb, align 8 1962 // CHECK4-NEXT: [[TMP98:%.*]] = load float, float* [[LC]], align 4 1963 // CHECK4-NEXT: [[CONV24:%.*]] = fptosi float [[TMP98]] to i64 1964 // CHECK4-NEXT: [[ADD25:%.*]] = add nsw i64 [[TMP97]], [[CONV24]] 1965 // CHECK4-NEXT: [[TMP99:%.*]] = trunc i64 [[ADD25]] to i32 1966 // CHECK4-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62.region_id, i32 5, i8** [[TMP93]], i8** [[TMP94]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes.11, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 [[ADD]], i32 [[TMP99]]) 1967 // CHECK4-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 1968 // CHECK4-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED26:%.*]], label [[OMP_OFFLOAD_CONT27:%.*]] 1969 // CHECK4: omp_offload.failed26: 1970 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62(i32 [[TMP61]], i32 [[TMP63]], i64* @Gblb, i32 [[TMP65]], i32 [[TMP67]]) #[[ATTR2]] 1971 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT27]] 1972 // CHECK4: omp_offload.cont27: 1973 // CHECK4-NEXT: [[TMP102:%.*]] = load i32*, i32** @Gblc, align 4 1974 // CHECK4-NEXT: store i32* [[TMP102]], i32** [[TMP]], align 4 1975 // CHECK4-NEXT: [[TMP103:%.*]] = load i32, i32* @Gbla, align 4 1976 // CHECK4-NEXT: store i32 [[TMP103]], i32* [[GBLC_CASTED]], align 4 1977 // CHECK4-NEXT: [[TMP104:%.*]] = load i32, i32* [[GBLC_CASTED]], align 4 1978 // CHECK4-NEXT: [[TMP105:%.*]] = load i32, i32* [[COMP]], align 4 1979 // CHECK4-NEXT: store i32 [[TMP105]], i32* [[COMP_CASTED28]], align 4 1980 // CHECK4-NEXT: [[TMP106:%.*]] = load i32, i32* [[COMP_CASTED28]], align 4 1981 // CHECK4-NEXT: [[TMP107:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 1982 // CHECK4-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to i32* 1983 // CHECK4-NEXT: store i32 [[TMP104]], i32* [[TMP108]], align 4 1984 // CHECK4-NEXT: [[TMP109:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 1985 // CHECK4-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to i32* 1986 // CHECK4-NEXT: store i32 [[TMP104]], i32* [[TMP110]], align 4 1987 // CHECK4-NEXT: [[TMP111:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i32 0, i32 0 1988 // CHECK4-NEXT: store i8* null, i8** [[TMP111]], align 4 1989 // CHECK4-NEXT: [[TMP112:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 1 1990 // CHECK4-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to i32* 1991 // CHECK4-NEXT: store i32 [[TMP106]], i32* [[TMP113]], align 4 1992 // CHECK4-NEXT: [[TMP114:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 1 1993 // CHECK4-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 1994 // CHECK4-NEXT: store i32 [[TMP106]], i32* [[TMP115]], align 4 1995 // CHECK4-NEXT: [[TMP116:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i32 0, i32 1 1996 // CHECK4-NEXT: store i8* null, i8** [[TMP116]], align 4 1997 // CHECK4-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 1998 // CHECK4-NEXT: [[TMP118:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 1999 // CHECK4-NEXT: [[TMP119:%.*]] = load i32*, i32** @Gblc, align 4 2000 // CHECK4-NEXT: store i32* [[TMP119]], i32** [[_TMP32]], align 4 2001 // CHECK4-NEXT: [[TMP120:%.*]] = load i32, i32* @Gbla, align 4 2002 // CHECK4-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP120]], 1 2003 // CHECK4-NEXT: [[TMP121:%.*]] = load i32*, i32** @Gblc, align 4 2004 // CHECK4-NEXT: store i32* [[TMP121]], i32** [[_TMP34]], align 4 2005 // CHECK4-NEXT: [[TMP122:%.*]] = load i32, i32* @Gbla, align 4 2006 // CHECK4-NEXT: [[ADD35:%.*]] = add nsw i32 [[TMP122]], 2 2007 // CHECK4-NEXT: [[TMP123:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71.region_id, i32 2, i8** [[TMP117]], i8** [[TMP118]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 [[ADD33]], i32 [[ADD35]]) 2008 // CHECK4-NEXT: [[TMP124:%.*]] = icmp ne i32 [[TMP123]], 0 2009 // CHECK4-NEXT: br i1 [[TMP124]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 2010 // CHECK4: omp_offload.failed36: 2011 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71(i32 [[TMP104]], i32 [[TMP106]]) #[[ATTR2]] 2012 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT37]] 2013 // CHECK4: omp_offload.cont37: 2014 // CHECK4-NEXT: [[TMP125:%.*]] = load i32, i32* [[COMP]], align 4 2015 // CHECK4-NEXT: ret i32 [[TMP125]] 2016 // 2017 // 2018 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l31 2019 // CHECK4-SAME: (i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 2020 // CHECK4-NEXT: entry: 2021 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 2022 // CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 2023 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 2024 // CHECK4-NEXT: ret void 2025 // 2026 // 2027 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 2028 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2029 // CHECK4-NEXT: entry: 2030 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2031 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2032 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 2033 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2034 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2035 // CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 2036 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 2037 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2038 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2039 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2040 // CHECK4-NEXT: ret void 2041 // 2042 // 2043 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l37 2044 // CHECK4-SAME: (i32 [[COMP:%.*]]) #[[ATTR1]] { 2045 // CHECK4-NEXT: entry: 2046 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 2047 // CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 2048 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 2049 // CHECK4-NEXT: ret void 2050 // 2051 // 2052 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 2053 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2054 // CHECK4-NEXT: entry: 2055 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2056 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2057 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 2058 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2059 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2060 // CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 2061 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 2062 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2063 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2064 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2065 // CHECK4-NEXT: ret void 2066 // 2067 // 2068 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l46 2069 // CHECK4-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 2070 // CHECK4-NEXT: entry: 2071 // CHECK4-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4 2072 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 2073 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2074 // CHECK4-NEXT: store i32 [[LA]], i32* [[LA_ADDR]], align 4 2075 // CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 2076 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[LA_ADDR]], align 4 2077 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 2078 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 2079 // CHECK4-NEXT: ret void 2080 // 2081 // 2082 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 2083 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2084 // CHECK4-NEXT: entry: 2085 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2086 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2087 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 2088 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2089 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2090 // CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 2091 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 2092 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2093 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2094 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2095 // CHECK4-NEXT: ret void 2096 // 2097 // 2098 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l53 2099 // CHECK4-SAME: (i32 [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 2100 // CHECK4-NEXT: entry: 2101 // CHECK4-NEXT: [[LA_ADDR:%.*]] = alloca i32, align 4 2102 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 2103 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2104 // CHECK4-NEXT: store i32 [[LA]], i32* [[LA_ADDR]], align 4 2105 // CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 2106 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[LA_ADDR]], align 4 2107 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 0, i32 [[TMP1]]) 2108 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 2109 // CHECK4-NEXT: ret void 2110 // 2111 // 2112 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 2113 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2114 // CHECK4-NEXT: entry: 2115 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2116 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2117 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 2118 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2119 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2120 // CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 2121 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 2122 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2123 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2124 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2125 // CHECK4-NEXT: ret void 2126 // 2127 // 2128 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l62 2129 // CHECK4-SAME: (i32 [[GBLA:%.*]], i32 [[A:%.*]], i64* nonnull align 4 dereferenceable(8) [[GBLB:%.*]], i32 [[LC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 2130 // CHECK4-NEXT: entry: 2131 // CHECK4-NEXT: [[GBLA_ADDR:%.*]] = alloca i32, align 4 2132 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2133 // CHECK4-NEXT: [[GBLB_ADDR:%.*]] = alloca i64*, align 4 2134 // CHECK4-NEXT: [[LC_ADDR:%.*]] = alloca i32, align 4 2135 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 2136 // CHECK4-NEXT: [[GBLB1:%.*]] = alloca i64, align 8 2137 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2138 // CHECK4-NEXT: store i32 [[GBLA]], i32* [[GBLA_ADDR]], align 4 2139 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2140 // CHECK4-NEXT: store i64* [[GBLB]], i64** [[GBLB_ADDR]], align 4 2141 // CHECK4-NEXT: store i32 [[LC]], i32* [[LC_ADDR]], align 4 2142 // CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 2143 // CHECK4-NEXT: [[TMP1:%.*]] = load i64*, i64** [[GBLB_ADDR]], align 4 2144 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[LC_ADDR]] to float* 2145 // CHECK4-NEXT: [[TMP2:%.*]] = load i64, i64* [[TMP1]], align 8 2146 // CHECK4-NEXT: store i64 [[TMP2]], i64* [[GBLB1]], align 8 2147 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[GBLA_ADDR]], align 4 2148 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 2149 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP4]] 2150 // CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[GBLB1]], align 8 2151 // CHECK4-NEXT: [[TMP6:%.*]] = load float, float* [[CONV]], align 4 2152 // CHECK4-NEXT: [[CONV2:%.*]] = fptosi float [[TMP6]] to i64 2153 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i64 [[TMP5]], [[CONV2]] 2154 // CHECK4-NEXT: [[TMP7:%.*]] = trunc i64 [[ADD3]] to i32 2155 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[TMP7]]) 2156 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 2157 // CHECK4-NEXT: ret void 2158 // 2159 // 2160 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 2161 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2162 // CHECK4-NEXT: entry: 2163 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2164 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2165 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 2166 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2167 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2168 // CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 2169 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 2170 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2171 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2172 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2173 // CHECK4-NEXT: ret void 2174 // 2175 // 2176 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z27teams_argument_global_locali_l71 2177 // CHECK4-SAME: (i32 [[GBLC:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 2178 // CHECK4-NEXT: entry: 2179 // CHECK4-NEXT: [[GBLC_ADDR:%.*]] = alloca i32, align 4 2180 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 2181 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2182 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2183 // CHECK4-NEXT: store i32 [[GBLC]], i32* [[GBLC_ADDR]], align 4 2184 // CHECK4-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 2185 // CHECK4-NEXT: store i32* [[GBLC_ADDR]], i32** [[TMP]], align 4 2186 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* @Gbla, align 4 2187 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2188 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4 2189 // CHECK4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], 2 2190 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[ADD]], i32 [[ADD1]]) 2191 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP]], align 4 2192 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]], i32* [[TMP3]]) 2193 // CHECK4-NEXT: ret void 2194 // 2195 // 2196 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 2197 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]], i32* nonnull align 4 dereferenceable(4) [[GBLC:%.*]]) #[[ATTR1]] { 2198 // CHECK4-NEXT: entry: 2199 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2200 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2201 // CHECK4-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 2202 // CHECK4-NEXT: [[GBLC_ADDR:%.*]] = alloca i32*, align 4 2203 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2204 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2205 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2206 // CHECK4-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 2207 // CHECK4-NEXT: store i32* [[GBLC]], i32** [[GBLC_ADDR]], align 4 2208 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 2209 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[GBLC_ADDR]], align 4 2210 // CHECK4-NEXT: store i32* [[TMP1]], i32** [[TMP]], align 4 2211 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @Gbla, align 4 2212 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4 2213 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] 2214 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP0]], align 4 2215 // CHECK4-NEXT: ret void 2216 // 2217 // 2218 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2219 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 2220 // CHECK4-NEXT: entry: 2221 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 2222 // CHECK4-NEXT: ret void 2223 // 2224 // 2225 // CHECK5-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali 2226 // CHECK5-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 2227 // CHECK5-NEXT: entry: 2228 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2229 // CHECK5-NEXT: [[COMP:%.*]] = alloca i32, align 4 2230 // CHECK5-NEXT: [[LA:%.*]] = alloca i32, align 4 2231 // CHECK5-NEXT: [[LC:%.*]] = alloca float, align 4 2232 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2233 // CHECK5-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 2234 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2235 // CHECK5-NEXT: store i32 1, i32* [[COMP]], align 4 2236 // CHECK5-NEXT: store i32 23, i32* [[LA]], align 4 2237 // CHECK5-NEXT: store float 2.500000e+01, float* [[LC]], align 4 2238 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 2239 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 2240 // CHECK5-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 2241 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 2242 // CHECK5-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 2243 // CHECK5-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 2244 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 2245 // CHECK5-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 2246 // CHECK5-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 2247 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 2248 // CHECK5-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 2249 // CHECK5-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 2250 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 2251 // CHECK5-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 2252 // CHECK5-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 2253 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 8 2254 // CHECK5-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 2255 // CHECK5-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 8 2256 // CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 2257 // CHECK5-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 8 2258 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 2259 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 2260 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 2261 // CHECK5-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 2262 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 2263 // CHECK5-NEXT: ret i32 [[TMP10]] 2264 // 2265 // 2266 // CHECK6-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali 2267 // CHECK6-SAME: (i32 signext [[A:%.*]]) #[[ATTR0:[0-9]+]] { 2268 // CHECK6-NEXT: entry: 2269 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2270 // CHECK6-NEXT: [[COMP:%.*]] = alloca i32, align 4 2271 // CHECK6-NEXT: [[LA:%.*]] = alloca i32, align 4 2272 // CHECK6-NEXT: [[LC:%.*]] = alloca float, align 4 2273 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2274 // CHECK6-NEXT: [[_TMP5:%.*]] = alloca i32*, align 8 2275 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2276 // CHECK6-NEXT: store i32 1, i32* [[COMP]], align 4 2277 // CHECK6-NEXT: store i32 23, i32* [[LA]], align 4 2278 // CHECK6-NEXT: store float 2.500000e+01, float* [[LC]], align 4 2279 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 2280 // CHECK6-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 2281 // CHECK6-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 2282 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 2283 // CHECK6-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 2284 // CHECK6-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 2285 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 2286 // CHECK6-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 2287 // CHECK6-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 2288 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 2289 // CHECK6-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 2290 // CHECK6-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 2291 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 2292 // CHECK6-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 2293 // CHECK6-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 2294 // CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 8 2295 // CHECK6-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 8 2296 // CHECK6-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 8 2297 // CHECK6-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 2298 // CHECK6-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 8 2299 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 2300 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 2301 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 2302 // CHECK6-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 2303 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 2304 // CHECK6-NEXT: ret i32 [[TMP10]] 2305 // 2306 // 2307 // CHECK7-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali 2308 // CHECK7-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { 2309 // CHECK7-NEXT: entry: 2310 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2311 // CHECK7-NEXT: [[COMP:%.*]] = alloca i32, align 4 2312 // CHECK7-NEXT: [[LA:%.*]] = alloca i32, align 4 2313 // CHECK7-NEXT: [[LC:%.*]] = alloca float, align 4 2314 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2315 // CHECK7-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 2316 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2317 // CHECK7-NEXT: store i32 1, i32* [[COMP]], align 4 2318 // CHECK7-NEXT: store i32 23, i32* [[LA]], align 4 2319 // CHECK7-NEXT: store float 2.500000e+01, float* [[LC]], align 4 2320 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 2321 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 2322 // CHECK7-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 2323 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 2324 // CHECK7-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 2325 // CHECK7-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 2326 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 2327 // CHECK7-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 2328 // CHECK7-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 2329 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 2330 // CHECK7-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 2331 // CHECK7-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 2332 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 2333 // CHECK7-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 2334 // CHECK7-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 2335 // CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 4 2336 // CHECK7-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 4 2337 // CHECK7-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 4 2338 // CHECK7-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 2339 // CHECK7-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 4 2340 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 2341 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 2342 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 2343 // CHECK7-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 2344 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 2345 // CHECK7-NEXT: ret i32 [[TMP10]] 2346 // 2347 // 2348 // CHECK8-LABEL: define {{[^@]+}}@_Z27teams_argument_global_locali 2349 // CHECK8-SAME: (i32 [[A:%.*]]) #[[ATTR0:[0-9]+]] { 2350 // CHECK8-NEXT: entry: 2351 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2352 // CHECK8-NEXT: [[COMP:%.*]] = alloca i32, align 4 2353 // CHECK8-NEXT: [[LA:%.*]] = alloca i32, align 4 2354 // CHECK8-NEXT: [[LC:%.*]] = alloca float, align 4 2355 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2356 // CHECK8-NEXT: [[_TMP5:%.*]] = alloca i32*, align 4 2357 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2358 // CHECK8-NEXT: store i32 1, i32* [[COMP]], align 4 2359 // CHECK8-NEXT: store i32 23, i32* [[LA]], align 4 2360 // CHECK8-NEXT: store float 2.500000e+01, float* [[LC]], align 4 2361 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 2362 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 2363 // CHECK8-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 2364 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 2365 // CHECK8-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 2366 // CHECK8-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 2367 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 2368 // CHECK8-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP2]], 1 2369 // CHECK8-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 2370 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[COMP]], align 4 2371 // CHECK8-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP3]], 1 2372 // CHECK8-NEXT: store i32 [[INC3]], i32* [[COMP]], align 4 2373 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[COMP]], align 4 2374 // CHECK8-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP4]], 1 2375 // CHECK8-NEXT: store i32 [[INC4]], i32* [[COMP]], align 4 2376 // CHECK8-NEXT: [[TMP5:%.*]] = load i32*, i32** @Gblc, align 4 2377 // CHECK8-NEXT: store i32* [[TMP5]], i32** [[TMP]], align 4 2378 // CHECK8-NEXT: [[TMP6:%.*]] = load i32*, i32** @Gblc, align 4 2379 // CHECK8-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 2380 // CHECK8-NEXT: store i32* [[TMP7]], i32** [[_TMP5]], align 4 2381 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* @Gbla, align 4 2382 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[COMP]], align 4 2383 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 2384 // CHECK8-NEXT: store i32 [[ADD]], i32* [[COMP]], align 4 2385 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[COMP]], align 4 2386 // CHECK8-NEXT: ret i32 [[TMP10]] 2387 // 2388 // 2389 // CHECK9-LABEL: define {{[^@]+}}@_Z18teams_template_argv 2390 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2391 // CHECK9-NEXT: entry: 2392 // CHECK9-NEXT: [[COMP:%.*]] = alloca i32, align 4 2393 // CHECK9-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 2394 // CHECK9-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 2395 // CHECK9-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 2396 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 2397 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 2398 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 2399 // CHECK9-NEXT: [[COMP_CASTED2:%.*]] = alloca i64, align 8 2400 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 8 2401 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 8 2402 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 8 2403 // CHECK9-NEXT: store i32 1, i32* [[COMP]], align 4 2404 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 2405 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* 2406 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 2407 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 2408 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2409 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** 2410 // CHECK9-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 8 2411 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2412 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** 2413 // CHECK9-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 8 2414 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2415 // CHECK9-NEXT: store i8* null, i8** [[TMP6]], align 8 2416 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2417 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** 2418 // CHECK9-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 8 2419 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2420 // CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** 2421 // CHECK9-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 8 2422 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2423 // CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 2424 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2425 // CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2426 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 2427 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2428 // CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 2429 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 2430 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2431 // CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 2432 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2433 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2434 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 2435 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 2436 // CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 2437 // CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP20]] to i64 2438 // CHECK9-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV1]] to i32 2439 // CHECK9-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) 2440 // CHECK9-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2441 // CHECK9-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2442 // CHECK9: omp_offload.failed: 2443 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 2444 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 2445 // CHECK9: omp_offload.cont: 2446 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 2447 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_CASTED2]] to i32* 2448 // CHECK9-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4 2449 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED2]], align 8 2450 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 2451 // CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** 2452 // CHECK9-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 8 2453 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 2454 // CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** 2455 // CHECK9-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 8 2456 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 2457 // CHECK9-NEXT: store i8* null, i8** [[TMP30]], align 8 2458 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 2459 // CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** 2460 // CHECK9-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 8 2461 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 2462 // CHECK9-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** 2463 // CHECK9-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 8 2464 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 2465 // CHECK9-NEXT: store i8* null, i8** [[TMP35]], align 8 2466 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 2467 // CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 2468 // CHECK9-NEXT: store i64 [[TMP25]], i64* [[TMP37]], align 8 2469 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 2470 // CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 2471 // CHECK9-NEXT: store i64 [[TMP25]], i64* [[TMP39]], align 8 2472 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2 2473 // CHECK9-NEXT: store i8* null, i8** [[TMP40]], align 8 2474 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 2475 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 2476 // CHECK9-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 2477 // CHECK9-NEXT: [[TMP43:%.*]] = load float, float* [[B7]], align 8 2478 // CHECK9-NEXT: [[CONV8:%.*]] = fptosi float [[TMP43]] to i64 2479 // CHECK9-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV8]] to i32 2480 // CHECK9-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 8 2481 // CHECK9-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 2482 // CHECK9-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) 2483 // CHECK9-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 2484 // CHECK9-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 2485 // CHECK9: omp_offload.failed9: 2486 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i64 [[TMP25]]) #[[ATTR2]] 2487 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT10]] 2488 // CHECK9: omp_offload.cont10: 2489 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 2490 // CHECK9-NEXT: ret i32 [[TMP49]] 2491 // 2492 // 2493 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 2494 // CHECK9-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 2495 // CHECK9-NEXT: entry: 2496 // CHECK9-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8 2497 // CHECK9-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8 2498 // CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 2499 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2500 // CHECK9-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 8 2501 // CHECK9-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 8 2502 // CHECK9-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 2503 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 8 2504 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 8 2505 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 2506 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 2507 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2508 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 2509 // CHECK9-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 2510 // CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP4]] to i64 2511 // CHECK9-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV1]] to i32 2512 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) 2513 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 2514 // CHECK9-NEXT: ret void 2515 // 2516 // 2517 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2518 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2519 // CHECK9-NEXT: entry: 2520 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2521 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2522 // CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 2523 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2524 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2525 // CHECK9-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 2526 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 2527 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2528 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2529 // CHECK9-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2530 // CHECK9-NEXT: ret void 2531 // 2532 // 2533 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 2534 // CHECK9-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 2535 // CHECK9-NEXT: entry: 2536 // CHECK9-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 2537 // CHECK9-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 2538 // CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 2539 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2540 // CHECK9-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 8 2541 // CHECK9-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 8 2542 // CHECK9-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 2543 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 8 2544 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 8 2545 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 2546 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 2547 // CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 8 2548 // CHECK9-NEXT: [[CONV1:%.*]] = fptosi float [[TMP3]] to i64 2549 // CHECK9-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV1]] to i32 2550 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 2551 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 8 2552 // CHECK9-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 2553 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) 2554 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 2555 // CHECK9-NEXT: ret void 2556 // 2557 // 2558 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 2559 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2560 // CHECK9-NEXT: entry: 2561 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2562 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2563 // CHECK9-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 2564 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2565 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2566 // CHECK9-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 2567 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 2568 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2569 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2570 // CHECK9-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2571 // CHECK9-NEXT: ret void 2572 // 2573 // 2574 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2575 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2576 // CHECK9-NEXT: entry: 2577 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 2578 // CHECK9-NEXT: ret void 2579 // 2580 // 2581 // CHECK10-LABEL: define {{[^@]+}}@_Z18teams_template_argv 2582 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 2583 // CHECK10-NEXT: entry: 2584 // CHECK10-NEXT: [[COMP:%.*]] = alloca i32, align 4 2585 // CHECK10-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 2586 // CHECK10-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 2587 // CHECK10-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 2588 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 2589 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 2590 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 2591 // CHECK10-NEXT: [[COMP_CASTED2:%.*]] = alloca i64, align 8 2592 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [3 x i8*], align 8 2593 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [3 x i8*], align 8 2594 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [3 x i8*], align 8 2595 // CHECK10-NEXT: store i32 1, i32* [[COMP]], align 4 2596 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 2597 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* 2598 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 2599 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 2600 // CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2601 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** 2602 // CHECK10-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 8 2603 // CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2604 // CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** 2605 // CHECK10-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 8 2606 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2607 // CHECK10-NEXT: store i8* null, i8** [[TMP6]], align 8 2608 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2609 // CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** 2610 // CHECK10-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 8 2611 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2612 // CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** 2613 // CHECK10-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 8 2614 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2615 // CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 2616 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2617 // CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2618 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP13]], align 8 2619 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2620 // CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 2621 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP15]], align 8 2622 // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2623 // CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 2624 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2625 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2626 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 2627 // CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 2628 // CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 2629 // CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP20]] to i64 2630 // CHECK10-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV1]] to i32 2631 // CHECK10-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) 2632 // CHECK10-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2633 // CHECK10-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2634 // CHECK10: omp_offload.failed: 2635 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 2636 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 2637 // CHECK10: omp_offload.cont: 2638 // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 2639 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[COMP_CASTED2]] to i32* 2640 // CHECK10-NEXT: store i32 [[TMP24]], i32* [[CONV3]], align 4 2641 // CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[COMP_CASTED2]], align 8 2642 // CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 2643 // CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** 2644 // CHECK10-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 8 2645 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 2646 // CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** 2647 // CHECK10-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 8 2648 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 2649 // CHECK10-NEXT: store i8* null, i8** [[TMP30]], align 8 2650 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 2651 // CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** 2652 // CHECK10-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 8 2653 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 2654 // CHECK10-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** 2655 // CHECK10-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 8 2656 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 2657 // CHECK10-NEXT: store i8* null, i8** [[TMP35]], align 8 2658 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2 2659 // CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 2660 // CHECK10-NEXT: store i64 [[TMP25]], i64* [[TMP37]], align 8 2661 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2 2662 // CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 2663 // CHECK10-NEXT: store i64 [[TMP25]], i64* [[TMP39]], align 8 2664 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2 2665 // CHECK10-NEXT: store i8* null, i8** [[TMP40]], align 8 2666 // CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 2667 // CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 2668 // CHECK10-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 2669 // CHECK10-NEXT: [[TMP43:%.*]] = load float, float* [[B7]], align 8 2670 // CHECK10-NEXT: [[CONV8:%.*]] = fptosi float [[TMP43]] to i64 2671 // CHECK10-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV8]] to i32 2672 // CHECK10-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 8 2673 // CHECK10-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 2674 // CHECK10-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) 2675 // CHECK10-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 2676 // CHECK10-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 2677 // CHECK10: omp_offload.failed9: 2678 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i64 [[TMP25]]) #[[ATTR2]] 2679 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT10]] 2680 // CHECK10: omp_offload.cont10: 2681 // CHECK10-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 2682 // CHECK10-NEXT: ret i32 [[TMP49]] 2683 // 2684 // 2685 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 2686 // CHECK10-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 2687 // CHECK10-NEXT: entry: 2688 // CHECK10-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 8 2689 // CHECK10-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 8 2690 // CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 2691 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2692 // CHECK10-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 8 2693 // CHECK10-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 8 2694 // CHECK10-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 2695 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 8 2696 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 8 2697 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 2698 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 2699 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2700 // CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 2701 // CHECK10-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 2702 // CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP4]] to i64 2703 // CHECK10-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV1]] to i32 2704 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) 2705 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 2706 // CHECK10-NEXT: ret void 2707 // 2708 // 2709 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 2710 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2711 // CHECK10-NEXT: entry: 2712 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2713 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2714 // CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 2715 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2716 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2717 // CHECK10-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 2718 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 2719 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2720 // CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2721 // CHECK10-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2722 // CHECK10-NEXT: ret void 2723 // 2724 // 2725 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 2726 // CHECK10-SAME: (%struct.SS.0* nonnull align 8 dereferenceable(16) [[LB:%.*]], %struct.SS.0* nonnull align 8 dereferenceable(16) [[GBLB:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 2727 // CHECK10-NEXT: entry: 2728 // CHECK10-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 2729 // CHECK10-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 8 2730 // CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 2731 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2732 // CHECK10-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 8 2733 // CHECK10-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 8 2734 // CHECK10-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 2735 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 8 2736 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 8 2737 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 2738 // CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 2739 // CHECK10-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 8 2740 // CHECK10-NEXT: [[CONV1:%.*]] = fptosi float [[TMP3]] to i64 2741 // CHECK10-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV1]] to i32 2742 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 2743 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 8 2744 // CHECK10-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 2745 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) 2746 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 2747 // CHECK10-NEXT: ret void 2748 // 2749 // 2750 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 2751 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2752 // CHECK10-NEXT: entry: 2753 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2754 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2755 // CHECK10-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 2756 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2757 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2758 // CHECK10-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 2759 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 2760 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2761 // CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2762 // CHECK10-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2763 // CHECK10-NEXT: ret void 2764 // 2765 // 2766 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2767 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 2768 // CHECK10-NEXT: entry: 2769 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 2770 // CHECK10-NEXT: ret void 2771 // 2772 // 2773 // CHECK11-LABEL: define {{[^@]+}}@_Z18teams_template_argv 2774 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2775 // CHECK11-NEXT: entry: 2776 // CHECK11-NEXT: [[COMP:%.*]] = alloca i32, align 4 2777 // CHECK11-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 2778 // CHECK11-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 2779 // CHECK11-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 2780 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 2781 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 2782 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 2783 // CHECK11-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4 2784 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [3 x i8*], align 4 2785 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [3 x i8*], align 4 2786 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [3 x i8*], align 4 2787 // CHECK11-NEXT: store i32 1, i32* [[COMP]], align 4 2788 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 2789 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 2790 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 2791 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2792 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** 2793 // CHECK11-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 4 2794 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2795 // CHECK11-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** 2796 // CHECK11-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 4 2797 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2798 // CHECK11-NEXT: store i8* null, i8** [[TMP6]], align 4 2799 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2800 // CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** 2801 // CHECK11-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 4 2802 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2803 // CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** 2804 // CHECK11-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 4 2805 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2806 // CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 2807 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2808 // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2809 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP13]], align 4 2810 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2811 // CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 2812 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP15]], align 4 2813 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2814 // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 2815 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2816 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2817 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 2818 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 2819 // CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 2820 // CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP20]] to i64 2821 // CHECK11-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV]] to i32 2822 // CHECK11-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) 2823 // CHECK11-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2824 // CHECK11-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2825 // CHECK11: omp_offload.failed: 2826 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 2827 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2828 // CHECK11: omp_offload.cont: 2829 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 2830 // CHECK11-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED1]], align 4 2831 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4 2832 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 2833 // CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** 2834 // CHECK11-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 4 2835 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 2836 // CHECK11-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** 2837 // CHECK11-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 4 2838 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 2839 // CHECK11-NEXT: store i8* null, i8** [[TMP30]], align 4 2840 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 2841 // CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** 2842 // CHECK11-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 4 2843 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 2844 // CHECK11-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** 2845 // CHECK11-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 4 2846 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 2847 // CHECK11-NEXT: store i8* null, i8** [[TMP35]], align 4 2848 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 2849 // CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 2850 // CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP37]], align 4 2851 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 2852 // CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 2853 // CHECK11-NEXT: store i32 [[TMP25]], i32* [[TMP39]], align 4 2854 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 2855 // CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 2856 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 2857 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 2858 // CHECK11-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 2859 // CHECK11-NEXT: [[TMP43:%.*]] = load float, float* [[B5]], align 4 2860 // CHECK11-NEXT: [[CONV6:%.*]] = fptosi float [[TMP43]] to i64 2861 // CHECK11-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV6]] to i32 2862 // CHECK11-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 4 2863 // CHECK11-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 2864 // CHECK11-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) 2865 // CHECK11-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 2866 // CHECK11-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 2867 // CHECK11: omp_offload.failed7: 2868 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i32 [[TMP25]]) #[[ATTR2]] 2869 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT8]] 2870 // CHECK11: omp_offload.cont8: 2871 // CHECK11-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 2872 // CHECK11-NEXT: ret i32 [[TMP49]] 2873 // 2874 // 2875 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 2876 // CHECK11-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 2877 // CHECK11-NEXT: entry: 2878 // CHECK11-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4 2879 // CHECK11-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4 2880 // CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 2881 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2882 // CHECK11-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 4 2883 // CHECK11-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 4 2884 // CHECK11-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 2885 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 4 2886 // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 4 2887 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 2888 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2889 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 2890 // CHECK11-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 2891 // CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i64 2892 // CHECK11-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV]] to i32 2893 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) 2894 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 2895 // CHECK11-NEXT: ret void 2896 // 2897 // 2898 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 2899 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2900 // CHECK11-NEXT: entry: 2901 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2902 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2903 // CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 2904 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2905 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2906 // CHECK11-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 2907 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 2908 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2909 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2910 // CHECK11-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2911 // CHECK11-NEXT: ret void 2912 // 2913 // 2914 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 2915 // CHECK11-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 2916 // CHECK11-NEXT: entry: 2917 // CHECK11-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 2918 // CHECK11-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 2919 // CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 2920 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2921 // CHECK11-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 4 2922 // CHECK11-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 4 2923 // CHECK11-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 2924 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 4 2925 // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 4 2926 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 2927 // CHECK11-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 4 2928 // CHECK11-NEXT: [[CONV:%.*]] = fptosi float [[TMP3]] to i64 2929 // CHECK11-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV]] to i32 2930 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 2931 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 4 2932 // CHECK11-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 2933 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) 2934 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 2935 // CHECK11-NEXT: ret void 2936 // 2937 // 2938 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2939 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 2940 // CHECK11-NEXT: entry: 2941 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2942 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2943 // CHECK11-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 2944 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2945 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2946 // CHECK11-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 2947 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 2948 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2949 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2950 // CHECK11-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2951 // CHECK11-NEXT: ret void 2952 // 2953 // 2954 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2955 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2956 // CHECK11-NEXT: entry: 2957 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 2958 // CHECK11-NEXT: ret void 2959 // 2960 // 2961 // CHECK12-LABEL: define {{[^@]+}}@_Z18teams_template_argv 2962 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 2963 // CHECK12-NEXT: entry: 2964 // CHECK12-NEXT: [[COMP:%.*]] = alloca i32, align 4 2965 // CHECK12-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 2966 // CHECK12-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 2967 // CHECK12-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 2968 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 2969 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 2970 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 2971 // CHECK12-NEXT: [[COMP_CASTED1:%.*]] = alloca i32, align 4 2972 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [3 x i8*], align 4 2973 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [3 x i8*], align 4 2974 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [3 x i8*], align 4 2975 // CHECK12-NEXT: store i32 1, i32* [[COMP]], align 4 2976 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 2977 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 2978 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 2979 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2980 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** 2981 // CHECK12-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP3]], align 4 2982 // CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2983 // CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to %struct.SS** 2984 // CHECK12-NEXT: store %struct.SS* @Gbla, %struct.SS** [[TMP5]], align 4 2985 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2986 // CHECK12-NEXT: store i8* null, i8** [[TMP6]], align 4 2987 // CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2988 // CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to %struct.SS** 2989 // CHECK12-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP8]], align 4 2990 // CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2991 // CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to %struct.SS** 2992 // CHECK12-NEXT: store %struct.SS* [[LA]], %struct.SS** [[TMP10]], align 4 2993 // CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2994 // CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 2995 // CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2996 // CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2997 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP13]], align 4 2998 // CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2999 // CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 3000 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP15]], align 4 3001 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3002 // CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 3003 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3004 // CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3005 // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_SS]], %struct.SS* @Gbla, i32 0, i32 0), align 4 3006 // CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[LA]], i32 0, i32 1 3007 // CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[B]], align 4 3008 // CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP20]] to i64 3009 // CHECK12-NEXT: [[TMP21:%.*]] = trunc i64 [[CONV]] to i32 3010 // CHECK12-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116.region_id, i32 3, i8** [[TMP17]], i8** [[TMP18]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP19]], i32 [[TMP21]]) 3011 // CHECK12-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3012 // CHECK12-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3013 // CHECK12: omp_offload.failed: 3014 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116(%struct.SS* @Gbla, %struct.SS* [[LA]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 3015 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 3016 // CHECK12: omp_offload.cont: 3017 // CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[COMP]], align 4 3018 // CHECK12-NEXT: store i32 [[TMP24]], i32* [[COMP_CASTED1]], align 4 3019 // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[COMP_CASTED1]], align 4 3020 // CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 3021 // CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.SS.0** 3022 // CHECK12-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP27]], align 4 3023 // CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 3024 // CHECK12-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to %struct.SS.0** 3025 // CHECK12-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[TMP29]], align 4 3026 // CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 3027 // CHECK12-NEXT: store i8* null, i8** [[TMP30]], align 4 3028 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 3029 // CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to %struct.SS.0** 3030 // CHECK12-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP32]], align 4 3031 // CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 3032 // CHECK12-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to %struct.SS.0** 3033 // CHECK12-NEXT: store %struct.SS.0* @Gblb, %struct.SS.0** [[TMP34]], align 4 3034 // CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 3035 // CHECK12-NEXT: store i8* null, i8** [[TMP35]], align 4 3036 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2 3037 // CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 3038 // CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP37]], align 4 3039 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2 3040 // CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 3041 // CHECK12-NEXT: store i32 [[TMP25]], i32* [[TMP39]], align 4 3042 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2 3043 // CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 3044 // CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 3045 // CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 3046 // CHECK12-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[LB]], i32 0, i32 1 3047 // CHECK12-NEXT: [[TMP43:%.*]] = load float, float* [[B5]], align 4 3048 // CHECK12-NEXT: [[CONV6:%.*]] = fptosi float [[TMP43]] to i64 3049 // CHECK12-NEXT: [[TMP44:%.*]] = trunc i64 [[CONV6]] to i32 3050 // CHECK12-NEXT: [[TMP45:%.*]] = load i64, i64* getelementptr inbounds ([[STRUCT_SS_0]], %struct.SS.0* @Gblb, i32 0, i32 0), align 4 3051 // CHECK12-NEXT: [[TMP46:%.*]] = trunc i64 [[TMP45]] to i32 3052 // CHECK12-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125.region_id, i32 3, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 [[TMP44]], i32 [[TMP46]]) 3053 // CHECK12-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 3054 // CHECK12-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 3055 // CHECK12: omp_offload.failed7: 3056 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125(%struct.SS.0* [[LB]], %struct.SS.0* @Gblb, i32 [[TMP25]]) #[[ATTR2]] 3057 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT8]] 3058 // CHECK12: omp_offload.cont8: 3059 // CHECK12-NEXT: [[TMP49:%.*]] = load i32, i32* [[COMP]], align 4 3060 // CHECK12-NEXT: ret i32 [[TMP49]] 3061 // 3062 // 3063 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l116 3064 // CHECK12-SAME: (%struct.SS* nonnull align 4 dereferenceable(8) [[GBLA:%.*]], %struct.SS* nonnull align 4 dereferenceable(8) [[LA:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 3065 // CHECK12-NEXT: entry: 3066 // CHECK12-NEXT: [[GBLA_ADDR:%.*]] = alloca %struct.SS*, align 4 3067 // CHECK12-NEXT: [[LA_ADDR:%.*]] = alloca %struct.SS*, align 4 3068 // CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 3069 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3070 // CHECK12-NEXT: store %struct.SS* [[GBLA]], %struct.SS** [[GBLA_ADDR]], align 4 3071 // CHECK12-NEXT: store %struct.SS* [[LA]], %struct.SS** [[LA_ADDR]], align 4 3072 // CHECK12-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 3073 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[GBLA_ADDR]], align 4 3074 // CHECK12-NEXT: [[TMP2:%.*]] = load %struct.SS*, %struct.SS** [[LA_ADDR]], align 4 3075 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 3076 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3077 // CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[TMP2]], i32 0, i32 1 3078 // CHECK12-NEXT: [[TMP4:%.*]] = load float, float* [[B]], align 4 3079 // CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i64 3080 // CHECK12-NEXT: [[TMP5:%.*]] = trunc i64 [[CONV]] to i32 3081 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP3]], i32 [[TMP5]]) 3082 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 3083 // CHECK12-NEXT: ret void 3084 // 3085 // 3086 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 3087 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3088 // CHECK12-NEXT: entry: 3089 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3090 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3091 // CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 3092 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3093 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3094 // CHECK12-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 3095 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 3096 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3097 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3098 // CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3099 // CHECK12-NEXT: ret void 3100 // 3101 // 3102 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z18teams_template_argv_l125 3103 // CHECK12-SAME: (%struct.SS.0* nonnull align 4 dereferenceable(12) [[LB:%.*]], %struct.SS.0* nonnull align 4 dereferenceable(12) [[GBLB:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 3104 // CHECK12-NEXT: entry: 3105 // CHECK12-NEXT: [[LB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 3106 // CHECK12-NEXT: [[GBLB_ADDR:%.*]] = alloca %struct.SS.0*, align 4 3107 // CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 3108 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3109 // CHECK12-NEXT: store %struct.SS.0* [[LB]], %struct.SS.0** [[LB_ADDR]], align 4 3110 // CHECK12-NEXT: store %struct.SS.0* [[GBLB]], %struct.SS.0** [[GBLB_ADDR]], align 4 3111 // CHECK12-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 3112 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.SS.0*, %struct.SS.0** [[LB_ADDR]], align 4 3113 // CHECK12-NEXT: [[TMP2:%.*]] = load %struct.SS.0*, %struct.SS.0** [[GBLB_ADDR]], align 4 3114 // CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS_0:%.*]], %struct.SS.0* [[TMP1]], i32 0, i32 1 3115 // CHECK12-NEXT: [[TMP3:%.*]] = load float, float* [[B]], align 4 3116 // CHECK12-NEXT: [[CONV:%.*]] = fptosi float [[TMP3]] to i64 3117 // CHECK12-NEXT: [[TMP4:%.*]] = trunc i64 [[CONV]] to i32 3118 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS_0]], %struct.SS.0* [[TMP2]], i32 0, i32 0 3119 // CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[A]], align 4 3120 // CHECK12-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 3121 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP4]], i32 [[TMP6]]) 3122 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 3123 // CHECK12-NEXT: ret void 3124 // 3125 // 3126 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 3127 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3128 // CHECK12-NEXT: entry: 3129 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3130 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3131 // CHECK12-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 3132 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3133 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3134 // CHECK12-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 3135 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 3136 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3137 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3138 // CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3139 // CHECK12-NEXT: ret void 3140 // 3141 // 3142 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3143 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 3144 // CHECK12-NEXT: entry: 3145 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) 3146 // CHECK12-NEXT: ret void 3147 // 3148 // 3149 // CHECK13-LABEL: define {{[^@]+}}@_Z18teams_template_argv 3150 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { 3151 // CHECK13-NEXT: entry: 3152 // CHECK13-NEXT: [[COMP:%.*]] = alloca i32, align 4 3153 // CHECK13-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3154 // CHECK13-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 3155 // CHECK13-NEXT: store i32 1, i32* [[COMP]], align 4 3156 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3157 // CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 3158 // CHECK13-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 3159 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 3160 // CHECK13-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 3161 // CHECK13-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 3162 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 3163 // CHECK13-NEXT: ret i32 [[TMP2]] 3164 // 3165 // 3166 // CHECK14-LABEL: define {{[^@]+}}@_Z18teams_template_argv 3167 // CHECK14-SAME: () #[[ATTR0:[0-9]+]] { 3168 // CHECK14-NEXT: entry: 3169 // CHECK14-NEXT: [[COMP:%.*]] = alloca i32, align 4 3170 // CHECK14-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3171 // CHECK14-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 8 3172 // CHECK14-NEXT: store i32 1, i32* [[COMP]], align 4 3173 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3174 // CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 3175 // CHECK14-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 3176 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 3177 // CHECK14-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 3178 // CHECK14-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 3179 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 3180 // CHECK14-NEXT: ret i32 [[TMP2]] 3181 // 3182 // 3183 // CHECK15-LABEL: define {{[^@]+}}@_Z18teams_template_argv 3184 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { 3185 // CHECK15-NEXT: entry: 3186 // CHECK15-NEXT: [[COMP:%.*]] = alloca i32, align 4 3187 // CHECK15-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3188 // CHECK15-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 3189 // CHECK15-NEXT: store i32 1, i32* [[COMP]], align 4 3190 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3191 // CHECK15-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 3192 // CHECK15-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 3193 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 3194 // CHECK15-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 3195 // CHECK15-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 3196 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 3197 // CHECK15-NEXT: ret i32 [[TMP2]] 3198 // 3199 // 3200 // CHECK16-LABEL: define {{[^@]+}}@_Z18teams_template_argv 3201 // CHECK16-SAME: () #[[ATTR0:[0-9]+]] { 3202 // CHECK16-NEXT: entry: 3203 // CHECK16-NEXT: [[COMP:%.*]] = alloca i32, align 4 3204 // CHECK16-NEXT: [[LA:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3205 // CHECK16-NEXT: [[LB:%.*]] = alloca [[STRUCT_SS_0:%.*]], align 4 3206 // CHECK16-NEXT: store i32 1, i32* [[COMP]], align 4 3207 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3208 // CHECK16-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 3209 // CHECK16-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 3210 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 3211 // CHECK16-NEXT: [[INC1:%.*]] = add nsw i32 [[TMP1]], 1 3212 // CHECK16-NEXT: store i32 [[INC1]], i32* [[COMP]], align 4 3213 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 3214 // CHECK16-NEXT: ret i32 [[TMP2]] 3215 // 3216 // 3217 // CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv 3218 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { 3219 // CHECK17-NEXT: entry: 3220 // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3221 // CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) 3222 // CHECK17-NEXT: ret i32 [[CALL]] 3223 // 3224 // 3225 // CHECK17-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 3226 // CHECK17-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 3227 // CHECK17-NEXT: entry: 3228 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3229 // CHECK17-NEXT: [[COMP:%.*]] = alloca i32, align 4 3230 // CHECK17-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 3231 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 3232 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 3233 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 3234 // CHECK17-NEXT: [[COMP_CASTED3:%.*]] = alloca i64, align 8 3235 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 8 3236 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 8 3237 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 8 3238 // CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3239 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3240 // CHECK17-NEXT: store i32 1, i32* [[COMP]], align 4 3241 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3242 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* 3243 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 3244 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 3245 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 3246 // CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3247 // CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** 3248 // CHECK17-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 8 3249 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3250 // CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** 3251 // CHECK17-NEXT: store i32* [[A]], i32** [[TMP5]], align 8 3252 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3253 // CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8 3254 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3255 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 3256 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 3257 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3258 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 3259 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 3260 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3261 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 3262 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3263 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3264 // CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 3265 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 3266 // CHECK17-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) 3267 // CHECK17-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 3268 // CHECK17-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3269 // CHECK17: omp_offload.failed: 3270 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 3271 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 3272 // CHECK17: omp_offload.cont: 3273 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 3274 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[COMP_CASTED3]] to i32* 3275 // CHECK17-NEXT: store i32 [[TMP17]], i32* [[CONV4]], align 4 3276 // CHECK17-NEXT: [[TMP18:%.*]] = load i64, i64* [[COMP_CASTED3]], align 8 3277 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3278 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3279 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** 3280 // CHECK17-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 8 3281 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3282 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 3283 // CHECK17-NEXT: store float* [[B]], float** [[TMP22]], align 8 3284 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 3285 // CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 3286 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 3287 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 3288 // CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP25]], align 8 3289 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 3290 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 3291 // CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 3292 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 3293 // CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8 3294 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3295 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3296 // CHECK17-NEXT: [[B8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3297 // CHECK17-NEXT: [[TMP31:%.*]] = load float, float* [[B8]], align 4 3298 // CHECK17-NEXT: [[CONV9:%.*]] = fptosi float [[TMP31]] to i32 3299 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 123 3300 // CHECK17-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) 3301 // CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 3302 // CHECK17-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 3303 // CHECK17: omp_offload.failed10: 3304 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i64 [[TMP18]]) #[[ATTR2]] 3305 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT11]] 3306 // CHECK17: omp_offload.cont11: 3307 // CHECK17-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 3308 // CHECK17-NEXT: ret i32 [[TMP34]] 3309 // 3310 // 3311 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 3312 // CHECK17-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 3313 // CHECK17-NEXT: entry: 3314 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3315 // CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 3316 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3317 // CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3318 // CHECK17-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 3319 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3320 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 3321 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 3322 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3323 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) 3324 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 3325 // CHECK17-NEXT: ret void 3326 // 3327 // 3328 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 3329 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3330 // CHECK17-NEXT: entry: 3331 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3332 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3333 // CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 3334 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3335 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3336 // CHECK17-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 3337 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 3338 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3339 // CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3340 // CHECK17-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3341 // CHECK17-NEXT: ret void 3342 // 3343 // 3344 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 3345 // CHECK17-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 3346 // CHECK17-NEXT: entry: 3347 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3348 // CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 3349 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3350 // CHECK17-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3351 // CHECK17-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 3352 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3353 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 3354 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 3355 // CHECK17-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 3356 // CHECK17-NEXT: [[CONV1:%.*]] = fptosi float [[TMP2]] to i32 3357 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 123 3358 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) 3359 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 3360 // CHECK17-NEXT: ret void 3361 // 3362 // 3363 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 3364 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3365 // CHECK17-NEXT: entry: 3366 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3367 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3368 // CHECK17-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 3369 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3370 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3371 // CHECK17-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 3372 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 3373 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3374 // CHECK17-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3375 // CHECK17-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3376 // CHECK17-NEXT: ret void 3377 // 3378 // 3379 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3380 // CHECK17-SAME: () #[[ATTR3:[0-9]+]] { 3381 // CHECK17-NEXT: entry: 3382 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 3383 // CHECK17-NEXT: ret void 3384 // 3385 // 3386 // CHECK18-LABEL: define {{[^@]+}}@_Z21teams_template_structv 3387 // CHECK18-SAME: () #[[ATTR0:[0-9]+]] { 3388 // CHECK18-NEXT: entry: 3389 // CHECK18-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3390 // CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) 3391 // CHECK18-NEXT: ret i32 [[CALL]] 3392 // 3393 // 3394 // CHECK18-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 3395 // CHECK18-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 3396 // CHECK18-NEXT: entry: 3397 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3398 // CHECK18-NEXT: [[COMP:%.*]] = alloca i32, align 4 3399 // CHECK18-NEXT: [[COMP_CASTED:%.*]] = alloca i64, align 8 3400 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8 3401 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8 3402 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8 3403 // CHECK18-NEXT: [[COMP_CASTED3:%.*]] = alloca i64, align 8 3404 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 8 3405 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 8 3406 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 8 3407 // CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3408 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3409 // CHECK18-NEXT: store i32 1, i32* [[COMP]], align 4 3410 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3411 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_CASTED]] to i32* 3412 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 3413 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[COMP_CASTED]], align 8 3414 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 3415 // CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3416 // CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** 3417 // CHECK18-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 8 3418 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3419 // CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** 3420 // CHECK18-NEXT: store i32* [[A]], i32** [[TMP5]], align 8 3421 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3422 // CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8 3423 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3424 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 3425 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 3426 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3427 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 3428 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 3429 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3430 // CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 3431 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3432 // CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3433 // CHECK18-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 3434 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 3435 // CHECK18-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) 3436 // CHECK18-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 3437 // CHECK18-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3438 // CHECK18: omp_offload.failed: 3439 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]] 3440 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 3441 // CHECK18: omp_offload.cont: 3442 // CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 3443 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[COMP_CASTED3]] to i32* 3444 // CHECK18-NEXT: store i32 [[TMP17]], i32* [[CONV4]], align 4 3445 // CHECK18-NEXT: [[TMP18:%.*]] = load i64, i64* [[COMP_CASTED3]], align 8 3446 // CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3447 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3448 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** 3449 // CHECK18-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 8 3450 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3451 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 3452 // CHECK18-NEXT: store float* [[B]], float** [[TMP22]], align 8 3453 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 3454 // CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 3455 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 3456 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 3457 // CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP25]], align 8 3458 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 3459 // CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 3460 // CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 3461 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1 3462 // CHECK18-NEXT: store i8* null, i8** [[TMP28]], align 8 3463 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3464 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3465 // CHECK18-NEXT: [[B8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3466 // CHECK18-NEXT: [[TMP31:%.*]] = load float, float* [[B8]], align 4 3467 // CHECK18-NEXT: [[CONV9:%.*]] = fptosi float [[TMP31]] to i32 3468 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV9]], 123 3469 // CHECK18-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) 3470 // CHECK18-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 3471 // CHECK18-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 3472 // CHECK18: omp_offload.failed10: 3473 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i64 [[TMP18]]) #[[ATTR2]] 3474 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT11]] 3475 // CHECK18: omp_offload.cont11: 3476 // CHECK18-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 3477 // CHECK18-NEXT: ret i32 [[TMP34]] 3478 // 3479 // 3480 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 3481 // CHECK18-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 3482 // CHECK18-NEXT: entry: 3483 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3484 // CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 3485 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3486 // CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3487 // CHECK18-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 3488 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3489 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 3490 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 3491 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3492 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) 3493 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 3494 // CHECK18-NEXT: ret void 3495 // 3496 // 3497 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 3498 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3499 // CHECK18-NEXT: entry: 3500 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3501 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3502 // CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 3503 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3504 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3505 // CHECK18-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 3506 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 3507 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3508 // CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3509 // CHECK18-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3510 // CHECK18-NEXT: ret void 3511 // 3512 // 3513 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 3514 // CHECK18-SAME: (%struct.SS* [[THIS:%.*]], i64 [[COMP:%.*]]) #[[ATTR1]] { 3515 // CHECK18-NEXT: entry: 3516 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3517 // CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i64, align 8 3518 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3519 // CHECK18-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3520 // CHECK18-NEXT: store i64 [[COMP]], i64* [[COMP_ADDR]], align 8 3521 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3522 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[COMP_ADDR]] to i32* 3523 // CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 3524 // CHECK18-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 3525 // CHECK18-NEXT: [[CONV1:%.*]] = fptosi float [[TMP2]] to i32 3526 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 123 3527 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) 3528 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]]) 3529 // CHECK18-NEXT: ret void 3530 // 3531 // 3532 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 3533 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3534 // CHECK18-NEXT: entry: 3535 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3536 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3537 // CHECK18-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 8 3538 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3539 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3540 // CHECK18-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 8 3541 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 8 3542 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3543 // CHECK18-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3544 // CHECK18-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3545 // CHECK18-NEXT: ret void 3546 // 3547 // 3548 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3549 // CHECK18-SAME: () #[[ATTR3:[0-9]+]] { 3550 // CHECK18-NEXT: entry: 3551 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 3552 // CHECK18-NEXT: ret void 3553 // 3554 // 3555 // CHECK19-LABEL: define {{[^@]+}}@_Z21teams_template_structv 3556 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { 3557 // CHECK19-NEXT: entry: 3558 // CHECK19-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3559 // CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) 3560 // CHECK19-NEXT: ret i32 [[CALL]] 3561 // 3562 // 3563 // CHECK19-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 3564 // CHECK19-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 3565 // CHECK19-NEXT: entry: 3566 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 3567 // CHECK19-NEXT: [[COMP:%.*]] = alloca i32, align 4 3568 // CHECK19-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 3569 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 3570 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 3571 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 3572 // CHECK19-NEXT: [[COMP_CASTED3:%.*]] = alloca i32, align 4 3573 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 4 3574 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 4 3575 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 4 3576 // CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 3577 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 3578 // CHECK19-NEXT: store i32 1, i32* [[COMP]], align 4 3579 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3580 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 3581 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 3582 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 3583 // CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3584 // CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** 3585 // CHECK19-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 4 3586 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3587 // CHECK19-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** 3588 // CHECK19-NEXT: store i32* [[A]], i32** [[TMP5]], align 4 3589 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3590 // CHECK19-NEXT: store i8* null, i8** [[TMP6]], align 4 3591 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3592 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3593 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3594 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3595 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3596 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3597 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3598 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 3599 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3600 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3601 // CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 3602 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 3603 // CHECK19-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) 3604 // CHECK19-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 3605 // CHECK19-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3606 // CHECK19: omp_offload.failed: 3607 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 3608 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 3609 // CHECK19: omp_offload.cont: 3610 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 3611 // CHECK19-NEXT: store i32 [[TMP17]], i32* [[COMP_CASTED3]], align 4 3612 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[COMP_CASTED3]], align 4 3613 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3614 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3615 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** 3616 // CHECK19-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 4 3617 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3618 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 3619 // CHECK19-NEXT: store float* [[B]], float** [[TMP22]], align 4 3620 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 3621 // CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 3622 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 3623 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 3624 // CHECK19-NEXT: store i32 [[TMP18]], i32* [[TMP25]], align 4 3625 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 3626 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3627 // CHECK19-NEXT: store i32 [[TMP18]], i32* [[TMP27]], align 4 3628 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 3629 // CHECK19-NEXT: store i8* null, i8** [[TMP28]], align 4 3630 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3631 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3632 // CHECK19-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3633 // CHECK19-NEXT: [[TMP31:%.*]] = load float, float* [[B7]], align 4 3634 // CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP31]] to i32 3635 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 3636 // CHECK19-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) 3637 // CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 3638 // CHECK19-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 3639 // CHECK19: omp_offload.failed8: 3640 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i32 [[TMP18]]) #[[ATTR2]] 3641 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT9]] 3642 // CHECK19: omp_offload.cont9: 3643 // CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 3644 // CHECK19-NEXT: ret i32 [[TMP34]] 3645 // 3646 // 3647 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 3648 // CHECK19-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 3649 // CHECK19-NEXT: entry: 3650 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 3651 // CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 3652 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3653 // CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 3654 // CHECK19-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 3655 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 3656 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 3657 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3658 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) 3659 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 3660 // CHECK19-NEXT: ret void 3661 // 3662 // 3663 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 3664 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3665 // CHECK19-NEXT: entry: 3666 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3667 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3668 // CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 3669 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3670 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3671 // CHECK19-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 3672 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 3673 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3674 // CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3675 // CHECK19-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3676 // CHECK19-NEXT: ret void 3677 // 3678 // 3679 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 3680 // CHECK19-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 3681 // CHECK19-NEXT: entry: 3682 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 3683 // CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 3684 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3685 // CHECK19-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 3686 // CHECK19-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 3687 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 3688 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 3689 // CHECK19-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 3690 // CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP2]] to i32 3691 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 3692 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) 3693 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 3694 // CHECK19-NEXT: ret void 3695 // 3696 // 3697 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 3698 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3699 // CHECK19-NEXT: entry: 3700 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3701 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3702 // CHECK19-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 3703 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3704 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3705 // CHECK19-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 3706 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 3707 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3708 // CHECK19-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3709 // CHECK19-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3710 // CHECK19-NEXT: ret void 3711 // 3712 // 3713 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3714 // CHECK19-SAME: () #[[ATTR3:[0-9]+]] { 3715 // CHECK19-NEXT: entry: 3716 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 3717 // CHECK19-NEXT: ret void 3718 // 3719 // 3720 // CHECK20-LABEL: define {{[^@]+}}@_Z21teams_template_structv 3721 // CHECK20-SAME: () #[[ATTR0:[0-9]+]] { 3722 // CHECK20-NEXT: entry: 3723 // CHECK20-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3724 // CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) 3725 // CHECK20-NEXT: ret i32 [[CALL]] 3726 // 3727 // 3728 // CHECK20-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 3729 // CHECK20-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 3730 // CHECK20-NEXT: entry: 3731 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 3732 // CHECK20-NEXT: [[COMP:%.*]] = alloca i32, align 4 3733 // CHECK20-NEXT: [[COMP_CASTED:%.*]] = alloca i32, align 4 3734 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4 3735 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4 3736 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4 3737 // CHECK20-NEXT: [[COMP_CASTED3:%.*]] = alloca i32, align 4 3738 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 4 3739 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 4 3740 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 4 3741 // CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 3742 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 3743 // CHECK20-NEXT: store i32 1, i32* [[COMP]], align 4 3744 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3745 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[COMP_CASTED]], align 4 3746 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP_CASTED]], align 4 3747 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 3748 // CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3749 // CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to %struct.SS** 3750 // CHECK20-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP3]], align 4 3751 // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3752 // CHECK20-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32** 3753 // CHECK20-NEXT: store i32* [[A]], i32** [[TMP5]], align 4 3754 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3755 // CHECK20-NEXT: store i8* null, i8** [[TMP6]], align 4 3756 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3757 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3758 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3759 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3760 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3761 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3762 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3763 // CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 3764 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3765 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3766 // CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 3767 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[A2]], align 4 3768 // CHECK20-NEXT: [[TMP15:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161.region_id, i32 2, i8** [[TMP12]], i8** [[TMP13]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP14]], i32 123) 3769 // CHECK20-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 3770 // CHECK20-NEXT: br i1 [[TMP16]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3771 // CHECK20: omp_offload.failed: 3772 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161(%struct.SS* [[THIS1]], i32 [[TMP1]]) #[[ATTR2:[0-9]+]] 3773 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 3774 // CHECK20: omp_offload.cont: 3775 // CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[COMP]], align 4 3776 // CHECK20-NEXT: store i32 [[TMP17]], i32* [[COMP_CASTED3]], align 4 3777 // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[COMP_CASTED3]], align 4 3778 // CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3779 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3780 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.SS** 3781 // CHECK20-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP20]], align 4 3782 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3783 // CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to float** 3784 // CHECK20-NEXT: store float* [[B]], float** [[TMP22]], align 4 3785 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0 3786 // CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 3787 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 3788 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 3789 // CHECK20-NEXT: store i32 [[TMP18]], i32* [[TMP25]], align 4 3790 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 3791 // CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3792 // CHECK20-NEXT: store i32 [[TMP18]], i32* [[TMP27]], align 4 3793 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1 3794 // CHECK20-NEXT: store i8* null, i8** [[TMP28]], align 4 3795 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3796 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3797 // CHECK20-NEXT: [[B7:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3798 // CHECK20-NEXT: [[TMP31:%.*]] = load float, float* [[B7]], align 4 3799 // CHECK20-NEXT: [[CONV:%.*]] = fptosi float [[TMP31]] to i32 3800 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 3801 // CHECK20-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169.region_id, i32 2, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 456, i32 [[ADD]]) 3802 // CHECK20-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 3803 // CHECK20-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 3804 // CHECK20: omp_offload.failed8: 3805 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169(%struct.SS* [[THIS1]], i32 [[TMP18]]) #[[ATTR2]] 3806 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT9]] 3807 // CHECK20: omp_offload.cont9: 3808 // CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[COMP]], align 4 3809 // CHECK20-NEXT: ret i32 [[TMP34]] 3810 // 3811 // 3812 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l161 3813 // CHECK20-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1:[0-9]+]] { 3814 // CHECK20-NEXT: entry: 3815 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 3816 // CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 3817 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3818 // CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 3819 // CHECK20-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 3820 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 3821 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 0 3822 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3823 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 123) 3824 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 3825 // CHECK20-NEXT: ret void 3826 // 3827 // 3828 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 3829 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3830 // CHECK20-NEXT: entry: 3831 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3832 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3833 // CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 3834 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3835 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3836 // CHECK20-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 3837 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 3838 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3839 // CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3840 // CHECK20-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3841 // CHECK20-NEXT: ret void 3842 // 3843 // 3844 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l169 3845 // CHECK20-SAME: (%struct.SS* [[THIS:%.*]], i32 [[COMP:%.*]]) #[[ATTR1]] { 3846 // CHECK20-NEXT: entry: 3847 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 3848 // CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32, align 4 3849 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3850 // CHECK20-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 3851 // CHECK20-NEXT: store i32 [[COMP]], i32* [[COMP_ADDR]], align 4 3852 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 3853 // CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP1]], i32 0, i32 1 3854 // CHECK20-NEXT: [[TMP2:%.*]] = load float, float* [[B]], align 4 3855 // CHECK20-NEXT: [[CONV:%.*]] = fptosi float [[TMP2]] to i32 3856 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 123 3857 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 456, i32 [[ADD]]) 3858 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[COMP_ADDR]]) 3859 // CHECK20-NEXT: ret void 3860 // 3861 // 3862 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 3863 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[COMP:%.*]]) #[[ATTR1]] { 3864 // CHECK20-NEXT: entry: 3865 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3866 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3867 // CHECK20-NEXT: [[COMP_ADDR:%.*]] = alloca i32*, align 4 3868 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3869 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3870 // CHECK20-NEXT: store i32* [[COMP]], i32** [[COMP_ADDR]], align 4 3871 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[COMP_ADDR]], align 4 3872 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3873 // CHECK20-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 3874 // CHECK20-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 3875 // CHECK20-NEXT: ret void 3876 // 3877 // 3878 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3879 // CHECK20-SAME: () #[[ATTR3:[0-9]+]] { 3880 // CHECK20-NEXT: entry: 3881 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 3882 // CHECK20-NEXT: ret void 3883 // 3884 // 3885 // CHECK21-LABEL: define {{[^@]+}}@_Z21teams_template_structv 3886 // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { 3887 // CHECK21-NEXT: entry: 3888 // CHECK21-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3889 // CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) 3890 // CHECK21-NEXT: ret i32 [[CALL]] 3891 // 3892 // 3893 // CHECK21-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 3894 // CHECK21-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 3895 // CHECK21-NEXT: entry: 3896 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3897 // CHECK21-NEXT: [[COMP:%.*]] = alloca i32, align 4 3898 // CHECK21-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3899 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3900 // CHECK21-NEXT: store i32 1, i32* [[COMP]], align 4 3901 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3902 // CHECK21-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 3903 // CHECK21-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 3904 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 3905 // CHECK21-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 3906 // CHECK21-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 3907 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 3908 // CHECK21-NEXT: ret i32 [[TMP2]] 3909 // 3910 // 3911 // CHECK22-LABEL: define {{[^@]+}}@_Z21teams_template_structv 3912 // CHECK22-SAME: () #[[ATTR0:[0-9]+]] { 3913 // CHECK22-NEXT: entry: 3914 // CHECK22-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3915 // CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) 3916 // CHECK22-NEXT: ret i32 [[CALL]] 3917 // 3918 // 3919 // CHECK22-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 3920 // CHECK22-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 3921 // CHECK22-NEXT: entry: 3922 // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3923 // CHECK22-NEXT: [[COMP:%.*]] = alloca i32, align 4 3924 // CHECK22-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3925 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3926 // CHECK22-NEXT: store i32 1, i32* [[COMP]], align 4 3927 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3928 // CHECK22-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 3929 // CHECK22-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 3930 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 3931 // CHECK22-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 3932 // CHECK22-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 3933 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 3934 // CHECK22-NEXT: ret i32 [[TMP2]] 3935 // 3936 // 3937 // CHECK23-LABEL: define {{[^@]+}}@_Z21teams_template_structv 3938 // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { 3939 // CHECK23-NEXT: entry: 3940 // CHECK23-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3941 // CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) 3942 // CHECK23-NEXT: ret i32 [[CALL]] 3943 // 3944 // 3945 // CHECK23-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 3946 // CHECK23-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 3947 // CHECK23-NEXT: entry: 3948 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 3949 // CHECK23-NEXT: [[COMP:%.*]] = alloca i32, align 4 3950 // CHECK23-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 3951 // CHECK23-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 3952 // CHECK23-NEXT: store i32 1, i32* [[COMP]], align 4 3953 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3954 // CHECK23-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 3955 // CHECK23-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 3956 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 3957 // CHECK23-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 3958 // CHECK23-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 3959 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 3960 // CHECK23-NEXT: ret i32 [[TMP2]] 3961 // 3962 // 3963 // CHECK24-LABEL: define {{[^@]+}}@_Z21teams_template_structv 3964 // CHECK24-SAME: () #[[ATTR0:[0-9]+]] { 3965 // CHECK24-NEXT: entry: 3966 // CHECK24-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 3967 // CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* nonnull dereferenceable(8) [[V]]) 3968 // CHECK24-NEXT: ret i32 [[CALL]] 3969 // 3970 // 3971 // CHECK24-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 3972 // CHECK24-SAME: (%struct.SS* nonnull dereferenceable(8) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 3973 // CHECK24-NEXT: entry: 3974 // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 3975 // CHECK24-NEXT: [[COMP:%.*]] = alloca i32, align 4 3976 // CHECK24-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 3977 // CHECK24-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 3978 // CHECK24-NEXT: store i32 1, i32* [[COMP]], align 4 3979 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[COMP]], align 4 3980 // CHECK24-NEXT: [[INC:%.*]] = add nsw i32 [[TMP0]], 1 3981 // CHECK24-NEXT: store i32 [[INC]], i32* [[COMP]], align 4 3982 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[COMP]], align 4 3983 // CHECK24-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP1]], 1 3984 // CHECK24-NEXT: store i32 [[INC2]], i32* [[COMP]], align 4 3985 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[COMP]], align 4 3986 // CHECK24-NEXT: ret i32 [[TMP2]] 3987 // 3988 // 3989 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 3990 // CHECK25-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { 3991 // CHECK25-NEXT: entry: 3992 // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 3993 // CHECK25-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 3994 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* 3995 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 3996 // CHECK25-NEXT: ret void 3997 // 3998 // 3999 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. 4000 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4001 // CHECK25-NEXT: entry: 4002 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4003 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4004 // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 4005 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4006 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4007 // CHECK25-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 4008 // CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 4009 // CHECK25-NEXT: store i32 0, i32* [[TMP0]], align 4 4010 // CHECK25-NEXT: ret void 4011 // 4012 // 4013 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 4014 // CHECK25-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { 4015 // CHECK25-NEXT: entry: 4016 // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 4017 // CHECK25-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 4018 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) 4019 // CHECK25-NEXT: ret void 4020 // 4021 // 4022 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 4023 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { 4024 // CHECK25-NEXT: entry: 4025 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4026 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4027 // CHECK25-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 4028 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4029 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4030 // CHECK25-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 4031 // CHECK25-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 4032 // CHECK25-NEXT: store i8** null, i8*** [[TMP0]], align 8 4033 // CHECK25-NEXT: ret void 4034 // 4035 // 4036 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 4037 // CHECK26-SAME: (i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { 4038 // CHECK26-NEXT: entry: 4039 // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 4040 // CHECK26-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 4041 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* 4042 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]]) 4043 // CHECK26-NEXT: ret void 4044 // 4045 // 4046 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. 4047 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4048 // CHECK26-NEXT: entry: 4049 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4050 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4051 // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 4052 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4053 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4054 // CHECK26-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 4055 // CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 4056 // CHECK26-NEXT: store i32 0, i32* [[TMP0]], align 4 4057 // CHECK26-NEXT: ret void 4058 // 4059 // 4060 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 4061 // CHECK26-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { 4062 // CHECK26-NEXT: entry: 4063 // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 4064 // CHECK26-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 4065 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) 4066 // CHECK26-NEXT: ret void 4067 // 4068 // 4069 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 4070 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { 4071 // CHECK26-NEXT: entry: 4072 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4073 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4074 // CHECK26-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 4075 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4076 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4077 // CHECK26-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 4078 // CHECK26-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 4079 // CHECK26-NEXT: store i8** null, i8*** [[TMP0]], align 8 4080 // CHECK26-NEXT: ret void 4081 // 4082 // 4083 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 4084 // CHECK27-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { 4085 // CHECK27-NEXT: entry: 4086 // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4087 // CHECK27-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4088 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) 4089 // CHECK27-NEXT: ret void 4090 // 4091 // 4092 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. 4093 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4094 // CHECK27-NEXT: entry: 4095 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4096 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4097 // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 4098 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4099 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4100 // CHECK27-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 4101 // CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 4102 // CHECK27-NEXT: store i32 0, i32* [[TMP0]], align 4 4103 // CHECK27-NEXT: ret void 4104 // 4105 // 4106 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 4107 // CHECK27-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { 4108 // CHECK27-NEXT: entry: 4109 // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 4110 // CHECK27-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 4111 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) 4112 // CHECK27-NEXT: ret void 4113 // 4114 // 4115 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 4116 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4117 // CHECK27-NEXT: entry: 4118 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4119 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4120 // CHECK27-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 4121 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4122 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4123 // CHECK27-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 4124 // CHECK27-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 4125 // CHECK27-NEXT: store i8** null, i8*** [[TMP0]], align 4 4126 // CHECK27-NEXT: ret void 4127 // 4128 // 4129 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l216 4130 // CHECK28-SAME: (i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { 4131 // CHECK28-NEXT: entry: 4132 // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4133 // CHECK28-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4134 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) 4135 // CHECK28-NEXT: ret void 4136 // 4137 // 4138 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. 4139 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4140 // CHECK28-NEXT: entry: 4141 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4142 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4143 // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 4144 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4145 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4146 // CHECK28-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 4147 // CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 4148 // CHECK28-NEXT: store i32 0, i32* [[TMP0]], align 4 4149 // CHECK28-NEXT: ret void 4150 // 4151 // 4152 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l209 4153 // CHECK28-SAME: (i8** [[ARGC:%.*]]) #[[ATTR0]] { 4154 // CHECK28-NEXT: entry: 4155 // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 4156 // CHECK28-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 4157 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) 4158 // CHECK28-NEXT: ret void 4159 // 4160 // 4161 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 4162 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4163 // CHECK28-NEXT: entry: 4164 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4165 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4166 // CHECK28-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 4167 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4168 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4169 // CHECK28-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 4170 // CHECK28-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 4171 // CHECK28-NEXT: store i8** null, i8*** [[TMP0]], align 4 4172 // CHECK28-NEXT: ret void 4173 // 4174 // 4175 // CHECK29-LABEL: define {{[^@]+}}@main 4176 // CHECK29-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 4177 // CHECK29-NEXT: entry: 4178 // CHECK29-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4179 // CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4180 // CHECK29-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 4181 // CHECK29-NEXT: store i32 0, i32* [[RETVAL]], align 4 4182 // CHECK29-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4183 // CHECK29-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 4184 // CHECK29-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 4185 // CHECK29-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 4186 // CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) 4187 // CHECK29-NEXT: ret i32 [[CALL]] 4188 // 4189 // 4190 // CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ 4191 // CHECK29-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { 4192 // CHECK29-NEXT: entry: 4193 // CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 4194 // CHECK29-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 4195 // CHECK29-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 4196 // CHECK29-NEXT: ret i32 0 4197 // 4198 // 4199 // CHECK30-LABEL: define {{[^@]+}}@main 4200 // CHECK30-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 4201 // CHECK30-NEXT: entry: 4202 // CHECK30-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4203 // CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4204 // CHECK30-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 4205 // CHECK30-NEXT: store i32 0, i32* [[RETVAL]], align 4 4206 // CHECK30-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4207 // CHECK30-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 4208 // CHECK30-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 4209 // CHECK30-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 4210 // CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) 4211 // CHECK30-NEXT: ret i32 [[CALL]] 4212 // 4213 // 4214 // CHECK30-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ 4215 // CHECK30-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { 4216 // CHECK30-NEXT: entry: 4217 // CHECK30-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 4218 // CHECK30-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 4219 // CHECK30-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 4220 // CHECK30-NEXT: ret i32 0 4221 // 4222 // 4223 // CHECK31-LABEL: define {{[^@]+}}@main 4224 // CHECK31-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 4225 // CHECK31-NEXT: entry: 4226 // CHECK31-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4227 // CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4228 // CHECK31-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 4229 // CHECK31-NEXT: store i32 0, i32* [[RETVAL]], align 4 4230 // CHECK31-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4231 // CHECK31-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 4232 // CHECK31-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 4233 // CHECK31-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 4234 // CHECK31-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) 4235 // CHECK31-NEXT: ret i32 [[CALL]] 4236 // 4237 // 4238 // CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ 4239 // CHECK31-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { 4240 // CHECK31-NEXT: entry: 4241 // CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 4242 // CHECK31-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 4243 // CHECK31-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 4244 // CHECK31-NEXT: ret i32 0 4245 // 4246 // 4247 // CHECK32-LABEL: define {{[^@]+}}@main 4248 // CHECK32-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 4249 // CHECK32-NEXT: entry: 4250 // CHECK32-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4251 // CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4252 // CHECK32-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 4253 // CHECK32-NEXT: store i32 0, i32* [[RETVAL]], align 4 4254 // CHECK32-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4255 // CHECK32-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 4256 // CHECK32-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 4257 // CHECK32-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 4258 // CHECK32-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) 4259 // CHECK32-NEXT: ret i32 [[CALL]] 4260 // 4261 // 4262 // CHECK32-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ 4263 // CHECK32-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { 4264 // CHECK32-NEXT: entry: 4265 // CHECK32-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 4266 // CHECK32-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 4267 // CHECK32-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 4268 // CHECK32-NEXT: ret i32 0 4269 // 4270 // 4271 // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 4272 // CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { 4273 // CHECK33-NEXT: entry: 4274 // CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4275 // CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4276 // CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 4277 // CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 4278 // CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4279 // CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4280 // CHECK33-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 4281 // CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4282 // CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4283 // CHECK33-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* 4284 // CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4285 // CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 4286 // CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4287 // CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]]) 4288 // CHECK33-NEXT: ret void 4289 // 4290 // 4291 // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined. 4292 // CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4293 // CHECK33-NEXT: entry: 4294 // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4295 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4296 // CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 4297 // CHECK33-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4298 // CHECK33-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4299 // CHECK33-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 4300 // CHECK33-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 4301 // CHECK33-NEXT: store i32 0, i32* [[TMP0]], align 4 4302 // CHECK33-NEXT: ret void 4303 // 4304 // 4305 // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 4306 // CHECK33-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { 4307 // CHECK33-NEXT: entry: 4308 // CHECK33-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4309 // CHECK33-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4310 // CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 4311 // CHECK33-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4312 // CHECK33-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4313 // CHECK33-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4314 // CHECK33-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 4315 // CHECK33-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4316 // CHECK33-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4317 // CHECK33-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4318 // CHECK33-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 4319 // CHECK33-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4320 // CHECK33-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) 4321 // CHECK33-NEXT: ret void 4322 // 4323 // 4324 // CHECK33-LABEL: define {{[^@]+}}@.omp_outlined..1 4325 // CHECK33-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { 4326 // CHECK33-NEXT: entry: 4327 // CHECK33-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4328 // CHECK33-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4329 // CHECK33-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 4330 // CHECK33-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4331 // CHECK33-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4332 // CHECK33-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 4333 // CHECK33-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 4334 // CHECK33-NEXT: store i8** null, i8*** [[TMP0]], align 8 4335 // CHECK33-NEXT: ret void 4336 // 4337 // 4338 // CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 4339 // CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { 4340 // CHECK34-NEXT: entry: 4341 // CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4342 // CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4343 // CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 4344 // CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 4345 // CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4346 // CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4347 // CHECK34-NEXT: store i64 [[ARGC]], i64* [[ARGC_ADDR]], align 8 4348 // CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4349 // CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4350 // CHECK34-NEXT: [[CONV2:%.*]] = bitcast i64* [[ARGC_ADDR]] to i32* 4351 // CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4352 // CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 4353 // CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4354 // CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV2]]) 4355 // CHECK34-NEXT: ret void 4356 // 4357 // 4358 // CHECK34-LABEL: define {{[^@]+}}@.omp_outlined. 4359 // CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4360 // CHECK34-NEXT: entry: 4361 // CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4362 // CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4363 // CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 8 4364 // CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4365 // CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4366 // CHECK34-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 8 4367 // CHECK34-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 8 4368 // CHECK34-NEXT: store i32 0, i32* [[TMP0]], align 4 4369 // CHECK34-NEXT: ret void 4370 // 4371 // 4372 // CHECK34-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 4373 // CHECK34-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { 4374 // CHECK34-NEXT: entry: 4375 // CHECK34-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4376 // CHECK34-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4377 // CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 4378 // CHECK34-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4379 // CHECK34-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4380 // CHECK34-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4381 // CHECK34-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 4382 // CHECK34-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4383 // CHECK34-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4384 // CHECK34-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4385 // CHECK34-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 4386 // CHECK34-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4387 // CHECK34-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) 4388 // CHECK34-NEXT: ret void 4389 // 4390 // 4391 // CHECK34-LABEL: define {{[^@]+}}@.omp_outlined..1 4392 // CHECK34-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 8 dereferenceable(8) [[ARGC:%.*]]) #[[ATTR0]] { 4393 // CHECK34-NEXT: entry: 4394 // CHECK34-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4395 // CHECK34-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4396 // CHECK34-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 8 4397 // CHECK34-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4398 // CHECK34-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4399 // CHECK34-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 8 4400 // CHECK34-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 8 4401 // CHECK34-NEXT: store i8** null, i8*** [[TMP0]], align 8 4402 // CHECK34-NEXT: ret void 4403 // 4404 // 4405 // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 4406 // CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { 4407 // CHECK35-NEXT: entry: 4408 // CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4409 // CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4410 // CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4411 // CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 4412 // CHECK35-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4413 // CHECK35-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4414 // CHECK35-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4415 // CHECK35-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4416 // CHECK35-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 4417 // CHECK35-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4418 // CHECK35-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) 4419 // CHECK35-NEXT: ret void 4420 // 4421 // 4422 // CHECK35-LABEL: define {{[^@]+}}@.omp_outlined. 4423 // CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4424 // CHECK35-NEXT: entry: 4425 // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4426 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4427 // CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 4428 // CHECK35-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4429 // CHECK35-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4430 // CHECK35-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 4431 // CHECK35-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 4432 // CHECK35-NEXT: store i32 0, i32* [[TMP0]], align 4 4433 // CHECK35-NEXT: ret void 4434 // 4435 // 4436 // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 4437 // CHECK35-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { 4438 // CHECK35-NEXT: entry: 4439 // CHECK35-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4440 // CHECK35-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4441 // CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 4442 // CHECK35-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4443 // CHECK35-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4444 // CHECK35-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4445 // CHECK35-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 4446 // CHECK35-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4447 // CHECK35-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 4448 // CHECK35-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4449 // CHECK35-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) 4450 // CHECK35-NEXT: ret void 4451 // 4452 // 4453 // CHECK35-LABEL: define {{[^@]+}}@.omp_outlined..1 4454 // CHECK35-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4455 // CHECK35-NEXT: entry: 4456 // CHECK35-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4457 // CHECK35-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4458 // CHECK35-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 4459 // CHECK35-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4460 // CHECK35-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4461 // CHECK35-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 4462 // CHECK35-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 4463 // CHECK35-NEXT: store i8** null, i8*** [[TMP0]], align 4 4464 // CHECK35-NEXT: ret void 4465 // 4466 // 4467 // CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l265 4468 // CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[ARGC:%.*]]) #[[ATTR0:[0-9]+]] { 4469 // CHECK36-NEXT: entry: 4470 // CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4471 // CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4472 // CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4473 // CHECK36-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 4474 // CHECK36-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4475 // CHECK36-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4476 // CHECK36-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4477 // CHECK36-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4478 // CHECK36-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 4479 // CHECK36-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4480 // CHECK36-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[ARGC_ADDR]]) 4481 // CHECK36-NEXT: ret void 4482 // 4483 // 4484 // CHECK36-LABEL: define {{[^@]+}}@.omp_outlined. 4485 // CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4486 // CHECK36-NEXT: entry: 4487 // CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4488 // CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4489 // CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i32*, align 4 4490 // CHECK36-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4491 // CHECK36-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4492 // CHECK36-NEXT: store i32* [[ARGC]], i32** [[ARGC_ADDR]], align 4 4493 // CHECK36-NEXT: [[TMP0:%.*]] = load i32*, i32** [[ARGC_ADDR]], align 4 4494 // CHECK36-NEXT: store i32 0, i32* [[TMP0]], align 4 4495 // CHECK36-NEXT: ret void 4496 // 4497 // 4498 // CHECK36-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPPcEiT__l254 4499 // CHECK36-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i8** [[ARGC:%.*]]) #[[ATTR0]] { 4500 // CHECK36-NEXT: entry: 4501 // CHECK36-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4502 // CHECK36-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4503 // CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 4504 // CHECK36-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4505 // CHECK36-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4506 // CHECK36-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4507 // CHECK36-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 4508 // CHECK36-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4509 // CHECK36-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 4510 // CHECK36-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4511 // CHECK36-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i8***)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i8*** [[ARGC_ADDR]]) 4512 // CHECK36-NEXT: ret void 4513 // 4514 // 4515 // CHECK36-LABEL: define {{[^@]+}}@.omp_outlined..1 4516 // CHECK36-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i8*** nonnull align 4 dereferenceable(4) [[ARGC:%.*]]) #[[ATTR0]] { 4517 // CHECK36-NEXT: entry: 4518 // CHECK36-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4519 // CHECK36-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4520 // CHECK36-NEXT: [[ARGC_ADDR:%.*]] = alloca i8***, align 4 4521 // CHECK36-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4522 // CHECK36-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4523 // CHECK36-NEXT: store i8*** [[ARGC]], i8**** [[ARGC_ADDR]], align 4 4524 // CHECK36-NEXT: [[TMP0:%.*]] = load i8***, i8**** [[ARGC_ADDR]], align 4 4525 // CHECK36-NEXT: store i8** null, i8*** [[TMP0]], align 4 4526 // CHECK36-NEXT: ret void 4527 // 4528 // 4529 // CHECK37-LABEL: define {{[^@]+}}@main 4530 // CHECK37-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 4531 // CHECK37-NEXT: entry: 4532 // CHECK37-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4533 // CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4534 // CHECK37-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 4535 // CHECK37-NEXT: [[A:%.*]] = alloca i32, align 4 4536 // CHECK37-NEXT: [[B:%.*]] = alloca i32, align 4 4537 // CHECK37-NEXT: store i32 0, i32* [[RETVAL]], align 4 4538 // CHECK37-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4539 // CHECK37-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 4540 // CHECK37-NEXT: store i32 20, i32* [[A]], align 4 4541 // CHECK37-NEXT: store i32 5, i32* [[B]], align 4 4542 // CHECK37-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 4543 // CHECK37-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 4544 // CHECK37-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) 4545 // CHECK37-NEXT: ret i32 [[CALL]] 4546 // 4547 // 4548 // CHECK37-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ 4549 // CHECK37-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { 4550 // CHECK37-NEXT: entry: 4551 // CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 4552 // CHECK37-NEXT: [[A:%.*]] = alloca i32, align 4 4553 // CHECK37-NEXT: [[B:%.*]] = alloca i32, align 4 4554 // CHECK37-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 4555 // CHECK37-NEXT: store i32 10, i32* [[A]], align 4 4556 // CHECK37-NEXT: store i32 5, i32* [[B]], align 4 4557 // CHECK37-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 4558 // CHECK37-NEXT: ret i32 0 4559 // 4560 // 4561 // CHECK38-LABEL: define {{[^@]+}}@main 4562 // CHECK38-SAME: (i32 signext [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 4563 // CHECK38-NEXT: entry: 4564 // CHECK38-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4565 // CHECK38-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4566 // CHECK38-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 4567 // CHECK38-NEXT: [[A:%.*]] = alloca i32, align 4 4568 // CHECK38-NEXT: [[B:%.*]] = alloca i32, align 4 4569 // CHECK38-NEXT: store i32 0, i32* [[RETVAL]], align 4 4570 // CHECK38-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4571 // CHECK38-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 4572 // CHECK38-NEXT: store i32 20, i32* [[A]], align 4 4573 // CHECK38-NEXT: store i32 5, i32* [[B]], align 4 4574 // CHECK38-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 4575 // CHECK38-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 8 4576 // CHECK38-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) 4577 // CHECK38-NEXT: ret i32 [[CALL]] 4578 // 4579 // 4580 // CHECK38-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ 4581 // CHECK38-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { 4582 // CHECK38-NEXT: entry: 4583 // CHECK38-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 8 4584 // CHECK38-NEXT: [[A:%.*]] = alloca i32, align 4 4585 // CHECK38-NEXT: [[B:%.*]] = alloca i32, align 4 4586 // CHECK38-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 8 4587 // CHECK38-NEXT: store i32 10, i32* [[A]], align 4 4588 // CHECK38-NEXT: store i32 5, i32* [[B]], align 4 4589 // CHECK38-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 8 4590 // CHECK38-NEXT: ret i32 0 4591 // 4592 // 4593 // CHECK39-LABEL: define {{[^@]+}}@main 4594 // CHECK39-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 4595 // CHECK39-NEXT: entry: 4596 // CHECK39-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4597 // CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4598 // CHECK39-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 4599 // CHECK39-NEXT: [[A:%.*]] = alloca i32, align 4 4600 // CHECK39-NEXT: [[B:%.*]] = alloca i32, align 4 4601 // CHECK39-NEXT: store i32 0, i32* [[RETVAL]], align 4 4602 // CHECK39-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4603 // CHECK39-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 4604 // CHECK39-NEXT: store i32 20, i32* [[A]], align 4 4605 // CHECK39-NEXT: store i32 5, i32* [[B]], align 4 4606 // CHECK39-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 4607 // CHECK39-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 4608 // CHECK39-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) 4609 // CHECK39-NEXT: ret i32 [[CALL]] 4610 // 4611 // 4612 // CHECK39-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ 4613 // CHECK39-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { 4614 // CHECK39-NEXT: entry: 4615 // CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 4616 // CHECK39-NEXT: [[A:%.*]] = alloca i32, align 4 4617 // CHECK39-NEXT: [[B:%.*]] = alloca i32, align 4 4618 // CHECK39-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 4619 // CHECK39-NEXT: store i32 10, i32* [[A]], align 4 4620 // CHECK39-NEXT: store i32 5, i32* [[B]], align 4 4621 // CHECK39-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 4622 // CHECK39-NEXT: ret i32 0 4623 // 4624 // 4625 // CHECK40-LABEL: define {{[^@]+}}@main 4626 // CHECK40-SAME: (i32 [[ARGC:%.*]], i8** [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 4627 // CHECK40-NEXT: entry: 4628 // CHECK40-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4629 // CHECK40-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 4630 // CHECK40-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 4631 // CHECK40-NEXT: [[A:%.*]] = alloca i32, align 4 4632 // CHECK40-NEXT: [[B:%.*]] = alloca i32, align 4 4633 // CHECK40-NEXT: store i32 0, i32* [[RETVAL]], align 4 4634 // CHECK40-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 4635 // CHECK40-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 4636 // CHECK40-NEXT: store i32 20, i32* [[A]], align 4 4637 // CHECK40-NEXT: store i32 5, i32* [[B]], align 4 4638 // CHECK40-NEXT: store i32 0, i32* [[ARGC_ADDR]], align 4 4639 // CHECK40-NEXT: [[TMP0:%.*]] = load i8**, i8*** [[ARGV_ADDR]], align 4 4640 // CHECK40-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIPPcEiT_(i8** [[TMP0]]) 4641 // CHECK40-NEXT: ret i32 [[CALL]] 4642 // 4643 // 4644 // CHECK40-LABEL: define {{[^@]+}}@_Z5tmainIPPcEiT_ 4645 // CHECK40-SAME: (i8** [[ARGC:%.*]]) #[[ATTR1:[0-9]+]] comdat { 4646 // CHECK40-NEXT: entry: 4647 // CHECK40-NEXT: [[ARGC_ADDR:%.*]] = alloca i8**, align 4 4648 // CHECK40-NEXT: [[A:%.*]] = alloca i32, align 4 4649 // CHECK40-NEXT: [[B:%.*]] = alloca i32, align 4 4650 // CHECK40-NEXT: store i8** [[ARGC]], i8*** [[ARGC_ADDR]], align 4 4651 // CHECK40-NEXT: store i32 10, i32* [[A]], align 4 4652 // CHECK40-NEXT: store i32 5, i32* [[B]], align 4 4653 // CHECK40-NEXT: store i8** null, i8*** [[ARGC_ADDR]], align 4 4654 // CHECK40-NEXT: ret i32 0 4655 // 4656 // 4657 // CHECK41-LABEL: define {{[^@]+}}@_Z3foov 4658 // CHECK41-SAME: () #[[ATTR0:[0-9]+]] { 4659 // CHECK41-NEXT: entry: 4660 // CHECK41-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4661 // CHECK41-NEXT: ret void 4662 // 4663 // 4664 // CHECK41-LABEL: define {{[^@]+}}@.omp_outlined. 4665 // CHECK41-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 4666 // CHECK41-NEXT: entry: 4667 // CHECK41-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4668 // CHECK41-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4669 // CHECK41-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4670 // CHECK41-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4671 // CHECK41-NEXT: ret void 4672 // 4673 // 4674 // CHECK42-LABEL: define {{[^@]+}}@_Z3foov 4675 // CHECK42-SAME: () #[[ATTR0:[0-9]+]] { 4676 // CHECK42-NEXT: entry: 4677 // CHECK42-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4678 // CHECK42-NEXT: ret void 4679 // 4680 // 4681 // CHECK42-LABEL: define {{[^@]+}}@.omp_outlined. 4682 // CHECK42-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 4683 // CHECK42-NEXT: entry: 4684 // CHECK42-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4685 // CHECK42-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4686 // CHECK42-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4687 // CHECK42-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4688 // CHECK42-NEXT: ret void 4689 // 4690 // 4691 // CHECK43-LABEL: define {{[^@]+}}@_Z3foov 4692 // CHECK43-SAME: () #[[ATTR0:[0-9]+]] { 4693 // CHECK43-NEXT: entry: 4694 // CHECK43-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4695 // CHECK43-NEXT: ret void 4696 // 4697 // 4698 // CHECK43-LABEL: define {{[^@]+}}@.omp_outlined. 4699 // CHECK43-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 4700 // CHECK43-NEXT: entry: 4701 // CHECK43-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4702 // CHECK43-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4703 // CHECK43-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4704 // CHECK43-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4705 // CHECK43-NEXT: ret void 4706 // 4707 // 4708 // CHECK44-LABEL: define {{[^@]+}}@_Z3foov 4709 // CHECK44-SAME: () #[[ATTR0:[0-9]+]] { 4710 // CHECK44-NEXT: entry: 4711 // CHECK44-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4712 // CHECK44-NEXT: ret void 4713 // 4714 // 4715 // CHECK44-LABEL: define {{[^@]+}}@.omp_outlined. 4716 // CHECK44-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 4717 // CHECK44-NEXT: entry: 4718 // CHECK44-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4719 // CHECK44-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4720 // CHECK44-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4721 // CHECK44-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4722 // CHECK44-NEXT: ret void 4723 // 4724 // 4725 // CHECK45-LABEL: define {{[^@]+}}@_Z3foov 4726 // CHECK45-SAME: () #[[ATTR0:[0-9]+]] { 4727 // CHECK45-NEXT: entry: 4728 // CHECK45-NEXT: ret void 4729 // 4730 // 4731 // CHECK46-LABEL: define {{[^@]+}}@_Z3foov 4732 // CHECK46-SAME: () #[[ATTR0:[0-9]+]] { 4733 // CHECK46-NEXT: entry: 4734 // CHECK46-NEXT: ret void 4735 // 4736 // 4737 // CHECK47-LABEL: define {{[^@]+}}@_Z3foov 4738 // CHECK47-SAME: () #[[ATTR0:[0-9]+]] { 4739 // CHECK47-NEXT: entry: 4740 // CHECK47-NEXT: ret void 4741 // 4742 // 4743 // CHECK48-LABEL: define {{[^@]+}}@_Z3foov 4744 // CHECK48-SAME: () #[[ATTR0:[0-9]+]] { 4745 // CHECK48-NEXT: entry: 4746 // CHECK48-NEXT: ret void 4747 // 4748