1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 26 27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 40 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 43 44 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 47 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 60 61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 6 target regions 78 79 80 81 // Check target registration is registered as a Ctor. 82 83 84 template<typename tx> 85 tx ftemplate(int n) { 86 tx a = 0; 87 88 #pragma omp target teams num_teams(tx(20)) 89 { 90 } 91 92 short b = 1; 93 #pragma omp target teams num_teams(b) 94 { 95 a += b; 96 } 97 98 return a; 99 } 100 101 static 102 int fstatic(int n) { 103 104 #pragma omp target teams num_teams(n) 105 { 106 } 107 108 #pragma omp target teams num_teams(32+n) 109 { 110 } 111 112 return n+1; 113 } 114 115 struct S1 { 116 double a; 117 118 int r1(int n){ 119 int b = 1; 120 121 #pragma omp target teams num_teams(n-b) 122 { 123 this->a = (double)b + 1.5; 124 } 125 126 #pragma omp target teams num_teams(1024) 127 { 128 this->a = 2.5; 129 } 130 131 return (int)a; 132 } 133 }; 134 135 int bar(int n){ 136 int a = 0; 137 138 S1 S; 139 a += S.r1(n); 140 141 a += fstatic(n); 142 143 a += ftemplate<int>(n); 144 145 return a; 146 } 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 // Check that the offloading functions are emitted and that the parallel function 169 // is appropriately guarded. 170 171 172 173 174 175 176 #endif 177 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 178 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 179 // CHECK1-NEXT: entry: 180 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 181 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 182 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 183 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 184 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 185 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 186 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 187 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 188 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 189 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 190 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 191 // CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 192 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 193 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 194 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 195 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 196 // CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 197 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 198 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 199 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 200 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 201 // CHECK1-NEXT: ret i32 [[TMP6]] 202 // 203 // 204 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 205 // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 206 // CHECK1-NEXT: entry: 207 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 208 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 209 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 210 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 211 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 212 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 213 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 214 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 215 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 216 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 217 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 218 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 219 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 220 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 221 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 222 // CHECK1-NEXT: store i32 1, i32* [[B]], align 4 223 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 224 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 225 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 226 // CHECK1-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 227 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 228 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 229 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 230 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 231 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 232 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 233 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 234 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 235 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 236 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 237 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 238 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 239 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 240 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 241 // CHECK1-NEXT: store double* [[A]], double** [[TMP9]], align 8 242 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 243 // CHECK1-NEXT: store i8* null, i8** [[TMP10]], align 8 244 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 245 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 246 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 247 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 248 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 249 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 250 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 251 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 252 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 253 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 254 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 255 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 256 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 257 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 258 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 259 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 260 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 261 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 262 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 263 // CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 264 // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 265 // CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 266 // CHECK1: omp_offload.failed: 267 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] 268 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 269 // CHECK1: omp_offload.cont: 270 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 271 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 272 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 273 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 274 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 275 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 276 // CHECK1-NEXT: store double* [[A3]], double** [[TMP29]], align 8 277 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 278 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 279 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 280 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 281 // CHECK1-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) 282 // CHECK1-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 283 // CHECK1-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 284 // CHECK1: omp_offload.failed7: 285 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 286 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]] 287 // CHECK1: omp_offload.cont8: 288 // CHECK1-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 289 // CHECK1-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 290 // CHECK1-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 291 // CHECK1-NEXT: ret i32 [[CONV10]] 292 // 293 // 294 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 295 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 296 // CHECK1-NEXT: entry: 297 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 300 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 301 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 302 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 303 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 304 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 305 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 306 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 307 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 308 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 309 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 310 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 311 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 312 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 313 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 314 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 315 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 316 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 317 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 318 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 319 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 320 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 321 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 322 // CHECK1-NEXT: store i8* null, i8** [[TMP7]], align 8 323 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 324 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 325 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 326 // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) 327 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 328 // CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 329 // CHECK1: omp_offload.failed: 330 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] 331 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 332 // CHECK1: omp_offload.cont: 333 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 334 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 335 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 336 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 337 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* 338 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 339 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 340 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 341 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 342 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 343 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 344 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 345 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 346 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 347 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 348 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 349 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 350 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 351 // CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 352 // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 353 // CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 354 // CHECK1: omp_offload.failed7: 355 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] 356 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]] 357 // CHECK1: omp_offload.cont8: 358 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 359 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 360 // CHECK1-NEXT: ret i32 [[ADD9]] 361 // 362 // 363 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 364 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 365 // CHECK1-NEXT: entry: 366 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 367 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 368 // CHECK1-NEXT: [[B:%.*]] = alloca i16, align 2 369 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 370 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 371 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 372 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 373 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 374 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 375 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 376 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 377 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 378 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) 379 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 380 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 381 // CHECK1: omp_offload.failed: 382 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 383 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 384 // CHECK1: omp_offload.cont: 385 // CHECK1-NEXT: store i16 1, i16* [[B]], align 2 386 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 387 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 388 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 389 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 390 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 391 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 392 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 393 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* 394 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 395 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 396 // CHECK1-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 397 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* 398 // CHECK1-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 399 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 400 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 401 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 402 // CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 403 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 404 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 405 // CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 406 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 407 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 408 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 409 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 410 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 411 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 412 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 413 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 414 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 415 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 416 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 417 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 418 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 419 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 420 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 421 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 422 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 423 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 424 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 425 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 426 // CHECK1-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 427 // CHECK1-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 428 // CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) 429 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 430 // CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 431 // CHECK1: omp_offload.failed3: 432 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] 433 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 434 // CHECK1: omp_offload.cont4: 435 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 436 // CHECK1-NEXT: ret i32 [[TMP30]] 437 // 438 // 439 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 440 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 441 // CHECK1-NEXT: entry: 442 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 443 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 444 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 445 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 446 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 447 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 448 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 449 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 450 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 451 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 452 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 453 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 454 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 455 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 456 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 457 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 458 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 459 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 460 // CHECK1-NEXT: ret void 461 // 462 // 463 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 464 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 465 // CHECK1-NEXT: entry: 466 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 467 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 468 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 469 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 470 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 471 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 472 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 473 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 474 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 475 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 476 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 477 // CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 478 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 479 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 480 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 481 // CHECK1-NEXT: ret void 482 // 483 // 484 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 485 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 486 // CHECK1-NEXT: entry: 487 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 488 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 489 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 490 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 491 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 492 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 493 // CHECK1-NEXT: ret void 494 // 495 // 496 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 497 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 498 // CHECK1-NEXT: entry: 499 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 500 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 501 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 502 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 503 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 504 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 505 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 506 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 507 // CHECK1-NEXT: store double 2.500000e+00, double* [[A]], align 8 508 // CHECK1-NEXT: ret void 509 // 510 // 511 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 512 // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 513 // CHECK1-NEXT: entry: 514 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 515 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 516 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 517 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 518 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 519 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 520 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 521 // CHECK1-NEXT: ret void 522 // 523 // 524 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 525 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 526 // CHECK1-NEXT: entry: 527 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 528 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 529 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 530 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 531 // CHECK1-NEXT: ret void 532 // 533 // 534 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 535 // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 536 // CHECK1-NEXT: entry: 537 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 538 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 539 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 540 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 541 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 542 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 543 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 544 // CHECK1-NEXT: ret void 545 // 546 // 547 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 548 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 549 // CHECK1-NEXT: entry: 550 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 551 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 552 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 553 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 554 // CHECK1-NEXT: ret void 555 // 556 // 557 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 558 // CHECK1-SAME: () #[[ATTR1]] { 559 // CHECK1-NEXT: entry: 560 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 561 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 562 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 563 // CHECK1-NEXT: ret void 564 // 565 // 566 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 567 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 568 // CHECK1-NEXT: entry: 569 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 570 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 571 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 572 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 573 // CHECK1-NEXT: ret void 574 // 575 // 576 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 577 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 578 // CHECK1-NEXT: entry: 579 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 580 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 581 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 582 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 583 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 584 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 585 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 586 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 587 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 588 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 589 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 590 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 591 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 592 // CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 593 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 594 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 595 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 596 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 597 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 598 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 599 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 600 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 601 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 602 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 603 // CHECK1-NEXT: ret void 604 // 605 // 606 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 607 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 608 // CHECK1-NEXT: entry: 609 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 610 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 611 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 612 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 613 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 614 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 615 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 616 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 617 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 618 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 619 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 620 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 621 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 622 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 623 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 624 // CHECK1-NEXT: ret void 625 // 626 // 627 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 628 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 629 // CHECK1-NEXT: entry: 630 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 631 // CHECK1-NEXT: ret void 632 // 633 // 634 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari 635 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 636 // CHECK2-NEXT: entry: 637 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 638 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 639 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 640 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 641 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 642 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 643 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 644 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 645 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 646 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 647 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 648 // CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 649 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 650 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 651 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 652 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 653 // CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 654 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 655 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 656 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 657 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 658 // CHECK2-NEXT: ret i32 [[TMP6]] 659 // 660 // 661 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 662 // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 663 // CHECK2-NEXT: entry: 664 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 665 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 666 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 667 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 668 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 669 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 670 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 671 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 672 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 673 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 674 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 675 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 676 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 677 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 678 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 679 // CHECK2-NEXT: store i32 1, i32* [[B]], align 4 680 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 681 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 682 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 683 // CHECK2-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 684 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 685 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 686 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 687 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 688 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 689 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 690 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 691 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 692 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 693 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 694 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 695 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 696 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 697 // CHECK2-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 698 // CHECK2-NEXT: store double* [[A]], double** [[TMP9]], align 8 699 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 700 // CHECK2-NEXT: store i8* null, i8** [[TMP10]], align 8 701 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 702 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 703 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 704 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 705 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 706 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 707 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 708 // CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8 709 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 710 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 711 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 712 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 713 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 714 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 715 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 716 // CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8 717 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 718 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 719 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 720 // CHECK2-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 721 // CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 722 // CHECK2-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 723 // CHECK2: omp_offload.failed: 724 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] 725 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 726 // CHECK2: omp_offload.cont: 727 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 728 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 729 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 730 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 731 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 732 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 733 // CHECK2-NEXT: store double* [[A3]], double** [[TMP29]], align 8 734 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 735 // CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8 736 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 737 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 738 // CHECK2-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) 739 // CHECK2-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 740 // CHECK2-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 741 // CHECK2: omp_offload.failed7: 742 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 743 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT8]] 744 // CHECK2: omp_offload.cont8: 745 // CHECK2-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 746 // CHECK2-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 747 // CHECK2-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 748 // CHECK2-NEXT: ret i32 [[CONV10]] 749 // 750 // 751 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici 752 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 753 // CHECK2-NEXT: entry: 754 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 755 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 756 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 757 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 758 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 759 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 760 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 761 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 762 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 763 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 764 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 765 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 766 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 767 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 768 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 769 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 770 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 771 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 772 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 773 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 774 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 775 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 776 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 777 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 778 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 779 // CHECK2-NEXT: store i8* null, i8** [[TMP7]], align 8 780 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 781 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 782 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 783 // CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) 784 // CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 785 // CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 786 // CHECK2: omp_offload.failed: 787 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] 788 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 789 // CHECK2: omp_offload.cont: 790 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 791 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 792 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 793 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 794 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* 795 // CHECK2-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 796 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 797 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 798 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 799 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 800 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 801 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 802 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 803 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 804 // CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8 805 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 806 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 807 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 808 // CHECK2-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 809 // CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 810 // CHECK2-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 811 // CHECK2: omp_offload.failed7: 812 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] 813 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT8]] 814 // CHECK2: omp_offload.cont8: 815 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 816 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 817 // CHECK2-NEXT: ret i32 [[ADD9]] 818 // 819 // 820 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 821 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 822 // CHECK2-NEXT: entry: 823 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 824 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 825 // CHECK2-NEXT: [[B:%.*]] = alloca i16, align 2 826 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 827 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 828 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 829 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 830 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 831 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 832 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 833 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 834 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 835 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) 836 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 837 // CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 838 // CHECK2: omp_offload.failed: 839 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 840 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 841 // CHECK2: omp_offload.cont: 842 // CHECK2-NEXT: store i16 1, i16* [[B]], align 2 843 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 844 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 845 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 846 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 847 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 848 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 849 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 850 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* 851 // CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 852 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 853 // CHECK2-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 854 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* 855 // CHECK2-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 856 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 857 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 858 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 859 // CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 860 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 861 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 862 // CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 863 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 864 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 865 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 866 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 867 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 868 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 869 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 870 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 871 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 872 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 873 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 874 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 875 // CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 876 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 877 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 878 // CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 879 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 880 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 881 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 882 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 883 // CHECK2-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 884 // CHECK2-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 885 // CHECK2-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) 886 // CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 887 // CHECK2-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 888 // CHECK2: omp_offload.failed3: 889 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] 890 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT4]] 891 // CHECK2: omp_offload.cont4: 892 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 893 // CHECK2-NEXT: ret i32 [[TMP30]] 894 // 895 // 896 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 897 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 898 // CHECK2-NEXT: entry: 899 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 900 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 901 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 902 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 903 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 904 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 905 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 906 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 907 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 908 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 909 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 910 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 911 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 912 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 913 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 914 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 915 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 916 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 917 // CHECK2-NEXT: ret void 918 // 919 // 920 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 921 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 922 // CHECK2-NEXT: entry: 923 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 924 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 925 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 926 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 927 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 928 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 929 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 930 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 931 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 932 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 933 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 934 // CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 935 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 936 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 937 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 938 // CHECK2-NEXT: ret void 939 // 940 // 941 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 942 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 943 // CHECK2-NEXT: entry: 944 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 945 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 946 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 947 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 948 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 949 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 950 // CHECK2-NEXT: ret void 951 // 952 // 953 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 954 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 955 // CHECK2-NEXT: entry: 956 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 957 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 958 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 959 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 960 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 961 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 962 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 963 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 964 // CHECK2-NEXT: store double 2.500000e+00, double* [[A]], align 8 965 // CHECK2-NEXT: ret void 966 // 967 // 968 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 969 // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 970 // CHECK2-NEXT: entry: 971 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 972 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 973 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 974 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 975 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 976 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 977 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 978 // CHECK2-NEXT: ret void 979 // 980 // 981 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 982 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 983 // CHECK2-NEXT: entry: 984 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 985 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 986 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 987 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 988 // CHECK2-NEXT: ret void 989 // 990 // 991 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 992 // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 993 // CHECK2-NEXT: entry: 994 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 995 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 996 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 997 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 998 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 999 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 1000 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 1001 // CHECK2-NEXT: ret void 1002 // 1003 // 1004 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 1005 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1006 // CHECK2-NEXT: entry: 1007 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1008 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1009 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1010 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1011 // CHECK2-NEXT: ret void 1012 // 1013 // 1014 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 1015 // CHECK2-SAME: () #[[ATTR1]] { 1016 // CHECK2-NEXT: entry: 1017 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1018 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 1019 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 1020 // CHECK2-NEXT: ret void 1021 // 1022 // 1023 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 1024 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1025 // CHECK2-NEXT: entry: 1026 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1027 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1028 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1029 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1030 // CHECK2-NEXT: ret void 1031 // 1032 // 1033 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 1034 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1035 // CHECK2-NEXT: entry: 1036 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1037 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1038 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1039 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1040 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1041 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1042 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1043 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1044 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1045 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1046 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 1047 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 1048 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 1049 // CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 1050 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 1051 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1052 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1053 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 1054 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 1055 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 1056 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 1057 // CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 1058 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1059 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 1060 // CHECK2-NEXT: ret void 1061 // 1062 // 1063 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 1064 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 1065 // CHECK2-NEXT: entry: 1066 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1067 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1068 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1069 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1070 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1071 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1072 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1073 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1074 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1075 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 1076 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 1077 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 1078 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1079 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 1080 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 1081 // CHECK2-NEXT: ret void 1082 // 1083 // 1084 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1085 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 1086 // CHECK2-NEXT: entry: 1087 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1088 // CHECK2-NEXT: ret void 1089 // 1090 // 1091 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 1092 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1093 // CHECK3-NEXT: entry: 1094 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1095 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1096 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 1097 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1098 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1099 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1100 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 1101 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1102 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1103 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1104 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1105 // CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 1106 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1107 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1108 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1109 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1110 // CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 1111 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1112 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1113 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1114 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 1115 // CHECK3-NEXT: ret i32 [[TMP6]] 1116 // 1117 // 1118 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1119 // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1120 // CHECK3-NEXT: entry: 1121 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1122 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1123 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 1124 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1125 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1126 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1127 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1128 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1129 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1130 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 1131 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 1132 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 1133 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1134 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1135 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1136 // CHECK3-NEXT: store i32 1, i32* [[B]], align 4 1137 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1138 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 1139 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 1140 // CHECK3-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 1141 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 1142 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 1143 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 1144 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1145 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1146 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1147 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1148 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1149 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 1150 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 1151 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1152 // CHECK3-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 1153 // CHECK3-NEXT: store double* [[A]], double** [[TMP9]], align 4 1154 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1155 // CHECK3-NEXT: store i8* null, i8** [[TMP10]], align 4 1156 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1157 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1158 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 1159 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1160 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1161 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 1162 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1163 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 1164 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1165 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1166 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 1167 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1168 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1169 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 1170 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1171 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 1172 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1173 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1174 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1175 // CHECK3-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 1176 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1177 // CHECK3-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1178 // CHECK3: omp_offload.failed: 1179 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] 1180 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1181 // CHECK3: omp_offload.cont: 1182 // CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 1183 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1184 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 1185 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 1186 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1187 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 1188 // CHECK3-NEXT: store double* [[A2]], double** [[TMP29]], align 4 1189 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 1190 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 1191 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1192 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1193 // CHECK3-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) 1194 // CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1195 // CHECK3-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1196 // CHECK3: omp_offload.failed6: 1197 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 1198 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1199 // CHECK3: omp_offload.cont7: 1200 // CHECK3-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 1201 // CHECK3-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 1202 // CHECK3-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 1203 // CHECK3-NEXT: ret i32 [[CONV]] 1204 // 1205 // 1206 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 1207 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 1208 // CHECK3-NEXT: entry: 1209 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1210 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1211 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1212 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1213 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1214 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1215 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1216 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 1217 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 1218 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 1219 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 1220 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1221 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1222 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 1223 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1224 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1225 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1226 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1227 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 1228 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 1229 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1230 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 1231 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 1232 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1233 // CHECK3-NEXT: store i8* null, i8** [[TMP7]], align 4 1234 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1235 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1236 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1237 // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) 1238 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1239 // CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1240 // CHECK3: omp_offload.failed: 1241 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] 1242 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1243 // CHECK3: omp_offload.cont: 1244 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 1245 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 1246 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1247 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1248 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 1249 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 1250 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1251 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1252 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 1253 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1254 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1255 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 1256 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 1257 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 1258 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1259 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1260 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1261 // CHECK3-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 1262 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1263 // CHECK3-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1264 // CHECK3: omp_offload.failed6: 1265 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] 1266 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1267 // CHECK3: omp_offload.cont7: 1268 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 1269 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 1270 // CHECK3-NEXT: ret i32 [[ADD8]] 1271 // 1272 // 1273 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1274 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 1275 // CHECK3-NEXT: entry: 1276 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1277 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1278 // CHECK3-NEXT: [[B:%.*]] = alloca i16, align 2 1279 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 1280 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1281 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1282 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1283 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1284 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1285 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1286 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1287 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1288 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) 1289 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 1290 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1291 // CHECK3: omp_offload.failed: 1292 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 1293 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1294 // CHECK3: omp_offload.cont: 1295 // CHECK3-NEXT: store i16 1, i16* [[B]], align 2 1296 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 1297 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 1298 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1299 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1300 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1301 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 1302 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1303 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 1304 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1305 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 1306 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* 1307 // CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 1308 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1309 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1310 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1311 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 1312 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1313 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1314 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 1315 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1316 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1317 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1318 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1319 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 1320 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1321 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1322 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 1323 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1324 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1325 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1326 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1327 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 1328 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1329 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 1330 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 1331 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1332 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1333 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1334 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1335 // CHECK3-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 1336 // CHECK3-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 1337 // CHECK3-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) 1338 // CHECK3-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 1339 // CHECK3-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] 1340 // CHECK3: omp_offload.failed2: 1341 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] 1342 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] 1343 // CHECK3: omp_offload.cont3: 1344 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 1345 // CHECK3-NEXT: ret i32 [[TMP30]] 1346 // 1347 // 1348 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 1349 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 1350 // CHECK3-NEXT: entry: 1351 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1352 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1353 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1354 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1355 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1356 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1357 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1358 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1359 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1360 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1361 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 1362 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 1363 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 1364 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 1365 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 1366 // CHECK3-NEXT: ret void 1367 // 1368 // 1369 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1370 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 1371 // CHECK3-NEXT: entry: 1372 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1373 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1374 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1375 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1376 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1377 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1378 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1379 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1380 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1381 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 1382 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 1383 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1384 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1385 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 1386 // CHECK3-NEXT: ret void 1387 // 1388 // 1389 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 1390 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 1391 // CHECK3-NEXT: entry: 1392 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1393 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1394 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1395 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1396 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 1397 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 1398 // CHECK3-NEXT: ret void 1399 // 1400 // 1401 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 1402 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 1403 // CHECK3-NEXT: entry: 1404 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1405 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1406 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1407 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1408 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1409 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1410 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1411 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1412 // CHECK3-NEXT: store double 2.500000e+00, double* [[A]], align 4 1413 // CHECK3-NEXT: ret void 1414 // 1415 // 1416 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 1417 // CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1418 // CHECK3-NEXT: entry: 1419 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1420 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1421 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1422 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1423 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 1424 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 1425 // CHECK3-NEXT: ret void 1426 // 1427 // 1428 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1429 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1430 // CHECK3-NEXT: entry: 1431 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1432 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1433 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1434 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1435 // CHECK3-NEXT: ret void 1436 // 1437 // 1438 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 1439 // CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1440 // CHECK3-NEXT: entry: 1441 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1442 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1443 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1444 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1445 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 1446 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 1447 // CHECK3-NEXT: ret void 1448 // 1449 // 1450 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 1451 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1452 // CHECK3-NEXT: entry: 1453 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1454 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1455 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1456 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1457 // CHECK3-NEXT: ret void 1458 // 1459 // 1460 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 1461 // CHECK3-SAME: () #[[ATTR1]] { 1462 // CHECK3-NEXT: entry: 1463 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1464 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 1465 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 1466 // CHECK3-NEXT: ret void 1467 // 1468 // 1469 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 1470 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1471 // CHECK3-NEXT: entry: 1472 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1473 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1474 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1475 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1476 // CHECK3-NEXT: ret void 1477 // 1478 // 1479 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 1480 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1481 // CHECK3-NEXT: entry: 1482 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1483 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1484 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1485 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1486 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1487 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1488 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1489 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1490 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1491 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1492 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 1493 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 1494 // CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 1495 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 1496 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 1497 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1498 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1499 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 1500 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1501 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 1502 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1503 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 1504 // CHECK3-NEXT: ret void 1505 // 1506 // 1507 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 1508 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 1509 // CHECK3-NEXT: entry: 1510 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1511 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1512 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1513 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1514 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1515 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1516 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1517 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1518 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1519 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 1520 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 1521 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 1522 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 1523 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1524 // CHECK3-NEXT: ret void 1525 // 1526 // 1527 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1528 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1529 // CHECK3-NEXT: entry: 1530 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1531 // CHECK3-NEXT: ret void 1532 // 1533 // 1534 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari 1535 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1536 // CHECK4-NEXT: entry: 1537 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1538 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 1539 // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 1540 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1541 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 1542 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1543 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 1544 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1545 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1546 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1547 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1548 // CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 1549 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1550 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1551 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1552 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1553 // CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 1554 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1555 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1556 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1557 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 1558 // CHECK4-NEXT: ret i32 [[TMP6]] 1559 // 1560 // 1561 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1562 // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1563 // CHECK4-NEXT: entry: 1564 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1565 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1566 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 1567 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1568 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1569 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1570 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1571 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1572 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1573 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 1574 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 1575 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 1576 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1577 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1578 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1579 // CHECK4-NEXT: store i32 1, i32* [[B]], align 4 1580 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1581 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 1582 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 1583 // CHECK4-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 1584 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 1585 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 1586 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 1587 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1588 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1589 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1590 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1591 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1592 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 1593 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 1594 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1595 // CHECK4-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 1596 // CHECK4-NEXT: store double* [[A]], double** [[TMP9]], align 4 1597 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1598 // CHECK4-NEXT: store i8* null, i8** [[TMP10]], align 4 1599 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1600 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1601 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 1602 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1603 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1604 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 1605 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1606 // CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4 1607 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1608 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1609 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 1610 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1611 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1612 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 1613 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1614 // CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4 1615 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1616 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1617 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1618 // CHECK4-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 1619 // CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1620 // CHECK4-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1621 // CHECK4: omp_offload.failed: 1622 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] 1623 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1624 // CHECK4: omp_offload.cont: 1625 // CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 1626 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1627 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 1628 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 1629 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1630 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 1631 // CHECK4-NEXT: store double* [[A2]], double** [[TMP29]], align 4 1632 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 1633 // CHECK4-NEXT: store i8* null, i8** [[TMP30]], align 4 1634 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1635 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1636 // CHECK4-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) 1637 // CHECK4-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1638 // CHECK4-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1639 // CHECK4: omp_offload.failed6: 1640 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 1641 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1642 // CHECK4: omp_offload.cont7: 1643 // CHECK4-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 1644 // CHECK4-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 1645 // CHECK4-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 1646 // CHECK4-NEXT: ret i32 [[CONV]] 1647 // 1648 // 1649 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici 1650 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 1651 // CHECK4-NEXT: entry: 1652 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1653 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1654 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1655 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1656 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1657 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1658 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1659 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 1660 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 1661 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 1662 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 1663 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1664 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1665 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 1666 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1667 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1668 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1669 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1670 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 1671 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 1672 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1673 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 1674 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 1675 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1676 // CHECK4-NEXT: store i8* null, i8** [[TMP7]], align 4 1677 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1678 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1679 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1680 // CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) 1681 // CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1682 // CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1683 // CHECK4: omp_offload.failed: 1684 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] 1685 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1686 // CHECK4: omp_offload.cont: 1687 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 1688 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 1689 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1690 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1691 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 1692 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 1693 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1694 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1695 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 1696 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1697 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1698 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 1699 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 1700 // CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4 1701 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1702 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1703 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1704 // CHECK4-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 1705 // CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1706 // CHECK4-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1707 // CHECK4: omp_offload.failed6: 1708 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] 1709 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1710 // CHECK4: omp_offload.cont7: 1711 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 1712 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 1713 // CHECK4-NEXT: ret i32 [[ADD8]] 1714 // 1715 // 1716 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1717 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 1718 // CHECK4-NEXT: entry: 1719 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1720 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 1721 // CHECK4-NEXT: [[B:%.*]] = alloca i16, align 2 1722 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 1723 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1724 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1725 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1726 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1727 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1728 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1729 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1730 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 1731 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) 1732 // CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 1733 // CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1734 // CHECK4: omp_offload.failed: 1735 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 1736 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1737 // CHECK4: omp_offload.cont: 1738 // CHECK4-NEXT: store i16 1, i16* [[B]], align 2 1739 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 1740 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 1741 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1742 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1743 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1744 // CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 1745 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1746 // CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 1747 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1748 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 1749 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* 1750 // CHECK4-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 1751 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1752 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1753 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1754 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 1755 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1756 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1757 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 1758 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1759 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 1760 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1761 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1762 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 1763 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1764 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1765 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 1766 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1767 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 1768 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1769 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1770 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 1771 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1772 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 1773 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 1774 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1775 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 1776 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1777 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1778 // CHECK4-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 1779 // CHECK4-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 1780 // CHECK4-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) 1781 // CHECK4-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 1782 // CHECK4-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] 1783 // CHECK4: omp_offload.failed2: 1784 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] 1785 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] 1786 // CHECK4: omp_offload.cont3: 1787 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 1788 // CHECK4-NEXT: ret i32 [[TMP30]] 1789 // 1790 // 1791 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 1792 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 1793 // CHECK4-NEXT: entry: 1794 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1795 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1796 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1797 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1798 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1799 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1800 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1801 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1802 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1803 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1804 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 1805 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 1806 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 1807 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 1808 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 1809 // CHECK4-NEXT: ret void 1810 // 1811 // 1812 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 1813 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 1814 // CHECK4-NEXT: entry: 1815 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1816 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1817 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1818 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1819 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1820 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1821 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1822 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1823 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1824 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 1825 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 1826 // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1827 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1828 // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4 1829 // CHECK4-NEXT: ret void 1830 // 1831 // 1832 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 1833 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 1834 // CHECK4-NEXT: entry: 1835 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1836 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1837 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1838 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1839 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 1840 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 1841 // CHECK4-NEXT: ret void 1842 // 1843 // 1844 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 1845 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 1846 // CHECK4-NEXT: entry: 1847 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1848 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1849 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1850 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1851 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1852 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1853 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1854 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1855 // CHECK4-NEXT: store double 2.500000e+00, double* [[A]], align 4 1856 // CHECK4-NEXT: ret void 1857 // 1858 // 1859 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 1860 // CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1861 // CHECK4-NEXT: entry: 1862 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1863 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1864 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1865 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1866 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 1867 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 1868 // CHECK4-NEXT: ret void 1869 // 1870 // 1871 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 1872 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1873 // CHECK4-NEXT: entry: 1874 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1875 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1876 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1877 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1878 // CHECK4-NEXT: ret void 1879 // 1880 // 1881 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 1882 // CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1883 // CHECK4-NEXT: entry: 1884 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1885 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1886 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1887 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1888 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 1889 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 1890 // CHECK4-NEXT: ret void 1891 // 1892 // 1893 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 1894 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1895 // CHECK4-NEXT: entry: 1896 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1897 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1898 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1899 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1900 // CHECK4-NEXT: ret void 1901 // 1902 // 1903 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 1904 // CHECK4-SAME: () #[[ATTR1]] { 1905 // CHECK4-NEXT: entry: 1906 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1907 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 1908 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 1909 // CHECK4-NEXT: ret void 1910 // 1911 // 1912 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 1913 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1914 // CHECK4-NEXT: entry: 1915 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1916 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1917 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1918 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1919 // CHECK4-NEXT: ret void 1920 // 1921 // 1922 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 1923 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1924 // CHECK4-NEXT: entry: 1925 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1926 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1927 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1928 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1929 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1930 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1931 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1932 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1933 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1934 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1935 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 1936 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 1937 // CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 1938 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 1939 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 1940 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1941 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1942 // CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 1943 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1944 // CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 1945 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1946 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 1947 // CHECK4-NEXT: ret void 1948 // 1949 // 1950 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 1951 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 1952 // CHECK4-NEXT: entry: 1953 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1954 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1955 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1956 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1957 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1958 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1959 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1960 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1961 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1962 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 1963 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 1964 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 1965 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 1966 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1967 // CHECK4-NEXT: ret void 1968 // 1969 // 1970 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1971 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 1972 // CHECK4-NEXT: entry: 1973 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 1974 // CHECK4-NEXT: ret void 1975 // 1976 // 1977 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari 1978 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1979 // CHECK5-NEXT: entry: 1980 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1981 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 1982 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1983 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1984 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 1985 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1986 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 1987 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1988 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1989 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1990 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1991 // CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 1992 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1993 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1994 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1995 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1996 // CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 1997 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1998 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1999 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2000 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2001 // CHECK5-NEXT: ret i32 [[TMP6]] 2002 // 2003 // 2004 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2005 // CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2006 // CHECK5-NEXT: entry: 2007 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2008 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2009 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 2010 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2011 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2012 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2013 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2014 // CHECK5-NEXT: store i32 1, i32* [[B]], align 4 2015 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2016 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 2017 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 2018 // CHECK5-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 2019 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 2020 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 2021 // CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2022 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2023 // CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 2024 // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2025 // CHECK5-NEXT: store double 2.500000e+00, double* [[A2]], align 8 2026 // CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2027 // CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 2028 // CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 2029 // CHECK5-NEXT: ret i32 [[CONV4]] 2030 // 2031 // 2032 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici 2033 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 2034 // CHECK5-NEXT: entry: 2035 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2036 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2037 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2038 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2039 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2040 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2041 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2042 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 2043 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2044 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2045 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 2046 // CHECK5-NEXT: ret i32 [[ADD2]] 2047 // 2048 // 2049 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2050 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 2051 // CHECK5-NEXT: entry: 2052 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2053 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 2054 // CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 2055 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 2056 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2057 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 2058 // CHECK5-NEXT: store i16 1, i16* [[B]], align 2 2059 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 2060 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 2061 // CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 2062 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2063 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2064 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 2065 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2066 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2067 // CHECK5-NEXT: ret i32 [[TMP3]] 2068 // 2069 // 2070 // CHECK6-LABEL: define {{[^@]+}}@_Z3bari 2071 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2072 // CHECK6-NEXT: entry: 2073 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2074 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 2075 // CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 2076 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2077 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 2078 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2079 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 2080 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2081 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2082 // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2083 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2084 // CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 2085 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2086 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2087 // CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2088 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2089 // CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 2090 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2091 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2092 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2093 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2094 // CHECK6-NEXT: ret i32 [[TMP6]] 2095 // 2096 // 2097 // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2098 // CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2099 // CHECK6-NEXT: entry: 2100 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2101 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2102 // CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 2103 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2104 // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2105 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2106 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2107 // CHECK6-NEXT: store i32 1, i32* [[B]], align 4 2108 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2109 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 2110 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 2111 // CHECK6-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 2112 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 2113 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 2114 // CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2115 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2116 // CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 2117 // CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2118 // CHECK6-NEXT: store double 2.500000e+00, double* [[A2]], align 8 2119 // CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2120 // CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 2121 // CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 2122 // CHECK6-NEXT: ret i32 [[CONV4]] 2123 // 2124 // 2125 // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici 2126 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 2127 // CHECK6-NEXT: entry: 2128 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2129 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2130 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2131 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2132 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2133 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2134 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2135 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 2136 // CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2137 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2138 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 2139 // CHECK6-NEXT: ret i32 [[ADD2]] 2140 // 2141 // 2142 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2143 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 2144 // CHECK6-NEXT: entry: 2145 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2146 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 2147 // CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 2148 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 2149 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2150 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 2151 // CHECK6-NEXT: store i16 1, i16* [[B]], align 2 2152 // CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 2153 // CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 2154 // CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 2155 // CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2156 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2157 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 2158 // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2159 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2160 // CHECK6-NEXT: ret i32 [[TMP3]] 2161 // 2162 // 2163 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari 2164 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2165 // CHECK7-NEXT: entry: 2166 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2167 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 2168 // CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2169 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2170 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 2171 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2172 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 2173 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2174 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2175 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2176 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2177 // CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 2178 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2179 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2180 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2181 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2182 // CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 2183 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2184 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2185 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2186 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2187 // CHECK7-NEXT: ret i32 [[TMP6]] 2188 // 2189 // 2190 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2191 // CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2192 // CHECK7-NEXT: entry: 2193 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2194 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2195 // CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 2196 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2197 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2198 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2199 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2200 // CHECK7-NEXT: store i32 1, i32* [[B]], align 4 2201 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2202 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 2203 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 2204 // CHECK7-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 2205 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 2206 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 2207 // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2208 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2209 // CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 2210 // CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2211 // CHECK7-NEXT: store double 2.500000e+00, double* [[A2]], align 4 2212 // CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2213 // CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 2214 // CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 2215 // CHECK7-NEXT: ret i32 [[CONV4]] 2216 // 2217 // 2218 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici 2219 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 2220 // CHECK7-NEXT: entry: 2221 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2222 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2223 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2224 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2225 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2226 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2227 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2228 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 2229 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2230 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2231 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 2232 // CHECK7-NEXT: ret i32 [[ADD2]] 2233 // 2234 // 2235 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2236 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 2237 // CHECK7-NEXT: entry: 2238 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2239 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 2240 // CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 2241 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 2242 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2243 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 2244 // CHECK7-NEXT: store i16 1, i16* [[B]], align 2 2245 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 2246 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 2247 // CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 2248 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2249 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2250 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 2251 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2252 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2253 // CHECK7-NEXT: ret i32 [[TMP3]] 2254 // 2255 // 2256 // CHECK8-LABEL: define {{[^@]+}}@_Z3bari 2257 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2258 // CHECK8-NEXT: entry: 2259 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2260 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 2261 // CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2262 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2263 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 2264 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2265 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 2266 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2267 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2268 // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2269 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2270 // CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 2271 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2272 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2273 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2274 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2275 // CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 2276 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2277 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2278 // CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2279 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2280 // CHECK8-NEXT: ret i32 [[TMP6]] 2281 // 2282 // 2283 // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2284 // CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2285 // CHECK8-NEXT: entry: 2286 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2287 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2288 // CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 2289 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2290 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2291 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2292 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2293 // CHECK8-NEXT: store i32 1, i32* [[B]], align 4 2294 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2295 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 2296 // CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 2297 // CHECK8-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 2298 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 2299 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 2300 // CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2301 // CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2302 // CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 2303 // CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2304 // CHECK8-NEXT: store double 2.500000e+00, double* [[A2]], align 4 2305 // CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2306 // CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 2307 // CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 2308 // CHECK8-NEXT: ret i32 [[CONV4]] 2309 // 2310 // 2311 // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici 2312 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 2313 // CHECK8-NEXT: entry: 2314 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2315 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2316 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2317 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2318 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2319 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2320 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2321 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 2322 // CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2323 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2324 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 2325 // CHECK8-NEXT: ret i32 [[ADD2]] 2326 // 2327 // 2328 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2329 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 2330 // CHECK8-NEXT: entry: 2331 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2332 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 2333 // CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 2334 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 2335 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2336 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 2337 // CHECK8-NEXT: store i16 1, i16* [[B]], align 2 2338 // CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 2339 // CHECK8-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 2340 // CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 2341 // CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2342 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2343 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 2344 // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2345 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2346 // CHECK8-NEXT: ret i32 [[TMP3]] 2347 // 2348 // 2349 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 2350 // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 2351 // CHECK9-NEXT: entry: 2352 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2353 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2354 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2355 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2356 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2357 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 2358 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2359 // CHECK9-NEXT: ret void 2360 // 2361 // 2362 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2363 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2364 // CHECK9-NEXT: entry: 2365 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2366 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2367 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2368 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2369 // CHECK9-NEXT: ret void 2370 // 2371 // 2372 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 2373 // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2374 // CHECK9-NEXT: entry: 2375 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2376 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2377 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2378 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2379 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2380 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 2381 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 2382 // CHECK9-NEXT: ret void 2383 // 2384 // 2385 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 2386 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2387 // CHECK9-NEXT: entry: 2388 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2389 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2390 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2391 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2392 // CHECK9-NEXT: ret void 2393 // 2394 // 2395 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 2396 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2397 // CHECK9-NEXT: entry: 2398 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2399 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2400 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2401 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2402 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2403 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2404 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2405 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2406 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2407 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2408 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2409 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 2410 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 2411 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 2412 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2413 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 2414 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 2415 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 2416 // CHECK9-NEXT: ret void 2417 // 2418 // 2419 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 2420 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 2421 // CHECK9-NEXT: entry: 2422 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2423 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2424 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2425 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2426 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2427 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2428 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2429 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2430 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2431 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2432 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2433 // CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 2434 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 2435 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2436 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 2437 // CHECK9-NEXT: ret void 2438 // 2439 // 2440 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 2441 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2442 // CHECK9-NEXT: entry: 2443 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2444 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2445 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2446 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2447 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 2448 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 2449 // CHECK9-NEXT: ret void 2450 // 2451 // 2452 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 2453 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2454 // CHECK9-NEXT: entry: 2455 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2456 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2457 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2458 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2459 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2460 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2461 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2462 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2463 // CHECK9-NEXT: store double 2.500000e+00, double* [[A]], align 8 2464 // CHECK9-NEXT: ret void 2465 // 2466 // 2467 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 2468 // CHECK9-SAME: () #[[ATTR0]] { 2469 // CHECK9-NEXT: entry: 2470 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2471 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 2472 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 2473 // CHECK9-NEXT: ret void 2474 // 2475 // 2476 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 2477 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2478 // CHECK9-NEXT: entry: 2479 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2480 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2481 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2482 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2483 // CHECK9-NEXT: ret void 2484 // 2485 // 2486 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 2487 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2488 // CHECK9-NEXT: entry: 2489 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2490 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2491 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2492 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2493 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2494 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2495 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2496 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2497 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2498 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2499 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 2500 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 2501 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 2502 // CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 2503 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 2504 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 2505 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2506 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 2507 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 2508 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 2509 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 2510 // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 2511 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 2512 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 2513 // CHECK9-NEXT: ret void 2514 // 2515 // 2516 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 2517 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 2518 // CHECK9-NEXT: entry: 2519 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2520 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2521 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2522 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2523 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2524 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2525 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2526 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2527 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2528 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 2529 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 2530 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 2531 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2532 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 2533 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 2534 // CHECK9-NEXT: ret void 2535 // 2536 // 2537 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 2538 // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 2539 // CHECK10-NEXT: entry: 2540 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2541 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2542 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2543 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2544 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2545 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 2546 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2547 // CHECK10-NEXT: ret void 2548 // 2549 // 2550 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 2551 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2552 // CHECK10-NEXT: entry: 2553 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2554 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2555 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2556 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2557 // CHECK10-NEXT: ret void 2558 // 2559 // 2560 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 2561 // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2562 // CHECK10-NEXT: entry: 2563 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2564 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2565 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2566 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2567 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2568 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 2569 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 2570 // CHECK10-NEXT: ret void 2571 // 2572 // 2573 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 2574 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2575 // CHECK10-NEXT: entry: 2576 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2577 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2578 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2579 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2580 // CHECK10-NEXT: ret void 2581 // 2582 // 2583 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 2584 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2585 // CHECK10-NEXT: entry: 2586 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2587 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2588 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2589 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2590 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2591 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2592 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2593 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2594 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2595 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2596 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2597 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 2598 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 2599 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 2600 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2601 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 2602 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 2603 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 2604 // CHECK10-NEXT: ret void 2605 // 2606 // 2607 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 2608 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 2609 // CHECK10-NEXT: entry: 2610 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2611 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2612 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2613 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2614 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2615 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2616 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2617 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2618 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2619 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2620 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2621 // CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 2622 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 2623 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2624 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 2625 // CHECK10-NEXT: ret void 2626 // 2627 // 2628 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 2629 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2630 // CHECK10-NEXT: entry: 2631 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2632 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2633 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2634 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2635 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 2636 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 2637 // CHECK10-NEXT: ret void 2638 // 2639 // 2640 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 2641 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2642 // CHECK10-NEXT: entry: 2643 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2644 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2645 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2646 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2647 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2648 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2649 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2650 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2651 // CHECK10-NEXT: store double 2.500000e+00, double* [[A]], align 8 2652 // CHECK10-NEXT: ret void 2653 // 2654 // 2655 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 2656 // CHECK10-SAME: () #[[ATTR0]] { 2657 // CHECK10-NEXT: entry: 2658 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2659 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 2660 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 2661 // CHECK10-NEXT: ret void 2662 // 2663 // 2664 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 2665 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2666 // CHECK10-NEXT: entry: 2667 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2668 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2669 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2670 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2671 // CHECK10-NEXT: ret void 2672 // 2673 // 2674 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 2675 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2676 // CHECK10-NEXT: entry: 2677 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2678 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2679 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2680 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2681 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2682 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2683 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2684 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2685 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2686 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2687 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 2688 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 2689 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 2690 // CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 2691 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 2692 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 2693 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2694 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 2695 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 2696 // CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 2697 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 2698 // CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 2699 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 2700 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 2701 // CHECK10-NEXT: ret void 2702 // 2703 // 2704 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 2705 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 2706 // CHECK10-NEXT: entry: 2707 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2708 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2709 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2710 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2711 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2712 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2713 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2714 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2715 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2716 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 2717 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 2718 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 2719 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2720 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 2721 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 2722 // CHECK10-NEXT: ret void 2723 // 2724 // 2725 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 2726 // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 2727 // CHECK11-NEXT: entry: 2728 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2729 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2730 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2731 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2732 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 2733 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2734 // CHECK11-NEXT: ret void 2735 // 2736 // 2737 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 2738 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2739 // CHECK11-NEXT: entry: 2740 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2741 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2742 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2743 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2744 // CHECK11-NEXT: ret void 2745 // 2746 // 2747 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 2748 // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2749 // CHECK11-NEXT: entry: 2750 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2751 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2752 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2753 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2754 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 2755 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 2756 // CHECK11-NEXT: ret void 2757 // 2758 // 2759 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2760 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2761 // CHECK11-NEXT: entry: 2762 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2763 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2764 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2765 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2766 // CHECK11-NEXT: ret void 2767 // 2768 // 2769 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 2770 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2771 // CHECK11-NEXT: entry: 2772 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2773 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2774 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2775 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2776 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2777 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2778 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2779 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2780 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2781 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2782 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 2783 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 2784 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 2785 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 2786 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 2787 // CHECK11-NEXT: ret void 2788 // 2789 // 2790 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 2791 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 2792 // CHECK11-NEXT: entry: 2793 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2794 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2795 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2796 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2797 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2798 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2799 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2800 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2801 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2802 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 2803 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 2804 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2805 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2806 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 2807 // CHECK11-NEXT: ret void 2808 // 2809 // 2810 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 2811 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2812 // CHECK11-NEXT: entry: 2813 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2814 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2815 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2816 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2817 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 2818 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 2819 // CHECK11-NEXT: ret void 2820 // 2821 // 2822 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 2823 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2824 // CHECK11-NEXT: entry: 2825 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2826 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2827 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2828 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2829 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2830 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2831 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2832 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2833 // CHECK11-NEXT: store double 2.500000e+00, double* [[A]], align 4 2834 // CHECK11-NEXT: ret void 2835 // 2836 // 2837 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 2838 // CHECK11-SAME: () #[[ATTR0]] { 2839 // CHECK11-NEXT: entry: 2840 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2841 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 2842 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 2843 // CHECK11-NEXT: ret void 2844 // 2845 // 2846 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 2847 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2848 // CHECK11-NEXT: entry: 2849 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2850 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2851 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2852 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2853 // CHECK11-NEXT: ret void 2854 // 2855 // 2856 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 2857 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2858 // CHECK11-NEXT: entry: 2859 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2860 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2861 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2862 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2863 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2864 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2865 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2866 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2867 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2868 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 2869 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 2870 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 2871 // CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 2872 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 2873 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 2874 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 2875 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 2876 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 2877 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 2878 // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 2879 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 2880 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 2881 // CHECK11-NEXT: ret void 2882 // 2883 // 2884 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 2885 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 2886 // CHECK11-NEXT: entry: 2887 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2888 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2889 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2890 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2891 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2892 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2893 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2894 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2895 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 2896 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 2897 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2898 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2899 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 2900 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2901 // CHECK11-NEXT: ret void 2902 // 2903 // 2904 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 2905 // CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 2906 // CHECK12-NEXT: entry: 2907 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2908 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2909 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2910 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2911 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 2912 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2913 // CHECK12-NEXT: ret void 2914 // 2915 // 2916 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 2917 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2918 // CHECK12-NEXT: entry: 2919 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2920 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2921 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2922 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2923 // CHECK12-NEXT: ret void 2924 // 2925 // 2926 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 2927 // CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2928 // CHECK12-NEXT: entry: 2929 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2930 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2931 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2932 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2933 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 2934 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 2935 // CHECK12-NEXT: ret void 2936 // 2937 // 2938 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 2939 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2940 // CHECK12-NEXT: entry: 2941 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2942 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2943 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2944 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2945 // CHECK12-NEXT: ret void 2946 // 2947 // 2948 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 2949 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2950 // CHECK12-NEXT: entry: 2951 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2952 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2953 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2954 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2955 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2956 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2957 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2958 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2959 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2960 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2961 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 2962 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 2963 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 2964 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 2965 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 2966 // CHECK12-NEXT: ret void 2967 // 2968 // 2969 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 2970 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 2971 // CHECK12-NEXT: entry: 2972 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2973 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2974 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2975 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2976 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2977 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2978 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2979 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2980 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2981 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 2982 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 2983 // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2984 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2985 // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 2986 // CHECK12-NEXT: ret void 2987 // 2988 // 2989 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 2990 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2991 // CHECK12-NEXT: entry: 2992 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2993 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2994 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2995 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2996 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 2997 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 2998 // CHECK12-NEXT: ret void 2999 // 3000 // 3001 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 3002 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 3003 // CHECK12-NEXT: entry: 3004 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3005 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3006 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3007 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3008 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3009 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3010 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3011 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3012 // CHECK12-NEXT: store double 2.500000e+00, double* [[A]], align 4 3013 // CHECK12-NEXT: ret void 3014 // 3015 // 3016 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 3017 // CHECK12-SAME: () #[[ATTR0]] { 3018 // CHECK12-NEXT: entry: 3019 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3020 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 3021 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 3022 // CHECK12-NEXT: ret void 3023 // 3024 // 3025 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 3026 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 3027 // CHECK12-NEXT: entry: 3028 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3029 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3030 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3031 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3032 // CHECK12-NEXT: ret void 3033 // 3034 // 3035 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 3036 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 3037 // CHECK12-NEXT: entry: 3038 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3039 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3040 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 3041 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3042 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3043 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3044 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3045 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3046 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3047 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 3048 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 3049 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 3050 // CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 3051 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 3052 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 3053 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 3054 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 3055 // CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 3056 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 3057 // CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 3058 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 3059 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 3060 // CHECK12-NEXT: ret void 3061 // 3062 // 3063 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 3064 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 3065 // CHECK12-NEXT: entry: 3066 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3067 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3068 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3069 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3070 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3071 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3072 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3073 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3074 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 3075 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 3076 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3077 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3078 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 3079 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3080 // CHECK12-NEXT: ret void 3081 // 3082 // 3083 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari 3084 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3085 // CHECK13-NEXT: entry: 3086 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3087 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 3088 // CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 3089 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3090 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 3091 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3092 // CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 3093 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3094 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3095 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3096 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3097 // CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 3098 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3099 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3100 // CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3101 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3102 // CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 3103 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3104 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3105 // CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3106 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3107 // CHECK13-NEXT: ret i32 [[TMP6]] 3108 // 3109 // 3110 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3111 // CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3112 // CHECK13-NEXT: entry: 3113 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3114 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3115 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 3116 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3117 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3118 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3119 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3120 // CHECK13-NEXT: store i32 1, i32* [[B]], align 4 3121 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3122 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3123 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3124 // CHECK13-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3125 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3126 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 3127 // CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3128 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3129 // CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 3130 // CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3131 // CHECK13-NEXT: store double 2.500000e+00, double* [[A2]], align 8 3132 // CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3133 // CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 3134 // CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 3135 // CHECK13-NEXT: ret i32 [[CONV4]] 3136 // 3137 // 3138 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici 3139 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 3140 // CHECK13-NEXT: entry: 3141 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3142 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3143 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3144 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3145 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3146 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3147 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3148 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 3149 // CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3150 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3151 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 3152 // CHECK13-NEXT: ret i32 [[ADD2]] 3153 // 3154 // 3155 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3156 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 3157 // CHECK13-NEXT: entry: 3158 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3159 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 3160 // CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 3161 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3162 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3163 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 3164 // CHECK13-NEXT: store i16 1, i16* [[B]], align 2 3165 // CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 3166 // CHECK13-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 3167 // CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 3168 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3169 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3170 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 3171 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3172 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3173 // CHECK13-NEXT: ret i32 [[TMP3]] 3174 // 3175 // 3176 // CHECK14-LABEL: define {{[^@]+}}@_Z3bari 3177 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3178 // CHECK14-NEXT: entry: 3179 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3180 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 3181 // CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 3182 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3183 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 3184 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3185 // CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 3186 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3187 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3188 // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3189 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3190 // CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 3191 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3192 // CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3193 // CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3194 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3195 // CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 3196 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3197 // CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3198 // CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3199 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3200 // CHECK14-NEXT: ret i32 [[TMP6]] 3201 // 3202 // 3203 // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3204 // CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3205 // CHECK14-NEXT: entry: 3206 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3207 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3208 // CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 3209 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3210 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3211 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3212 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3213 // CHECK14-NEXT: store i32 1, i32* [[B]], align 4 3214 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3215 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3216 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3217 // CHECK14-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3218 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3219 // CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 3220 // CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3221 // CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3222 // CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 3223 // CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3224 // CHECK14-NEXT: store double 2.500000e+00, double* [[A2]], align 8 3225 // CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3226 // CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 3227 // CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 3228 // CHECK14-NEXT: ret i32 [[CONV4]] 3229 // 3230 // 3231 // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici 3232 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 3233 // CHECK14-NEXT: entry: 3234 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3235 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3236 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3237 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3238 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3239 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3240 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3241 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 3242 // CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3243 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3244 // CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 3245 // CHECK14-NEXT: ret i32 [[ADD2]] 3246 // 3247 // 3248 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3249 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 3250 // CHECK14-NEXT: entry: 3251 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3252 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 3253 // CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 3254 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3255 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3256 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 3257 // CHECK14-NEXT: store i16 1, i16* [[B]], align 2 3258 // CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 3259 // CHECK14-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 3260 // CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 3261 // CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3262 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3263 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 3264 // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3265 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3266 // CHECK14-NEXT: ret i32 [[TMP3]] 3267 // 3268 // 3269 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari 3270 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3271 // CHECK15-NEXT: entry: 3272 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3273 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 3274 // CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3275 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3276 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 3277 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3278 // CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 3279 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3280 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3281 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3282 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3283 // CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 3284 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3285 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3286 // CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3287 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3288 // CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 3289 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3290 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3291 // CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3292 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3293 // CHECK15-NEXT: ret i32 [[TMP6]] 3294 // 3295 // 3296 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3297 // CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3298 // CHECK15-NEXT: entry: 3299 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3300 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3301 // CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 3302 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3303 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3304 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3305 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3306 // CHECK15-NEXT: store i32 1, i32* [[B]], align 4 3307 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3308 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3309 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3310 // CHECK15-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3311 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3312 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 3313 // CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3314 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3315 // CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 3316 // CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3317 // CHECK15-NEXT: store double 2.500000e+00, double* [[A2]], align 4 3318 // CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3319 // CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 3320 // CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 3321 // CHECK15-NEXT: ret i32 [[CONV4]] 3322 // 3323 // 3324 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici 3325 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 3326 // CHECK15-NEXT: entry: 3327 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3328 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3329 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3330 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3331 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3332 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3333 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3334 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 3335 // CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3336 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3337 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 3338 // CHECK15-NEXT: ret i32 [[ADD2]] 3339 // 3340 // 3341 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3342 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 3343 // CHECK15-NEXT: entry: 3344 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3345 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 3346 // CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 3347 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3348 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3349 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 3350 // CHECK15-NEXT: store i16 1, i16* [[B]], align 2 3351 // CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 3352 // CHECK15-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 3353 // CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 3354 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3355 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3356 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 3357 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3358 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3359 // CHECK15-NEXT: ret i32 [[TMP3]] 3360 // 3361 // 3362 // CHECK16-LABEL: define {{[^@]+}}@_Z3bari 3363 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3364 // CHECK16-NEXT: entry: 3365 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3366 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 3367 // CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3368 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3369 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 3370 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3371 // CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 3372 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3373 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3374 // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3375 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3376 // CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 3377 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3378 // CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3379 // CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3380 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3381 // CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 3382 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3383 // CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3384 // CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3385 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3386 // CHECK16-NEXT: ret i32 [[TMP6]] 3387 // 3388 // 3389 // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3390 // CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3391 // CHECK16-NEXT: entry: 3392 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3393 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3394 // CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 3395 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3396 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3397 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3398 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3399 // CHECK16-NEXT: store i32 1, i32* [[B]], align 4 3400 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3401 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3402 // CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3403 // CHECK16-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3404 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3405 // CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 3406 // CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3407 // CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3408 // CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 3409 // CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3410 // CHECK16-NEXT: store double 2.500000e+00, double* [[A2]], align 4 3411 // CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3412 // CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 3413 // CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 3414 // CHECK16-NEXT: ret i32 [[CONV4]] 3415 // 3416 // 3417 // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici 3418 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 3419 // CHECK16-NEXT: entry: 3420 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3421 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3422 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3423 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3424 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3425 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3426 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3427 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 3428 // CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3429 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3430 // CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 3431 // CHECK16-NEXT: ret i32 [[ADD2]] 3432 // 3433 // 3434 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3435 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 3436 // CHECK16-NEXT: entry: 3437 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3438 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 3439 // CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 3440 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3441 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3442 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 3443 // CHECK16-NEXT: store i16 1, i16* [[B]], align 2 3444 // CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 3445 // CHECK16-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 3446 // CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 3447 // CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3448 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3449 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 3450 // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3451 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3452 // CHECK16-NEXT: ret i32 [[TMP3]] 3453 // 3454 // 3455 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari 3456 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3457 // CHECK17-NEXT: entry: 3458 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3459 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 3460 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 3461 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3462 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 3463 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3464 // CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 3465 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3466 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3467 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3468 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3469 // CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 3470 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3471 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3472 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3473 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3474 // CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 3475 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3476 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3477 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3478 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3479 // CHECK17-NEXT: ret i32 [[TMP6]] 3480 // 3481 // 3482 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3483 // CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3484 // CHECK17-NEXT: entry: 3485 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3486 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3487 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 3488 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3489 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3490 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3491 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3492 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3493 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3494 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 3495 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 3496 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 3497 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3498 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3499 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3500 // CHECK17-NEXT: store i32 1, i32* [[B]], align 4 3501 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3502 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3503 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3504 // CHECK17-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3505 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3506 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3507 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 3508 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 3509 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3510 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3511 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 3512 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3513 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3514 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3515 // CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 3516 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 3517 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3518 // CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 3519 // CHECK17-NEXT: store double* [[A]], double** [[TMP9]], align 8 3520 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3521 // CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 3522 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3523 // CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 3524 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 3525 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3526 // CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 3527 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 3528 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3529 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 3530 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3531 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 3532 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 3533 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3534 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 3535 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 3536 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3537 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 3538 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3539 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3540 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3541 // CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 3542 // CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 3543 // CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3544 // CHECK17: omp_offload.failed: 3545 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] 3546 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 3547 // CHECK17: omp_offload.cont: 3548 // CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3549 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3550 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 3551 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 3552 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3553 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 3554 // CHECK17-NEXT: store double* [[A3]], double** [[TMP29]], align 8 3555 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 3556 // CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 3557 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3558 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3559 // CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) 3560 // CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 3561 // CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 3562 // CHECK17: omp_offload.failed7: 3563 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 3564 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] 3565 // CHECK17: omp_offload.cont8: 3566 // CHECK17-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3567 // CHECK17-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 3568 // CHECK17-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 3569 // CHECK17-NEXT: ret i32 [[CONV10]] 3570 // 3571 // 3572 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici 3573 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 3574 // CHECK17-NEXT: entry: 3575 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3576 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3577 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3578 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 3579 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 3580 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 3581 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3582 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 3583 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 3584 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 3585 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 3586 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3587 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3588 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3589 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3590 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3591 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 3592 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3593 // CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3594 // CHECK17-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 3595 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 3596 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3597 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 3598 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 3599 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3600 // CHECK17-NEXT: store i8* null, i8** [[TMP7]], align 8 3601 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3602 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3603 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3604 // CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) 3605 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 3606 // CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3607 // CHECK17: omp_offload.failed: 3608 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] 3609 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 3610 // CHECK17: omp_offload.cont: 3611 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 3612 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 3613 // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3614 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3615 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* 3616 // CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 3617 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 3618 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3619 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 3620 // CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 3621 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3622 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 3623 // CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 3624 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 3625 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 3626 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3627 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3628 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3629 // CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 3630 // CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 3631 // CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 3632 // CHECK17: omp_offload.failed7: 3633 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] 3634 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] 3635 // CHECK17: omp_offload.cont8: 3636 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 3637 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 3638 // CHECK17-NEXT: ret i32 [[ADD9]] 3639 // 3640 // 3641 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3642 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 3643 // CHECK17-NEXT: entry: 3644 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3645 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 3646 // CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 3647 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3648 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3649 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3650 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3651 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3652 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3653 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3654 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3655 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 3656 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) 3657 // CHECK17-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 3658 // CHECK17-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3659 // CHECK17: omp_offload.failed: 3660 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 3661 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 3662 // CHECK17: omp_offload.cont: 3663 // CHECK17-NEXT: store i16 1, i16* [[B]], align 2 3664 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 3665 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 3666 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3667 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3668 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 3669 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 3670 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 3671 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* 3672 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 3673 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 3674 // CHECK17-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 3675 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* 3676 // CHECK17-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 3677 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3678 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3679 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 3680 // CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 3681 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3682 // CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 3683 // CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 3684 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3685 // CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 3686 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3687 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 3688 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 3689 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3690 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 3691 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 3692 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3693 // CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 3694 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3695 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 3696 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 3697 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3698 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 3699 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 3700 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3701 // CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 3702 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3703 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3704 // CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 3705 // CHECK17-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 3706 // CHECK17-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) 3707 // CHECK17-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 3708 // CHECK17-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 3709 // CHECK17: omp_offload.failed3: 3710 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] 3711 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT4]] 3712 // CHECK17: omp_offload.cont4: 3713 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 3714 // CHECK17-NEXT: ret i32 [[TMP30]] 3715 // 3716 // 3717 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 3718 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 3719 // CHECK17-NEXT: entry: 3720 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3721 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3722 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3723 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3724 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3725 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3726 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3727 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3728 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3729 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3730 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3731 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 3732 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 3733 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 3734 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3735 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 3736 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 3737 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 3738 // CHECK17-NEXT: ret void 3739 // 3740 // 3741 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 3742 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 3743 // CHECK17-NEXT: entry: 3744 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3745 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3746 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3747 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3748 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3749 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3750 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3751 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3752 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3753 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3754 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3755 // CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 3756 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 3757 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3758 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 3759 // CHECK17-NEXT: ret void 3760 // 3761 // 3762 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 3763 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 3764 // CHECK17-NEXT: entry: 3765 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3766 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3767 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3768 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3769 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 3770 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 3771 // CHECK17-NEXT: ret void 3772 // 3773 // 3774 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 3775 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 3776 // CHECK17-NEXT: entry: 3777 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3778 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3779 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3780 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3781 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3782 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3783 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3784 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3785 // CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 3786 // CHECK17-NEXT: ret void 3787 // 3788 // 3789 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 3790 // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 3791 // CHECK17-NEXT: entry: 3792 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3793 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3794 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3795 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3796 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3797 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 3798 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 3799 // CHECK17-NEXT: ret void 3800 // 3801 // 3802 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 3803 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 3804 // CHECK17-NEXT: entry: 3805 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3806 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3807 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3808 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3809 // CHECK17-NEXT: ret void 3810 // 3811 // 3812 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 3813 // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 3814 // CHECK17-NEXT: entry: 3815 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3816 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3817 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3818 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3819 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3820 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 3821 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 3822 // CHECK17-NEXT: ret void 3823 // 3824 // 3825 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 3826 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 3827 // CHECK17-NEXT: entry: 3828 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3829 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3830 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3831 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3832 // CHECK17-NEXT: ret void 3833 // 3834 // 3835 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 3836 // CHECK17-SAME: () #[[ATTR1]] { 3837 // CHECK17-NEXT: entry: 3838 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3839 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 3840 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 3841 // CHECK17-NEXT: ret void 3842 // 3843 // 3844 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 3845 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 3846 // CHECK17-NEXT: entry: 3847 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3848 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3849 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3850 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3851 // CHECK17-NEXT: ret void 3852 // 3853 // 3854 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 3855 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 3856 // CHECK17-NEXT: entry: 3857 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3858 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3859 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3860 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3861 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3862 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3863 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3864 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3865 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3866 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3867 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 3868 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 3869 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 3870 // CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 3871 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 3872 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 3873 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3874 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 3875 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 3876 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 3877 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 3878 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 3879 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 3880 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 3881 // CHECK17-NEXT: ret void 3882 // 3883 // 3884 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 3885 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 3886 // CHECK17-NEXT: entry: 3887 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3888 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3889 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3890 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3891 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3892 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3893 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3894 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3895 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3896 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 3897 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 3898 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 3899 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3900 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 3901 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 3902 // CHECK17-NEXT: ret void 3903 // 3904 // 3905 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3906 // CHECK17-SAME: () #[[ATTR3:[0-9]+]] { 3907 // CHECK17-NEXT: entry: 3908 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 3909 // CHECK17-NEXT: ret void 3910 // 3911 // 3912 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari 3913 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3914 // CHECK18-NEXT: entry: 3915 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3916 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 3917 // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 3918 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3919 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 3920 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3921 // CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 3922 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3923 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3924 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3925 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3926 // CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 3927 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3928 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3929 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3930 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3931 // CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 3932 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3933 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3934 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3935 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3936 // CHECK18-NEXT: ret i32 [[TMP6]] 3937 // 3938 // 3939 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3940 // CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3941 // CHECK18-NEXT: entry: 3942 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3943 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3944 // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 3945 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3946 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3947 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3948 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3949 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3950 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3951 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 3952 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 3953 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 3954 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3955 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3956 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3957 // CHECK18-NEXT: store i32 1, i32* [[B]], align 4 3958 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3959 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3960 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3961 // CHECK18-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3962 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3963 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3964 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 3965 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 3966 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3967 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3968 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 3969 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3970 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3971 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3972 // CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 3973 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 3974 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3975 // CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 3976 // CHECK18-NEXT: store double* [[A]], double** [[TMP9]], align 8 3977 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3978 // CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 3979 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3980 // CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 3981 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 3982 // CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3983 // CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 3984 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 3985 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3986 // CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 3987 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3988 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 3989 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 3990 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3991 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 3992 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 3993 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3994 // CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 3995 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3996 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3997 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3998 // CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 3999 // CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4000 // CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4001 // CHECK18: omp_offload.failed: 4002 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] 4003 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 4004 // CHECK18: omp_offload.cont: 4005 // CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4006 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 4007 // CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 4008 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 4009 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 4010 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 4011 // CHECK18-NEXT: store double* [[A3]], double** [[TMP29]], align 8 4012 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 4013 // CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 4014 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 4015 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 4016 // CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) 4017 // CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 4018 // CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 4019 // CHECK18: omp_offload.failed7: 4020 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 4021 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] 4022 // CHECK18: omp_offload.cont8: 4023 // CHECK18-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4024 // CHECK18-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 4025 // CHECK18-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 4026 // CHECK18-NEXT: ret i32 [[CONV10]] 4027 // 4028 // 4029 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici 4030 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 4031 // CHECK18-NEXT: entry: 4032 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4033 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4034 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4035 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 4036 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 4037 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 4038 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4039 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 4040 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 4041 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 4042 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 4043 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4044 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4045 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 4046 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4047 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 4048 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 4049 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4050 // CHECK18-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4051 // CHECK18-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 4052 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 4053 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4054 // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 4055 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 4056 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4057 // CHECK18-NEXT: store i8* null, i8** [[TMP7]], align 8 4058 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4059 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4060 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4061 // CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) 4062 // CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4063 // CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4064 // CHECK18: omp_offload.failed: 4065 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] 4066 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 4067 // CHECK18: omp_offload.cont: 4068 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 4069 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 4070 // CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4071 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4072 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* 4073 // CHECK18-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 4074 // CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 4075 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 4076 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 4077 // CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 4078 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 4079 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 4080 // CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 4081 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 4082 // CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 4083 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 4084 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 4085 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4086 // CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 4087 // CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4088 // CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 4089 // CHECK18: omp_offload.failed7: 4090 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] 4091 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] 4092 // CHECK18: omp_offload.cont8: 4093 // CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 4094 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 4095 // CHECK18-NEXT: ret i32 [[ADD9]] 4096 // 4097 // 4098 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4099 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 4100 // CHECK18-NEXT: entry: 4101 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4102 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 4103 // CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 4104 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 4105 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4106 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4107 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4108 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 4109 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 4110 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 4111 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4112 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 4113 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) 4114 // CHECK18-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 4115 // CHECK18-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4116 // CHECK18: omp_offload.failed: 4117 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 4118 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 4119 // CHECK18: omp_offload.cont: 4120 // CHECK18-NEXT: store i16 1, i16* [[B]], align 2 4121 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 4122 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 4123 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4124 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4125 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 4126 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 4127 // CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 4128 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* 4129 // CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 4130 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 4131 // CHECK18-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 4132 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* 4133 // CHECK18-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 4134 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4135 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4136 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 4137 // CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 4138 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4139 // CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 4140 // CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 4141 // CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4142 // CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 4143 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4144 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 4145 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 4146 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4147 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 4148 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 4149 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4150 // CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 4151 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4152 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 4153 // CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 4154 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4155 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 4156 // CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 4157 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4158 // CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 4159 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4160 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4161 // CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 4162 // CHECK18-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 4163 // CHECK18-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) 4164 // CHECK18-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 4165 // CHECK18-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 4166 // CHECK18: omp_offload.failed3: 4167 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] 4168 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT4]] 4169 // CHECK18: omp_offload.cont4: 4170 // CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 4171 // CHECK18-NEXT: ret i32 [[TMP30]] 4172 // 4173 // 4174 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 4175 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 4176 // CHECK18-NEXT: entry: 4177 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4178 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4179 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4180 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4181 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4182 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4183 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4184 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4185 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4186 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4187 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4188 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 4189 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 4190 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 4191 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4192 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 4193 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 4194 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 4195 // CHECK18-NEXT: ret void 4196 // 4197 // 4198 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 4199 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 4200 // CHECK18-NEXT: entry: 4201 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4202 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4203 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4204 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4205 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4206 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4207 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4208 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4209 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4210 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4211 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4212 // CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 4213 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 4214 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4215 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 4216 // CHECK18-NEXT: ret void 4217 // 4218 // 4219 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 4220 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 4221 // CHECK18-NEXT: entry: 4222 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4223 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4224 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4225 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4226 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 4227 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 4228 // CHECK18-NEXT: ret void 4229 // 4230 // 4231 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 4232 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 4233 // CHECK18-NEXT: entry: 4234 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4235 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4236 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4237 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4238 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4239 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4240 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4241 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4242 // CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 4243 // CHECK18-NEXT: ret void 4244 // 4245 // 4246 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 4247 // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4248 // CHECK18-NEXT: entry: 4249 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4250 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4251 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4252 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4253 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4254 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 4255 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 4256 // CHECK18-NEXT: ret void 4257 // 4258 // 4259 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 4260 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4261 // CHECK18-NEXT: entry: 4262 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4263 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4264 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4265 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4266 // CHECK18-NEXT: ret void 4267 // 4268 // 4269 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 4270 // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4271 // CHECK18-NEXT: entry: 4272 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4273 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4274 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4275 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4276 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4277 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 4278 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 4279 // CHECK18-NEXT: ret void 4280 // 4281 // 4282 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 4283 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4284 // CHECK18-NEXT: entry: 4285 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4286 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4287 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4288 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4289 // CHECK18-NEXT: ret void 4290 // 4291 // 4292 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 4293 // CHECK18-SAME: () #[[ATTR1]] { 4294 // CHECK18-NEXT: entry: 4295 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4296 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 4297 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 4298 // CHECK18-NEXT: ret void 4299 // 4300 // 4301 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 4302 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4303 // CHECK18-NEXT: entry: 4304 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4305 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4306 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4307 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4308 // CHECK18-NEXT: ret void 4309 // 4310 // 4311 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 4312 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4313 // CHECK18-NEXT: entry: 4314 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4315 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4316 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4317 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4318 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4319 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4320 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4321 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4322 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4323 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4324 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 4325 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 4326 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 4327 // CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 4328 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 4329 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 4330 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4331 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 4332 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 4333 // CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 4334 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 4335 // CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 4336 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 4337 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 4338 // CHECK18-NEXT: ret void 4339 // 4340 // 4341 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 4342 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 4343 // CHECK18-NEXT: entry: 4344 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4345 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4346 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4347 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4348 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4349 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4350 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4351 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4352 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4353 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 4354 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 4355 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 4356 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4357 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 4358 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 4359 // CHECK18-NEXT: ret void 4360 // 4361 // 4362 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4363 // CHECK18-SAME: () #[[ATTR3:[0-9]+]] { 4364 // CHECK18-NEXT: entry: 4365 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 4366 // CHECK18-NEXT: ret void 4367 // 4368 // 4369 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari 4370 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 4371 // CHECK19-NEXT: entry: 4372 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4373 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 4374 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 4375 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4376 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 4377 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4378 // CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 4379 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 4380 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4381 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 4382 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4383 // CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 4384 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4385 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4386 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 4387 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4388 // CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 4389 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4390 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4391 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 4392 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 4393 // CHECK19-NEXT: ret i32 [[TMP6]] 4394 // 4395 // 4396 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4397 // CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4398 // CHECK19-NEXT: entry: 4399 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4400 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4401 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 4402 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4403 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4404 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4405 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4406 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4407 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4408 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 4409 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 4410 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 4411 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4412 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4413 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4414 // CHECK19-NEXT: store i32 1, i32* [[B]], align 4 4415 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4416 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 4417 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 4418 // CHECK19-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 4419 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 4420 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 4421 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 4422 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4423 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4424 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4425 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 4426 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4427 // CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 4428 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 4429 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4430 // CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 4431 // CHECK19-NEXT: store double* [[A]], double** [[TMP9]], align 4 4432 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4433 // CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 4434 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4435 // CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 4436 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 4437 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4438 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 4439 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 4440 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4441 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 4442 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4443 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4444 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 4445 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4446 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4447 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 4448 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4449 // CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 4450 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4451 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4452 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4453 // CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 4454 // CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4455 // CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4456 // CHECK19: omp_offload.failed: 4457 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] 4458 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 4459 // CHECK19: omp_offload.cont: 4460 // CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4461 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4462 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 4463 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 4464 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4465 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 4466 // CHECK19-NEXT: store double* [[A2]], double** [[TMP29]], align 4 4467 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 4468 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 4469 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4470 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4471 // CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) 4472 // CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 4473 // CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 4474 // CHECK19: omp_offload.failed6: 4475 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 4476 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] 4477 // CHECK19: omp_offload.cont7: 4478 // CHECK19-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4479 // CHECK19-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 4480 // CHECK19-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 4481 // CHECK19-NEXT: ret i32 [[CONV]] 4482 // 4483 // 4484 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici 4485 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 4486 // CHECK19-NEXT: entry: 4487 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4488 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4489 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4490 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 4491 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 4492 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 4493 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4494 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 4495 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 4496 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 4497 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 4498 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4499 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4500 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 4501 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4502 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4503 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4504 // CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4505 // CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 4506 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 4507 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4508 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4509 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 4510 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4511 // CHECK19-NEXT: store i8* null, i8** [[TMP7]], align 4 4512 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4513 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4514 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4515 // CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) 4516 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4517 // CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4518 // CHECK19: omp_offload.failed: 4519 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] 4520 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 4521 // CHECK19: omp_offload.cont: 4522 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 4523 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 4524 // CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4525 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4526 // CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 4527 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 4528 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4529 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4530 // CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 4531 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4532 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4533 // CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 4534 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 4535 // CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 4536 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4537 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4538 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4539 // CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 4540 // CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4541 // CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 4542 // CHECK19: omp_offload.failed6: 4543 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] 4544 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] 4545 // CHECK19: omp_offload.cont7: 4546 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 4547 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 4548 // CHECK19-NEXT: ret i32 [[ADD8]] 4549 // 4550 // 4551 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4552 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 4553 // CHECK19-NEXT: entry: 4554 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4555 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 4556 // CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 4557 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 4558 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4559 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4560 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4561 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4562 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4563 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4564 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4565 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 4566 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) 4567 // CHECK19-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 4568 // CHECK19-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4569 // CHECK19: omp_offload.failed: 4570 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 4571 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 4572 // CHECK19: omp_offload.cont: 4573 // CHECK19-NEXT: store i16 1, i16* [[B]], align 2 4574 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 4575 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 4576 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4577 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 4578 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 4579 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 4580 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 4581 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 4582 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 4583 // CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 4584 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* 4585 // CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 4586 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4587 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4588 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 4589 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 4590 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4591 // CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 4592 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 4593 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4594 // CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 4595 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4596 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 4597 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 4598 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4599 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4600 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 4601 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4602 // CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 4603 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4604 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 4605 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 4606 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4607 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 4608 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 4609 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4610 // CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 4611 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4612 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4613 // CHECK19-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 4614 // CHECK19-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 4615 // CHECK19-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) 4616 // CHECK19-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 4617 // CHECK19-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] 4618 // CHECK19: omp_offload.failed2: 4619 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] 4620 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT3]] 4621 // CHECK19: omp_offload.cont3: 4622 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 4623 // CHECK19-NEXT: ret i32 [[TMP30]] 4624 // 4625 // 4626 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 4627 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 4628 // CHECK19-NEXT: entry: 4629 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4630 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4631 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4632 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4633 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4634 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4635 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4636 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4637 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4638 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4639 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 4640 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 4641 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 4642 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 4643 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 4644 // CHECK19-NEXT: ret void 4645 // 4646 // 4647 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 4648 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 4649 // CHECK19-NEXT: entry: 4650 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4651 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4652 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4653 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4654 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4655 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4656 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4657 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4658 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4659 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 4660 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 4661 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4662 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4663 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 4664 // CHECK19-NEXT: ret void 4665 // 4666 // 4667 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 4668 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 4669 // CHECK19-NEXT: entry: 4670 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4671 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4672 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4673 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4674 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 4675 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 4676 // CHECK19-NEXT: ret void 4677 // 4678 // 4679 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 4680 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 4681 // CHECK19-NEXT: entry: 4682 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4683 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4684 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4685 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4686 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4687 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4688 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4689 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4690 // CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 4691 // CHECK19-NEXT: ret void 4692 // 4693 // 4694 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 4695 // CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4696 // CHECK19-NEXT: entry: 4697 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4698 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4699 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4700 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4701 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 4702 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 4703 // CHECK19-NEXT: ret void 4704 // 4705 // 4706 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 4707 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4708 // CHECK19-NEXT: entry: 4709 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4710 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4711 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4712 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4713 // CHECK19-NEXT: ret void 4714 // 4715 // 4716 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 4717 // CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4718 // CHECK19-NEXT: entry: 4719 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4720 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4721 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4722 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4723 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 4724 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 4725 // CHECK19-NEXT: ret void 4726 // 4727 // 4728 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 4729 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4730 // CHECK19-NEXT: entry: 4731 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4732 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4733 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4734 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4735 // CHECK19-NEXT: ret void 4736 // 4737 // 4738 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 4739 // CHECK19-SAME: () #[[ATTR1]] { 4740 // CHECK19-NEXT: entry: 4741 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4742 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 4743 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 4744 // CHECK19-NEXT: ret void 4745 // 4746 // 4747 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 4748 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4749 // CHECK19-NEXT: entry: 4750 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4751 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4752 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4753 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4754 // CHECK19-NEXT: ret void 4755 // 4756 // 4757 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 4758 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4759 // CHECK19-NEXT: entry: 4760 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4761 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4762 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4763 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4764 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4765 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4766 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4767 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4768 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4769 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 4770 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 4771 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 4772 // CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 4773 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 4774 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 4775 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 4776 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 4777 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 4778 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 4779 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 4780 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 4781 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 4782 // CHECK19-NEXT: ret void 4783 // 4784 // 4785 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 4786 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 4787 // CHECK19-NEXT: entry: 4788 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4789 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4790 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4791 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4792 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4793 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4794 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4795 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4796 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 4797 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 4798 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 4799 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4800 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 4801 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4802 // CHECK19-NEXT: ret void 4803 // 4804 // 4805 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4806 // CHECK19-SAME: () #[[ATTR3:[0-9]+]] { 4807 // CHECK19-NEXT: entry: 4808 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 4809 // CHECK19-NEXT: ret void 4810 // 4811 // 4812 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari 4813 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 4814 // CHECK20-NEXT: entry: 4815 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4816 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 4817 // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 4818 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4819 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 4820 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4821 // CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 4822 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 4823 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4824 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 4825 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4826 // CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 4827 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4828 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4829 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 4830 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4831 // CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 4832 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4833 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4834 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 4835 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 4836 // CHECK20-NEXT: ret i32 [[TMP6]] 4837 // 4838 // 4839 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4840 // CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4841 // CHECK20-NEXT: entry: 4842 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4843 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4844 // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 4845 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4846 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4847 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4848 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4849 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4850 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4851 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 4852 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 4853 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 4854 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4855 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4856 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4857 // CHECK20-NEXT: store i32 1, i32* [[B]], align 4 4858 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4859 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 4860 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 4861 // CHECK20-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 4862 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 4863 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 4864 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 4865 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4866 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4867 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4868 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 4869 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4870 // CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 4871 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 4872 // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4873 // CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 4874 // CHECK20-NEXT: store double* [[A]], double** [[TMP9]], align 4 4875 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4876 // CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 4877 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4878 // CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 4879 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 4880 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4881 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 4882 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 4883 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4884 // CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 4885 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4886 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4887 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 4888 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4889 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4890 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 4891 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4892 // CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 4893 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4894 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4895 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4896 // CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 4897 // CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4898 // CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4899 // CHECK20: omp_offload.failed: 4900 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] 4901 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 4902 // CHECK20: omp_offload.cont: 4903 // CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4904 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4905 // CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 4906 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 4907 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4908 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 4909 // CHECK20-NEXT: store double* [[A2]], double** [[TMP29]], align 4 4910 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 4911 // CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 4912 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4913 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4914 // CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1024, i32 0) 4915 // CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 4916 // CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 4917 // CHECK20: omp_offload.failed6: 4918 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 4919 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] 4920 // CHECK20: omp_offload.cont7: 4921 // CHECK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4922 // CHECK20-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 4923 // CHECK20-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 4924 // CHECK20-NEXT: ret i32 [[CONV]] 4925 // 4926 // 4927 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici 4928 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 4929 // CHECK20-NEXT: entry: 4930 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4931 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4932 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4933 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 4934 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 4935 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 4936 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4937 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 4938 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 4939 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 4940 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 4941 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4942 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4943 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 4944 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4945 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4946 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4947 // CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4948 // CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 4949 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 4950 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4951 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4952 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 4953 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4954 // CHECK20-NEXT: store i8* null, i8** [[TMP7]], align 4 4955 // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4956 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4957 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4958 // CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 [[TMP10]], i32 0) 4959 // CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4960 // CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4961 // CHECK20: omp_offload.failed: 4962 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] 4963 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 4964 // CHECK20: omp_offload.cont: 4965 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 4966 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 4967 // CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4968 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4969 // CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 4970 // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 4971 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4972 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4973 // CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 4974 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4975 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4976 // CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 4977 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 4978 // CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 4979 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4980 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4981 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4982 // CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 [[TMP23]], i32 0) 4983 // CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4984 // CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 4985 // CHECK20: omp_offload.failed6: 4986 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] 4987 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] 4988 // CHECK20: omp_offload.cont7: 4989 // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 4990 // CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 4991 // CHECK20-NEXT: ret i32 [[ADD8]] 4992 // 4993 // 4994 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4995 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 4996 // CHECK20-NEXT: entry: 4997 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4998 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 4999 // CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 5000 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5001 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5002 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5003 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5004 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 5005 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 5006 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 5007 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5008 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 5009 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 20, i32 0) 5010 // CHECK20-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 5011 // CHECK20-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5012 // CHECK20: omp_offload.failed: 5013 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 5014 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 5015 // CHECK20: omp_offload.cont: 5016 // CHECK20-NEXT: store i16 1, i16* [[B]], align 2 5017 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 5018 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 5019 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5020 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 5021 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 5022 // CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 5023 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 5024 // CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 5025 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 5026 // CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 5027 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* 5028 // CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 5029 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5030 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5031 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 5032 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 5033 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5034 // CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 5035 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 5036 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5037 // CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 5038 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5039 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 5040 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 5041 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5042 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 5043 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 5044 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5045 // CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 5046 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5047 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 5048 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 5049 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5050 // CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 5051 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 5052 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5053 // CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 5054 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5055 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5056 // CHECK20-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 5057 // CHECK20-NEXT: [[TMP27:%.*]] = sext i16 [[TMP26]] to i32 5058 // CHECK20-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 [[TMP27]], i32 0) 5059 // CHECK20-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 5060 // CHECK20-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] 5061 // CHECK20: omp_offload.failed2: 5062 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] 5063 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT3]] 5064 // CHECK20: omp_offload.cont3: 5065 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 5066 // CHECK20-NEXT: ret i32 [[TMP30]] 5067 // 5068 // 5069 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 5070 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 5071 // CHECK20-NEXT: entry: 5072 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5073 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5074 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5075 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5076 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5077 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5078 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5079 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5080 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5081 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5082 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 5083 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 5084 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 5085 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 5086 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 5087 // CHECK20-NEXT: ret void 5088 // 5089 // 5090 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 5091 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 5092 // CHECK20-NEXT: entry: 5093 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5094 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5095 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5096 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5097 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5098 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5099 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5100 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5101 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5102 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 5103 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 5104 // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5105 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5106 // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 5107 // CHECK20-NEXT: ret void 5108 // 5109 // 5110 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 5111 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 5112 // CHECK20-NEXT: entry: 5113 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5114 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5115 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5116 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5117 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 5118 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 5119 // CHECK20-NEXT: ret void 5120 // 5121 // 5122 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 5123 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 5124 // CHECK20-NEXT: entry: 5125 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5126 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5127 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5128 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5129 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5130 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5131 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5132 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5133 // CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 5134 // CHECK20-NEXT: ret void 5135 // 5136 // 5137 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 5138 // CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 5139 // CHECK20-NEXT: entry: 5140 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5141 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5142 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5143 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5144 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 5145 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 5146 // CHECK20-NEXT: ret void 5147 // 5148 // 5149 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 5150 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 5151 // CHECK20-NEXT: entry: 5152 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5153 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5154 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5155 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5156 // CHECK20-NEXT: ret void 5157 // 5158 // 5159 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 5160 // CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 5161 // CHECK20-NEXT: entry: 5162 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5163 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5164 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5165 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5166 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 5167 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 5168 // CHECK20-NEXT: ret void 5169 // 5170 // 5171 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 5172 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 5173 // CHECK20-NEXT: entry: 5174 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5175 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5176 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5177 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5178 // CHECK20-NEXT: ret void 5179 // 5180 // 5181 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 5182 // CHECK20-SAME: () #[[ATTR1]] { 5183 // CHECK20-NEXT: entry: 5184 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5185 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 5186 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 5187 // CHECK20-NEXT: ret void 5188 // 5189 // 5190 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 5191 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 5192 // CHECK20-NEXT: entry: 5193 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5194 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5195 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5196 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5197 // CHECK20-NEXT: ret void 5198 // 5199 // 5200 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 5201 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 5202 // CHECK20-NEXT: entry: 5203 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5204 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5205 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5206 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5207 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5208 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5209 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5210 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5211 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5212 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 5213 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 5214 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 5215 // CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 5216 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 5217 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 5218 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 5219 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 5220 // CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 5221 // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 5222 // CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 5223 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 5224 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 5225 // CHECK20-NEXT: ret void 5226 // 5227 // 5228 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 5229 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 5230 // CHECK20-NEXT: entry: 5231 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5232 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5233 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5234 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5235 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5236 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5237 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5238 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5239 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 5240 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 5241 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 5242 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5243 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 5244 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5245 // CHECK20-NEXT: ret void 5246 // 5247 // 5248 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5249 // CHECK20-SAME: () #[[ATTR3:[0-9]+]] { 5250 // CHECK20-NEXT: entry: 5251 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 5252 // CHECK20-NEXT: ret void 5253 // 5254 // 5255 // CHECK21-LABEL: define {{[^@]+}}@_Z3bari 5256 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5257 // CHECK21-NEXT: entry: 5258 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5259 // CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 5260 // CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 5261 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5262 // CHECK21-NEXT: store i32 0, i32* [[A]], align 4 5263 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5264 // CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 5265 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5266 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5267 // CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5268 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5269 // CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 5270 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5271 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5272 // CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5273 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5274 // CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 5275 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5276 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5277 // CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5278 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5279 // CHECK21-NEXT: ret i32 [[TMP6]] 5280 // 5281 // 5282 // CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5283 // CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5284 // CHECK21-NEXT: entry: 5285 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5286 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5287 // CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 5288 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5289 // CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5290 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5291 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5292 // CHECK21-NEXT: store i32 1, i32* [[B]], align 4 5293 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5294 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 5295 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 5296 // CHECK21-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 5297 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 5298 // CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 5299 // CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5300 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5301 // CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 5302 // CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5303 // CHECK21-NEXT: store double 2.500000e+00, double* [[A2]], align 8 5304 // CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5305 // CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 5306 // CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 5307 // CHECK21-NEXT: ret i32 [[CONV4]] 5308 // 5309 // 5310 // CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici 5311 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 5312 // CHECK21-NEXT: entry: 5313 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5314 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5315 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5316 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5317 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5318 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5319 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5320 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 5321 // CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5322 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5323 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 5324 // CHECK21-NEXT: ret i32 [[ADD2]] 5325 // 5326 // 5327 // CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5328 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 5329 // CHECK21-NEXT: entry: 5330 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5331 // CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 5332 // CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 5333 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5334 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5335 // CHECK21-NEXT: store i32 0, i32* [[A]], align 4 5336 // CHECK21-NEXT: store i16 1, i16* [[B]], align 2 5337 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 5338 // CHECK21-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 5339 // CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 5340 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5341 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 5342 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 5343 // CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5344 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5345 // CHECK21-NEXT: ret i32 [[TMP3]] 5346 // 5347 // 5348 // CHECK22-LABEL: define {{[^@]+}}@_Z3bari 5349 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5350 // CHECK22-NEXT: entry: 5351 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5352 // CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 5353 // CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 5354 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5355 // CHECK22-NEXT: store i32 0, i32* [[A]], align 4 5356 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5357 // CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 5358 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5359 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5360 // CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5361 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5362 // CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 5363 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5364 // CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5365 // CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5366 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5367 // CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 5368 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5369 // CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5370 // CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5371 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5372 // CHECK22-NEXT: ret i32 [[TMP6]] 5373 // 5374 // 5375 // CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5376 // CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5377 // CHECK22-NEXT: entry: 5378 // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5379 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5380 // CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 5381 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5382 // CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5383 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5384 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5385 // CHECK22-NEXT: store i32 1, i32* [[B]], align 4 5386 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5387 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 5388 // CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 5389 // CHECK22-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 5390 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 5391 // CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 5392 // CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5393 // CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5394 // CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 5395 // CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5396 // CHECK22-NEXT: store double 2.500000e+00, double* [[A2]], align 8 5397 // CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5398 // CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 5399 // CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 5400 // CHECK22-NEXT: ret i32 [[CONV4]] 5401 // 5402 // 5403 // CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici 5404 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 5405 // CHECK22-NEXT: entry: 5406 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5407 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5408 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5409 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5410 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5411 // CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5412 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5413 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 5414 // CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5415 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5416 // CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 5417 // CHECK22-NEXT: ret i32 [[ADD2]] 5418 // 5419 // 5420 // CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5421 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 5422 // CHECK22-NEXT: entry: 5423 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5424 // CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 5425 // CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 5426 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5427 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5428 // CHECK22-NEXT: store i32 0, i32* [[A]], align 4 5429 // CHECK22-NEXT: store i16 1, i16* [[B]], align 2 5430 // CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 5431 // CHECK22-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 5432 // CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 5433 // CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5434 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 5435 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 5436 // CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5437 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5438 // CHECK22-NEXT: ret i32 [[TMP3]] 5439 // 5440 // 5441 // CHECK23-LABEL: define {{[^@]+}}@_Z3bari 5442 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5443 // CHECK23-NEXT: entry: 5444 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5445 // CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 5446 // CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 5447 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5448 // CHECK23-NEXT: store i32 0, i32* [[A]], align 4 5449 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5450 // CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 5451 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5452 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5453 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5454 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5455 // CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 5456 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5457 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5458 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5459 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5460 // CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 5461 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5462 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5463 // CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5464 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5465 // CHECK23-NEXT: ret i32 [[TMP6]] 5466 // 5467 // 5468 // CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5469 // CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5470 // CHECK23-NEXT: entry: 5471 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5472 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5473 // CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 5474 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5475 // CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5476 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5477 // CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5478 // CHECK23-NEXT: store i32 1, i32* [[B]], align 4 5479 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5480 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 5481 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 5482 // CHECK23-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 5483 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 5484 // CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 5485 // CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5486 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5487 // CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 5488 // CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5489 // CHECK23-NEXT: store double 2.500000e+00, double* [[A2]], align 4 5490 // CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5491 // CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 5492 // CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 5493 // CHECK23-NEXT: ret i32 [[CONV4]] 5494 // 5495 // 5496 // CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici 5497 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 5498 // CHECK23-NEXT: entry: 5499 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5500 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5501 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5502 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5503 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5504 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5505 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5506 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 5507 // CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5508 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5509 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 5510 // CHECK23-NEXT: ret i32 [[ADD2]] 5511 // 5512 // 5513 // CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5514 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 5515 // CHECK23-NEXT: entry: 5516 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5517 // CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 5518 // CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 5519 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5520 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5521 // CHECK23-NEXT: store i32 0, i32* [[A]], align 4 5522 // CHECK23-NEXT: store i16 1, i16* [[B]], align 2 5523 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 5524 // CHECK23-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 5525 // CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 5526 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5527 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 5528 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 5529 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5530 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5531 // CHECK23-NEXT: ret i32 [[TMP3]] 5532 // 5533 // 5534 // CHECK24-LABEL: define {{[^@]+}}@_Z3bari 5535 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5536 // CHECK24-NEXT: entry: 5537 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5538 // CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 5539 // CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 5540 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5541 // CHECK24-NEXT: store i32 0, i32* [[A]], align 4 5542 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5543 // CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 5544 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5545 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5546 // CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5547 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5548 // CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 5549 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5550 // CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5551 // CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5552 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5553 // CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 5554 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5555 // CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5556 // CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5557 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5558 // CHECK24-NEXT: ret i32 [[TMP6]] 5559 // 5560 // 5561 // CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5562 // CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5563 // CHECK24-NEXT: entry: 5564 // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5565 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5566 // CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 5567 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5568 // CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5569 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5570 // CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5571 // CHECK24-NEXT: store i32 1, i32* [[B]], align 4 5572 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5573 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 5574 // CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 5575 // CHECK24-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 5576 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 5577 // CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 5578 // CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5579 // CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5580 // CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 5581 // CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5582 // CHECK24-NEXT: store double 2.500000e+00, double* [[A2]], align 4 5583 // CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5584 // CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 5585 // CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 5586 // CHECK24-NEXT: ret i32 [[CONV4]] 5587 // 5588 // 5589 // CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici 5590 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 5591 // CHECK24-NEXT: entry: 5592 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5593 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5594 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5595 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5596 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5597 // CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5598 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5599 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 5600 // CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5601 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5602 // CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 5603 // CHECK24-NEXT: ret i32 [[ADD2]] 5604 // 5605 // 5606 // CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5607 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 5608 // CHECK24-NEXT: entry: 5609 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5610 // CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 5611 // CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 5612 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5613 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5614 // CHECK24-NEXT: store i32 0, i32* [[A]], align 4 5615 // CHECK24-NEXT: store i16 1, i16* [[B]], align 2 5616 // CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 5617 // CHECK24-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 5618 // CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 5619 // CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5620 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 5621 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 5622 // CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5623 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5624 // CHECK24-NEXT: ret i32 [[TMP3]] 5625 // 5626 // 5627 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 5628 // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 5629 // CHECK25-NEXT: entry: 5630 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5631 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 5632 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5633 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5634 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5635 // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 5636 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5637 // CHECK25-NEXT: ret void 5638 // 5639 // 5640 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. 5641 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5642 // CHECK25-NEXT: entry: 5643 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5644 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5645 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5646 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5647 // CHECK25-NEXT: ret void 5648 // 5649 // 5650 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 5651 // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5652 // CHECK25-NEXT: entry: 5653 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5654 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5655 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5656 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5657 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5658 // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 5659 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 5660 // CHECK25-NEXT: ret void 5661 // 5662 // 5663 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 5664 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5665 // CHECK25-NEXT: entry: 5666 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5667 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5668 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5669 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5670 // CHECK25-NEXT: ret void 5671 // 5672 // 5673 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 5674 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5675 // CHECK25-NEXT: entry: 5676 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5677 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5678 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5679 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5680 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5681 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5682 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5683 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5684 // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5685 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5686 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5687 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 5688 // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 5689 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 5690 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 5691 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 5692 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 5693 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 5694 // CHECK25-NEXT: ret void 5695 // 5696 // 5697 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 5698 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 5699 // CHECK25-NEXT: entry: 5700 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5701 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5702 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5703 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5704 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5705 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5706 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5707 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5708 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5709 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5710 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5711 // CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 5712 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 5713 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5714 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 5715 // CHECK25-NEXT: ret void 5716 // 5717 // 5718 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 5719 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 5720 // CHECK25-NEXT: entry: 5721 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5722 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5723 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5724 // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5725 // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 5726 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 5727 // CHECK25-NEXT: ret void 5728 // 5729 // 5730 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 5731 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 5732 // CHECK25-NEXT: entry: 5733 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5734 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5735 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5736 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5737 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5738 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5739 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5740 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5741 // CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 5742 // CHECK25-NEXT: ret void 5743 // 5744 // 5745 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 5746 // CHECK25-SAME: () #[[ATTR0]] { 5747 // CHECK25-NEXT: entry: 5748 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5749 // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 5750 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 5751 // CHECK25-NEXT: ret void 5752 // 5753 // 5754 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 5755 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5756 // CHECK25-NEXT: entry: 5757 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5758 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5759 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5760 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5761 // CHECK25-NEXT: ret void 5762 // 5763 // 5764 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 5765 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5766 // CHECK25-NEXT: entry: 5767 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5768 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5769 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5770 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5771 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5772 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5773 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5774 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5775 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5776 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5777 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 5778 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 5779 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 5780 // CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 5781 // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 5782 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 5783 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5784 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 5785 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 5786 // CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 5787 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 5788 // CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 5789 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 5790 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 5791 // CHECK25-NEXT: ret void 5792 // 5793 // 5794 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 5795 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 5796 // CHECK25-NEXT: entry: 5797 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5798 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5799 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5800 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5801 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5802 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5803 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5804 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5805 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5806 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 5807 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 5808 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 5809 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5810 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 5811 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 5812 // CHECK25-NEXT: ret void 5813 // 5814 // 5815 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 5816 // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 5817 // CHECK26-NEXT: entry: 5818 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5819 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 5820 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5821 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5822 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5823 // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 5824 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5825 // CHECK26-NEXT: ret void 5826 // 5827 // 5828 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. 5829 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5830 // CHECK26-NEXT: entry: 5831 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5832 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5833 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5834 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5835 // CHECK26-NEXT: ret void 5836 // 5837 // 5838 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 5839 // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5840 // CHECK26-NEXT: entry: 5841 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5842 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5843 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5844 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5845 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5846 // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 5847 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 5848 // CHECK26-NEXT: ret void 5849 // 5850 // 5851 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 5852 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5853 // CHECK26-NEXT: entry: 5854 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5855 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5856 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5857 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5858 // CHECK26-NEXT: ret void 5859 // 5860 // 5861 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 5862 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5863 // CHECK26-NEXT: entry: 5864 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5865 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5866 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5867 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5868 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5869 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5870 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5871 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5872 // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5873 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5874 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5875 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 5876 // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 5877 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 5878 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 5879 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 5880 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 5881 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 5882 // CHECK26-NEXT: ret void 5883 // 5884 // 5885 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 5886 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 5887 // CHECK26-NEXT: entry: 5888 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5889 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5890 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5891 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5892 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5893 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5894 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5895 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5896 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5897 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5898 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5899 // CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 5900 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 5901 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5902 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 5903 // CHECK26-NEXT: ret void 5904 // 5905 // 5906 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 5907 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 5908 // CHECK26-NEXT: entry: 5909 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5910 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5911 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5912 // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5913 // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 5914 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 5915 // CHECK26-NEXT: ret void 5916 // 5917 // 5918 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 5919 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 5920 // CHECK26-NEXT: entry: 5921 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5922 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5923 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5924 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5925 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5926 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5927 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5928 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5929 // CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 5930 // CHECK26-NEXT: ret void 5931 // 5932 // 5933 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 5934 // CHECK26-SAME: () #[[ATTR0]] { 5935 // CHECK26-NEXT: entry: 5936 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5937 // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 5938 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 5939 // CHECK26-NEXT: ret void 5940 // 5941 // 5942 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 5943 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5944 // CHECK26-NEXT: entry: 5945 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5946 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5947 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5948 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5949 // CHECK26-NEXT: ret void 5950 // 5951 // 5952 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 5953 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5954 // CHECK26-NEXT: entry: 5955 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5956 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5957 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5958 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5959 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5960 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5961 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5962 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5963 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5964 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5965 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 5966 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 5967 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 5968 // CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 5969 // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 5970 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 5971 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5972 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 5973 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 5974 // CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 5975 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 5976 // CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 5977 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 5978 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 5979 // CHECK26-NEXT: ret void 5980 // 5981 // 5982 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 5983 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 5984 // CHECK26-NEXT: entry: 5985 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5986 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5987 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5988 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5989 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5990 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5991 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5992 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5993 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5994 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 5995 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 5996 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 5997 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5998 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 5999 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 6000 // CHECK26-NEXT: ret void 6001 // 6002 // 6003 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 6004 // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 6005 // CHECK27-NEXT: entry: 6006 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6007 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 6008 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6009 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6010 // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 6011 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 6012 // CHECK27-NEXT: ret void 6013 // 6014 // 6015 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. 6016 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6017 // CHECK27-NEXT: entry: 6018 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6019 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6020 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6021 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6022 // CHECK27-NEXT: ret void 6023 // 6024 // 6025 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 6026 // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6027 // CHECK27-NEXT: entry: 6028 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6029 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6030 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6031 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6032 // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 6033 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 6034 // CHECK27-NEXT: ret void 6035 // 6036 // 6037 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 6038 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6039 // CHECK27-NEXT: entry: 6040 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6041 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6042 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6043 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6044 // CHECK27-NEXT: ret void 6045 // 6046 // 6047 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 6048 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6049 // CHECK27-NEXT: entry: 6050 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6051 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6052 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6053 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6054 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6055 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6056 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6057 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6058 // CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6059 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6060 // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 6061 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 6062 // CHECK27-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 6063 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 6064 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 6065 // CHECK27-NEXT: ret void 6066 // 6067 // 6068 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 6069 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 6070 // CHECK27-NEXT: entry: 6071 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6072 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6073 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6074 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6075 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6076 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6077 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6078 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6079 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6080 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 6081 // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 6082 // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6083 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6084 // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 6085 // CHECK27-NEXT: ret void 6086 // 6087 // 6088 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 6089 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 6090 // CHECK27-NEXT: entry: 6091 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6092 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6093 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6094 // CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6095 // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 6096 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 6097 // CHECK27-NEXT: ret void 6098 // 6099 // 6100 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 6101 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 6102 // CHECK27-NEXT: entry: 6103 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6104 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6105 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6106 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6107 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6108 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6109 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6110 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6111 // CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 6112 // CHECK27-NEXT: ret void 6113 // 6114 // 6115 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 6116 // CHECK27-SAME: () #[[ATTR0]] { 6117 // CHECK27-NEXT: entry: 6118 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6119 // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 6120 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 6121 // CHECK27-NEXT: ret void 6122 // 6123 // 6124 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 6125 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6126 // CHECK27-NEXT: entry: 6127 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6128 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6129 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6130 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6131 // CHECK27-NEXT: ret void 6132 // 6133 // 6134 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 6135 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6136 // CHECK27-NEXT: entry: 6137 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6138 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6139 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6140 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6141 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6142 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6143 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6144 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6145 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6146 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 6147 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 6148 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 6149 // CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 6150 // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 6151 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 6152 // CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 6153 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 6154 // CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 6155 // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 6156 // CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 6157 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 6158 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 6159 // CHECK27-NEXT: ret void 6160 // 6161 // 6162 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 6163 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 6164 // CHECK27-NEXT: entry: 6165 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6166 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6167 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6168 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6169 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6170 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6171 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6172 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6173 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 6174 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 6175 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 6176 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6177 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 6178 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 6179 // CHECK27-NEXT: ret void 6180 // 6181 // 6182 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 6183 // CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 6184 // CHECK28-NEXT: entry: 6185 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6186 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 6187 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6188 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6189 // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 6190 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 6191 // CHECK28-NEXT: ret void 6192 // 6193 // 6194 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. 6195 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6196 // CHECK28-NEXT: entry: 6197 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6198 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6199 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6200 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6201 // CHECK28-NEXT: ret void 6202 // 6203 // 6204 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 6205 // CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6206 // CHECK28-NEXT: entry: 6207 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6208 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6209 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6210 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6211 // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 0) 6212 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 6213 // CHECK28-NEXT: ret void 6214 // 6215 // 6216 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 6217 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6218 // CHECK28-NEXT: entry: 6219 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6220 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6221 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6222 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6223 // CHECK28-NEXT: ret void 6224 // 6225 // 6226 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 6227 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6228 // CHECK28-NEXT: entry: 6229 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6230 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6231 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6232 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6233 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6234 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6235 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6236 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6237 // CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6238 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6239 // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 6240 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 6241 // CHECK28-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 6242 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 6243 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 6244 // CHECK28-NEXT: ret void 6245 // 6246 // 6247 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 6248 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 6249 // CHECK28-NEXT: entry: 6250 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6251 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6252 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6253 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6254 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6255 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6256 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6257 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6258 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6259 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 6260 // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 6261 // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6262 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6263 // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 6264 // CHECK28-NEXT: ret void 6265 // 6266 // 6267 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 6268 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 6269 // CHECK28-NEXT: entry: 6270 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6271 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6272 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6273 // CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6274 // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024, i32 0) 6275 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 6276 // CHECK28-NEXT: ret void 6277 // 6278 // 6279 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 6280 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 6281 // CHECK28-NEXT: entry: 6282 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6283 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6284 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6285 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6286 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6287 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6288 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6289 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6290 // CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 6291 // CHECK28-NEXT: ret void 6292 // 6293 // 6294 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 6295 // CHECK28-SAME: () #[[ATTR0]] { 6296 // CHECK28-NEXT: entry: 6297 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6298 // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20, i32 0) 6299 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 6300 // CHECK28-NEXT: ret void 6301 // 6302 // 6303 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 6304 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6305 // CHECK28-NEXT: entry: 6306 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6307 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6308 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6309 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6310 // CHECK28-NEXT: ret void 6311 // 6312 // 6313 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 6314 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6315 // CHECK28-NEXT: entry: 6316 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6317 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6318 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6319 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6320 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6321 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6322 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6323 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6324 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6325 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 6326 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 6327 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 6328 // CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 6329 // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]], i32 0) 6330 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 6331 // CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 6332 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 6333 // CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 6334 // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 6335 // CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 6336 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 6337 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 6338 // CHECK28-NEXT: ret void 6339 // 6340 // 6341 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 6342 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 6343 // CHECK28-NEXT: entry: 6344 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6345 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6346 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6347 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6348 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6349 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6350 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6351 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6352 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 6353 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 6354 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 6355 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6356 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 6357 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 6358 // CHECK28-NEXT: ret void 6359 // 6360 // 6361 // CHECK29-LABEL: define {{[^@]+}}@_Z3bari 6362 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6363 // CHECK29-NEXT: entry: 6364 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6365 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 6366 // CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 6367 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6368 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 6369 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6370 // CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 6371 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6372 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6373 // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6374 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6375 // CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 6376 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6377 // CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6378 // CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6379 // CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6380 // CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 6381 // CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6382 // CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6383 // CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6384 // CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6385 // CHECK29-NEXT: ret i32 [[TMP6]] 6386 // 6387 // 6388 // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6389 // CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6390 // CHECK29-NEXT: entry: 6391 // CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6392 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6393 // CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 6394 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6395 // CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6396 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6397 // CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6398 // CHECK29-NEXT: store i32 1, i32* [[B]], align 4 6399 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6400 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 6401 // CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 6402 // CHECK29-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 6403 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 6404 // CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 6405 // CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6406 // CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6407 // CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 6408 // CHECK29-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6409 // CHECK29-NEXT: store double 2.500000e+00, double* [[A2]], align 8 6410 // CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6411 // CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 6412 // CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 6413 // CHECK29-NEXT: ret i32 [[CONV4]] 6414 // 6415 // 6416 // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici 6417 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 6418 // CHECK29-NEXT: entry: 6419 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6420 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6421 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6422 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6423 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6424 // CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 6425 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6426 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 6427 // CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6428 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6429 // CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 6430 // CHECK29-NEXT: ret i32 [[ADD2]] 6431 // 6432 // 6433 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6434 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 6435 // CHECK29-NEXT: entry: 6436 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6437 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 6438 // CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 6439 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 6440 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6441 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 6442 // CHECK29-NEXT: store i16 1, i16* [[B]], align 2 6443 // CHECK29-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 6444 // CHECK29-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 6445 // CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 6446 // CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6447 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 6448 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 6449 // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6450 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6451 // CHECK29-NEXT: ret i32 [[TMP3]] 6452 // 6453 // 6454 // CHECK30-LABEL: define {{[^@]+}}@_Z3bari 6455 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6456 // CHECK30-NEXT: entry: 6457 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6458 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 6459 // CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 6460 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6461 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 6462 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6463 // CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 6464 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6465 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6466 // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6467 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6468 // CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 6469 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6470 // CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6471 // CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6472 // CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6473 // CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 6474 // CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6475 // CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6476 // CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6477 // CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6478 // CHECK30-NEXT: ret i32 [[TMP6]] 6479 // 6480 // 6481 // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6482 // CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6483 // CHECK30-NEXT: entry: 6484 // CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6485 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6486 // CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 6487 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6488 // CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6489 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6490 // CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6491 // CHECK30-NEXT: store i32 1, i32* [[B]], align 4 6492 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6493 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 6494 // CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 6495 // CHECK30-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 6496 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 6497 // CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 6498 // CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6499 // CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6500 // CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 6501 // CHECK30-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6502 // CHECK30-NEXT: store double 2.500000e+00, double* [[A2]], align 8 6503 // CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6504 // CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 6505 // CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 6506 // CHECK30-NEXT: ret i32 [[CONV4]] 6507 // 6508 // 6509 // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici 6510 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 6511 // CHECK30-NEXT: entry: 6512 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6513 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6514 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6515 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6516 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6517 // CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 6518 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6519 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 6520 // CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6521 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6522 // CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 6523 // CHECK30-NEXT: ret i32 [[ADD2]] 6524 // 6525 // 6526 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6527 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 6528 // CHECK30-NEXT: entry: 6529 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6530 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 6531 // CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 6532 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 6533 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6534 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 6535 // CHECK30-NEXT: store i16 1, i16* [[B]], align 2 6536 // CHECK30-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 6537 // CHECK30-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 6538 // CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 6539 // CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6540 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 6541 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 6542 // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6543 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6544 // CHECK30-NEXT: ret i32 [[TMP3]] 6545 // 6546 // 6547 // CHECK31-LABEL: define {{[^@]+}}@_Z3bari 6548 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6549 // CHECK31-NEXT: entry: 6550 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6551 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 6552 // CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6553 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6554 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 6555 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6556 // CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 6557 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6558 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6559 // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6560 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6561 // CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 6562 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6563 // CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6564 // CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6565 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6566 // CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 6567 // CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6568 // CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6569 // CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6570 // CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6571 // CHECK31-NEXT: ret i32 [[TMP6]] 6572 // 6573 // 6574 // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6575 // CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6576 // CHECK31-NEXT: entry: 6577 // CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6578 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6579 // CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 6580 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6581 // CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6582 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6583 // CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6584 // CHECK31-NEXT: store i32 1, i32* [[B]], align 4 6585 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6586 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 6587 // CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 6588 // CHECK31-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 6589 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 6590 // CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 6591 // CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6592 // CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6593 // CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 6594 // CHECK31-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6595 // CHECK31-NEXT: store double 2.500000e+00, double* [[A2]], align 4 6596 // CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6597 // CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 6598 // CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 6599 // CHECK31-NEXT: ret i32 [[CONV4]] 6600 // 6601 // 6602 // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici 6603 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 6604 // CHECK31-NEXT: entry: 6605 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6606 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6607 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6608 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6609 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6610 // CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 6611 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6612 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 6613 // CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6614 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6615 // CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 6616 // CHECK31-NEXT: ret i32 [[ADD2]] 6617 // 6618 // 6619 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6620 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 6621 // CHECK31-NEXT: entry: 6622 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6623 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 6624 // CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 6625 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 6626 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6627 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 6628 // CHECK31-NEXT: store i16 1, i16* [[B]], align 2 6629 // CHECK31-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 6630 // CHECK31-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 6631 // CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 6632 // CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6633 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 6634 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 6635 // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6636 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6637 // CHECK31-NEXT: ret i32 [[TMP3]] 6638 // 6639 // 6640 // CHECK32-LABEL: define {{[^@]+}}@_Z3bari 6641 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6642 // CHECK32-NEXT: entry: 6643 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6644 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 6645 // CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6646 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6647 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 6648 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6649 // CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 6650 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6651 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6652 // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6653 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6654 // CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 6655 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6656 // CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6657 // CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6658 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6659 // CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 6660 // CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6661 // CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6662 // CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6663 // CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6664 // CHECK32-NEXT: ret i32 [[TMP6]] 6665 // 6666 // 6667 // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6668 // CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6669 // CHECK32-NEXT: entry: 6670 // CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6671 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6672 // CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 6673 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6674 // CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6675 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6676 // CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6677 // CHECK32-NEXT: store i32 1, i32* [[B]], align 4 6678 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6679 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 6680 // CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 6681 // CHECK32-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 6682 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 6683 // CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 6684 // CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6685 // CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6686 // CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 6687 // CHECK32-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6688 // CHECK32-NEXT: store double 2.500000e+00, double* [[A2]], align 4 6689 // CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6690 // CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 6691 // CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 6692 // CHECK32-NEXT: ret i32 [[CONV4]] 6693 // 6694 // 6695 // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici 6696 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 6697 // CHECK32-NEXT: entry: 6698 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6699 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6700 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6701 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6702 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6703 // CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 6704 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6705 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 6706 // CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6707 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6708 // CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 6709 // CHECK32-NEXT: ret i32 [[ADD2]] 6710 // 6711 // 6712 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6713 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 6714 // CHECK32-NEXT: entry: 6715 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6716 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 6717 // CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 6718 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 6719 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6720 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 6721 // CHECK32-NEXT: store i16 1, i16* [[B]], align 2 6722 // CHECK32-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 6723 // CHECK32-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 6724 // CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 6725 // CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6726 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 6727 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 6728 // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6729 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6730 // CHECK32-NEXT: ret i32 [[TMP3]] 6731 // 6732