1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 template <typename T> 29 T tmain() { 30 T t_var = T(); 31 T vec[] = {1, 2}; 32 #pragma omp target teams distribute simd reduction(+: t_var) 33 for (int i = 0; i < 2; ++i) { 34 t_var += (T) i; 35 } 36 return T(); 37 } 38 39 int main() { 40 static int sivar; 41 #ifdef LAMBDA 42 43 [&]() { 44 #pragma omp target teams distribute simd reduction(+: sivar) 45 for (int i = 0; i < 2; ++i) { 46 47 // Skip global and bound tid vars 48 49 sivar += i; 50 51 [&]() { 52 53 sivar += 4; 54 55 }(); 56 } 57 }(); 58 return 0; 59 #else 60 #pragma omp target teams distribute simd reduction(+: sivar) 61 for (int i = 0; i < 2; ++i) { 62 sivar += i; 63 } 64 return tmain<int>(); 65 #endif 66 } 67 68 69 70 71 // Skip global and bound tid vars 72 73 74 75 76 77 // Skip global and bound tid vars 78 79 80 #endif 81 // CHECK1-LABEL: define {{[^@]+}}@main 82 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 83 // CHECK1-NEXT: entry: 84 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 85 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 86 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 87 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 88 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 89 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 90 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 91 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32** 92 // CHECK1-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 8 93 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 94 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32** 95 // CHECK1-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 8 96 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 97 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8 98 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 99 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 100 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 101 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 102 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 103 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 104 // CHECK1: omp_offload.failed: 105 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] 106 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 107 // CHECK1: omp_offload.cont: 108 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 109 // CHECK1-NEXT: ret i32 [[CALL]] 110 // 111 // 112 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 113 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 114 // CHECK1-NEXT: entry: 115 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 116 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 117 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 118 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) 119 // CHECK1-NEXT: ret void 120 // 121 // 122 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 123 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 124 // CHECK1-NEXT: entry: 125 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 126 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 127 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 128 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 129 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 130 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 131 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 132 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 133 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 134 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 135 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 136 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 137 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 138 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 139 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 140 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 141 // CHECK1-NEXT: store i32 0, i32* [[SIVAR1]], align 4 142 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 143 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 144 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 145 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 146 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 147 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 148 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 149 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 150 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 151 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 152 // CHECK1: cond.true: 153 // CHECK1-NEXT: br label [[COND_END:%.*]] 154 // CHECK1: cond.false: 155 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 156 // CHECK1-NEXT: br label [[COND_END]] 157 // CHECK1: cond.end: 158 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 159 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 160 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 161 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 162 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 163 // CHECK1: omp.inner.for.cond: 164 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 165 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 166 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 167 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 168 // CHECK1: omp.inner.for.body: 169 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 170 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 171 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 172 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 173 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 174 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 175 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 176 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 177 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 178 // CHECK1: omp.body.continue: 179 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 180 // CHECK1: omp.inner.for.inc: 181 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 182 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 183 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 184 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 185 // CHECK1: omp.inner.for.end: 186 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 187 // CHECK1: omp.loop.exit: 188 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 189 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 190 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 191 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 192 // CHECK1: .omp.final.then: 193 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 194 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 195 // CHECK1: .omp.final.done: 196 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 197 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 198 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 199 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 200 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 201 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 202 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 203 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 204 // CHECK1-NEXT: ] 205 // CHECK1: .omp.reduction.case1: 206 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 207 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 208 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 209 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 210 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 211 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 212 // CHECK1: .omp.reduction.case2: 213 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 214 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 215 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 216 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 217 // CHECK1: .omp.reduction.default: 218 // CHECK1-NEXT: ret void 219 // 220 // 221 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 222 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 223 // CHECK1-NEXT: entry: 224 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 225 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 226 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 227 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 228 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 229 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 230 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 231 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 232 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 233 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 234 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 235 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 236 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 237 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 238 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 239 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 240 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 241 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 242 // CHECK1-NEXT: ret void 243 // 244 // 245 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 246 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 247 // CHECK1-NEXT: entry: 248 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 249 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 250 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 251 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 252 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 253 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 254 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 255 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 256 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 257 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 258 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 259 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 260 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 261 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 262 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 263 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 264 // CHECK1-NEXT: store i8* null, i8** [[TMP5]], align 8 265 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 266 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 267 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 268 // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 269 // CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 270 // CHECK1-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 271 // CHECK1: omp_offload.failed: 272 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR3]] 273 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 274 // CHECK1: omp_offload.cont: 275 // CHECK1-NEXT: ret i32 0 276 // 277 // 278 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 279 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 280 // CHECK1-NEXT: entry: 281 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 282 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 283 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 284 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) 285 // CHECK1-NEXT: ret void 286 // 287 // 288 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 289 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { 290 // CHECK1-NEXT: entry: 291 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 292 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 293 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 294 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 295 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 296 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 297 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 302 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 303 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 304 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 305 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 306 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 307 // CHECK1-NEXT: store i32 0, i32* [[T_VAR1]], align 4 308 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 309 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 310 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 311 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 312 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 313 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 314 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 315 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 316 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 317 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 318 // CHECK1: cond.true: 319 // CHECK1-NEXT: br label [[COND_END:%.*]] 320 // CHECK1: cond.false: 321 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 322 // CHECK1-NEXT: br label [[COND_END]] 323 // CHECK1: cond.end: 324 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 325 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 326 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 327 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 328 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 329 // CHECK1: omp.inner.for.cond: 330 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 331 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 332 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 333 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 334 // CHECK1: omp.inner.for.body: 335 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 336 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 337 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 338 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 339 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 340 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 341 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 342 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 343 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 344 // CHECK1: omp.body.continue: 345 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 346 // CHECK1: omp.inner.for.inc: 347 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 348 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 349 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 350 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 351 // CHECK1: omp.inner.for.end: 352 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 353 // CHECK1: omp.loop.exit: 354 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 355 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 356 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 357 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 358 // CHECK1: .omp.final.then: 359 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 360 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 361 // CHECK1: .omp.final.done: 362 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 363 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 364 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 365 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 366 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 367 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 368 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 369 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 370 // CHECK1-NEXT: ] 371 // CHECK1: .omp.reduction.case1: 372 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 373 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 374 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 375 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 376 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 377 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 378 // CHECK1: .omp.reduction.case2: 379 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 380 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 381 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 382 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 383 // CHECK1: .omp.reduction.default: 384 // CHECK1-NEXT: ret void 385 // 386 // 387 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 388 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { 389 // CHECK1-NEXT: entry: 390 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 391 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 392 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 393 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 394 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 395 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 396 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 397 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 398 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 399 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 400 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 401 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 402 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 403 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 404 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 405 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 406 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 407 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 408 // CHECK1-NEXT: ret void 409 // 410 // 411 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 412 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { 413 // CHECK1-NEXT: entry: 414 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 415 // CHECK1-NEXT: ret void 416 // 417 // 418 // CHECK3-LABEL: define {{[^@]+}}@main 419 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 420 // CHECK3-NEXT: entry: 421 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 422 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 423 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 424 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 425 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 426 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 427 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 428 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32** 429 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 4 430 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 431 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32** 432 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 4 433 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 434 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4 435 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 436 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 437 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 438 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 439 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 440 // CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 441 // CHECK3: omp_offload.failed: 442 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] 443 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 444 // CHECK3: omp_offload.cont: 445 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 446 // CHECK3-NEXT: ret i32 [[CALL]] 447 // 448 // 449 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 450 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 451 // CHECK3-NEXT: entry: 452 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 453 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 454 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 455 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) 456 // CHECK3-NEXT: ret void 457 // 458 // 459 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 460 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 461 // CHECK3-NEXT: entry: 462 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 463 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 464 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 465 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 466 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 467 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 468 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 469 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 470 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 471 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 472 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 473 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 474 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 475 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 476 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 477 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 478 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4 479 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 480 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 481 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 482 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 483 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 484 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 485 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 486 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 487 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 488 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 489 // CHECK3: cond.true: 490 // CHECK3-NEXT: br label [[COND_END:%.*]] 491 // CHECK3: cond.false: 492 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 493 // CHECK3-NEXT: br label [[COND_END]] 494 // CHECK3: cond.end: 495 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 496 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 497 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 498 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 499 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 500 // CHECK3: omp.inner.for.cond: 501 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 502 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 503 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 504 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 505 // CHECK3: omp.inner.for.body: 506 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 507 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 508 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 509 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 510 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 511 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 512 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 513 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 514 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 515 // CHECK3: omp.body.continue: 516 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 517 // CHECK3: omp.inner.for.inc: 518 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 519 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 520 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 521 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 522 // CHECK3: omp.inner.for.end: 523 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 524 // CHECK3: omp.loop.exit: 525 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 526 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 527 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 528 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 529 // CHECK3: .omp.final.then: 530 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 531 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 532 // CHECK3: .omp.final.done: 533 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 534 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 535 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 536 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 537 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 538 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 539 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 540 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 541 // CHECK3-NEXT: ] 542 // CHECK3: .omp.reduction.case1: 543 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 544 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 545 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 546 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 547 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 548 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 549 // CHECK3: .omp.reduction.case2: 550 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 551 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 552 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 553 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 554 // CHECK3: .omp.reduction.default: 555 // CHECK3-NEXT: ret void 556 // 557 // 558 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 559 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 560 // CHECK3-NEXT: entry: 561 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 562 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 563 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 564 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 565 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 566 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 567 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 568 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 569 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 570 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 571 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 572 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 573 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 574 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 575 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 576 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 577 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 578 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 579 // CHECK3-NEXT: ret void 580 // 581 // 582 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 583 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 584 // CHECK3-NEXT: entry: 585 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 586 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 587 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 588 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 589 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 590 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 591 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 592 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 593 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 594 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 595 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 596 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 597 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 598 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 599 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 600 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 601 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4 602 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 603 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 604 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 605 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 606 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 607 // CHECK3-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 608 // CHECK3: omp_offload.failed: 609 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR3]] 610 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 611 // CHECK3: omp_offload.cont: 612 // CHECK3-NEXT: ret i32 0 613 // 614 // 615 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 616 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 617 // CHECK3-NEXT: entry: 618 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 619 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 620 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 621 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) 622 // CHECK3-NEXT: ret void 623 // 624 // 625 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 626 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { 627 // CHECK3-NEXT: entry: 628 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 629 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 630 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 631 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 632 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 633 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 634 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 635 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 636 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 637 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 638 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 639 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 640 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 641 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 642 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 643 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 644 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4 645 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 646 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 647 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 648 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 649 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 650 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 651 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 652 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 653 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 654 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 655 // CHECK3: cond.true: 656 // CHECK3-NEXT: br label [[COND_END:%.*]] 657 // CHECK3: cond.false: 658 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 659 // CHECK3-NEXT: br label [[COND_END]] 660 // CHECK3: cond.end: 661 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 662 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 663 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 664 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 665 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 666 // CHECK3: omp.inner.for.cond: 667 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 668 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 669 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 670 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 671 // CHECK3: omp.inner.for.body: 672 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 673 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 674 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 675 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 676 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 677 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 678 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 679 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 680 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 681 // CHECK3: omp.body.continue: 682 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 683 // CHECK3: omp.inner.for.inc: 684 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 685 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 686 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 687 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 688 // CHECK3: omp.inner.for.end: 689 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 690 // CHECK3: omp.loop.exit: 691 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 692 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 693 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 694 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 695 // CHECK3: .omp.final.then: 696 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 697 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 698 // CHECK3: .omp.final.done: 699 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 700 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 701 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 702 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 703 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 704 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 705 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 706 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 707 // CHECK3-NEXT: ] 708 // CHECK3: .omp.reduction.case1: 709 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 710 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 711 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 712 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 713 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 714 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 715 // CHECK3: .omp.reduction.case2: 716 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 717 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 718 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 719 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 720 // CHECK3: .omp.reduction.default: 721 // CHECK3-NEXT: ret void 722 // 723 // 724 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 725 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { 726 // CHECK3-NEXT: entry: 727 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 728 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 729 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 730 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 731 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 732 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 733 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 734 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 735 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 736 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 737 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 738 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 739 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 740 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 741 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 742 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 743 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 744 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 745 // CHECK3-NEXT: ret void 746 // 747 // 748 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 749 // CHECK3-SAME: () #[[ATTR8:[0-9]+]] { 750 // CHECK3-NEXT: entry: 751 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 752 // CHECK3-NEXT: ret void 753 // 754 // 755 // CHECK5-LABEL: define {{[^@]+}}@main 756 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 757 // CHECK5-NEXT: entry: 758 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 759 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 760 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 761 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 762 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 763 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 764 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 765 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 766 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 767 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 768 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 769 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 770 // CHECK5-NEXT: store i32 0, i32* [[SIVAR]], align 4 771 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 772 // CHECK5: omp.inner.for.cond: 773 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 774 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 775 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 776 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 777 // CHECK5: omp.inner.for.body: 778 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 779 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 780 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 781 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 782 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 783 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2 784 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 785 // CHECK5-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2 786 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 787 // CHECK5: omp.body.continue: 788 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 789 // CHECK5: omp.inner.for.inc: 790 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 791 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 792 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 793 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 794 // CHECK5: omp.inner.for.end: 795 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 796 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 797 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 798 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 799 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 800 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 801 // CHECK5-NEXT: ret i32 [[CALL]] 802 // 803 // 804 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 805 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { 806 // CHECK5-NEXT: entry: 807 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 808 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 809 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 810 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 811 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 812 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 813 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 814 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 815 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 816 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 817 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 818 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 819 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 820 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 821 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 822 // CHECK5-NEXT: store i32 0, i32* [[T_VAR1]], align 4 823 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 824 // CHECK5: omp.inner.for.cond: 825 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 826 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 827 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 828 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 829 // CHECK5: omp.inner.for.body: 830 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 831 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 832 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 833 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 834 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 835 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6 836 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 837 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6 838 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 839 // CHECK5: omp.body.continue: 840 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 841 // CHECK5: omp.inner.for.inc: 842 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 843 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 844 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 845 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 846 // CHECK5: omp.inner.for.end: 847 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 848 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 849 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 850 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 851 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 852 // CHECK5-NEXT: ret i32 0 853 // 854 // 855 // CHECK7-LABEL: define {{[^@]+}}@main 856 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 857 // CHECK7-NEXT: entry: 858 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 859 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 860 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 861 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 862 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 863 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 864 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 865 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 866 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 867 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 868 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 869 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 870 // CHECK7-NEXT: store i32 0, i32* [[SIVAR]], align 4 871 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 872 // CHECK7: omp.inner.for.cond: 873 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 874 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 875 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 876 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 877 // CHECK7: omp.inner.for.body: 878 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 879 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 880 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 881 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 882 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 883 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3 884 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 885 // CHECK7-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3 886 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 887 // CHECK7: omp.body.continue: 888 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 889 // CHECK7: omp.inner.for.inc: 890 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 891 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 892 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 893 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 894 // CHECK7: omp.inner.for.end: 895 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 896 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 897 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 898 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 899 // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 900 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 901 // CHECK7-NEXT: ret i32 [[CALL]] 902 // 903 // 904 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 905 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { 906 // CHECK7-NEXT: entry: 907 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 908 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 909 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 910 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 911 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 912 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 913 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 914 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 915 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 916 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 917 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 918 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 919 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 920 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 921 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 922 // CHECK7-NEXT: store i32 0, i32* [[T_VAR1]], align 4 923 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 924 // CHECK7: omp.inner.for.cond: 925 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 926 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 927 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 928 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 929 // CHECK7: omp.inner.for.body: 930 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 931 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 932 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 933 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 934 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 935 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7 936 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 937 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7 938 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 939 // CHECK7: omp.body.continue: 940 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 941 // CHECK7: omp.inner.for.inc: 942 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 943 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 944 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 945 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 946 // CHECK7: omp.inner.for.end: 947 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 948 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 949 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 950 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 951 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 952 // CHECK7-NEXT: ret i32 0 953 // 954 // 955 // CHECK9-LABEL: define {{[^@]+}}@main 956 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 957 // CHECK9-NEXT: entry: 958 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 959 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 960 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 961 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 962 // CHECK9-NEXT: ret i32 0 963 // 964 // 965 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 966 // CHECK9-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 967 // CHECK9-NEXT: entry: 968 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 969 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 970 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 971 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) 972 // CHECK9-NEXT: ret void 973 // 974 // 975 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 976 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 977 // CHECK9-NEXT: entry: 978 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 979 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 980 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 981 // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 982 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 983 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 984 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 985 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 986 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 987 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 988 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 989 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 990 // CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 991 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 992 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 993 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 994 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 995 // CHECK9-NEXT: store i32 0, i32* [[SIVAR1]], align 4 996 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 997 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 998 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 999 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1000 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1001 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1002 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1003 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1004 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1005 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1006 // CHECK9: cond.true: 1007 // CHECK9-NEXT: br label [[COND_END:%.*]] 1008 // CHECK9: cond.false: 1009 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1010 // CHECK9-NEXT: br label [[COND_END]] 1011 // CHECK9: cond.end: 1012 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1013 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1014 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1015 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1016 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1017 // CHECK9: omp.inner.for.cond: 1018 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1019 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 1020 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1021 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1022 // CHECK9: omp.inner.for.body: 1023 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1024 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1025 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1026 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 1027 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 1028 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 1029 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1030 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 1031 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 1032 // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 1033 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group !4 1034 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1035 // CHECK9: omp.body.continue: 1036 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1037 // CHECK9: omp.inner.for.inc: 1038 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1039 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 1040 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1041 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 1042 // CHECK9: omp.inner.for.end: 1043 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1044 // CHECK9: omp.loop.exit: 1045 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1046 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1047 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1048 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1049 // CHECK9: .omp.final.then: 1050 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 1051 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1052 // CHECK9: .omp.final.done: 1053 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1054 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR1]] to i8* 1055 // CHECK9-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 1056 // CHECK9-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1057 // CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 1058 // CHECK9-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1059 // CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1060 // CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1061 // CHECK9-NEXT: ] 1062 // CHECK9: .omp.reduction.case1: 1063 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 1064 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 1065 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 1066 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1067 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1068 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1069 // CHECK9: .omp.reduction.case2: 1070 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4 1071 // CHECK9-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 1072 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1073 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1074 // CHECK9: .omp.reduction.default: 1075 // CHECK9-NEXT: ret void 1076 // 1077 // 1078 // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 1079 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 1080 // CHECK9-NEXT: entry: 1081 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1082 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 1083 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1084 // CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 1085 // CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 1086 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1087 // CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 1088 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1089 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 1090 // CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1091 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1092 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 1093 // CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 1094 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1095 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1096 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1097 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1098 // CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1099 // CHECK9-NEXT: ret void 1100 // 1101 // 1102 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1103 // CHECK9-SAME: () #[[ATTR7:[0-9]+]] { 1104 // CHECK9-NEXT: entry: 1105 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1106 // CHECK9-NEXT: ret void 1107 // 1108 // 1109 // CHECK11-LABEL: define {{[^@]+}}@main 1110 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1111 // CHECK11-NEXT: entry: 1112 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1113 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1114 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1115 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 1116 // CHECK11-NEXT: ret i32 0 1117 // 1118