1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 template <typename T> 29 T tmain() { 30 T t_var = T(); 31 T vec[] = {1, 2}; 32 #pragma omp target teams distribute simd reduction(+: t_var) 33 for (int i = 0; i < 2; ++i) { 34 t_var += (T) i; 35 } 36 return T(); 37 } 38 39 int main() { 40 static int sivar; 41 #ifdef LAMBDA 42 43 [&]() { 44 #pragma omp target teams distribute simd reduction(+: sivar) 45 for (int i = 0; i < 2; ++i) { 46 47 // Skip global and bound tid vars 48 49 sivar += i; 50 51 [&]() { 52 53 sivar += 4; 54 55 }(); 56 } 57 }(); 58 return 0; 59 #else 60 #pragma omp target teams distribute simd reduction(+: sivar) 61 for (int i = 0; i < 2; ++i) { 62 sivar += i; 63 } 64 return tmain<int>(); 65 #endif 66 } 67 68 69 70 71 // Skip global and bound tid vars 72 73 74 75 76 77 // Skip global and bound tid vars 78 79 80 #endif 81 // CHECK1-LABEL: define {{[^@]+}}@main 82 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 83 // CHECK1-NEXT: entry: 84 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 85 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 86 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 87 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 88 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 89 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 90 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 91 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32** 92 // CHECK1-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 8 93 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 94 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32** 95 // CHECK1-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 8 96 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 97 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8 98 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 99 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 100 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 101 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 102 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 103 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 104 // CHECK1: omp_offload.failed: 105 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] 106 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 107 // CHECK1: omp_offload.cont: 108 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 109 // CHECK1-NEXT: ret i32 [[CALL]] 110 // 111 // 112 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 113 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 114 // CHECK1-NEXT: entry: 115 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 116 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 117 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 118 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) 119 // CHECK1-NEXT: ret void 120 // 121 // 122 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 123 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 124 // CHECK1-NEXT: entry: 125 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 126 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 127 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 128 // CHECK1-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 129 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 130 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 131 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 132 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 133 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 134 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 135 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 136 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 137 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 138 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 139 // CHECK1-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 140 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 141 // CHECK1-NEXT: store i32 0, i32* [[SIVAR1]], align 4 142 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 143 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 144 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 145 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 146 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 147 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 148 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 149 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 150 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 151 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 152 // CHECK1: cond.true: 153 // CHECK1-NEXT: br label [[COND_END:%.*]] 154 // CHECK1: cond.false: 155 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 156 // CHECK1-NEXT: br label [[COND_END]] 157 // CHECK1: cond.end: 158 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 159 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 160 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 161 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 162 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 163 // CHECK1: omp.inner.for.cond: 164 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 165 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 166 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 167 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 168 // CHECK1: omp.inner.for.body: 169 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 170 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 171 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 172 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 173 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 174 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 175 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 176 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 177 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 178 // CHECK1: omp.body.continue: 179 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 180 // CHECK1: omp.inner.for.inc: 181 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 182 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 183 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 184 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 185 // CHECK1: omp.inner.for.end: 186 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 187 // CHECK1: omp.loop.exit: 188 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 189 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 190 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 191 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 192 // CHECK1: .omp.final.then: 193 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 194 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 195 // CHECK1: .omp.final.done: 196 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 197 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 198 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 199 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 200 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 201 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 202 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 203 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 204 // CHECK1-NEXT: ] 205 // CHECK1: .omp.reduction.case1: 206 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 207 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 208 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 209 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 210 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 211 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 212 // CHECK1: .omp.reduction.case2: 213 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 214 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 215 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 216 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 217 // CHECK1: .omp.reduction.default: 218 // CHECK1-NEXT: ret void 219 // 220 // 221 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 222 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 223 // CHECK1-NEXT: entry: 224 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 225 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 226 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 227 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 228 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 229 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 230 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 231 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 232 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 233 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 234 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 235 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 236 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 237 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 238 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 239 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 240 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 241 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 242 // CHECK1-NEXT: ret void 243 // 244 // 245 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 246 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 247 // CHECK1-NEXT: entry: 248 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 249 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 250 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 251 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 252 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 253 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 254 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 255 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 256 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 257 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 258 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 259 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 260 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 261 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 262 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 263 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 264 // CHECK1-NEXT: store i8* null, i8** [[TMP5]], align 8 265 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 266 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 267 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 268 // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 269 // CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 270 // CHECK1-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 271 // CHECK1: omp_offload.failed: 272 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR3]] 273 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 274 // CHECK1: omp_offload.cont: 275 // CHECK1-NEXT: ret i32 0 276 // 277 // 278 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 279 // CHECK1-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 280 // CHECK1-NEXT: entry: 281 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 282 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 283 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 284 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) 285 // CHECK1-NEXT: ret void 286 // 287 // 288 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 289 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { 290 // CHECK1-NEXT: entry: 291 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 292 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 293 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 294 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 295 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 296 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 297 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 302 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 303 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 304 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 305 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 306 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 307 // CHECK1-NEXT: store i32 0, i32* [[T_VAR1]], align 4 308 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 309 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 310 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 311 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 312 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 313 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 314 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 315 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 316 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 317 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 318 // CHECK1: cond.true: 319 // CHECK1-NEXT: br label [[COND_END:%.*]] 320 // CHECK1: cond.false: 321 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 322 // CHECK1-NEXT: br label [[COND_END]] 323 // CHECK1: cond.end: 324 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 325 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 326 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 327 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 328 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 329 // CHECK1: omp.inner.for.cond: 330 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 331 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 332 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 333 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 334 // CHECK1: omp.inner.for.body: 335 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 336 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 337 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 338 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 339 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 340 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 341 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 342 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 343 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 344 // CHECK1: omp.body.continue: 345 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 346 // CHECK1: omp.inner.for.inc: 347 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 348 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 349 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 350 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 351 // CHECK1: omp.inner.for.end: 352 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 353 // CHECK1: omp.loop.exit: 354 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 355 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 356 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 357 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 358 // CHECK1: .omp.final.then: 359 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 360 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 361 // CHECK1: .omp.final.done: 362 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 363 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 364 // CHECK1-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 365 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 366 // CHECK1-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 367 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 368 // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 369 // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 370 // CHECK1-NEXT: ] 371 // CHECK1: .omp.reduction.case1: 372 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 373 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 374 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 375 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 376 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 377 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 378 // CHECK1: .omp.reduction.case2: 379 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 380 // CHECK1-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 381 // CHECK1-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 382 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 383 // CHECK1: .omp.reduction.default: 384 // CHECK1-NEXT: ret void 385 // 386 // 387 // CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 388 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { 389 // CHECK1-NEXT: entry: 390 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 391 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 392 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 393 // CHECK1-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 394 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 395 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 396 // CHECK1-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 397 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 398 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 399 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 400 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 401 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 402 // CHECK1-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 403 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 404 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 405 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 406 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 407 // CHECK1-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 408 // CHECK1-NEXT: ret void 409 // 410 // 411 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 412 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { 413 // CHECK1-NEXT: entry: 414 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 415 // CHECK1-NEXT: ret void 416 // 417 // 418 // CHECK2-LABEL: define {{[^@]+}}@main 419 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 420 // CHECK2-NEXT: entry: 421 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 422 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 423 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 424 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 425 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 426 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 427 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 428 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32** 429 // CHECK2-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 8 430 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 431 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32** 432 // CHECK2-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 8 433 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 434 // CHECK2-NEXT: store i8* null, i8** [[TMP4]], align 8 435 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 436 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 437 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 438 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 439 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 440 // CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 441 // CHECK2: omp_offload.failed: 442 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] 443 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 444 // CHECK2: omp_offload.cont: 445 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 446 // CHECK2-NEXT: ret i32 [[CALL]] 447 // 448 // 449 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 450 // CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 451 // CHECK2-NEXT: entry: 452 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 453 // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 454 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 455 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) 456 // CHECK2-NEXT: ret void 457 // 458 // 459 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 460 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 461 // CHECK2-NEXT: entry: 462 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 463 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 464 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 465 // CHECK2-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 466 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 467 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 468 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 469 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 470 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 471 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 472 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 473 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 474 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 475 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 476 // CHECK2-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 477 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 478 // CHECK2-NEXT: store i32 0, i32* [[SIVAR1]], align 4 479 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 480 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 481 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 482 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 483 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 484 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 485 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 486 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 487 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 488 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 489 // CHECK2: cond.true: 490 // CHECK2-NEXT: br label [[COND_END:%.*]] 491 // CHECK2: cond.false: 492 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 493 // CHECK2-NEXT: br label [[COND_END]] 494 // CHECK2: cond.end: 495 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 496 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 497 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 498 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 499 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 500 // CHECK2: omp.inner.for.cond: 501 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 502 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 503 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 504 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 505 // CHECK2: omp.inner.for.body: 506 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 507 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 508 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 509 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 510 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 511 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !5 512 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 513 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !5 514 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 515 // CHECK2: omp.body.continue: 516 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 517 // CHECK2: omp.inner.for.inc: 518 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 519 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 520 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 521 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 522 // CHECK2: omp.inner.for.end: 523 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 524 // CHECK2: omp.loop.exit: 525 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 526 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 527 // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 528 // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 529 // CHECK2: .omp.final.then: 530 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 531 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 532 // CHECK2: .omp.final.done: 533 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 534 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 535 // CHECK2-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 536 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 537 // CHECK2-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 538 // CHECK2-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 539 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 540 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 541 // CHECK2-NEXT: ] 542 // CHECK2: .omp.reduction.case1: 543 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 544 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 545 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 546 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 547 // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 548 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 549 // CHECK2: .omp.reduction.case2: 550 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 551 // CHECK2-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 552 // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 553 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 554 // CHECK2: .omp.reduction.default: 555 // CHECK2-NEXT: ret void 556 // 557 // 558 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 559 // CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 560 // CHECK2-NEXT: entry: 561 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 562 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 563 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 564 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 565 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 566 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 567 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 568 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 569 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 570 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 571 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 572 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 573 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 574 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 575 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 576 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 577 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 578 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 579 // CHECK2-NEXT: ret void 580 // 581 // 582 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 583 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat { 584 // CHECK2-NEXT: entry: 585 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 586 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 587 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 588 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 589 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 590 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 591 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 592 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 593 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 594 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 595 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 596 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 597 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 598 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 599 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 600 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 601 // CHECK2-NEXT: store i8* null, i8** [[TMP5]], align 8 602 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 603 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 604 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 605 // CHECK2-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 606 // CHECK2-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 607 // CHECK2-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 608 // CHECK2: omp_offload.failed: 609 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR3]] 610 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 611 // CHECK2: omp_offload.cont: 612 // CHECK2-NEXT: ret i32 0 613 // 614 // 615 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 616 // CHECK2-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 617 // CHECK2-NEXT: entry: 618 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 619 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 620 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 621 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) 622 // CHECK2-NEXT: ret void 623 // 624 // 625 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 626 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { 627 // CHECK2-NEXT: entry: 628 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 629 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 630 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 631 // CHECK2-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 632 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 633 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 634 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 635 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 636 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 637 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 638 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 639 // CHECK2-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 640 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 641 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 642 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 643 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 644 // CHECK2-NEXT: store i32 0, i32* [[T_VAR1]], align 4 645 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 646 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 647 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 648 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 649 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 650 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 651 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 652 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 653 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 654 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 655 // CHECK2: cond.true: 656 // CHECK2-NEXT: br label [[COND_END:%.*]] 657 // CHECK2: cond.false: 658 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 659 // CHECK2-NEXT: br label [[COND_END]] 660 // CHECK2: cond.end: 661 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 662 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 663 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 664 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 665 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 666 // CHECK2: omp.inner.for.cond: 667 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 668 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 669 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 670 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 671 // CHECK2: omp.inner.for.body: 672 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 673 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 674 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 675 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 676 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 677 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !11 678 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 679 // CHECK2-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !11 680 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 681 // CHECK2: omp.body.continue: 682 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 683 // CHECK2: omp.inner.for.inc: 684 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 685 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 686 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 687 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 688 // CHECK2: omp.inner.for.end: 689 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 690 // CHECK2: omp.loop.exit: 691 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 692 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 693 // CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 694 // CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 695 // CHECK2: .omp.final.then: 696 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 697 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 698 // CHECK2: .omp.final.done: 699 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 700 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 701 // CHECK2-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8 702 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 703 // CHECK2-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 704 // CHECK2-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 705 // CHECK2-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 706 // CHECK2-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 707 // CHECK2-NEXT: ] 708 // CHECK2: .omp.reduction.case1: 709 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 710 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 711 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 712 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 713 // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 714 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 715 // CHECK2: .omp.reduction.case2: 716 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 717 // CHECK2-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 718 // CHECK2-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 719 // CHECK2-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 720 // CHECK2: .omp.reduction.default: 721 // CHECK2-NEXT: ret void 722 // 723 // 724 // CHECK2-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 725 // CHECK2-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { 726 // CHECK2-NEXT: entry: 727 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 728 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 729 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 730 // CHECK2-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 731 // CHECK2-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 732 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 733 // CHECK2-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 734 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 735 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 736 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 737 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 738 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 739 // CHECK2-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 740 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 741 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 742 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 743 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 744 // CHECK2-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 745 // CHECK2-NEXT: ret void 746 // 747 // 748 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 749 // CHECK2-SAME: () #[[ATTR8:[0-9]+]] { 750 // CHECK2-NEXT: entry: 751 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 752 // CHECK2-NEXT: ret void 753 // 754 // 755 // CHECK3-LABEL: define {{[^@]+}}@main 756 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 757 // CHECK3-NEXT: entry: 758 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 759 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 760 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 761 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 762 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 763 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 764 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 765 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32** 766 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 4 767 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 768 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32** 769 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 4 770 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 771 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4 772 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 773 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 774 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 775 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 776 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 777 // CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 778 // CHECK3: omp_offload.failed: 779 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] 780 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 781 // CHECK3: omp_offload.cont: 782 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 783 // CHECK3-NEXT: ret i32 [[CALL]] 784 // 785 // 786 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 787 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 788 // CHECK3-NEXT: entry: 789 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 790 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 791 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 792 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) 793 // CHECK3-NEXT: ret void 794 // 795 // 796 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 797 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 798 // CHECK3-NEXT: entry: 799 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 800 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 801 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 802 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 803 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 804 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 805 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 806 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 807 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 808 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 809 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 810 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 811 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 812 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 813 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 814 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 815 // CHECK3-NEXT: store i32 0, i32* [[SIVAR1]], align 4 816 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 817 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 818 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 819 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 820 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 821 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 822 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 823 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 824 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 825 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 826 // CHECK3: cond.true: 827 // CHECK3-NEXT: br label [[COND_END:%.*]] 828 // CHECK3: cond.false: 829 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 830 // CHECK3-NEXT: br label [[COND_END]] 831 // CHECK3: cond.end: 832 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 833 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 834 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 835 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 836 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 837 // CHECK3: omp.inner.for.cond: 838 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 839 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 840 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 841 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 842 // CHECK3: omp.inner.for.body: 843 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 844 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 845 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 846 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 847 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 848 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 849 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 850 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 851 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 852 // CHECK3: omp.body.continue: 853 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 854 // CHECK3: omp.inner.for.inc: 855 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 856 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 857 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 858 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 859 // CHECK3: omp.inner.for.end: 860 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 861 // CHECK3: omp.loop.exit: 862 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 863 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 864 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 865 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 866 // CHECK3: .omp.final.then: 867 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 868 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 869 // CHECK3: .omp.final.done: 870 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 871 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 872 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 873 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 874 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 875 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 876 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 877 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 878 // CHECK3-NEXT: ] 879 // CHECK3: .omp.reduction.case1: 880 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 881 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 882 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 883 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 884 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 885 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 886 // CHECK3: .omp.reduction.case2: 887 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 888 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 889 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 890 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 891 // CHECK3: .omp.reduction.default: 892 // CHECK3-NEXT: ret void 893 // 894 // 895 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 896 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 897 // CHECK3-NEXT: entry: 898 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 899 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 900 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 901 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 902 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 903 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 904 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 905 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 906 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 907 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 908 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 909 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 910 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 911 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 912 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 913 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 914 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 915 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 916 // CHECK3-NEXT: ret void 917 // 918 // 919 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 920 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 921 // CHECK3-NEXT: entry: 922 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 923 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 924 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 925 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 926 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 927 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 928 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 929 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 930 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 931 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 932 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 933 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 934 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 935 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 936 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 937 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 938 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4 939 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 940 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 941 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 942 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 943 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 944 // CHECK3-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 945 // CHECK3: omp_offload.failed: 946 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR3]] 947 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 948 // CHECK3: omp_offload.cont: 949 // CHECK3-NEXT: ret i32 0 950 // 951 // 952 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 953 // CHECK3-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 954 // CHECK3-NEXT: entry: 955 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 956 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 957 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 958 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) 959 // CHECK3-NEXT: ret void 960 // 961 // 962 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 963 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { 964 // CHECK3-NEXT: entry: 965 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 966 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 967 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 968 // CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 969 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 970 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 971 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 972 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 973 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 974 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 975 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 976 // CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 977 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 978 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 979 // CHECK3-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 980 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 981 // CHECK3-NEXT: store i32 0, i32* [[T_VAR1]], align 4 982 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 983 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 984 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 985 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 986 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 987 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 988 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 989 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 990 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 991 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 992 // CHECK3: cond.true: 993 // CHECK3-NEXT: br label [[COND_END:%.*]] 994 // CHECK3: cond.false: 995 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 996 // CHECK3-NEXT: br label [[COND_END]] 997 // CHECK3: cond.end: 998 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 999 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1000 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1001 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1002 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1003 // CHECK3: omp.inner.for.cond: 1004 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1005 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 1006 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1007 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1008 // CHECK3: omp.inner.for.body: 1009 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1010 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1011 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1012 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 1013 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1014 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 1015 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1016 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 1017 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1018 // CHECK3: omp.body.continue: 1019 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1020 // CHECK3: omp.inner.for.inc: 1021 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1022 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 1023 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1024 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1025 // CHECK3: omp.inner.for.end: 1026 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1027 // CHECK3: omp.loop.exit: 1028 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1029 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1030 // CHECK3-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 1031 // CHECK3-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1032 // CHECK3: .omp.final.then: 1033 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 1034 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1035 // CHECK3: .omp.final.done: 1036 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1037 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 1038 // CHECK3-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 1039 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1040 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 1041 // CHECK3-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1042 // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1043 // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1044 // CHECK3-NEXT: ] 1045 // CHECK3: .omp.reduction.case1: 1046 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 1047 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 1048 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1049 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1050 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1051 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1052 // CHECK3: .omp.reduction.case2: 1053 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 1054 // CHECK3-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 1055 // CHECK3-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1056 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1057 // CHECK3: .omp.reduction.default: 1058 // CHECK3-NEXT: ret void 1059 // 1060 // 1061 // CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 1062 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { 1063 // CHECK3-NEXT: entry: 1064 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1065 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 1066 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1067 // CHECK3-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 1068 // CHECK3-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 1069 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1070 // CHECK3-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 1071 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1072 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 1073 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 1074 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1075 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 1076 // CHECK3-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 1077 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1078 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1079 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1080 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1081 // CHECK3-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1082 // CHECK3-NEXT: ret void 1083 // 1084 // 1085 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1086 // CHECK3-SAME: () #[[ATTR8:[0-9]+]] { 1087 // CHECK3-NEXT: entry: 1088 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1089 // CHECK3-NEXT: ret void 1090 // 1091 // 1092 // CHECK4-LABEL: define {{[^@]+}}@main 1093 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 1094 // CHECK4-NEXT: entry: 1095 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1096 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1097 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1098 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1099 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1100 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 1101 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1102 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to i32** 1103 // CHECK4-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP1]], align 4 1104 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1105 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32** 1106 // CHECK4-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP3]], align 4 1107 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1108 // CHECK4-NEXT: store i8* null, i8** [[TMP4]], align 4 1109 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1110 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1111 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 2) 1112 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1113 // CHECK4-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1114 // CHECK4-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1115 // CHECK4: omp_offload.failed: 1116 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60(i32* @_ZZ4mainE5sivar) #[[ATTR3:[0-9]+]] 1117 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1118 // CHECK4: omp_offload.cont: 1119 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1120 // CHECK4-NEXT: ret i32 [[CALL]] 1121 // 1122 // 1123 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l60 1124 // CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] { 1125 // CHECK4-NEXT: entry: 1126 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 1127 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 1128 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 1129 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) 1130 // CHECK4-NEXT: ret void 1131 // 1132 // 1133 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 1134 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 1135 // CHECK4-NEXT: entry: 1136 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1137 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1138 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 4 1139 // CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1140 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1141 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1142 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1143 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1144 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1145 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1146 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1147 // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 1148 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1149 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1150 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 4 1151 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 4 1152 // CHECK4-NEXT: store i32 0, i32* [[SIVAR1]], align 4 1153 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1154 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1155 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1156 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1157 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1158 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1159 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1160 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1161 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1162 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1163 // CHECK4: cond.true: 1164 // CHECK4-NEXT: br label [[COND_END:%.*]] 1165 // CHECK4: cond.false: 1166 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1167 // CHECK4-NEXT: br label [[COND_END]] 1168 // CHECK4: cond.end: 1169 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1170 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1171 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1172 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1173 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1174 // CHECK4: omp.inner.for.cond: 1175 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1176 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1177 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1178 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1179 // CHECK4: omp.inner.for.body: 1180 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1181 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1182 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1183 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1184 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1185 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !6 1186 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1187 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !6 1188 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1189 // CHECK4: omp.body.continue: 1190 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1191 // CHECK4: omp.inner.for.inc: 1192 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1193 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 1194 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1195 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1196 // CHECK4: omp.inner.for.end: 1197 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1198 // CHECK4: omp.loop.exit: 1199 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1200 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1201 // CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 1202 // CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1203 // CHECK4: .omp.final.then: 1204 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 1205 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 1206 // CHECK4: .omp.final.done: 1207 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1208 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i32* [[SIVAR1]] to i8* 1209 // CHECK4-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 1210 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1211 // CHECK4-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 1212 // CHECK4-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1213 // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1214 // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1215 // CHECK4-NEXT: ] 1216 // CHECK4: .omp.reduction.case1: 1217 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 1218 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[SIVAR1]], align 4 1219 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1220 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1221 // CHECK4-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1222 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1223 // CHECK4: .omp.reduction.case2: 1224 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 1225 // CHECK4-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 1226 // CHECK4-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1227 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1228 // CHECK4: .omp.reduction.default: 1229 // CHECK4-NEXT: ret void 1230 // 1231 // 1232 // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 1233 // CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { 1234 // CHECK4-NEXT: entry: 1235 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1236 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 1237 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1238 // CHECK4-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 1239 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 1240 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1241 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 1242 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1243 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 1244 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 1245 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1246 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 1247 // CHECK4-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 1248 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1249 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1250 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1251 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1252 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1253 // CHECK4-NEXT: ret void 1254 // 1255 // 1256 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1257 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat { 1258 // CHECK4-NEXT: entry: 1259 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1260 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1261 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1262 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1263 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1264 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1265 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 1266 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1267 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1268 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1269 // CHECK4-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 1270 // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 1271 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1272 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 1273 // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 1274 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1275 // CHECK4-NEXT: store i8* null, i8** [[TMP5]], align 4 1276 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1277 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1278 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 2) 1279 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.3, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.4, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1280 // CHECK4-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 1281 // CHECK4-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1282 // CHECK4: omp_offload.failed: 1283 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32* [[T_VAR]]) #[[ATTR3]] 1284 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1285 // CHECK4: omp_offload.cont: 1286 // CHECK4-NEXT: ret i32 0 1287 // 1288 // 1289 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32 1290 // CHECK4-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { 1291 // CHECK4-NEXT: entry: 1292 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 1293 // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1294 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1295 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]]) 1296 // CHECK4-NEXT: ret void 1297 // 1298 // 1299 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 1300 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR2]] { 1301 // CHECK4-NEXT: entry: 1302 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1303 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1304 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 1305 // CHECK4-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1306 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1307 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 1308 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1309 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1310 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1311 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1312 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 1313 // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 4 1314 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1315 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1316 // CHECK4-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1317 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1318 // CHECK4-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1319 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1320 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1321 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1322 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1323 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1324 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1325 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1326 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1327 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1328 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1329 // CHECK4: cond.true: 1330 // CHECK4-NEXT: br label [[COND_END:%.*]] 1331 // CHECK4: cond.false: 1332 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1333 // CHECK4-NEXT: br label [[COND_END]] 1334 // CHECK4: cond.end: 1335 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1336 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1337 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1338 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1339 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1340 // CHECK4: omp.inner.for.cond: 1341 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1342 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 1343 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1344 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1345 // CHECK4: omp.inner.for.body: 1346 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1347 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1348 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1349 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 1350 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1351 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !12 1352 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1353 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[T_VAR1]], align 4, !llvm.access.group !12 1354 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1355 // CHECK4: omp.body.continue: 1356 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1357 // CHECK4: omp.inner.for.inc: 1358 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1359 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 1360 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1361 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1362 // CHECK4: omp.inner.for.end: 1363 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1364 // CHECK4: omp.loop.exit: 1365 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1366 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1367 // CHECK4-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 1368 // CHECK4-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1369 // CHECK4: .omp.final.then: 1370 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 1371 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 1372 // CHECK4: .omp.final.done: 1373 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 1374 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i32* [[T_VAR1]] to i8* 1375 // CHECK4-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 4 1376 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1377 // CHECK4-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, i8* [[TMP16]], void (i8*, i8*)* @.omp.reduction.reduction_func.2, [8 x i32]* @.gomp_critical_user_.reduction.var) 1378 // CHECK4-NEXT: switch i32 [[TMP17]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1379 // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1380 // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1381 // CHECK4-NEXT: ] 1382 // CHECK4: .omp.reduction.case1: 1383 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP0]], align 4 1384 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[T_VAR1]], align 4 1385 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] 1386 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1387 // CHECK4-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1388 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1389 // CHECK4: .omp.reduction.case2: 1390 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[T_VAR1]], align 4 1391 // CHECK4-NEXT: [[TMP21:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP20]] monotonic, align 4 1392 // CHECK4-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1393 // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1394 // CHECK4: .omp.reduction.default: 1395 // CHECK4-NEXT: ret void 1396 // 1397 // 1398 // CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 1399 // CHECK4-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR4]] { 1400 // CHECK4-NEXT: entry: 1401 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1402 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 4 1403 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1404 // CHECK4-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 4 1405 // CHECK4-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 4 1406 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1407 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 4 1408 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1409 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i32 0, i32 0 1410 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 1411 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1412 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i32 0, i32 0 1413 // CHECK4-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 4 1414 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1415 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1416 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1417 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1418 // CHECK4-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1419 // CHECK4-NEXT: ret void 1420 // 1421 // 1422 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1423 // CHECK4-SAME: () #[[ATTR8:[0-9]+]] { 1424 // CHECK4-NEXT: entry: 1425 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 1426 // CHECK4-NEXT: ret void 1427 // 1428 // 1429 // CHECK5-LABEL: define {{[^@]+}}@main 1430 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1431 // CHECK5-NEXT: entry: 1432 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1433 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1434 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1435 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1436 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1437 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1438 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1439 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1440 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1441 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1442 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1443 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1444 // CHECK5-NEXT: store i32 0, i32* [[SIVAR]], align 4 1445 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1446 // CHECK5: omp.inner.for.cond: 1447 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1448 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 1449 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1450 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1451 // CHECK5: omp.inner.for.body: 1452 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1453 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1454 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1455 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 1456 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1457 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2 1458 // CHECK5-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1459 // CHECK5-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2 1460 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1461 // CHECK5: omp.body.continue: 1462 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1463 // CHECK5: omp.inner.for.inc: 1464 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1465 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1466 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1467 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1468 // CHECK5: omp.inner.for.end: 1469 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1470 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1471 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 1472 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1473 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 1474 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1475 // CHECK5-NEXT: ret i32 [[CALL]] 1476 // 1477 // 1478 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1479 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat { 1480 // CHECK5-NEXT: entry: 1481 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1482 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1483 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1484 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1485 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1486 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1487 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1488 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1489 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 1490 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1491 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1492 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1493 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1494 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1495 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1496 // CHECK5-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1497 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1498 // CHECK5: omp.inner.for.cond: 1499 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1500 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1501 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1502 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1503 // CHECK5: omp.inner.for.body: 1504 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1505 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1506 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1507 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1508 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1509 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6 1510 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 1511 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6 1512 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1513 // CHECK5: omp.body.continue: 1514 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1515 // CHECK5: omp.inner.for.inc: 1516 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1517 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 1518 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1519 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1520 // CHECK5: omp.inner.for.end: 1521 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1522 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1523 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 1524 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1525 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 1526 // CHECK5-NEXT: ret i32 0 1527 // 1528 // 1529 // CHECK6-LABEL: define {{[^@]+}}@main 1530 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 1531 // CHECK6-NEXT: entry: 1532 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1533 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 1534 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1535 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1536 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1537 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 1538 // CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1539 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 1540 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1541 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1542 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1543 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1544 // CHECK6-NEXT: store i32 0, i32* [[SIVAR]], align 4 1545 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1546 // CHECK6: omp.inner.for.cond: 1547 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1548 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 1549 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1550 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1551 // CHECK6: omp.inner.for.body: 1552 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1553 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1554 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1555 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 1556 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1557 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2 1558 // CHECK6-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1559 // CHECK6-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !2 1560 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1561 // CHECK6: omp.body.continue: 1562 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1563 // CHECK6: omp.inner.for.inc: 1564 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1565 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1566 // CHECK6-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1567 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1568 // CHECK6: omp.inner.for.end: 1569 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 1570 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1571 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 1572 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1573 // CHECK6-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 1574 // CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1575 // CHECK6-NEXT: ret i32 [[CALL]] 1576 // 1577 // 1578 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1579 // CHECK6-SAME: () #[[ATTR1:[0-9]+]] comdat { 1580 // CHECK6-NEXT: entry: 1581 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1582 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1583 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 1584 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1585 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1586 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1587 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 1588 // CHECK6-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1589 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 1590 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1591 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1592 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1593 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1594 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1595 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1596 // CHECK6-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1597 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1598 // CHECK6: omp.inner.for.cond: 1599 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1600 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1601 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1602 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1603 // CHECK6: omp.inner.for.body: 1604 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1605 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1606 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1607 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1608 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1609 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !6 1610 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 1611 // CHECK6-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !6 1612 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1613 // CHECK6: omp.body.continue: 1614 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1615 // CHECK6: omp.inner.for.inc: 1616 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1617 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 1618 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1619 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1620 // CHECK6: omp.inner.for.end: 1621 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 1622 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1623 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 1624 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1625 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 1626 // CHECK6-NEXT: ret i32 0 1627 // 1628 // 1629 // CHECK7-LABEL: define {{[^@]+}}@main 1630 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 1631 // CHECK7-NEXT: entry: 1632 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1633 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1634 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1635 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1636 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1637 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1638 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1639 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 1640 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1641 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1642 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1643 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1644 // CHECK7-NEXT: store i32 0, i32* [[SIVAR]], align 4 1645 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1646 // CHECK7: omp.inner.for.cond: 1647 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1648 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 1649 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1650 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1651 // CHECK7: omp.inner.for.body: 1652 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1653 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1654 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1655 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 1656 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1657 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3 1658 // CHECK7-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1659 // CHECK7-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3 1660 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1661 // CHECK7: omp.body.continue: 1662 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1663 // CHECK7: omp.inner.for.inc: 1664 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1665 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1666 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1667 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1668 // CHECK7: omp.inner.for.end: 1669 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 1670 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1671 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 1672 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1673 // CHECK7-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 1674 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1675 // CHECK7-NEXT: ret i32 [[CALL]] 1676 // 1677 // 1678 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1679 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat { 1680 // CHECK7-NEXT: entry: 1681 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1682 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1683 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1684 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1685 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1686 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1687 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1688 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1689 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 1690 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1691 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1692 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1693 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1694 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1695 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1696 // CHECK7-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1697 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1698 // CHECK7: omp.inner.for.cond: 1699 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1700 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1701 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1702 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1703 // CHECK7: omp.inner.for.body: 1704 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1705 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1706 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1707 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 1708 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1709 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7 1710 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 1711 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7 1712 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1713 // CHECK7: omp.body.continue: 1714 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1715 // CHECK7: omp.inner.for.inc: 1716 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1717 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 1718 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1719 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1720 // CHECK7: omp.inner.for.end: 1721 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 1722 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1723 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 1724 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1725 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 1726 // CHECK7-NEXT: ret i32 0 1727 // 1728 // 1729 // CHECK8-LABEL: define {{[^@]+}}@main 1730 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 1731 // CHECK8-NEXT: entry: 1732 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1733 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 1734 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1735 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1736 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1737 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 1738 // CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1739 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 1740 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1741 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1742 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1743 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1744 // CHECK8-NEXT: store i32 0, i32* [[SIVAR]], align 4 1745 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1746 // CHECK8: omp.inner.for.cond: 1747 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1748 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 1749 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1750 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1751 // CHECK8: omp.inner.for.body: 1752 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1753 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1754 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1755 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 1756 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 1757 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3 1758 // CHECK8-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] 1759 // CHECK8-NEXT: store i32 [[ADD1]], i32* [[SIVAR]], align 4, !llvm.access.group !3 1760 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1761 // CHECK8: omp.body.continue: 1762 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1763 // CHECK8: omp.inner.for.inc: 1764 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1765 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 1766 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 1767 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1768 // CHECK8: omp.inner.for.end: 1769 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 1770 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1771 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[SIVAR]], align 4 1772 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]] 1773 // CHECK8-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4 1774 // CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1775 // CHECK8-NEXT: ret i32 [[CALL]] 1776 // 1777 // 1778 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1779 // CHECK8-SAME: () #[[ATTR1:[0-9]+]] comdat { 1780 // CHECK8-NEXT: entry: 1781 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1782 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1783 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 1784 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1785 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1786 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1787 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 1788 // CHECK8-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1789 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 1790 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1791 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1792 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1793 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1794 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1795 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4 1796 // CHECK8-NEXT: store i32 0, i32* [[T_VAR1]], align 4 1797 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1798 // CHECK8: omp.inner.for.cond: 1799 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1800 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1801 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] 1802 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1803 // CHECK8: omp.inner.for.body: 1804 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1805 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1 1806 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1807 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 1808 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1809 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR1]], align 4, !llvm.access.group !7 1810 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] 1811 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[T_VAR1]], align 4, !llvm.access.group !7 1812 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1813 // CHECK8: omp.body.continue: 1814 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1815 // CHECK8: omp.inner.for.inc: 1816 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1817 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 1818 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1819 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1820 // CHECK8: omp.inner.for.end: 1821 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 1822 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4 1823 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 4 1824 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] 1825 // CHECK8-NEXT: store i32 [[ADD4]], i32* [[T_VAR]], align 4 1826 // CHECK8-NEXT: ret i32 0 1827 // 1828 // 1829 // CHECK9-LABEL: define {{[^@]+}}@main 1830 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1831 // CHECK9-NEXT: entry: 1832 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1833 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1834 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 1835 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 1836 // CHECK9-NEXT: ret i32 0 1837 // 1838 // 1839 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 1840 // CHECK9-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 1841 // CHECK9-NEXT: entry: 1842 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 1843 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 1844 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 1845 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) 1846 // CHECK9-NEXT: ret void 1847 // 1848 // 1849 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 1850 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 1851 // CHECK9-NEXT: entry: 1852 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1853 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1854 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 1855 // CHECK9-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1856 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1857 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1858 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1859 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1860 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1861 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1862 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1863 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1864 // CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 1865 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1866 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1867 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 1868 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 1869 // CHECK9-NEXT: store i32 0, i32* [[SIVAR1]], align 4 1870 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1871 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1872 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1873 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1874 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1875 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1876 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1877 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1878 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 1879 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1880 // CHECK9: cond.true: 1881 // CHECK9-NEXT: br label [[COND_END:%.*]] 1882 // CHECK9: cond.false: 1883 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1884 // CHECK9-NEXT: br label [[COND_END]] 1885 // CHECK9: cond.end: 1886 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1887 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1888 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1889 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1890 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1891 // CHECK9: omp.inner.for.cond: 1892 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1893 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 1894 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1895 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1896 // CHECK9: omp.inner.for.body: 1897 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1898 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1899 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1900 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 1901 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 1902 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 1903 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 1904 // CHECK9-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 1905 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 1906 // CHECK9-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 1907 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 1908 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1909 // CHECK9: omp.body.continue: 1910 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1911 // CHECK9: omp.inner.for.inc: 1912 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1913 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 1914 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 1915 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 1916 // CHECK9: omp.inner.for.end: 1917 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1918 // CHECK9: omp.loop.exit: 1919 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1920 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1921 // CHECK9-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1922 // CHECK9-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1923 // CHECK9: .omp.final.then: 1924 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 1925 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1926 // CHECK9: .omp.final.done: 1927 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 1928 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR1]] to i8* 1929 // CHECK9-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 1930 // CHECK9-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 1931 // CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 1932 // CHECK9-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 1933 // CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 1934 // CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 1935 // CHECK9-NEXT: ] 1936 // CHECK9: .omp.reduction.case1: 1937 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 1938 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 1939 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 1940 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 1941 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1942 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1943 // CHECK9: .omp.reduction.case2: 1944 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4 1945 // CHECK9-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 1946 // CHECK9-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 1947 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 1948 // CHECK9: .omp.reduction.default: 1949 // CHECK9-NEXT: ret void 1950 // 1951 // 1952 // CHECK9-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 1953 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 1954 // CHECK9-NEXT: entry: 1955 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1956 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 1957 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1958 // CHECK9-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 1959 // CHECK9-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 1960 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 1961 // CHECK9-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 1962 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 1963 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 1964 // CHECK9-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1965 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 1966 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 1967 // CHECK9-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 1968 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 1969 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1970 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 1971 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 1972 // CHECK9-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 1973 // CHECK9-NEXT: ret void 1974 // 1975 // 1976 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1977 // CHECK9-SAME: () #[[ATTR7:[0-9]+]] { 1978 // CHECK9-NEXT: entry: 1979 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1980 // CHECK9-NEXT: ret void 1981 // 1982 // 1983 // CHECK10-LABEL: define {{[^@]+}}@main 1984 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 1985 // CHECK10-NEXT: entry: 1986 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1987 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 1988 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1989 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 1990 // CHECK10-NEXT: ret i32 0 1991 // 1992 // 1993 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l44 1994 // CHECK10-SAME: (i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 1995 // CHECK10-NEXT: entry: 1996 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 1997 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 1998 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 1999 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[TMP0]]) 2000 // CHECK10-NEXT: ret void 2001 // 2002 // 2003 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 2004 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 2005 // CHECK10-NEXT: entry: 2006 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2007 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2008 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 2009 // CHECK10-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 2010 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2011 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 2012 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2013 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2014 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2015 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2016 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 2017 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2018 // CHECK10-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x i8*], align 8 2019 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2020 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2021 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 2022 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 2023 // CHECK10-NEXT: store i32 0, i32* [[SIVAR1]], align 4 2024 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2025 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2026 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2027 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2028 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2029 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2030 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2031 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2032 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1 2033 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2034 // CHECK10: cond.true: 2035 // CHECK10-NEXT: br label [[COND_END:%.*]] 2036 // CHECK10: cond.false: 2037 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2038 // CHECK10-NEXT: br label [[COND_END]] 2039 // CHECK10: cond.end: 2040 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2041 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2042 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2043 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2044 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2045 // CHECK10: omp.inner.for.cond: 2046 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2047 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 2048 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2049 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2050 // CHECK10: omp.inner.for.body: 2051 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2052 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 2053 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2054 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 2055 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 2056 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR1]], align 4, !llvm.access.group !4 2057 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] 2058 // CHECK10-NEXT: store i32 [[ADD3]], i32* [[SIVAR1]], align 4, !llvm.access.group !4 2059 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 2060 // CHECK10-NEXT: store i32* [[SIVAR1]], i32** [[TMP11]], align 8, !llvm.access.group !4 2061 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 2062 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2063 // CHECK10: omp.body.continue: 2064 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2065 // CHECK10: omp.inner.for.inc: 2066 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2067 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2068 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2069 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2070 // CHECK10: omp.inner.for.end: 2071 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2072 // CHECK10: omp.loop.exit: 2073 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2074 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2075 // CHECK10-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2076 // CHECK10-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2077 // CHECK10: .omp.final.then: 2078 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 2079 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] 2080 // CHECK10: .omp.final.done: 2081 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 2082 // CHECK10-NEXT: [[TMP16:%.*]] = bitcast i32* [[SIVAR1]] to i8* 2083 // CHECK10-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8 2084 // CHECK10-NEXT: [[TMP17:%.*]] = bitcast [1 x i8*]* [[DOTOMP_REDUCTION_RED_LIST]] to i8* 2085 // CHECK10-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, i8* [[TMP17]], void (i8*, i8*)* @.omp.reduction.reduction_func, [8 x i32]* @.gomp_critical_user_.reduction.var) 2086 // CHECK10-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ 2087 // CHECK10-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] 2088 // CHECK10-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] 2089 // CHECK10-NEXT: ] 2090 // CHECK10: .omp.reduction.case1: 2091 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP0]], align 4 2092 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[SIVAR1]], align 4 2093 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] 2094 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[TMP0]], align 4 2095 // CHECK10-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 2096 // CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2097 // CHECK10: .omp.reduction.case2: 2098 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR1]], align 4 2099 // CHECK10-NEXT: [[TMP22:%.*]] = atomicrmw add i32* [[TMP0]], i32 [[TMP21]] monotonic, align 4 2100 // CHECK10-NEXT: call void @__kmpc_end_reduce(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], [8 x i32]* @.gomp_critical_user_.reduction.var) 2101 // CHECK10-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] 2102 // CHECK10: .omp.reduction.default: 2103 // CHECK10-NEXT: ret void 2104 // 2105 // 2106 // CHECK10-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func 2107 // CHECK10-SAME: (i8* noundef [[TMP0:%.*]], i8* noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2108 // CHECK10-NEXT: entry: 2109 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2110 // CHECK10-NEXT: [[DOTADDR1:%.*]] = alloca i8*, align 8 2111 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2112 // CHECK10-NEXT: store i8* [[TMP1]], i8** [[DOTADDR1]], align 8 2113 // CHECK10-NEXT: [[TMP2:%.*]] = load i8*, i8** [[DOTADDR]], align 8 2114 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [1 x i8*]* 2115 // CHECK10-NEXT: [[TMP4:%.*]] = load i8*, i8** [[DOTADDR1]], align 8 2116 // CHECK10-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to [1 x i8*]* 2117 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP5]], i64 0, i64 0 2118 // CHECK10-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2119 // CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32* 2120 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[TMP3]], i64 0, i64 0 2121 // CHECK10-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8 2122 // CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8* [[TMP10]] to i32* 2123 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 2124 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP8]], align 4 2125 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] 2126 // CHECK10-NEXT: store i32 [[ADD]], i32* [[TMP11]], align 4 2127 // CHECK10-NEXT: ret void 2128 // 2129 // 2130 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2131 // CHECK10-SAME: () #[[ATTR7:[0-9]+]] { 2132 // CHECK10-NEXT: entry: 2133 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 2134 // CHECK10-NEXT: ret void 2135 // 2136 // 2137 // CHECK11-LABEL: define {{[^@]+}}@main 2138 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2139 // CHECK11-NEXT: entry: 2140 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2141 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2142 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 2143 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 2144 // CHECK11-NEXT: ret i32 0 2145 // 2146 // 2147 // CHECK12-LABEL: define {{[^@]+}}@main 2148 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 2149 // CHECK12-NEXT: entry: 2150 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2151 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2152 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2153 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 2154 // CHECK12-NEXT: ret i32 0 2155 // 2156