1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -no-opaque-pointers -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target teams distribute simd firstprivate(t_var, vec, s_arr, var) 57 for (int i = 0; i < 2; ++i) { 58 vec[i] = t_var; 59 s_arr[i] = var; 60 } 61 return T(); 62 } 63 64 S<float> test; 65 int t_var = 333; 66 int vec[] = {1, 2}; 67 S<float> s_arr[] = {1, 2}; 68 S<float> var(3); 69 70 int main() { 71 static int sivar; 72 #ifdef LAMBDA 73 [&]() { 74 #pragma omp target teams distribute simd firstprivate(g, g1, sivar) 75 for (int i = 0; i < 2; ++i) { 76 77 // Skip global and bound tid vars 78 // skip loop vars 79 g = 1; 80 g1 = 1; 81 sivar = 2; 82 [&]() { 83 g = 2; 84 g1 = 2; 85 sivar = 4; 86 87 }(); 88 } 89 }(); 90 return 0; 91 #else 92 #pragma omp target teams distribute simd firstprivate(t_var, vec, s_arr, var, sivar) 93 for (int i = 0; i < 2; ++i) { 94 vec[i] = t_var; 95 s_arr[i] = var; 96 sivar += i; 97 } 98 return tmain<int>(); 99 #endif 100 } 101 102 103 104 105 106 // Skip global and bound tid vars 107 // Skip temp vars for loop 108 109 // param copy 110 111 // T_VAR and SIVAR 112 113 // preparation vars 114 115 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 116 117 // firstprivate(s_arr) 118 119 // firstprivate(var) 120 121 122 123 124 125 126 // Skip global and bound tid vars 127 // Skip temp vars for loop 128 129 // param copy 130 131 132 // T_VAR and preparation variables 133 134 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 135 136 // firstprivate(s_arr) 137 138 // firstprivate(var) 139 140 141 #endif 142 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 143 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 144 // CHECK1-NEXT: entry: 145 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 146 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 151 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 154 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 156 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 157 // CHECK1-NEXT: ret void 158 // 159 // 160 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 161 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 164 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 165 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 166 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 167 // CHECK1-NEXT: ret void 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 171 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 174 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 175 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 176 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 177 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 178 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 179 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 180 // CHECK1-NEXT: ret void 181 // 182 // 183 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 184 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 187 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: ret void 190 // 191 // 192 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 193 // CHECK1-SAME: () #[[ATTR0]] { 194 // CHECK1-NEXT: entry: 195 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 196 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 197 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 198 // CHECK1-NEXT: ret void 199 // 200 // 201 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 202 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 203 // CHECK1-NEXT: entry: 204 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 205 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 206 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 207 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 208 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 209 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 210 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 211 // CHECK1-NEXT: ret void 212 // 213 // 214 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 215 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 216 // CHECK1-NEXT: entry: 217 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 218 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 219 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 220 // CHECK1: arraydestroy.body: 221 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 222 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 223 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 224 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 225 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 226 // CHECK1: arraydestroy.done1: 227 // CHECK1-NEXT: ret void 228 // 229 // 230 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 231 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 232 // CHECK1-NEXT: entry: 233 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 234 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 235 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 236 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 237 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 238 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 239 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 241 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 242 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 243 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 244 // CHECK1-NEXT: ret void 245 // 246 // 247 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 248 // CHECK1-SAME: () #[[ATTR0]] { 249 // CHECK1-NEXT: entry: 250 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 251 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 252 // CHECK1-NEXT: ret void 253 // 254 // 255 // CHECK1-LABEL: define {{[^@]+}}@main 256 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 257 // CHECK1-NEXT: entry: 258 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 259 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 260 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 261 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 262 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 263 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 264 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 265 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 266 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 267 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 268 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 269 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 270 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 271 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 272 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 273 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 274 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 275 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 276 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 8 277 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 278 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 279 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 8 280 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 281 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 282 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 283 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 284 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 285 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 286 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 287 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 288 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 289 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 290 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 291 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 292 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 293 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 294 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 295 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 296 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 297 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 298 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 299 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 300 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 301 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 302 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 303 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 304 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 305 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 306 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 307 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 308 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 309 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 310 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 311 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 312 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 313 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 314 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 315 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 316 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 317 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 318 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 319 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 320 // CHECK1: omp_offload.failed: 321 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 322 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 323 // CHECK1: omp_offload.cont: 324 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 325 // CHECK1-NEXT: ret i32 [[CALL]] 326 // 327 // 328 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 329 // CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 330 // CHECK1-NEXT: entry: 331 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 332 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 334 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 335 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 336 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 337 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 338 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 339 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 340 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 341 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 342 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 343 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 344 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 345 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 346 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 347 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 348 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 349 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 350 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 351 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 352 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 353 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 354 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 355 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 356 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 357 // CHECK1-NEXT: ret void 358 // 359 // 360 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 361 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 362 // CHECK1-NEXT: entry: 363 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 364 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 365 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 366 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 367 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 368 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 369 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 370 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 371 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 372 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 373 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 374 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 375 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 376 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 377 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 378 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 379 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 380 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 381 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 383 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 384 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 385 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 386 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 387 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 388 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 389 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 390 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 391 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 392 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 393 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 394 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 395 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 396 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 398 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 399 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 400 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 401 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 402 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 403 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 404 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 405 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 406 // CHECK1: omp.arraycpy.body: 407 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 408 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 409 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 410 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 411 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 412 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 413 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 414 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 415 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 416 // CHECK1: omp.arraycpy.done4: 417 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 418 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) 419 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 420 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 421 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 422 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 423 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 424 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 425 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 426 // CHECK1: cond.true: 427 // CHECK1-NEXT: br label [[COND_END:%.*]] 428 // CHECK1: cond.false: 429 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 430 // CHECK1-NEXT: br label [[COND_END]] 431 // CHECK1: cond.end: 432 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 433 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 434 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 435 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 436 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 437 // CHECK1: omp.inner.for.cond: 438 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 439 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 440 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 441 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 442 // CHECK1: omp.inner.for.cond.cleanup: 443 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 444 // CHECK1: omp.inner.for.body: 445 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 446 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 447 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 448 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 449 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5 450 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 451 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 452 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 453 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 454 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 455 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 456 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 457 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* 458 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 459 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 460 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 461 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5 462 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 463 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5 464 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 465 // CHECK1: omp.body.continue: 466 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 467 // CHECK1: omp.inner.for.inc: 468 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 469 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 470 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 471 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 472 // CHECK1: omp.inner.for.end: 473 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 474 // CHECK1: omp.loop.exit: 475 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 476 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 477 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 478 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 479 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 480 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 481 // CHECK1: .omp.final.then: 482 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 483 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 484 // CHECK1: .omp.final.done: 485 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 486 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 487 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 488 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 489 // CHECK1: arraydestroy.body: 490 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 491 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 492 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 493 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 494 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 495 // CHECK1: arraydestroy.done13: 496 // CHECK1-NEXT: ret void 497 // 498 // 499 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 500 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 501 // CHECK1-NEXT: entry: 502 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 503 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 504 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 505 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 506 // CHECK1-NEXT: ret void 507 // 508 // 509 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 510 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 511 // CHECK1-NEXT: entry: 512 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 513 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 514 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 515 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 516 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 517 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 518 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 519 // CHECK1-NEXT: ret void 520 // 521 // 522 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 523 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 524 // CHECK1-NEXT: entry: 525 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 526 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 527 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 528 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 529 // CHECK1-NEXT: ret void 530 // 531 // 532 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 533 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat { 534 // CHECK1-NEXT: entry: 535 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 536 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 537 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 538 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 539 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 540 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 541 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 542 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 543 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 544 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 545 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 546 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 547 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 548 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 549 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 550 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 551 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 552 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 553 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 554 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 555 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 556 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 557 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 558 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 559 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 560 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 561 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 562 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 563 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 564 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 565 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8 566 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 567 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 568 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 569 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 570 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 571 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 572 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 573 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 574 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 575 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 576 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 577 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 578 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 579 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 580 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 581 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8 582 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 583 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 584 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 585 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 586 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 587 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 588 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 589 // CHECK1-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8 590 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 591 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 592 // CHECK1-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8 593 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 594 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 595 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 596 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 597 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 598 // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 599 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 600 // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 601 // CHECK1: omp_offload.failed: 602 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 603 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 604 // CHECK1: omp_offload.cont: 605 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 606 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 607 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 608 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 609 // CHECK1: arraydestroy.body: 610 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 611 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 612 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 613 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 614 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 615 // CHECK1: arraydestroy.done2: 616 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 617 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 618 // CHECK1-NEXT: ret i32 [[TMP30]] 619 // 620 // 621 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 622 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 623 // CHECK1-NEXT: entry: 624 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 625 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 626 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 627 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 628 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 629 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 630 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4 631 // CHECK1-NEXT: ret void 632 // 633 // 634 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 635 // CHECK1-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 636 // CHECK1-NEXT: entry: 637 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 638 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 639 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 640 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 641 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 642 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 643 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 644 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 645 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 646 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 647 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 648 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 649 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 650 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 651 // CHECK1-NEXT: ret void 652 // 653 // 654 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 655 // CHECK1-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 656 // CHECK1-NEXT: entry: 657 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 658 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 659 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 660 // CHECK1-NEXT: ret void 661 // 662 // 663 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 664 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 665 // CHECK1-NEXT: entry: 666 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 667 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 668 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 669 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 670 // CHECK1-NEXT: ret void 671 // 672 // 673 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 674 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 675 // CHECK1-NEXT: entry: 676 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 677 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 678 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 679 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 680 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 681 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 682 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 683 // CHECK1-NEXT: ret void 684 // 685 // 686 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 687 // CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 688 // CHECK1-NEXT: entry: 689 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 690 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 691 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 692 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 693 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 694 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 695 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 696 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 697 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 698 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 699 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 700 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 701 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 702 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 703 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 704 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 705 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 706 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 707 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 708 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 709 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 710 // CHECK1-NEXT: ret void 711 // 712 // 713 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 714 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { 715 // CHECK1-NEXT: entry: 716 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 717 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 718 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 719 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 720 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 721 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 722 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 723 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 724 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 725 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 726 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 727 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 728 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 729 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 730 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 731 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 732 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 733 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 734 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 735 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 736 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 737 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 738 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 739 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 740 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 741 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 742 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 743 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 744 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 745 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 746 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 747 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 748 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 749 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 750 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 751 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 752 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 753 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 754 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 755 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 756 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 757 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 758 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 759 // CHECK1: omp.arraycpy.body: 760 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 761 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 762 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 763 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 764 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 765 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 766 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 767 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 768 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 769 // CHECK1: omp.arraycpy.done4: 770 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 771 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 772 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) 773 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 774 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 775 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 776 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 777 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 778 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 779 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 780 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 781 // CHECK1: cond.true: 782 // CHECK1-NEXT: br label [[COND_END:%.*]] 783 // CHECK1: cond.false: 784 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 785 // CHECK1-NEXT: br label [[COND_END]] 786 // CHECK1: cond.end: 787 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 788 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 789 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 790 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 791 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 792 // CHECK1: omp.inner.for.cond: 793 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 794 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 795 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 796 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 797 // CHECK1: omp.inner.for.cond.cleanup: 798 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 799 // CHECK1: omp.inner.for.body: 800 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 801 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 802 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 803 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 804 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11 805 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 806 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 807 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 808 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 809 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 810 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 811 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 812 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 813 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* 814 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 815 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !11 816 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 817 // CHECK1: omp.body.continue: 818 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 819 // CHECK1: omp.inner.for.inc: 820 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 821 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 822 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 823 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 824 // CHECK1: omp.inner.for.end: 825 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 826 // CHECK1: omp.loop.exit: 827 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 828 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 829 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 830 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 831 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 832 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 833 // CHECK1: .omp.final.then: 834 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 835 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 836 // CHECK1: .omp.final.done: 837 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 838 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 839 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 840 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 841 // CHECK1: arraydestroy.body: 842 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 843 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 844 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 845 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 846 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 847 // CHECK1: arraydestroy.done13: 848 // CHECK1-NEXT: ret void 849 // 850 // 851 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 852 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 853 // CHECK1-NEXT: entry: 854 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 855 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 856 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 857 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 858 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 859 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 860 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 861 // CHECK1-NEXT: ret void 862 // 863 // 864 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 865 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 866 // CHECK1-NEXT: entry: 867 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 868 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 869 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 870 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 871 // CHECK1-NEXT: ret void 872 // 873 // 874 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 875 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 876 // CHECK1-NEXT: entry: 877 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 878 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 879 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 880 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 881 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 882 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 883 // CHECK1-NEXT: ret void 884 // 885 // 886 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 887 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 888 // CHECK1-NEXT: entry: 889 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 890 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 891 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 892 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 893 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 894 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 895 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 896 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 897 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 898 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 899 // CHECK1-NEXT: ret void 900 // 901 // 902 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 903 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 904 // CHECK1-NEXT: entry: 905 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 906 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 907 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 908 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 909 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 910 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 911 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 912 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 913 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 914 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 915 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 916 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 917 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 918 // CHECK1-NEXT: ret void 919 // 920 // 921 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 922 // CHECK1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 923 // CHECK1-NEXT: entry: 924 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 925 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 926 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 927 // CHECK1-NEXT: ret void 928 // 929 // 930 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 931 // CHECK1-SAME: () #[[ATTR0]] { 932 // CHECK1-NEXT: entry: 933 // CHECK1-NEXT: call void @__cxx_global_var_init() 934 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 935 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 936 // CHECK1-NEXT: ret void 937 // 938 // 939 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 940 // CHECK1-SAME: () #[[ATTR0]] { 941 // CHECK1-NEXT: entry: 942 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 943 // CHECK1-NEXT: ret void 944 // 945 // 946 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 947 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 948 // CHECK3-NEXT: entry: 949 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 950 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 951 // CHECK3-NEXT: ret void 952 // 953 // 954 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 955 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 956 // CHECK3-NEXT: entry: 957 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 958 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 959 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 960 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 961 // CHECK3-NEXT: ret void 962 // 963 // 964 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 965 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 966 // CHECK3-NEXT: entry: 967 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 968 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 969 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 970 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 971 // CHECK3-NEXT: ret void 972 // 973 // 974 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 975 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 976 // CHECK3-NEXT: entry: 977 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 978 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 979 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 980 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 981 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 982 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 983 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 984 // CHECK3-NEXT: ret void 985 // 986 // 987 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 988 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 989 // CHECK3-NEXT: entry: 990 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 991 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 992 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 993 // CHECK3-NEXT: ret void 994 // 995 // 996 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 997 // CHECK3-SAME: () #[[ATTR0]] { 998 // CHECK3-NEXT: entry: 999 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 1000 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 1001 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1002 // CHECK3-NEXT: ret void 1003 // 1004 // 1005 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1006 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1007 // CHECK3-NEXT: entry: 1008 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1009 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1010 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1011 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1012 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1013 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1014 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1015 // CHECK3-NEXT: ret void 1016 // 1017 // 1018 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1019 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1020 // CHECK3-NEXT: entry: 1021 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1022 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1023 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1024 // CHECK3: arraydestroy.body: 1025 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1026 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1027 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1028 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1029 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1030 // CHECK3: arraydestroy.done1: 1031 // CHECK3-NEXT: ret void 1032 // 1033 // 1034 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1035 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1036 // CHECK3-NEXT: entry: 1037 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1038 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1039 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1040 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1041 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1042 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1043 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1044 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1045 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1046 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1047 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1048 // CHECK3-NEXT: ret void 1049 // 1050 // 1051 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1052 // CHECK3-SAME: () #[[ATTR0]] { 1053 // CHECK3-NEXT: entry: 1054 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1055 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1056 // CHECK3-NEXT: ret void 1057 // 1058 // 1059 // CHECK3-LABEL: define {{[^@]+}}@main 1060 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1061 // CHECK3-NEXT: entry: 1062 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1063 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1064 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1065 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1066 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1067 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1068 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1069 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1070 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1071 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 1072 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1073 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1074 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 1075 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1076 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1077 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 1078 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 4 1079 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1080 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 1081 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 4 1082 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1083 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1084 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1085 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1086 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 1087 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1088 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1089 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 1090 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1091 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1092 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1093 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 1094 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 1095 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1096 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 1097 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 1098 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1099 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1100 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1101 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 1102 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 1103 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1104 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 1105 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 1106 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1107 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1108 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1109 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1110 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 1111 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1112 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 1113 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 1114 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1115 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 1116 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1117 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1118 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1119 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1120 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1121 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1122 // CHECK3: omp_offload.failed: 1123 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 1124 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1125 // CHECK3: omp_offload.cont: 1126 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1127 // CHECK3-NEXT: ret i32 [[CALL]] 1128 // 1129 // 1130 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 1131 // CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1132 // CHECK3-NEXT: entry: 1133 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1134 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1135 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1136 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1137 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1138 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1139 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1140 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1141 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1142 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1143 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1144 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1145 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1146 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1147 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1148 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1149 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 1150 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1151 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 1152 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 1153 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1154 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 1155 // CHECK3-NEXT: ret void 1156 // 1157 // 1158 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1159 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 1160 // CHECK3-NEXT: entry: 1161 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1162 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1163 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1164 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1165 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1166 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1167 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1168 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1169 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1170 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1171 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1172 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1173 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1174 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1175 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1176 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1177 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1178 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1179 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1180 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1181 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1182 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1183 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1184 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1185 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1186 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1187 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1188 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1189 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1190 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1191 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1192 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1193 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1194 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 1195 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1196 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 1197 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1198 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1199 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1200 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1201 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1202 // CHECK3: omp.arraycpy.body: 1203 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1204 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1205 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1206 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 1207 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1208 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1209 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1210 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1211 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1212 // CHECK3: omp.arraycpy.done3: 1213 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1214 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) 1215 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] 1216 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1217 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1218 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1219 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1220 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1221 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1222 // CHECK3: cond.true: 1223 // CHECK3-NEXT: br label [[COND_END:%.*]] 1224 // CHECK3: cond.false: 1225 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1226 // CHECK3-NEXT: br label [[COND_END]] 1227 // CHECK3: cond.end: 1228 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1229 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1230 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1231 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 1232 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1233 // CHECK3: omp.inner.for.cond: 1234 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1235 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1236 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1237 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1238 // CHECK3: omp.inner.for.cond.cleanup: 1239 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1240 // CHECK3: omp.inner.for.body: 1241 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1242 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 1243 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1244 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1245 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 1246 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1247 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] 1248 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 1249 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1250 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] 1251 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 1252 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 1253 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6 1254 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1255 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 1256 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 1257 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 1258 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1259 // CHECK3: omp.body.continue: 1260 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1261 // CHECK3: omp.inner.for.inc: 1262 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1263 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 1264 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1265 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1266 // CHECK3: omp.inner.for.end: 1267 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1268 // CHECK3: omp.loop.exit: 1269 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1270 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1271 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1272 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1273 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1274 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1275 // CHECK3: .omp.final.then: 1276 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 1277 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1278 // CHECK3: .omp.final.done: 1279 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] 1280 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1281 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 1282 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1283 // CHECK3: arraydestroy.body: 1284 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1285 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1286 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1287 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1288 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1289 // CHECK3: arraydestroy.done11: 1290 // CHECK3-NEXT: ret void 1291 // 1292 // 1293 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1294 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1295 // CHECK3-NEXT: entry: 1296 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1297 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1298 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1299 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) 1300 // CHECK3-NEXT: ret void 1301 // 1302 // 1303 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1304 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1305 // CHECK3-NEXT: entry: 1306 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1307 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 1308 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1309 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 1310 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1311 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 1312 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 1313 // CHECK3-NEXT: ret void 1314 // 1315 // 1316 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1317 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1318 // CHECK3-NEXT: entry: 1319 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1320 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1321 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1322 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 1323 // CHECK3-NEXT: ret void 1324 // 1325 // 1326 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1327 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat { 1328 // CHECK3-NEXT: entry: 1329 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1330 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1331 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1332 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1333 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1334 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 1335 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 1336 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1337 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1338 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1339 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1340 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1341 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1342 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 1343 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1344 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1345 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1346 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 1347 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1348 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1349 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 1350 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 1351 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 1352 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 1353 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 1354 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1355 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 1356 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1357 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 1358 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4 1359 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1360 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 1361 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 1362 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1363 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 1364 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1365 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 1366 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 1367 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1368 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 1369 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 1370 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1371 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 1372 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1373 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 1374 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4 1375 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1376 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 1377 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 1378 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1379 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 1380 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1381 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 1382 // CHECK3-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4 1383 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1384 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 1385 // CHECK3-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4 1386 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1387 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4 1388 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1389 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1390 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 1391 // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1392 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 1393 // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1394 // CHECK3: omp_offload.failed: 1395 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 1396 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1397 // CHECK3: omp_offload.cont: 1398 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1399 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1400 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1401 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1402 // CHECK3: arraydestroy.body: 1403 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1404 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1405 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1406 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1407 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1408 // CHECK3: arraydestroy.done2: 1409 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1410 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 1411 // CHECK3-NEXT: ret i32 [[TMP30]] 1412 // 1413 // 1414 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1415 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1416 // CHECK3-NEXT: entry: 1417 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1418 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1419 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1420 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1421 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1422 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1423 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4 1424 // CHECK3-NEXT: ret void 1425 // 1426 // 1427 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1428 // CHECK3-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1429 // CHECK3-NEXT: entry: 1430 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1431 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 1432 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1433 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 1434 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1435 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1436 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 1437 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1438 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1439 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1440 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1441 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1442 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1443 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1444 // CHECK3-NEXT: ret void 1445 // 1446 // 1447 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1448 // CHECK3-SAME: (%struct.St* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1449 // CHECK3-NEXT: entry: 1450 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1451 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1452 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1453 // CHECK3-NEXT: ret void 1454 // 1455 // 1456 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1457 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1458 // CHECK3-NEXT: entry: 1459 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1460 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1461 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1462 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1463 // CHECK3-NEXT: ret void 1464 // 1465 // 1466 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1467 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1468 // CHECK3-NEXT: entry: 1469 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1470 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1471 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1472 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1473 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1474 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1475 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1476 // CHECK3-NEXT: ret void 1477 // 1478 // 1479 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1480 // CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1481 // CHECK3-NEXT: entry: 1482 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1483 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1484 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 1485 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 1486 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 1487 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1488 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1489 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1490 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1491 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 1492 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1493 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1494 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 1495 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 1496 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1497 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 1498 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1499 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 1500 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 1501 // CHECK3-NEXT: ret void 1502 // 1503 // 1504 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 1505 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { 1506 // CHECK3-NEXT: entry: 1507 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1508 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1509 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1510 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1511 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 1512 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 1513 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 1514 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1515 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1516 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1517 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1518 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1519 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1520 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1521 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1522 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1523 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1524 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1525 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 1526 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1527 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1528 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1529 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1530 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1531 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1532 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 1533 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1534 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1535 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 1536 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 1537 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1538 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1539 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1540 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1541 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1542 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1543 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 1544 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1545 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 1546 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1547 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 1548 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1549 // CHECK3: omp.arraycpy.body: 1550 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1551 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1552 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1553 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 1554 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1555 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1556 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1557 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1558 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1559 // CHECK3: omp.arraycpy.done4: 1560 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 1561 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1562 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) 1563 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1564 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 1565 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1566 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 1567 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1568 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1569 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 1570 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1571 // CHECK3: cond.true: 1572 // CHECK3-NEXT: br label [[COND_END:%.*]] 1573 // CHECK3: cond.false: 1574 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1575 // CHECK3-NEXT: br label [[COND_END]] 1576 // CHECK3: cond.end: 1577 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1578 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1579 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1580 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1581 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1582 // CHECK3: omp.inner.for.cond: 1583 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1584 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 1585 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1586 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1587 // CHECK3: omp.inner.for.cond.cleanup: 1588 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1589 // CHECK3: omp.inner.for.body: 1590 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1591 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 1592 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1593 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 1594 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !12 1595 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1596 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] 1597 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 1598 // CHECK3-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12 1599 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1600 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] 1601 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 1602 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 1603 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !12 1604 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1605 // CHECK3: omp.body.continue: 1606 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1607 // CHECK3: omp.inner.for.inc: 1608 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1609 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 1610 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1611 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1612 // CHECK3: omp.inner.for.end: 1613 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1614 // CHECK3: omp.loop.exit: 1615 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1616 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1617 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1618 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1619 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1620 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1621 // CHECK3: .omp.final.then: 1622 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 1623 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1624 // CHECK3: .omp.final.done: 1625 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1626 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1627 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 1628 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1629 // CHECK3: arraydestroy.body: 1630 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1631 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1632 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1633 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 1634 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 1635 // CHECK3: arraydestroy.done12: 1636 // CHECK3-NEXT: ret void 1637 // 1638 // 1639 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1640 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1641 // CHECK3-NEXT: entry: 1642 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1643 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 1644 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1645 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 1646 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1647 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 1648 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 1649 // CHECK3-NEXT: ret void 1650 // 1651 // 1652 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1653 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1654 // CHECK3-NEXT: entry: 1655 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1656 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1657 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1658 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1659 // CHECK3-NEXT: ret void 1660 // 1661 // 1662 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1663 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1664 // CHECK3-NEXT: entry: 1665 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1666 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1667 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1668 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1669 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1670 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1671 // CHECK3-NEXT: ret void 1672 // 1673 // 1674 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1675 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1676 // CHECK3-NEXT: entry: 1677 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1678 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1679 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1680 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1681 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1682 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1683 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1684 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1685 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1686 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1687 // CHECK3-NEXT: ret void 1688 // 1689 // 1690 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1691 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1692 // CHECK3-NEXT: entry: 1693 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1694 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 1695 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1696 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 1697 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1698 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1699 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 1700 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1701 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1702 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1703 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1704 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1705 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1706 // CHECK3-NEXT: ret void 1707 // 1708 // 1709 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1710 // CHECK3-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1711 // CHECK3-NEXT: entry: 1712 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1713 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1714 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1715 // CHECK3-NEXT: ret void 1716 // 1717 // 1718 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 1719 // CHECK3-SAME: () #[[ATTR0]] { 1720 // CHECK3-NEXT: entry: 1721 // CHECK3-NEXT: call void @__cxx_global_var_init() 1722 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1723 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1724 // CHECK3-NEXT: ret void 1725 // 1726 // 1727 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1728 // CHECK3-SAME: () #[[ATTR0]] { 1729 // CHECK3-NEXT: entry: 1730 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1731 // CHECK3-NEXT: ret void 1732 // 1733 // 1734 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1735 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1736 // CHECK5-NEXT: entry: 1737 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 1738 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1739 // CHECK5-NEXT: ret void 1740 // 1741 // 1742 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1743 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1744 // CHECK5-NEXT: entry: 1745 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1746 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1747 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1748 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1749 // CHECK5-NEXT: ret void 1750 // 1751 // 1752 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1753 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1754 // CHECK5-NEXT: entry: 1755 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1756 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1757 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1758 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1759 // CHECK5-NEXT: ret void 1760 // 1761 // 1762 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1763 // CHECK5-SAME: () #[[ATTR0]] { 1764 // CHECK5-NEXT: entry: 1765 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 1766 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 1767 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1768 // CHECK5-NEXT: ret void 1769 // 1770 // 1771 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1772 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1773 // CHECK5-NEXT: entry: 1774 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1775 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1776 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1777 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1778 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1779 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1780 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1781 // CHECK5-NEXT: ret void 1782 // 1783 // 1784 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1785 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1786 // CHECK5-NEXT: entry: 1787 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1788 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1789 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1790 // CHECK5: arraydestroy.body: 1791 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1792 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1793 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1794 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1795 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1796 // CHECK5: arraydestroy.done1: 1797 // CHECK5-NEXT: ret void 1798 // 1799 // 1800 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1801 // CHECK5-SAME: () #[[ATTR0]] { 1802 // CHECK5-NEXT: entry: 1803 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1804 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1805 // CHECK5-NEXT: ret void 1806 // 1807 // 1808 // CHECK5-LABEL: define {{[^@]+}}@main 1809 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1810 // CHECK5-NEXT: entry: 1811 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1812 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1813 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1814 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1815 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1816 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1817 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1818 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1819 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1820 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1821 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1822 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1823 // CHECK5: omp.inner.for.cond: 1824 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1825 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 1826 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1827 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1828 // CHECK5: omp.inner.for.body: 1829 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1830 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1831 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1832 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 1833 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !2 1834 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1835 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1836 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 1837 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2 1838 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1839 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 1840 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 1841 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 1842 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false), !llvm.access.group !2 1843 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 1844 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2 1845 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 1846 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2 1847 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1848 // CHECK5: omp.body.continue: 1849 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1850 // CHECK5: omp.inner.for.inc: 1851 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1852 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 1853 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 1854 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1855 // CHECK5: omp.inner.for.end: 1856 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1857 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1858 // CHECK5-NEXT: ret i32 [[CALL]] 1859 // 1860 // 1861 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1862 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 1863 // CHECK5-NEXT: entry: 1864 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1865 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1866 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1867 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1868 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1869 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 1870 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1871 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1872 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1873 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1874 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1875 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1876 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1877 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 1878 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1879 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1880 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1881 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 1882 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1883 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1884 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 1885 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 1886 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 1887 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 1888 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 1889 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1890 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1891 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1892 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1893 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1894 // CHECK5: omp.inner.for.cond: 1895 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1896 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1897 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1898 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1899 // CHECK5: omp.inner.for.body: 1900 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1901 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1902 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1903 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1904 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 1905 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1906 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 1907 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 1908 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 1909 // CHECK5-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8, !llvm.access.group !6 1910 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1911 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP11]] to i64 1912 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 1913 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* 1914 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 1915 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6 1916 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1917 // CHECK5: omp.body.continue: 1918 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1919 // CHECK5: omp.inner.for.inc: 1920 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1921 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 1922 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1923 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1924 // CHECK5: omp.inner.for.end: 1925 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 1926 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1927 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1928 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1929 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1930 // CHECK5: arraydestroy.body: 1931 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1932 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1933 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1934 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1935 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1936 // CHECK5: arraydestroy.done5: 1937 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1938 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 1939 // CHECK5-NEXT: ret i32 [[TMP16]] 1940 // 1941 // 1942 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1943 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1944 // CHECK5-NEXT: entry: 1945 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1946 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1947 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1948 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1949 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1950 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1951 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 1952 // CHECK5-NEXT: ret void 1953 // 1954 // 1955 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1956 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1957 // CHECK5-NEXT: entry: 1958 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1959 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1960 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1961 // CHECK5-NEXT: ret void 1962 // 1963 // 1964 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1965 // CHECK5-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1966 // CHECK5-NEXT: entry: 1967 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1968 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1969 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1970 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1971 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1972 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1973 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1974 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1975 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1976 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1977 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 1978 // CHECK5-NEXT: ret void 1979 // 1980 // 1981 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1982 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1983 // CHECK5-NEXT: entry: 1984 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1985 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1986 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1987 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1988 // CHECK5-NEXT: ret void 1989 // 1990 // 1991 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1992 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1993 // CHECK5-NEXT: entry: 1994 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1995 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1996 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1997 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1998 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1999 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2000 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 2001 // CHECK5-NEXT: ret void 2002 // 2003 // 2004 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2005 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2006 // CHECK5-NEXT: entry: 2007 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2008 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2009 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2010 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2011 // CHECK5-NEXT: ret void 2012 // 2013 // 2014 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2015 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2016 // CHECK5-NEXT: entry: 2017 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2018 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2019 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2020 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2021 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2022 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2023 // CHECK5-NEXT: ret void 2024 // 2025 // 2026 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2027 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2028 // CHECK5-NEXT: entry: 2029 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2030 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2031 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2032 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2033 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2034 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2035 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2036 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2037 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2038 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2039 // CHECK5-NEXT: ret void 2040 // 2041 // 2042 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2043 // CHECK5-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2044 // CHECK5-NEXT: entry: 2045 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2046 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2047 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2048 // CHECK5-NEXT: ret void 2049 // 2050 // 2051 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 2052 // CHECK5-SAME: () #[[ATTR0]] { 2053 // CHECK5-NEXT: entry: 2054 // CHECK5-NEXT: call void @__cxx_global_var_init() 2055 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 2056 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 2057 // CHECK5-NEXT: ret void 2058 // 2059 // 2060 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 2061 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 2062 // CHECK7-NEXT: entry: 2063 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 2064 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2065 // CHECK7-NEXT: ret void 2066 // 2067 // 2068 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2069 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2070 // CHECK7-NEXT: entry: 2071 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2072 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2073 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2074 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2075 // CHECK7-NEXT: ret void 2076 // 2077 // 2078 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2079 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2080 // CHECK7-NEXT: entry: 2081 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2082 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2083 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2084 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2085 // CHECK7-NEXT: ret void 2086 // 2087 // 2088 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2089 // CHECK7-SAME: () #[[ATTR0]] { 2090 // CHECK7-NEXT: entry: 2091 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 2092 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 2093 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2094 // CHECK7-NEXT: ret void 2095 // 2096 // 2097 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2098 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2099 // CHECK7-NEXT: entry: 2100 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2101 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2102 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2103 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2104 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2105 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2106 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2107 // CHECK7-NEXT: ret void 2108 // 2109 // 2110 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2111 // CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2112 // CHECK7-NEXT: entry: 2113 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 2114 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 2115 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2116 // CHECK7: arraydestroy.body: 2117 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2118 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2119 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2120 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2121 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2122 // CHECK7: arraydestroy.done1: 2123 // CHECK7-NEXT: ret void 2124 // 2125 // 2126 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2127 // CHECK7-SAME: () #[[ATTR0]] { 2128 // CHECK7-NEXT: entry: 2129 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2130 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2131 // CHECK7-NEXT: ret void 2132 // 2133 // 2134 // CHECK7-LABEL: define {{[^@]+}}@main 2135 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 2136 // CHECK7-NEXT: entry: 2137 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2138 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 2139 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2140 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2141 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2142 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2143 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 2144 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2145 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2146 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2147 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 2148 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2149 // CHECK7: omp.inner.for.cond: 2150 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2151 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 2152 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2153 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2154 // CHECK7: omp.inner.for.body: 2155 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2156 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 2157 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2158 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 2159 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !3 2160 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 2161 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP5]] 2162 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3 2163 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 2164 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP6]] 2165 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 2166 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false), !llvm.access.group !3 2167 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 2168 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3 2169 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 2170 // CHECK7-NEXT: store i32 [[ADD2]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3 2171 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2172 // CHECK7: omp.body.continue: 2173 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2174 // CHECK7: omp.inner.for.inc: 2175 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2176 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 2177 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 2178 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 2179 // CHECK7: omp.inner.for.end: 2180 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 2181 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 2182 // CHECK7-NEXT: ret i32 [[CALL]] 2183 // 2184 // 2185 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2186 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 2187 // CHECK7-NEXT: entry: 2188 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2189 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2190 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2191 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2192 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2193 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2194 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2195 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2196 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2197 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2198 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2199 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 2200 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) 2201 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 2202 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2203 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2204 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2205 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 2206 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2207 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2208 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2209 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2210 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 2211 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2212 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2213 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2214 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2215 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2216 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2217 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2218 // CHECK7: omp.inner.for.cond: 2219 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 2220 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 2221 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2222 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2223 // CHECK7: omp.inner.for.body: 2224 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 2225 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2226 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2227 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 2228 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7 2229 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 2230 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 2231 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7 2232 // CHECK7-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4, !llvm.access.group !7 2233 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 2234 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 2235 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* 2236 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 2237 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7 2238 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2239 // CHECK7: omp.body.continue: 2240 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2241 // CHECK7: omp.inner.for.inc: 2242 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 2243 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 2244 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 2245 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2246 // CHECK7: omp.inner.for.end: 2247 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 2248 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 2249 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2250 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2251 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2252 // CHECK7: arraydestroy.body: 2253 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2254 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2255 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2256 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2257 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 2258 // CHECK7: arraydestroy.done4: 2259 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 2260 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 2261 // CHECK7-NEXT: ret i32 [[TMP16]] 2262 // 2263 // 2264 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2265 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2266 // CHECK7-NEXT: entry: 2267 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2268 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2269 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2270 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2271 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2272 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2273 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 2274 // CHECK7-NEXT: ret void 2275 // 2276 // 2277 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2278 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2279 // CHECK7-NEXT: entry: 2280 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2281 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2282 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2283 // CHECK7-NEXT: ret void 2284 // 2285 // 2286 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2287 // CHECK7-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2288 // CHECK7-NEXT: entry: 2289 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2290 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2291 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2292 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2293 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2294 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2295 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2296 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2297 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2298 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2299 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 2300 // CHECK7-NEXT: ret void 2301 // 2302 // 2303 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2304 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2305 // CHECK7-NEXT: entry: 2306 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2307 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2308 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2309 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2310 // CHECK7-NEXT: ret void 2311 // 2312 // 2313 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2314 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2315 // CHECK7-NEXT: entry: 2316 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2317 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2318 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2319 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2320 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2321 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2322 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 2323 // CHECK7-NEXT: ret void 2324 // 2325 // 2326 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2327 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2328 // CHECK7-NEXT: entry: 2329 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2330 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2331 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2332 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2333 // CHECK7-NEXT: ret void 2334 // 2335 // 2336 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2337 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2338 // CHECK7-NEXT: entry: 2339 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2340 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2341 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2342 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2343 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2344 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2345 // CHECK7-NEXT: ret void 2346 // 2347 // 2348 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2349 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2350 // CHECK7-NEXT: entry: 2351 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2352 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2353 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2354 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2355 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2356 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2357 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2358 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2359 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2360 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2361 // CHECK7-NEXT: ret void 2362 // 2363 // 2364 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2365 // CHECK7-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2366 // CHECK7-NEXT: entry: 2367 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2368 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2369 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2370 // CHECK7-NEXT: ret void 2371 // 2372 // 2373 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 2374 // CHECK7-SAME: () #[[ATTR0]] { 2375 // CHECK7-NEXT: entry: 2376 // CHECK7-NEXT: call void @__cxx_global_var_init() 2377 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 2378 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 2379 // CHECK7-NEXT: ret void 2380 // 2381 // 2382 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 2383 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2384 // CHECK9-NEXT: entry: 2385 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 2386 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2387 // CHECK9-NEXT: ret void 2388 // 2389 // 2390 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2391 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2392 // CHECK9-NEXT: entry: 2393 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2394 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2395 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2396 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2397 // CHECK9-NEXT: ret void 2398 // 2399 // 2400 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2401 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2402 // CHECK9-NEXT: entry: 2403 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2404 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2405 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2406 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2407 // CHECK9-NEXT: ret void 2408 // 2409 // 2410 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2411 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2412 // CHECK9-NEXT: entry: 2413 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2414 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2415 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2416 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2417 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2418 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2419 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 2420 // CHECK9-NEXT: ret void 2421 // 2422 // 2423 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2424 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2425 // CHECK9-NEXT: entry: 2426 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2427 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2428 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2429 // CHECK9-NEXT: ret void 2430 // 2431 // 2432 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2433 // CHECK9-SAME: () #[[ATTR0]] { 2434 // CHECK9-NEXT: entry: 2435 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 2436 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 2437 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2438 // CHECK9-NEXT: ret void 2439 // 2440 // 2441 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2442 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2443 // CHECK9-NEXT: entry: 2444 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2445 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2446 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2447 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2448 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2449 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2450 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2451 // CHECK9-NEXT: ret void 2452 // 2453 // 2454 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2455 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2456 // CHECK9-NEXT: entry: 2457 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2458 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2459 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2460 // CHECK9: arraydestroy.body: 2461 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2462 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2463 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2464 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2465 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2466 // CHECK9: arraydestroy.done1: 2467 // CHECK9-NEXT: ret void 2468 // 2469 // 2470 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2471 // CHECK9-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2472 // CHECK9-NEXT: entry: 2473 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2474 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2475 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2476 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2477 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2478 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2479 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2480 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2481 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2482 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2483 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 2484 // CHECK9-NEXT: ret void 2485 // 2486 // 2487 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2488 // CHECK9-SAME: () #[[ATTR0]] { 2489 // CHECK9-NEXT: entry: 2490 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2491 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2492 // CHECK9-NEXT: ret void 2493 // 2494 // 2495 // CHECK9-LABEL: define {{[^@]+}}@main 2496 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2497 // CHECK9-NEXT: entry: 2498 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2499 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2500 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 2501 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2502 // CHECK9-NEXT: ret i32 0 2503 // 2504 // 2505 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 2506 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 2507 // CHECK9-NEXT: entry: 2508 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2509 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2510 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2511 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2512 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 2513 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 2514 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2515 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 2516 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 2517 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 2518 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 2519 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 2520 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 2521 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 2522 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2523 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 2524 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 2525 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 2526 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 2527 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 2528 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 2529 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 2530 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 2531 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4 2532 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 2533 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 2534 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 2535 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 2536 // CHECK9-NEXT: ret void 2537 // 2538 // 2539 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2540 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR6:[0-9]+]] { 2541 // CHECK9-NEXT: entry: 2542 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2543 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2544 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 2545 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2546 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2547 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2548 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2549 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2550 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2551 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2552 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2553 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2554 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2555 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2556 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2557 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2558 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 2559 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 2560 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 2561 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 2562 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 2563 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 2564 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 2565 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2566 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2567 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2568 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2569 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2570 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2571 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2572 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2573 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2574 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2575 // CHECK9: cond.true: 2576 // CHECK9-NEXT: br label [[COND_END:%.*]] 2577 // CHECK9: cond.false: 2578 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2579 // CHECK9-NEXT: br label [[COND_END]] 2580 // CHECK9: cond.end: 2581 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2582 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2583 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2584 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2585 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2586 // CHECK9: omp.inner.for.cond: 2587 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2588 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 2589 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2590 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2591 // CHECK9: omp.inner.for.body: 2592 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2593 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2594 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2595 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 2596 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4 2597 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 2598 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 2599 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4 2600 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 2601 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 2602 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 2603 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 2604 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 2605 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 2606 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 2607 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group !4 2608 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2609 // CHECK9: omp.body.continue: 2610 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2611 // CHECK9: omp.inner.for.inc: 2612 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2613 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 2614 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 2615 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2616 // CHECK9: omp.inner.for.end: 2617 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2618 // CHECK9: omp.loop.exit: 2619 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2620 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2621 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2622 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2623 // CHECK9: .omp.final.then: 2624 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 2625 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 2626 // CHECK9: .omp.final.done: 2627 // CHECK9-NEXT: ret void 2628 // 2629 // 2630 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 2631 // CHECK9-SAME: () #[[ATTR0]] { 2632 // CHECK9-NEXT: entry: 2633 // CHECK9-NEXT: call void @__cxx_global_var_init() 2634 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2635 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2636 // CHECK9-NEXT: ret void 2637 // 2638 // 2639 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2640 // CHECK9-SAME: () #[[ATTR0]] { 2641 // CHECK9-NEXT: entry: 2642 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 2643 // CHECK9-NEXT: ret void 2644 // 2645 // 2646 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 2647 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2648 // CHECK11-NEXT: entry: 2649 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) @test) 2650 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2651 // CHECK11-NEXT: ret void 2652 // 2653 // 2654 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2655 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2656 // CHECK11-NEXT: entry: 2657 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2658 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2659 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2660 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2661 // CHECK11-NEXT: ret void 2662 // 2663 // 2664 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2665 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2666 // CHECK11-NEXT: entry: 2667 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2668 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2669 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2670 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2671 // CHECK11-NEXT: ret void 2672 // 2673 // 2674 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2675 // CHECK11-SAME: () #[[ATTR0]] { 2676 // CHECK11-NEXT: entry: 2677 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 2678 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 2679 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2680 // CHECK11-NEXT: ret void 2681 // 2682 // 2683 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2684 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2685 // CHECK11-NEXT: entry: 2686 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2687 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2688 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2689 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2690 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2691 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2692 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2693 // CHECK11-NEXT: ret void 2694 // 2695 // 2696 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2697 // CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2698 // CHECK11-NEXT: entry: 2699 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2700 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2701 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2702 // CHECK11: arraydestroy.body: 2703 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2704 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2705 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2706 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2707 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2708 // CHECK11: arraydestroy.done1: 2709 // CHECK11-NEXT: ret void 2710 // 2711 // 2712 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2713 // CHECK11-SAME: () #[[ATTR0]] { 2714 // CHECK11-NEXT: entry: 2715 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2716 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2717 // CHECK11-NEXT: ret void 2718 // 2719 // 2720 // CHECK11-LABEL: define {{[^@]+}}@main 2721 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2722 // CHECK11-NEXT: entry: 2723 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2724 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2725 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 2726 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2727 // CHECK11-NEXT: ret i32 0 2728 // 2729 // 2730 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2731 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2732 // CHECK11-NEXT: entry: 2733 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2734 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2735 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2736 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2737 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2738 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2739 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 2740 // CHECK11-NEXT: ret void 2741 // 2742 // 2743 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2744 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2745 // CHECK11-NEXT: entry: 2746 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2747 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2748 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2749 // CHECK11-NEXT: ret void 2750 // 2751 // 2752 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2753 // CHECK11-SAME: (%struct.S* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2754 // CHECK11-NEXT: entry: 2755 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2756 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2757 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2758 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2759 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2760 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2761 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2762 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2763 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2764 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2765 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 2766 // CHECK11-NEXT: ret void 2767 // 2768 // 2769 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 2770 // CHECK11-SAME: () #[[ATTR0]] { 2771 // CHECK11-NEXT: entry: 2772 // CHECK11-NEXT: call void @__cxx_global_var_init() 2773 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 2774 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 2775 // CHECK11-NEXT: ret void 2776 // 2777