1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target teams distribute simd firstprivate(t_var, vec, s_arr, var) 57 for (int i = 0; i < 2; ++i) { 58 vec[i] = t_var; 59 s_arr[i] = var; 60 } 61 return T(); 62 } 63 64 S<float> test; 65 int t_var = 333; 66 int vec[] = {1, 2}; 67 S<float> s_arr[] = {1, 2}; 68 S<float> var(3); 69 70 int main() { 71 static int sivar; 72 #ifdef LAMBDA 73 [&]() { 74 #pragma omp target teams distribute simd firstprivate(g, g1, sivar) 75 for (int i = 0; i < 2; ++i) { 76 77 // Skip global and bound tid vars 78 // skip loop vars 79 g = 1; 80 g1 = 1; 81 sivar = 2; 82 [&]() { 83 g = 2; 84 g1 = 2; 85 sivar = 4; 86 87 }(); 88 } 89 }(); 90 return 0; 91 #else 92 #pragma omp target teams distribute simd firstprivate(t_var, vec, s_arr, var, sivar) 93 for (int i = 0; i < 2; ++i) { 94 vec[i] = t_var; 95 s_arr[i] = var; 96 sivar += i; 97 } 98 return tmain<int>(); 99 #endif 100 } 101 102 103 104 105 106 // Skip global and bound tid vars 107 // Skip temp vars for loop 108 109 // param copy 110 111 // T_VAR and SIVAR 112 113 // preparation vars 114 115 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 116 117 // firstprivate(s_arr) 118 119 // firstprivate(var) 120 121 122 123 124 125 126 // Skip global and bound tid vars 127 // Skip temp vars for loop 128 129 // param copy 130 131 132 // T_VAR and preparation variables 133 134 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2 135 136 // firstprivate(s_arr) 137 138 // firstprivate(var) 139 140 141 #endif 142 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 143 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 144 // CHECK1-NEXT: entry: 145 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 146 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 147 // CHECK1-NEXT: ret void 148 // 149 // 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 151 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 154 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 155 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 156 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 157 // CHECK1-NEXT: ret void 158 // 159 // 160 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 161 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 164 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 165 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 166 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 167 // CHECK1-NEXT: ret void 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 171 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 174 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 175 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 176 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 177 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 178 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 179 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 180 // CHECK1-NEXT: ret void 181 // 182 // 183 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 184 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 185 // CHECK1-NEXT: entry: 186 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 187 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 188 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: ret void 190 // 191 // 192 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 193 // CHECK1-SAME: () #[[ATTR0]] { 194 // CHECK1-NEXT: entry: 195 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 196 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 197 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 198 // CHECK1-NEXT: ret void 199 // 200 // 201 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 202 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 203 // CHECK1-NEXT: entry: 204 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 205 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 206 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 207 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 208 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 209 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 210 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 211 // CHECK1-NEXT: ret void 212 // 213 // 214 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 215 // CHECK1-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 216 // CHECK1-NEXT: entry: 217 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 218 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 219 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 220 // CHECK1: arraydestroy.body: 221 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 222 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 223 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 224 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 225 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 226 // CHECK1: arraydestroy.done1: 227 // CHECK1-NEXT: ret void 228 // 229 // 230 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 231 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 232 // CHECK1-NEXT: entry: 233 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 234 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 235 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 236 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 237 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 238 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 239 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 240 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 241 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 242 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 243 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 244 // CHECK1-NEXT: ret void 245 // 246 // 247 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 248 // CHECK1-SAME: () #[[ATTR0]] { 249 // CHECK1-NEXT: entry: 250 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 251 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 252 // CHECK1-NEXT: ret void 253 // 254 // 255 // CHECK1-LABEL: define {{[^@]+}}@main 256 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 257 // CHECK1-NEXT: entry: 258 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 259 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 260 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 261 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 262 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 263 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 264 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 265 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 266 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 267 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 268 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 269 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 270 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 271 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 272 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 273 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 274 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 275 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 276 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 8 277 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 278 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 279 // CHECK1-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 8 280 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 281 // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 282 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 283 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 284 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 285 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 286 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 287 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 288 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 289 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 290 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 291 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 292 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 293 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 294 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 295 // CHECK1-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 296 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 297 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 298 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 299 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 300 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 301 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 302 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 303 // CHECK1-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 304 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 305 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 306 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 307 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 308 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 309 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 310 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 311 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 312 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 313 // CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8 314 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 315 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 316 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 317 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 318 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 319 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 320 // CHECK1: omp_offload.failed: 321 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 322 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 323 // CHECK1: omp_offload.cont: 324 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 325 // CHECK1-NEXT: ret i32 [[CALL]] 326 // 327 // 328 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 329 // CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 330 // CHECK1-NEXT: entry: 331 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 332 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 334 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 335 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 336 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 337 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 338 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 339 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 340 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 341 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 342 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 343 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 344 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 345 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 346 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 347 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 348 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 349 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 350 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 351 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 352 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 353 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 354 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 355 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 356 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 357 // CHECK1-NEXT: ret void 358 // 359 // 360 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 361 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 362 // CHECK1-NEXT: entry: 363 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 364 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 365 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 366 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 367 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 368 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 369 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 370 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 371 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 372 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 373 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 374 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 375 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 376 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 377 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 378 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 379 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 380 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 381 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 383 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 384 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 385 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 386 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 387 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 388 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 389 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 390 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 391 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 392 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 393 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 394 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 395 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 396 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 398 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 399 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 400 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 401 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 402 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 403 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 404 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 405 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 406 // CHECK1: omp.arraycpy.body: 407 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 408 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 409 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) 410 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 411 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] 412 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 413 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 414 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 415 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 416 // CHECK1: omp.arraycpy.done4: 417 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) 418 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) 419 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] 420 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 421 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 422 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 423 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 424 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 425 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 426 // CHECK1: cond.true: 427 // CHECK1-NEXT: br label [[COND_END:%.*]] 428 // CHECK1: cond.false: 429 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 430 // CHECK1-NEXT: br label [[COND_END]] 431 // CHECK1: cond.end: 432 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 433 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 434 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 435 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 436 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 437 // CHECK1: omp.inner.for.cond: 438 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 439 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 440 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 441 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 442 // CHECK1: omp.inner.for.cond.cleanup: 443 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 444 // CHECK1: omp.inner.for.body: 445 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 446 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 447 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 448 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 449 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5 450 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 451 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 452 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 453 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 454 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 455 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 456 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 457 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* 458 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 459 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 460 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 461 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5 462 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 463 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5 464 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 465 // CHECK1: omp.body.continue: 466 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 467 // CHECK1: omp.inner.for.inc: 468 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 469 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 470 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 471 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 472 // CHECK1: omp.inner.for.end: 473 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 474 // CHECK1: omp.loop.exit: 475 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 476 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 477 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 478 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 479 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 480 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 481 // CHECK1: .omp.final.then: 482 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 483 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 484 // CHECK1: .omp.final.done: 485 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] 486 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 487 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 488 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 489 // CHECK1: arraydestroy.body: 490 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 491 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 492 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 493 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 494 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 495 // CHECK1: arraydestroy.done13: 496 // CHECK1-NEXT: ret void 497 // 498 // 499 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 500 // CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 501 // CHECK1-NEXT: entry: 502 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 503 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 504 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 505 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) 506 // CHECK1-NEXT: ret void 507 // 508 // 509 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 510 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 511 // CHECK1-NEXT: entry: 512 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 513 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 514 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 515 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 516 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 517 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 518 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 519 // CHECK1-NEXT: ret void 520 // 521 // 522 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 523 // CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 524 // CHECK1-NEXT: entry: 525 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 526 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 527 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 528 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] 529 // CHECK1-NEXT: ret void 530 // 531 // 532 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 533 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat { 534 // CHECK1-NEXT: entry: 535 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 536 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 537 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 538 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 539 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 540 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 541 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 542 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 543 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 544 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 545 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 546 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 547 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 548 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 549 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 550 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 551 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 552 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 553 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 554 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 555 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 556 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 557 // CHECK1-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 558 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 559 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 560 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 561 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 562 // CHECK1-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 563 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 564 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 565 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8 566 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 567 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 568 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 569 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 570 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 571 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 572 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 573 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 574 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 575 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 576 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 577 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 578 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 579 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 580 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 581 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8 582 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 583 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 584 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 585 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 586 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 587 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 588 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 589 // CHECK1-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8 590 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 591 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 592 // CHECK1-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8 593 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 594 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 595 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 596 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 597 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 598 // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 599 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 600 // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 601 // CHECK1: omp_offload.failed: 602 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 603 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 604 // CHECK1: omp_offload.cont: 605 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 606 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 607 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 608 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 609 // CHECK1: arraydestroy.body: 610 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 611 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 612 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 613 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 614 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 615 // CHECK1: arraydestroy.done2: 616 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 617 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 618 // CHECK1-NEXT: ret i32 [[TMP30]] 619 // 620 // 621 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 622 // CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 623 // CHECK1-NEXT: entry: 624 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 625 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 626 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 627 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 628 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 629 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 630 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4 631 // CHECK1-NEXT: ret void 632 // 633 // 634 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 635 // CHECK1-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 636 // CHECK1-NEXT: entry: 637 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 638 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 639 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 640 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 641 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 642 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 643 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 644 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 645 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 646 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 647 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 648 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 649 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 650 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 651 // CHECK1-NEXT: ret void 652 // 653 // 654 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 655 // CHECK1-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 656 // CHECK1-NEXT: entry: 657 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 658 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 659 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 660 // CHECK1-NEXT: ret void 661 // 662 // 663 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 664 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 665 // CHECK1-NEXT: entry: 666 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 667 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 668 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 669 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 670 // CHECK1-NEXT: ret void 671 // 672 // 673 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 674 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 675 // CHECK1-NEXT: entry: 676 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 677 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 678 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 679 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 680 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 681 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 682 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) 683 // CHECK1-NEXT: ret void 684 // 685 // 686 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 687 // CHECK1-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 688 // CHECK1-NEXT: entry: 689 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 690 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 691 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 692 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 693 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 694 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 695 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 696 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 697 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 698 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 699 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 700 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 701 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 702 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 703 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 704 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 705 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 706 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 707 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 708 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 709 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 710 // CHECK1-NEXT: ret void 711 // 712 // 713 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 714 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { 715 // CHECK1-NEXT: entry: 716 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 717 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 718 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 719 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 720 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 721 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 722 // CHECK1-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 723 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 724 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 725 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 726 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 727 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 728 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 729 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 730 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 731 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 732 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 733 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 734 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 735 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 736 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 737 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 738 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 739 // CHECK1-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 740 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 741 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 742 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 743 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 744 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 745 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 746 // CHECK1-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 747 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 748 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 749 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 750 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 751 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 752 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 753 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 754 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 755 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 756 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 757 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 758 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 759 // CHECK1: omp.arraycpy.body: 760 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 761 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 762 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) 763 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 764 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] 765 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 766 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 767 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 768 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 769 // CHECK1: omp.arraycpy.done4: 770 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 771 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) 772 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) 773 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] 774 // CHECK1-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 775 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 776 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 777 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 778 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 779 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 780 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 781 // CHECK1: cond.true: 782 // CHECK1-NEXT: br label [[COND_END:%.*]] 783 // CHECK1: cond.false: 784 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 785 // CHECK1-NEXT: br label [[COND_END]] 786 // CHECK1: cond.end: 787 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 788 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 789 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 790 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 791 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 792 // CHECK1: omp.inner.for.cond: 793 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 794 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 795 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 796 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 797 // CHECK1: omp.inner.for.cond.cleanup: 798 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 799 // CHECK1: omp.inner.for.body: 800 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 801 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 802 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 803 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 804 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11 805 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 806 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 807 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 808 // CHECK1-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 809 // CHECK1-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 810 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 811 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 812 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 813 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* 814 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 815 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !11 816 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 817 // CHECK1: omp.body.continue: 818 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 819 // CHECK1: omp.inner.for.inc: 820 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 821 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 822 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 823 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 824 // CHECK1: omp.inner.for.end: 825 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 826 // CHECK1: omp.loop.exit: 827 // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 828 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 829 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 830 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 831 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 832 // CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 833 // CHECK1: .omp.final.then: 834 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4 835 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 836 // CHECK1: .omp.final.done: 837 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] 838 // CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 839 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 840 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 841 // CHECK1: arraydestroy.body: 842 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 843 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 844 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 845 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 846 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 847 // CHECK1: arraydestroy.done13: 848 // CHECK1-NEXT: ret void 849 // 850 // 851 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 852 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 853 // CHECK1-NEXT: entry: 854 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 855 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 856 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 857 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 858 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 859 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 860 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 861 // CHECK1-NEXT: ret void 862 // 863 // 864 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 865 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 866 // CHECK1-NEXT: entry: 867 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 868 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 869 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 870 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 871 // CHECK1-NEXT: ret void 872 // 873 // 874 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 875 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 876 // CHECK1-NEXT: entry: 877 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 878 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 879 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 880 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 881 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 882 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 883 // CHECK1-NEXT: ret void 884 // 885 // 886 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 887 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 888 // CHECK1-NEXT: entry: 889 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 890 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 891 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 892 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 893 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 894 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 895 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 896 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 897 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 898 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 899 // CHECK1-NEXT: ret void 900 // 901 // 902 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 903 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 904 // CHECK1-NEXT: entry: 905 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 906 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 907 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 908 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 909 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 910 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 911 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 912 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 913 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 914 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 915 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 916 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 917 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 918 // CHECK1-NEXT: ret void 919 // 920 // 921 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 922 // CHECK1-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 923 // CHECK1-NEXT: entry: 924 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 925 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 926 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 927 // CHECK1-NEXT: ret void 928 // 929 // 930 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 931 // CHECK1-SAME: () #[[ATTR0]] { 932 // CHECK1-NEXT: entry: 933 // CHECK1-NEXT: call void @__cxx_global_var_init() 934 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 935 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 936 // CHECK1-NEXT: ret void 937 // 938 // 939 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 940 // CHECK1-SAME: () #[[ATTR0]] { 941 // CHECK1-NEXT: entry: 942 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 943 // CHECK1-NEXT: ret void 944 // 945 // 946 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 947 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 948 // CHECK2-NEXT: entry: 949 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 950 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 951 // CHECK2-NEXT: ret void 952 // 953 // 954 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 955 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 956 // CHECK2-NEXT: entry: 957 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 958 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 959 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 960 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 961 // CHECK2-NEXT: ret void 962 // 963 // 964 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 965 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 966 // CHECK2-NEXT: entry: 967 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 968 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 969 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 970 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 971 // CHECK2-NEXT: ret void 972 // 973 // 974 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 975 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 976 // CHECK2-NEXT: entry: 977 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 978 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 979 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 980 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 981 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 982 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 983 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 984 // CHECK2-NEXT: ret void 985 // 986 // 987 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 988 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 989 // CHECK2-NEXT: entry: 990 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 991 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 992 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 993 // CHECK2-NEXT: ret void 994 // 995 // 996 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 997 // CHECK2-SAME: () #[[ATTR0]] { 998 // CHECK2-NEXT: entry: 999 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 1000 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 1001 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1002 // CHECK2-NEXT: ret void 1003 // 1004 // 1005 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1006 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1007 // CHECK2-NEXT: entry: 1008 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1009 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1010 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1011 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1012 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1013 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1014 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 1015 // CHECK2-NEXT: ret void 1016 // 1017 // 1018 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1019 // CHECK2-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1020 // CHECK2-NEXT: entry: 1021 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1022 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1023 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1024 // CHECK2: arraydestroy.body: 1025 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1026 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1027 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1028 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1029 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1030 // CHECK2: arraydestroy.done1: 1031 // CHECK2-NEXT: ret void 1032 // 1033 // 1034 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1035 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1036 // CHECK2-NEXT: entry: 1037 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1038 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1039 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1040 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1041 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1042 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1043 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1044 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1045 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1046 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1047 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1048 // CHECK2-NEXT: ret void 1049 // 1050 // 1051 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1052 // CHECK2-SAME: () #[[ATTR0]] { 1053 // CHECK2-NEXT: entry: 1054 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 1055 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1056 // CHECK2-NEXT: ret void 1057 // 1058 // 1059 // CHECK2-LABEL: define {{[^@]+}}@main 1060 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 1061 // CHECK2-NEXT: entry: 1062 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1063 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1064 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1065 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1066 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1067 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1068 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1069 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1070 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1071 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1072 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1073 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1074 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1075 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1076 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV1]], align 4 1077 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1078 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1079 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 1080 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 8 1081 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1082 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 1083 // CHECK2-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 8 1084 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1085 // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8 1086 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1087 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1088 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1089 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1090 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 1091 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP12]], align 8 1092 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1093 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 1094 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1095 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 1096 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 8 1097 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1098 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 1099 // CHECK2-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 8 1100 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1101 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 1102 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1103 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 1104 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 8 1105 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1106 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 1107 // CHECK2-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 8 1108 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1109 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 1110 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1111 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1112 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP25]], align 8 1113 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1114 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1115 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP27]], align 8 1116 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1117 // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8 1118 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1119 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1120 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1121 // CHECK2-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1122 // CHECK2-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1123 // CHECK2-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1124 // CHECK2: omp_offload.failed: 1125 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i64 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i64 [[TMP3]]) #[[ATTR2]] 1126 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1127 // CHECK2: omp_offload.cont: 1128 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1129 // CHECK2-NEXT: ret i32 [[CALL]] 1130 // 1131 // 1132 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 1133 // CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1134 // CHECK2-NEXT: entry: 1135 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1136 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1137 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1138 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1139 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1140 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1141 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1142 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1143 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1144 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1145 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1146 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1147 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1148 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1149 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1150 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1151 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1152 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 1153 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1154 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 1155 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1156 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 4 1157 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1158 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 1159 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1160 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 1161 // CHECK2-NEXT: ret void 1162 // 1163 // 1164 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1165 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 1166 // CHECK2-NEXT: entry: 1167 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1168 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1169 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1170 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1171 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1172 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1173 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1174 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1175 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1176 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1177 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1178 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1179 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1180 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1181 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 1182 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1183 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1184 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1185 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1186 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1187 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1188 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1189 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1190 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1191 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1192 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1193 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1194 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1195 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1196 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1197 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1198 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1199 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1200 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1201 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1202 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1203 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1204 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1205 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1206 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1207 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1208 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1209 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1210 // CHECK2: omp.arraycpy.body: 1211 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1212 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1213 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) 1214 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 1215 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] 1216 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1217 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1218 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1219 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1220 // CHECK2: omp.arraycpy.done4: 1221 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) 1222 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR5]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP6]]) 1223 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] 1224 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1225 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1226 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1227 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1228 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 1229 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1230 // CHECK2: cond.true: 1231 // CHECK2-NEXT: br label [[COND_END:%.*]] 1232 // CHECK2: cond.false: 1233 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1234 // CHECK2-NEXT: br label [[COND_END]] 1235 // CHECK2: cond.end: 1236 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1237 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1238 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1239 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 1240 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1241 // CHECK2: omp.inner.for.cond: 1242 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 1243 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 1244 // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 1245 // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1246 // CHECK2: omp.inner.for.cond.cleanup: 1247 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1248 // CHECK2: omp.inner.for.body: 1249 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 1250 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 1251 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1252 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 1253 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !5 1254 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 1255 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 1256 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 1257 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !5 1258 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 1259 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP17]] to i64 1260 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 [[IDXPROM8]] 1261 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX9]] to i8* 1262 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 1263 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i64 4, i1 false), !llvm.access.group !5 1264 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 1265 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV1]], align 4, !llvm.access.group !5 1266 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 1267 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[CONV1]], align 4, !llvm.access.group !5 1268 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1269 // CHECK2: omp.body.continue: 1270 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1271 // CHECK2: omp.inner.for.inc: 1272 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 1273 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 1274 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 1275 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 1276 // CHECK2: omp.inner.for.end: 1277 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1278 // CHECK2: omp.loop.exit: 1279 // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1280 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1281 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1282 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1283 // CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1284 // CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1285 // CHECK2: .omp.final.then: 1286 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 1287 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 1288 // CHECK2: .omp.final.done: 1289 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR5]]) #[[ATTR2]] 1290 // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1291 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN12]], i64 2 1292 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1293 // CHECK2: arraydestroy.body: 1294 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1295 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1296 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1297 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 1298 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 1299 // CHECK2: arraydestroy.done13: 1300 // CHECK2-NEXT: ret void 1301 // 1302 // 1303 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1304 // CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1305 // CHECK2-NEXT: entry: 1306 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1307 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1308 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1309 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) 1310 // CHECK2-NEXT: ret void 1311 // 1312 // 1313 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1314 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1315 // CHECK2-NEXT: entry: 1316 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1317 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1318 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1319 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1320 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1321 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1322 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 1323 // CHECK2-NEXT: ret void 1324 // 1325 // 1326 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1327 // CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1328 // CHECK2-NEXT: entry: 1329 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1330 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1331 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1332 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] 1333 // CHECK2-NEXT: ret void 1334 // 1335 // 1336 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1337 // CHECK2-SAME: () #[[ATTR7:[0-9]+]] comdat { 1338 // CHECK2-NEXT: entry: 1339 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1340 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1341 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1342 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1343 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1344 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 1345 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1346 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1347 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1348 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1349 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1350 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1351 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 1352 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 1353 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1354 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1355 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1356 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 1357 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1358 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1359 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 1360 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 1361 // CHECK2-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 1362 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 1363 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1364 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 1365 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1366 // CHECK2-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1367 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1368 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 1369 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 8 1370 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1371 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 1372 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 8 1373 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1374 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8 1375 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1376 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1377 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1378 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1379 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1380 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1381 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1382 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8 1383 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1384 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 1385 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 8 1386 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1387 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 1388 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 1389 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1390 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 1391 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1392 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 1393 // CHECK2-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 8 1394 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1395 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 1396 // CHECK2-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 8 1397 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1398 // CHECK2-NEXT: store i8* null, i8** [[TMP24]], align 8 1399 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1400 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1401 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 1402 // CHECK2-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1403 // CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 1404 // CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1405 // CHECK2: omp_offload.failed: 1406 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i64 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 1407 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1408 // CHECK2: omp_offload.cont: 1409 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1410 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1411 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1412 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1413 // CHECK2: arraydestroy.body: 1414 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1415 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1416 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1417 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1418 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1419 // CHECK2: arraydestroy.done2: 1420 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 1421 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 1422 // CHECK2-NEXT: ret i32 [[TMP30]] 1423 // 1424 // 1425 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1426 // CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1427 // CHECK2-NEXT: entry: 1428 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1429 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1430 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1431 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1432 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1433 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1434 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4 1435 // CHECK2-NEXT: ret void 1436 // 1437 // 1438 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1439 // CHECK2-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1440 // CHECK2-NEXT: entry: 1441 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1442 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1443 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1444 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1445 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1446 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1447 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1448 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1449 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1450 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1451 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1452 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1453 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1454 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1455 // CHECK2-NEXT: ret void 1456 // 1457 // 1458 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1459 // CHECK2-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1460 // CHECK2-NEXT: entry: 1461 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1462 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1463 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1464 // CHECK2-NEXT: ret void 1465 // 1466 // 1467 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1468 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1469 // CHECK2-NEXT: entry: 1470 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1471 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1472 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1473 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 1474 // CHECK2-NEXT: ret void 1475 // 1476 // 1477 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1478 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1479 // CHECK2-NEXT: entry: 1480 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1481 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1482 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1483 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1484 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1485 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1486 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) 1487 // CHECK2-NEXT: ret void 1488 // 1489 // 1490 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1491 // CHECK2-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1492 // CHECK2-NEXT: entry: 1493 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1494 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1495 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1496 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1497 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1498 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1499 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1500 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1501 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1502 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1503 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1504 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1505 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1506 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1507 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 1508 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 1509 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1510 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 1511 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1512 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1513 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 1514 // CHECK2-NEXT: ret void 1515 // 1516 // 1517 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1518 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { 1519 // CHECK2-NEXT: entry: 1520 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1521 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1522 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1523 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1524 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1525 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1526 // CHECK2-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 1527 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1528 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1529 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1530 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1531 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1532 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1533 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1534 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1535 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1536 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1537 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1538 // CHECK2-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 8 1539 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1540 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1541 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1542 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1543 // CHECK2-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1544 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1545 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1546 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1547 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1548 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1549 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1550 // CHECK2-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 1551 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1552 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1553 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1554 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1555 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1556 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1557 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1558 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1559 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 1560 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1561 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 1562 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1563 // CHECK2: omp.arraycpy.body: 1564 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1565 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1566 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) 1567 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 1568 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] 1569 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1570 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1571 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1572 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1573 // CHECK2: omp.arraycpy.done4: 1574 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 1575 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) 1576 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) 1577 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] 1578 // CHECK2-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 8 1579 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1580 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 1581 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1582 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1583 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 1584 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1585 // CHECK2: cond.true: 1586 // CHECK2-NEXT: br label [[COND_END:%.*]] 1587 // CHECK2: cond.false: 1588 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1589 // CHECK2-NEXT: br label [[COND_END]] 1590 // CHECK2: cond.end: 1591 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1592 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1593 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1594 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1595 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1596 // CHECK2: omp.inner.for.cond: 1597 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1598 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 1599 // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1600 // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1601 // CHECK2: omp.inner.for.cond.cleanup: 1602 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1603 // CHECK2: omp.inner.for.body: 1604 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1605 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 1606 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1607 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 1608 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !11 1609 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1610 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 1611 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 [[IDXPROM]] 1612 // CHECK2-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !11 1613 // CHECK2-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 8, !llvm.access.group !11 1614 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1615 // CHECK2-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 1616 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 [[IDXPROM9]] 1617 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* 1618 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 1619 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i64 4, i1 false), !llvm.access.group !11 1620 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1621 // CHECK2: omp.body.continue: 1622 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1623 // CHECK2: omp.inner.for.inc: 1624 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1625 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], 1 1626 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1627 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1628 // CHECK2: omp.inner.for.end: 1629 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1630 // CHECK2: omp.loop.exit: 1631 // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1632 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 1633 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 1634 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1635 // CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1636 // CHECK2-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1637 // CHECK2: .omp.final.then: 1638 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4 1639 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 1640 // CHECK2: .omp.final.done: 1641 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] 1642 // CHECK2-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1643 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2 1644 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1645 // CHECK2: arraydestroy.body: 1646 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1647 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1648 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1649 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] 1650 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] 1651 // CHECK2: arraydestroy.done13: 1652 // CHECK2-NEXT: ret void 1653 // 1654 // 1655 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1656 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1657 // CHECK2-NEXT: entry: 1658 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1659 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1660 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1661 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1662 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1663 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1664 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 1665 // CHECK2-NEXT: ret void 1666 // 1667 // 1668 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1669 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1670 // CHECK2-NEXT: entry: 1671 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1672 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1673 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1674 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 1675 // CHECK2-NEXT: ret void 1676 // 1677 // 1678 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1679 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1680 // CHECK2-NEXT: entry: 1681 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1682 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1683 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1684 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1685 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1686 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1687 // CHECK2-NEXT: ret void 1688 // 1689 // 1690 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1691 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1692 // CHECK2-NEXT: entry: 1693 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1694 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1695 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1696 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1697 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1698 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1699 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1700 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1701 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1702 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1703 // CHECK2-NEXT: ret void 1704 // 1705 // 1706 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1707 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1708 // CHECK2-NEXT: entry: 1709 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1710 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1711 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1712 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1713 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1714 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1715 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1716 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1717 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1718 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1719 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1720 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1721 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1722 // CHECK2-NEXT: ret void 1723 // 1724 // 1725 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1726 // CHECK2-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1727 // CHECK2-NEXT: entry: 1728 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1729 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1730 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1731 // CHECK2-NEXT: ret void 1732 // 1733 // 1734 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 1735 // CHECK2-SAME: () #[[ATTR0]] { 1736 // CHECK2-NEXT: entry: 1737 // CHECK2-NEXT: call void @__cxx_global_var_init() 1738 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 1739 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 1740 // CHECK2-NEXT: ret void 1741 // 1742 // 1743 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1744 // CHECK2-SAME: () #[[ATTR0]] { 1745 // CHECK2-NEXT: entry: 1746 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1747 // CHECK2-NEXT: ret void 1748 // 1749 // 1750 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1751 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1752 // CHECK3-NEXT: entry: 1753 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 1754 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1755 // CHECK3-NEXT: ret void 1756 // 1757 // 1758 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1759 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1760 // CHECK3-NEXT: entry: 1761 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1762 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1763 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1764 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 1765 // CHECK3-NEXT: ret void 1766 // 1767 // 1768 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1769 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1770 // CHECK3-NEXT: entry: 1771 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1772 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1773 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1774 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 1775 // CHECK3-NEXT: ret void 1776 // 1777 // 1778 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1779 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1780 // CHECK3-NEXT: entry: 1781 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1782 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1783 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1784 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1785 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1786 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1787 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 1788 // CHECK3-NEXT: ret void 1789 // 1790 // 1791 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1792 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1793 // CHECK3-NEXT: entry: 1794 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1795 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1796 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1797 // CHECK3-NEXT: ret void 1798 // 1799 // 1800 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1801 // CHECK3-SAME: () #[[ATTR0]] { 1802 // CHECK3-NEXT: entry: 1803 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 1804 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 1805 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1806 // CHECK3-NEXT: ret void 1807 // 1808 // 1809 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1810 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1811 // CHECK3-NEXT: entry: 1812 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1813 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1814 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1815 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1816 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1817 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1818 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 1819 // CHECK3-NEXT: ret void 1820 // 1821 // 1822 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1823 // CHECK3-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 1824 // CHECK3-NEXT: entry: 1825 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 1826 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 1827 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1828 // CHECK3: arraydestroy.body: 1829 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1830 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1831 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1832 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1833 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1834 // CHECK3: arraydestroy.done1: 1835 // CHECK3-NEXT: ret void 1836 // 1837 // 1838 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1839 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1840 // CHECK3-NEXT: entry: 1841 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1842 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1843 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1844 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1845 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1846 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1847 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1848 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1849 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1850 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1851 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1852 // CHECK3-NEXT: ret void 1853 // 1854 // 1855 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1856 // CHECK3-SAME: () #[[ATTR0]] { 1857 // CHECK3-NEXT: entry: 1858 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 1859 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1860 // CHECK3-NEXT: ret void 1861 // 1862 // 1863 // CHECK3-LABEL: define {{[^@]+}}@main 1864 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1865 // CHECK3-NEXT: entry: 1866 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1867 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1868 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1869 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1870 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1871 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1872 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1873 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1874 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1875 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 1876 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1877 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1878 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 1879 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1880 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1881 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 1882 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 4 1883 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1884 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 1885 // CHECK3-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 4 1886 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1887 // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 1888 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1889 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1890 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 1891 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1892 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1893 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 1894 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1895 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1896 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1897 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 1898 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 1899 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1900 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 1901 // CHECK3-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 1902 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1903 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1904 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1905 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 1906 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 1907 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1908 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 1909 // CHECK3-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 1910 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1911 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1912 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1913 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1914 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 1915 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1916 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 1917 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 1918 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1919 // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 4 1920 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1921 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1922 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 1923 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1924 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1925 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1926 // CHECK3: omp_offload.failed: 1927 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 1928 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1929 // CHECK3: omp_offload.cont: 1930 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1931 // CHECK3-NEXT: ret i32 [[CALL]] 1932 // 1933 // 1934 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 1935 // CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1936 // CHECK3-NEXT: entry: 1937 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1938 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1939 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1940 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1941 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1942 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1943 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1944 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1945 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1946 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1947 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1948 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1949 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1950 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1951 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1952 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1953 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 1954 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1955 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 1956 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 1957 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1958 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 1959 // CHECK3-NEXT: ret void 1960 // 1961 // 1962 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1963 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 1964 // CHECK3-NEXT: entry: 1965 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1966 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1967 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1968 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1969 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1970 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1971 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1972 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1973 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1974 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1975 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1976 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1977 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1978 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1979 // CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1980 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1981 // CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1982 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1983 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1984 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1985 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1986 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1987 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1988 // CHECK3-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1989 // CHECK3-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1990 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1991 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1992 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1993 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1994 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1995 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 1996 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1997 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1998 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 1999 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2000 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2001 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2002 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2003 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2004 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2005 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2006 // CHECK3: omp.arraycpy.body: 2007 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2008 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2009 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) 2010 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 2011 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] 2012 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2013 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2014 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2015 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2016 // CHECK3: omp.arraycpy.done3: 2017 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) 2018 // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) 2019 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] 2020 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2021 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 2022 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2023 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2024 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2025 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2026 // CHECK3: cond.true: 2027 // CHECK3-NEXT: br label [[COND_END:%.*]] 2028 // CHECK3: cond.false: 2029 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2030 // CHECK3-NEXT: br label [[COND_END]] 2031 // CHECK3: cond.end: 2032 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2033 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2034 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2035 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 2036 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2037 // CHECK3: omp.inner.for.cond: 2038 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2039 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 2040 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2041 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2042 // CHECK3: omp.inner.for.cond.cleanup: 2043 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2044 // CHECK3: omp.inner.for.body: 2045 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2046 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2047 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2048 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 2049 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 2050 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 2051 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] 2052 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 2053 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 2054 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] 2055 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 2056 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2057 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6 2058 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 2059 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 2060 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 2061 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 2062 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2063 // CHECK3: omp.body.continue: 2064 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2065 // CHECK3: omp.inner.for.inc: 2066 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2067 // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 2068 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2069 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2070 // CHECK3: omp.inner.for.end: 2071 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2072 // CHECK3: omp.loop.exit: 2073 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2074 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 2075 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 2076 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2077 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 2078 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2079 // CHECK3: .omp.final.then: 2080 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 2081 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2082 // CHECK3: .omp.final.done: 2083 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] 2084 // CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2085 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 2086 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2087 // CHECK3: arraydestroy.body: 2088 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2089 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2090 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2091 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2092 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2093 // CHECK3: arraydestroy.done11: 2094 // CHECK3-NEXT: ret void 2095 // 2096 // 2097 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2098 // CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2099 // CHECK3-NEXT: entry: 2100 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2101 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2102 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2103 // CHECK3-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) 2104 // CHECK3-NEXT: ret void 2105 // 2106 // 2107 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2108 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2109 // CHECK3-NEXT: entry: 2110 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2111 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2112 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2113 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2114 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2115 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2116 // CHECK3-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 2117 // CHECK3-NEXT: ret void 2118 // 2119 // 2120 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2121 // CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2122 // CHECK3-NEXT: entry: 2123 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2124 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2125 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2126 // CHECK3-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] 2127 // CHECK3-NEXT: ret void 2128 // 2129 // 2130 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2131 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat { 2132 // CHECK3-NEXT: entry: 2133 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2134 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2135 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2136 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2137 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2138 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2139 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2140 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2141 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2142 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2143 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2144 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2145 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 2146 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4 2147 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2148 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2149 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2150 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) 2151 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2152 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2153 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2154 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2155 // CHECK3-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 2156 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 2157 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 2158 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2159 // CHECK3-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2160 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2161 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 2162 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4 2163 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2164 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 2165 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 2166 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2167 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 2168 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2169 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 2170 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 2171 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2172 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2173 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2174 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2175 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 2176 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2177 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 2178 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4 2179 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2180 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 2181 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 2182 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2183 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 2184 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2185 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 2186 // CHECK3-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4 2187 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2188 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 2189 // CHECK3-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4 2190 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2191 // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4 2192 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2193 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2194 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 2195 // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2196 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2197 // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2198 // CHECK3: omp_offload.failed: 2199 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 2200 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2201 // CHECK3: omp_offload.cont: 2202 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 2203 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2204 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2205 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2206 // CHECK3: arraydestroy.body: 2207 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2208 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2209 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2210 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2211 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2212 // CHECK3: arraydestroy.done2: 2213 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 2214 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 2215 // CHECK3-NEXT: ret i32 [[TMP30]] 2216 // 2217 // 2218 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2219 // CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2220 // CHECK3-NEXT: entry: 2221 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2222 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2223 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2224 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 2225 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2226 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2227 // CHECK3-NEXT: store i32 0, i32* [[B]], align 4 2228 // CHECK3-NEXT: ret void 2229 // 2230 // 2231 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 2232 // CHECK3-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2233 // CHECK3-NEXT: entry: 2234 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2235 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2236 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2237 // CHECK3-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2238 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2239 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2240 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2241 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 2242 // CHECK3-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 2243 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2244 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2245 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 2246 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 2247 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 2248 // CHECK3-NEXT: ret void 2249 // 2250 // 2251 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev 2252 // CHECK3-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2253 // CHECK3-NEXT: entry: 2254 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2255 // CHECK3-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2256 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2257 // CHECK3-NEXT: ret void 2258 // 2259 // 2260 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2261 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2262 // CHECK3-NEXT: entry: 2263 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2264 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2265 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2266 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 2267 // CHECK3-NEXT: ret void 2268 // 2269 // 2270 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2271 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2272 // CHECK3-NEXT: entry: 2273 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2274 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2275 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2276 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2277 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2278 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2279 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) 2280 // CHECK3-NEXT: ret void 2281 // 2282 // 2283 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 2284 // CHECK3-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 2285 // CHECK3-NEXT: entry: 2286 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2287 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2288 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2289 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2290 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2291 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2292 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2293 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2294 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2295 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2296 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2297 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2298 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2299 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 2300 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2301 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2302 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2303 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2304 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 2305 // CHECK3-NEXT: ret void 2306 // 2307 // 2308 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2309 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { 2310 // CHECK3-NEXT: entry: 2311 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2312 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2313 // CHECK3-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2314 // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2315 // CHECK3-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2316 // CHECK3-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2317 // CHECK3-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2318 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2319 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2320 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2321 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2322 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2323 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2324 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2325 // CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 2326 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2327 // CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2328 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2329 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 2330 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2331 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2332 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2333 // CHECK3-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2334 // CHECK3-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2335 // CHECK3-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2336 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2337 // CHECK3-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2338 // CHECK3-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2339 // CHECK3-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2340 // CHECK3-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 2341 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2342 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2343 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2344 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2345 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 2346 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2347 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2348 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2349 // CHECK3-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 2350 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2351 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 2352 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2353 // CHECK3: omp.arraycpy.body: 2354 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2355 // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2356 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) 2357 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 2358 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] 2359 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2360 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2361 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2362 // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2363 // CHECK3: omp.arraycpy.done4: 2364 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2365 // CHECK3-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) 2366 // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) 2367 // CHECK3-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] 2368 // CHECK3-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 2369 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2370 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 2371 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2372 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2373 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 2374 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2375 // CHECK3: cond.true: 2376 // CHECK3-NEXT: br label [[COND_END:%.*]] 2377 // CHECK3: cond.false: 2378 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2379 // CHECK3-NEXT: br label [[COND_END]] 2380 // CHECK3: cond.end: 2381 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2382 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2383 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2384 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2385 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2386 // CHECK3: omp.inner.for.cond: 2387 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2388 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 2389 // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2390 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2391 // CHECK3: omp.inner.for.cond.cleanup: 2392 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2393 // CHECK3: omp.inner.for.body: 2394 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2395 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 2396 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2397 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 2398 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !12 2399 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2400 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] 2401 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 2402 // CHECK3-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12 2403 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2404 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] 2405 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 2406 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 2407 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !12 2408 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2409 // CHECK3: omp.body.continue: 2410 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2411 // CHECK3: omp.inner.for.inc: 2412 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2413 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 2414 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2415 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 2416 // CHECK3: omp.inner.for.end: 2417 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2418 // CHECK3: omp.loop.exit: 2419 // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2420 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 2421 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 2422 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2423 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 2424 // CHECK3-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2425 // CHECK3: .omp.final.then: 2426 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4 2427 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2428 // CHECK3: .omp.final.done: 2429 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] 2430 // CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2431 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 2432 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2433 // CHECK3: arraydestroy.body: 2434 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2435 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2436 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2437 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 2438 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 2439 // CHECK3: arraydestroy.done12: 2440 // CHECK3-NEXT: ret void 2441 // 2442 // 2443 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 2444 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2445 // CHECK3-NEXT: entry: 2446 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2447 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2448 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2449 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2450 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2451 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2452 // CHECK3-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 2453 // CHECK3-NEXT: ret void 2454 // 2455 // 2456 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2457 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2458 // CHECK3-NEXT: entry: 2459 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2460 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2461 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2462 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 2463 // CHECK3-NEXT: ret void 2464 // 2465 // 2466 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2467 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2468 // CHECK3-NEXT: entry: 2469 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2470 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2471 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2472 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2473 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2474 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2475 // CHECK3-NEXT: ret void 2476 // 2477 // 2478 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2479 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2480 // CHECK3-NEXT: entry: 2481 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2482 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2483 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2484 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2485 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2486 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2487 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2488 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2489 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2490 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2491 // CHECK3-NEXT: ret void 2492 // 2493 // 2494 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 2495 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2496 // CHECK3-NEXT: entry: 2497 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2498 // CHECK3-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2499 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2500 // CHECK3-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2501 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2502 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2503 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2504 // CHECK3-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 2505 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 2506 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2507 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2508 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 2509 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2510 // CHECK3-NEXT: ret void 2511 // 2512 // 2513 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2514 // CHECK3-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2515 // CHECK3-NEXT: entry: 2516 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2517 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2518 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2519 // CHECK3-NEXT: ret void 2520 // 2521 // 2522 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 2523 // CHECK3-SAME: () #[[ATTR0]] { 2524 // CHECK3-NEXT: entry: 2525 // CHECK3-NEXT: call void @__cxx_global_var_init() 2526 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 2527 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 2528 // CHECK3-NEXT: ret void 2529 // 2530 // 2531 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2532 // CHECK3-SAME: () #[[ATTR0]] { 2533 // CHECK3-NEXT: entry: 2534 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 2535 // CHECK3-NEXT: ret void 2536 // 2537 // 2538 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 2539 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 2540 // CHECK4-NEXT: entry: 2541 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 2542 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2543 // CHECK4-NEXT: ret void 2544 // 2545 // 2546 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2547 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2548 // CHECK4-NEXT: entry: 2549 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2550 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2551 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2552 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 2553 // CHECK4-NEXT: ret void 2554 // 2555 // 2556 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2557 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2558 // CHECK4-NEXT: entry: 2559 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2560 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2561 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2562 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 2563 // CHECK4-NEXT: ret void 2564 // 2565 // 2566 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2567 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2568 // CHECK4-NEXT: entry: 2569 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2570 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2571 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2572 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2573 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2574 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2575 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4 2576 // CHECK4-NEXT: ret void 2577 // 2578 // 2579 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2580 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2581 // CHECK4-NEXT: entry: 2582 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2583 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2584 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2585 // CHECK4-NEXT: ret void 2586 // 2587 // 2588 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2589 // CHECK4-SAME: () #[[ATTR0]] { 2590 // CHECK4-NEXT: entry: 2591 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 2592 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 2593 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2594 // CHECK4-NEXT: ret void 2595 // 2596 // 2597 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2598 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2599 // CHECK4-NEXT: entry: 2600 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2601 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2602 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2603 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2604 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2605 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2606 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 2607 // CHECK4-NEXT: ret void 2608 // 2609 // 2610 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2611 // CHECK4-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 2612 // CHECK4-NEXT: entry: 2613 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 2614 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 2615 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2616 // CHECK4: arraydestroy.body: 2617 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2618 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2619 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2620 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2621 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2622 // CHECK4: arraydestroy.done1: 2623 // CHECK4-NEXT: ret void 2624 // 2625 // 2626 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2627 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2628 // CHECK4-NEXT: entry: 2629 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2630 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2631 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2632 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2633 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2634 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2635 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2636 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2637 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2638 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2639 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 2640 // CHECK4-NEXT: ret void 2641 // 2642 // 2643 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2644 // CHECK4-SAME: () #[[ATTR0]] { 2645 // CHECK4-NEXT: entry: 2646 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 2647 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2648 // CHECK4-NEXT: ret void 2649 // 2650 // 2651 // CHECK4-LABEL: define {{[^@]+}}@main 2652 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 2653 // CHECK4-NEXT: entry: 2654 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2655 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2656 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2657 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2658 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2659 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2660 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2661 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 2662 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 2663 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 2664 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2665 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 2666 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 2667 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2668 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2669 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to [2 x i32]** 2670 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP5]], align 4 2671 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2672 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 2673 // CHECK4-NEXT: store [2 x i32]* @vec, [2 x i32]** [[TMP7]], align 4 2674 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2675 // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4 2676 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2677 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 2678 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 2679 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2680 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 2681 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 2682 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2683 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 2684 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2685 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x %struct.S]** 2686 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP15]], align 4 2687 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2688 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x %struct.S]** 2689 // CHECK4-NEXT: store [2 x %struct.S]* @s_arr, [2 x %struct.S]** [[TMP17]], align 4 2690 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2691 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 2692 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2693 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.S** 2694 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP20]], align 4 2695 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2696 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.S** 2697 // CHECK4-NEXT: store %struct.S* @var, %struct.S** [[TMP22]], align 4 2698 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2699 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 2700 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2701 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2702 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP25]], align 4 2703 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2704 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2705 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP27]], align 4 2706 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2707 // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4 2708 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2709 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2710 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) 2711 // CHECK4-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92.region_id, i32 5, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2712 // CHECK4-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2713 // CHECK4-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2714 // CHECK4: omp_offload.failed: 2715 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92([2 x i32]* @vec, i32 [[TMP1]], [2 x %struct.S]* @s_arr, %struct.S* @var, i32 [[TMP3]]) #[[ATTR2]] 2716 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2717 // CHECK4: omp_offload.cont: 2718 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 2719 // CHECK4-NEXT: ret i32 [[CALL]] 2720 // 2721 // 2722 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l92 2723 // CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 2724 // CHECK4-NEXT: entry: 2725 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2726 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2727 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2728 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2729 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2730 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2731 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2732 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2733 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2734 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2735 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2736 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2737 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2738 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2739 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2740 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2741 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2742 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2743 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2744 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 2745 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2746 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 2747 // CHECK4-NEXT: ret void 2748 // 2749 // 2750 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 2751 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 2752 // CHECK4-NEXT: entry: 2753 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2754 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2755 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2756 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2757 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2758 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2759 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2760 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2761 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 2762 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2763 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2764 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2765 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2766 // CHECK4-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2767 // CHECK4-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2768 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2769 // CHECK4-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2770 // CHECK4-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2771 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 2772 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2773 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2774 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2775 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2776 // CHECK4-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2777 // CHECK4-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2778 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2779 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2780 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2781 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2782 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2783 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 2784 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2785 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2786 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 2787 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2788 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2789 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2790 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2791 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2792 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2793 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2794 // CHECK4: omp.arraycpy.body: 2795 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2796 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2797 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) 2798 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 2799 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] 2800 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2801 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2802 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2803 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2804 // CHECK4: omp.arraycpy.done3: 2805 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP5]]) 2806 // CHECK4-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* noundef [[VAR4]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* noundef [[AGG_TMP5]]) 2807 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP5]]) #[[ATTR2]] 2808 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2809 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 2810 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP8]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2811 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2812 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1 2813 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2814 // CHECK4: cond.true: 2815 // CHECK4-NEXT: br label [[COND_END:%.*]] 2816 // CHECK4: cond.false: 2817 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2818 // CHECK4-NEXT: br label [[COND_END]] 2819 // CHECK4: cond.end: 2820 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2821 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2822 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2823 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 2824 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2825 // CHECK4: omp.inner.for.cond: 2826 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2827 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 2828 // CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] 2829 // CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2830 // CHECK4: omp.inner.for.cond.cleanup: 2831 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2832 // CHECK4: omp.inner.for.body: 2833 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2834 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 2835 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2836 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 2837 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !6 2838 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 2839 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 [[TMP16]] 2840 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 2841 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 2842 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 [[TMP17]] 2843 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 2844 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2845 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP18]], i8* align 4 [[TMP19]], i32 4, i1 false), !llvm.access.group !6 2846 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 2847 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 2848 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP21]], [[TMP20]] 2849 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[SIVAR_ADDR]], align 4, !llvm.access.group !6 2850 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2851 // CHECK4: omp.body.continue: 2852 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2853 // CHECK4: omp.inner.for.inc: 2854 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2855 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP22]], 1 2856 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2857 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2858 // CHECK4: omp.inner.for.end: 2859 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2860 // CHECK4: omp.loop.exit: 2861 // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2862 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 2863 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 2864 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2865 // CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 2866 // CHECK4-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2867 // CHECK4: .omp.final.then: 2868 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 2869 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 2870 // CHECK4: .omp.final.done: 2871 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[VAR4]]) #[[ATTR2]] 2872 // CHECK4-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2873 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN10]], i32 2 2874 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2875 // CHECK4: arraydestroy.body: 2876 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2877 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2878 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2879 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 2880 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 2881 // CHECK4: arraydestroy.done11: 2882 // CHECK4-NEXT: ret void 2883 // 2884 // 2885 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2886 // CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2887 // CHECK4-NEXT: entry: 2888 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2889 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2890 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2891 // CHECK4-NEXT: call void @_ZN2StC2Ev(%struct.St* noundef [[THIS1]]) 2892 // CHECK4-NEXT: ret void 2893 // 2894 // 2895 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2896 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2897 // CHECK4-NEXT: entry: 2898 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2899 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2900 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2901 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2902 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2903 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2904 // CHECK4-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* noundef [[THIS1]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 2905 // CHECK4-NEXT: ret void 2906 // 2907 // 2908 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2909 // CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2910 // CHECK4-NEXT: entry: 2911 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2912 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2913 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2914 // CHECK4-NEXT: call void @_ZN2StD2Ev(%struct.St* noundef [[THIS1]]) #[[ATTR2]] 2915 // CHECK4-NEXT: ret void 2916 // 2917 // 2918 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2919 // CHECK4-SAME: () #[[ATTR7:[0-9]+]] comdat { 2920 // CHECK4-NEXT: entry: 2921 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2922 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2923 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2924 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2925 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2926 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 2927 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 2928 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2929 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2930 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2931 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2932 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2933 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 2934 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4 2935 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2936 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2937 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2938 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) 2939 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2940 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) 2941 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 2942 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 2943 // CHECK4-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 2944 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 2945 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 2946 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2947 // CHECK4-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 2948 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2949 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to [2 x i32]** 2950 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP6]], align 4 2951 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2952 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [2 x i32]** 2953 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP8]], align 4 2954 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2955 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4 2956 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2957 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 2958 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 2959 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2960 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2961 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2962 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2963 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4 2964 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2965 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S.0]** 2966 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP16]], align 4 2967 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2968 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** 2969 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 2970 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2971 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 2972 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2973 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S.0** 2974 // CHECK4-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP21]], align 4 2975 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2976 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** 2977 // CHECK4-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[TMP23]], align 4 2978 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2979 // CHECK4-NEXT: store i8* null, i8** [[TMP24]], align 4 2980 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2981 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2982 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) 2983 // CHECK4-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 4, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2984 // CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2985 // CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2986 // CHECK4: omp_offload.failed: 2987 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56([2 x i32]* [[VEC]], i32 [[TMP3]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR2]] 2988 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 2989 // CHECK4: omp_offload.cont: 2990 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 2991 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2992 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2993 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2994 // CHECK4: arraydestroy.body: 2995 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2996 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2997 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2998 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2999 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 3000 // CHECK4: arraydestroy.done2: 3001 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 3002 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 3003 // CHECK4-NEXT: ret i32 [[TMP30]] 3004 // 3005 // 3006 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StC2Ev 3007 // CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3008 // CHECK4-NEXT: entry: 3009 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3010 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3011 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3012 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 3013 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 3014 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 3015 // CHECK4-NEXT: store i32 0, i32* [[B]], align 4 3016 // CHECK4-NEXT: ret void 3017 // 3018 // 3019 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 3020 // CHECK4-SAME: (%struct.S* noundef [[THIS:%.*]], %struct.S* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3021 // CHECK4-NEXT: entry: 3022 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3023 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 3024 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3025 // CHECK4-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 3026 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3027 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3028 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 3029 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 3030 // CHECK4-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 3031 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3032 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3033 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 3034 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 3035 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 3036 // CHECK4-NEXT: ret void 3037 // 3038 // 3039 // CHECK4-LABEL: define {{[^@]+}}@_ZN2StD2Ev 3040 // CHECK4-SAME: (%struct.St* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3041 // CHECK4-NEXT: entry: 3042 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3043 // CHECK4-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3044 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3045 // CHECK4-NEXT: ret void 3046 // 3047 // 3048 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3049 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3050 // CHECK4-NEXT: entry: 3051 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3052 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3053 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3054 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 3055 // CHECK4-NEXT: ret void 3056 // 3057 // 3058 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3059 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3060 // CHECK4-NEXT: entry: 3061 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3062 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3063 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3064 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3065 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3066 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3067 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) 3068 // CHECK4-NEXT: ret void 3069 // 3070 // 3071 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 3072 // CHECK4-SAME: ([2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 3073 // CHECK4-NEXT: entry: 3074 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3075 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3076 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3077 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3078 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3079 // CHECK4-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 3080 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3081 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3082 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3083 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3084 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3085 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3086 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3087 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 3088 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 3089 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 3090 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 3091 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3092 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP5]]) 3093 // CHECK4-NEXT: ret void 3094 // 3095 // 3096 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 3097 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] { 3098 // CHECK4-NEXT: entry: 3099 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3100 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3101 // CHECK4-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3102 // CHECK4-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 3103 // CHECK4-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3104 // CHECK4-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3105 // CHECK4-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 3106 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3107 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3108 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3109 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3110 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3111 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3112 // CHECK4-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 3113 // CHECK4-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 3114 // CHECK4-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3115 // CHECK4-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3116 // CHECK4-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3117 // CHECK4-NEXT: [[_TMP7:%.*]] = alloca %struct.S.0*, align 4 3118 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3119 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3120 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3121 // CHECK4-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3122 // CHECK4-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 3123 // CHECK4-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3124 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3125 // CHECK4-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3126 // CHECK4-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3127 // CHECK4-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3128 // CHECK4-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 3129 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3130 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3131 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3132 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3133 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 3134 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3135 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 3136 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3137 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0* 3138 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3139 // CHECK4-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP6]] 3140 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3141 // CHECK4: omp.arraycpy.body: 3142 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3143 // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3144 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP]]) 3145 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* noundef [[AGG_TMP]]) 3146 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP]]) #[[ATTR2]] 3147 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3148 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3149 // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 3150 // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3151 // CHECK4: omp.arraycpy.done4: 3152 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 3153 // CHECK4-NEXT: call void @_ZN2StC1Ev(%struct.St* noundef [[AGG_TMP6]]) 3154 // CHECK4-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* noundef [[VAR5]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP7]], %struct.St* noundef [[AGG_TMP6]]) 3155 // CHECK4-NEXT: call void @_ZN2StD1Ev(%struct.St* noundef [[AGG_TMP6]]) #[[ATTR2]] 3156 // CHECK4-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP7]], align 4 3157 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3158 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 3159 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3160 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3161 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 3162 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3163 // CHECK4: cond.true: 3164 // CHECK4-NEXT: br label [[COND_END:%.*]] 3165 // CHECK4: cond.false: 3166 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3167 // CHECK4-NEXT: br label [[COND_END]] 3168 // CHECK4: cond.end: 3169 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 3170 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3171 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3172 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 3173 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3174 // CHECK4: omp.inner.for.cond: 3175 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 3176 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 3177 // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 3178 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3179 // CHECK4: omp.inner.for.cond.cleanup: 3180 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3181 // CHECK4: omp.inner.for.body: 3182 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 3183 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 3184 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3185 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 3186 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4, !llvm.access.group !12 3187 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 3188 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 [[TMP17]] 3189 // CHECK4-NEXT: store i32 [[TMP16]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !12 3190 // CHECK4-NEXT: [[TMP18:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP7]], align 4, !llvm.access.group !12 3191 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 3192 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 [[TMP19]] 3193 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[ARRAYIDX9]] to i8* 3194 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast %struct.S.0* [[TMP18]] to i8* 3195 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP20]], i8* align 4 [[TMP21]], i32 4, i1 false), !llvm.access.group !12 3196 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3197 // CHECK4: omp.body.continue: 3198 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3199 // CHECK4: omp.inner.for.inc: 3200 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 3201 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], 1 3202 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 3203 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 3204 // CHECK4: omp.inner.for.end: 3205 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3206 // CHECK4: omp.loop.exit: 3207 // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3208 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 3209 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) 3210 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3211 // CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 3212 // CHECK4-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3213 // CHECK4: .omp.final.then: 3214 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4 3215 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 3216 // CHECK4: .omp.final.done: 3217 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[VAR5]]) #[[ATTR2]] 3218 // CHECK4-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3219 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2 3220 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3221 // CHECK4: arraydestroy.body: 3222 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3223 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3224 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3225 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] 3226 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] 3227 // CHECK4: arraydestroy.done12: 3228 // CHECK4-NEXT: ret void 3229 // 3230 // 3231 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3232 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3233 // CHECK4-NEXT: entry: 3234 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3235 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3236 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3237 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3238 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3239 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3240 // CHECK4-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* noundef [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* noundef [[T]]) 3241 // CHECK4-NEXT: ret void 3242 // 3243 // 3244 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3245 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3246 // CHECK4-NEXT: entry: 3247 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3248 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3249 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3250 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 3251 // CHECK4-NEXT: ret void 3252 // 3253 // 3254 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3255 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3256 // CHECK4-NEXT: entry: 3257 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3258 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3259 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3260 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3261 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3262 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3263 // CHECK4-NEXT: ret void 3264 // 3265 // 3266 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3267 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3268 // CHECK4-NEXT: entry: 3269 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3270 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3271 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3272 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3273 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3274 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3275 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3276 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3277 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3278 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3279 // CHECK4-NEXT: ret void 3280 // 3281 // 3282 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 3283 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3284 // CHECK4-NEXT: entry: 3285 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3286 // CHECK4-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3287 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3288 // CHECK4-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3289 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3290 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3291 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3292 // CHECK4-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 3293 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 3294 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3295 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3296 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 3297 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3298 // CHECK4-NEXT: ret void 3299 // 3300 // 3301 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3302 // CHECK4-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3303 // CHECK4-NEXT: entry: 3304 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3305 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3306 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3307 // CHECK4-NEXT: ret void 3308 // 3309 // 3310 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 3311 // CHECK4-SAME: () #[[ATTR0]] { 3312 // CHECK4-NEXT: entry: 3313 // CHECK4-NEXT: call void @__cxx_global_var_init() 3314 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 3315 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 3316 // CHECK4-NEXT: ret void 3317 // 3318 // 3319 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3320 // CHECK4-SAME: () #[[ATTR0]] { 3321 // CHECK4-NEXT: entry: 3322 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 3323 // CHECK4-NEXT: ret void 3324 // 3325 // 3326 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 3327 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 3328 // CHECK5-NEXT: entry: 3329 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 3330 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3331 // CHECK5-NEXT: ret void 3332 // 3333 // 3334 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3335 // CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3336 // CHECK5-NEXT: entry: 3337 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3338 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3339 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3340 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 3341 // CHECK5-NEXT: ret void 3342 // 3343 // 3344 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3345 // CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3346 // CHECK5-NEXT: entry: 3347 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3348 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3349 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3350 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 3351 // CHECK5-NEXT: ret void 3352 // 3353 // 3354 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3355 // CHECK5-SAME: () #[[ATTR0]] { 3356 // CHECK5-NEXT: entry: 3357 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 3358 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 3359 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3360 // CHECK5-NEXT: ret void 3361 // 3362 // 3363 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3364 // CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3365 // CHECK5-NEXT: entry: 3366 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3367 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3368 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3369 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3370 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3371 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3372 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 3373 // CHECK5-NEXT: ret void 3374 // 3375 // 3376 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3377 // CHECK5-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 3378 // CHECK5-NEXT: entry: 3379 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3380 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3381 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3382 // CHECK5: arraydestroy.body: 3383 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3384 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3385 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3386 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3387 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3388 // CHECK5: arraydestroy.done1: 3389 // CHECK5-NEXT: ret void 3390 // 3391 // 3392 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3393 // CHECK5-SAME: () #[[ATTR0]] { 3394 // CHECK5-NEXT: entry: 3395 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 3396 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3397 // CHECK5-NEXT: ret void 3398 // 3399 // 3400 // CHECK5-LABEL: define {{[^@]+}}@main 3401 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 3402 // CHECK5-NEXT: entry: 3403 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3404 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3405 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3406 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3407 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3408 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3409 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 3410 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3411 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3412 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3413 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3414 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3415 // CHECK5: omp.inner.for.cond: 3416 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3417 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 3418 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3419 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3420 // CHECK5: omp.inner.for.body: 3421 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3422 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 3423 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3424 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 3425 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !2 3426 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3427 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 3428 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 3429 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2 3430 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3431 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 3432 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 3433 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 3434 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false), !llvm.access.group !2 3435 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3436 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2 3437 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 3438 // CHECK5-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2 3439 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3440 // CHECK5: omp.body.continue: 3441 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3442 // CHECK5: omp.inner.for.inc: 3443 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3444 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 3445 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3446 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 3447 // CHECK5: omp.inner.for.end: 3448 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 3449 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 3450 // CHECK5-NEXT: ret i32 [[CALL]] 3451 // 3452 // 3453 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3454 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 3455 // CHECK5-NEXT: entry: 3456 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3457 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3458 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3459 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3460 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3461 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 3462 // CHECK5-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 3463 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3464 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3465 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3466 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3467 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3468 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 3469 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 3470 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3471 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3472 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3473 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 3474 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3475 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 3476 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 3477 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3478 // CHECK5-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 3479 // CHECK5-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3480 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3481 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3482 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3483 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3484 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3485 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3486 // CHECK5: omp.inner.for.cond: 3487 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3488 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 3489 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3490 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3491 // CHECK5: omp.inner.for.body: 3492 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3493 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3494 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3495 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 3496 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 3497 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 3498 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 3499 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 3500 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 3501 // CHECK5-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8, !llvm.access.group !6 3502 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 3503 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP11]] to i64 3504 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 3505 // CHECK5-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* 3506 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 3507 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6 3508 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3509 // CHECK5: omp.body.continue: 3510 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3511 // CHECK5: omp.inner.for.inc: 3512 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3513 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 3514 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3515 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3516 // CHECK5: omp.inner.for.end: 3517 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4 3518 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 3519 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3520 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3521 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3522 // CHECK5: arraydestroy.body: 3523 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3524 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3525 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3526 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3527 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 3528 // CHECK5: arraydestroy.done5: 3529 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 3530 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 3531 // CHECK5-NEXT: ret i32 [[TMP16]] 3532 // 3533 // 3534 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3535 // CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3536 // CHECK5-NEXT: entry: 3537 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3538 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3539 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3540 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3541 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3542 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3543 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 3544 // CHECK5-NEXT: ret void 3545 // 3546 // 3547 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3548 // CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3549 // CHECK5-NEXT: entry: 3550 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3551 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3552 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3553 // CHECK5-NEXT: ret void 3554 // 3555 // 3556 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3557 // CHECK5-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3558 // CHECK5-NEXT: entry: 3559 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3560 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3561 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3562 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3563 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3564 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3565 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3566 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3567 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3568 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3569 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 3570 // CHECK5-NEXT: ret void 3571 // 3572 // 3573 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3574 // CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3575 // CHECK5-NEXT: entry: 3576 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3577 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3578 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3579 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 3580 // CHECK5-NEXT: ret void 3581 // 3582 // 3583 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3584 // CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3585 // CHECK5-NEXT: entry: 3586 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3587 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3588 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3589 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3590 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3591 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3592 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) 3593 // CHECK5-NEXT: ret void 3594 // 3595 // 3596 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3597 // CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3598 // CHECK5-NEXT: entry: 3599 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3600 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3601 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3602 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 3603 // CHECK5-NEXT: ret void 3604 // 3605 // 3606 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3607 // CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3608 // CHECK5-NEXT: entry: 3609 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3610 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3611 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3612 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3613 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3614 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3615 // CHECK5-NEXT: ret void 3616 // 3617 // 3618 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3619 // CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3620 // CHECK5-NEXT: entry: 3621 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3622 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3623 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3624 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3625 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3626 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3627 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3628 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3629 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3630 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3631 // CHECK5-NEXT: ret void 3632 // 3633 // 3634 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3635 // CHECK5-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3636 // CHECK5-NEXT: entry: 3637 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3638 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3639 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3640 // CHECK5-NEXT: ret void 3641 // 3642 // 3643 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 3644 // CHECK5-SAME: () #[[ATTR0]] { 3645 // CHECK5-NEXT: entry: 3646 // CHECK5-NEXT: call void @__cxx_global_var_init() 3647 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 3648 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 3649 // CHECK5-NEXT: ret void 3650 // 3651 // 3652 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init 3653 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 3654 // CHECK6-NEXT: entry: 3655 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 3656 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3657 // CHECK6-NEXT: ret void 3658 // 3659 // 3660 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3661 // CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3662 // CHECK6-NEXT: entry: 3663 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3664 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3665 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3666 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 3667 // CHECK6-NEXT: ret void 3668 // 3669 // 3670 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3671 // CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3672 // CHECK6-NEXT: entry: 3673 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3674 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3675 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3676 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 3677 // CHECK6-NEXT: ret void 3678 // 3679 // 3680 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 3681 // CHECK6-SAME: () #[[ATTR0]] { 3682 // CHECK6-NEXT: entry: 3683 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 3684 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 3685 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 3686 // CHECK6-NEXT: ret void 3687 // 3688 // 3689 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 3690 // CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3691 // CHECK6-NEXT: entry: 3692 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3693 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3694 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3695 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3696 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3697 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3698 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 3699 // CHECK6-NEXT: ret void 3700 // 3701 // 3702 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 3703 // CHECK6-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 3704 // CHECK6-NEXT: entry: 3705 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 3706 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 3707 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3708 // CHECK6: arraydestroy.body: 3709 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3710 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3711 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3712 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 3713 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3714 // CHECK6: arraydestroy.done1: 3715 // CHECK6-NEXT: ret void 3716 // 3717 // 3718 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 3719 // CHECK6-SAME: () #[[ATTR0]] { 3720 // CHECK6-NEXT: entry: 3721 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 3722 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 3723 // CHECK6-NEXT: ret void 3724 // 3725 // 3726 // CHECK6-LABEL: define {{[^@]+}}@main 3727 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] { 3728 // CHECK6-NEXT: entry: 3729 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3730 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 3731 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3732 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3733 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3734 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3735 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 3736 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3737 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3738 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3739 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3740 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3741 // CHECK6: omp.inner.for.cond: 3742 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3743 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 3744 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3745 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3746 // CHECK6: omp.inner.for.body: 3747 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3748 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 3749 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3750 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 3751 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !2 3752 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3753 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 3754 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i64 0, i64 [[IDXPROM]] 3755 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2 3756 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3757 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 3758 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 [[IDXPROM1]] 3759 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* 3760 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false), !llvm.access.group !2 3761 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 3762 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2 3763 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 3764 // CHECK6-NEXT: store i32 [[ADD3]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !2 3765 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3766 // CHECK6: omp.body.continue: 3767 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3768 // CHECK6: omp.inner.for.inc: 3769 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3770 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 3771 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 3772 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 3773 // CHECK6: omp.inner.for.end: 3774 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 3775 // CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 3776 // CHECK6-NEXT: ret i32 [[CALL]] 3777 // 3778 // 3779 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3780 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat { 3781 // CHECK6-NEXT: entry: 3782 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3783 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3784 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 3785 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 3786 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 3787 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 3788 // CHECK6-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 3789 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3790 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3791 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3792 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3793 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3794 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 3795 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 3796 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3797 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3798 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3799 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 3800 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3801 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 3802 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 3803 // CHECK6-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3804 // CHECK6-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 3805 // CHECK6-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3806 // CHECK6-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 3807 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3808 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 3809 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3810 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3811 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3812 // CHECK6: omp.inner.for.cond: 3813 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3814 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 3815 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3816 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3817 // CHECK6: omp.inner.for.body: 3818 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3819 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3820 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3821 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 3822 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !6 3823 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 3824 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 3825 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]] 3826 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6 3827 // CHECK6-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8, !llvm.access.group !6 3828 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 3829 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP11]] to i64 3830 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM2]] 3831 // CHECK6-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX3]] to i8* 3832 // CHECK6-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 3833 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false), !llvm.access.group !6 3834 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3835 // CHECK6: omp.body.continue: 3836 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3837 // CHECK6: omp.inner.for.inc: 3838 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3839 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 3840 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3841 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3842 // CHECK6: omp.inner.for.end: 3843 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4 3844 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 3845 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3846 // CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3847 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3848 // CHECK6: arraydestroy.body: 3849 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3850 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3851 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 3852 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3853 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 3854 // CHECK6: arraydestroy.done5: 3855 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 3856 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 3857 // CHECK6-NEXT: ret i32 [[TMP16]] 3858 // 3859 // 3860 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3861 // CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3862 // CHECK6-NEXT: entry: 3863 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3864 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3865 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3866 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3867 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3868 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3869 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 3870 // CHECK6-NEXT: ret void 3871 // 3872 // 3873 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3874 // CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3875 // CHECK6-NEXT: entry: 3876 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3877 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3878 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3879 // CHECK6-NEXT: ret void 3880 // 3881 // 3882 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3883 // CHECK6-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3884 // CHECK6-NEXT: entry: 3885 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3886 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3887 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3888 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3889 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3890 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3891 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3892 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3893 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3894 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3895 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 3896 // CHECK6-NEXT: ret void 3897 // 3898 // 3899 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3900 // CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3901 // CHECK6-NEXT: entry: 3902 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3903 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3904 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3905 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 3906 // CHECK6-NEXT: ret void 3907 // 3908 // 3909 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3910 // CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3911 // CHECK6-NEXT: entry: 3912 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3913 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3914 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3915 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3916 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3917 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3918 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef signext [[TMP0]]) 3919 // CHECK6-NEXT: ret void 3920 // 3921 // 3922 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3923 // CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3924 // CHECK6-NEXT: entry: 3925 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3926 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3927 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3928 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 3929 // CHECK6-NEXT: ret void 3930 // 3931 // 3932 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3933 // CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3934 // CHECK6-NEXT: entry: 3935 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3936 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3937 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3938 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3939 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 3940 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3941 // CHECK6-NEXT: ret void 3942 // 3943 // 3944 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3945 // CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3946 // CHECK6-NEXT: entry: 3947 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3948 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3949 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3950 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3951 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3952 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3953 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3954 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 3955 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3956 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3957 // CHECK6-NEXT: ret void 3958 // 3959 // 3960 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3961 // CHECK6-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3962 // CHECK6-NEXT: entry: 3963 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3964 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3965 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3966 // CHECK6-NEXT: ret void 3967 // 3968 // 3969 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 3970 // CHECK6-SAME: () #[[ATTR0]] { 3971 // CHECK6-NEXT: entry: 3972 // CHECK6-NEXT: call void @__cxx_global_var_init() 3973 // CHECK6-NEXT: call void @__cxx_global_var_init.1() 3974 // CHECK6-NEXT: call void @__cxx_global_var_init.2() 3975 // CHECK6-NEXT: ret void 3976 // 3977 // 3978 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 3979 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 3980 // CHECK7-NEXT: entry: 3981 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 3982 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 3983 // CHECK7-NEXT: ret void 3984 // 3985 // 3986 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 3987 // CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3988 // CHECK7-NEXT: entry: 3989 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3990 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3991 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3992 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 3993 // CHECK7-NEXT: ret void 3994 // 3995 // 3996 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3997 // CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3998 // CHECK7-NEXT: entry: 3999 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4000 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4001 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4002 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 4003 // CHECK7-NEXT: ret void 4004 // 4005 // 4006 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4007 // CHECK7-SAME: () #[[ATTR0]] { 4008 // CHECK7-NEXT: entry: 4009 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 4010 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 4011 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4012 // CHECK7-NEXT: ret void 4013 // 4014 // 4015 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4016 // CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4017 // CHECK7-NEXT: entry: 4018 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4019 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4020 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4021 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4022 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4023 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4024 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 4025 // CHECK7-NEXT: ret void 4026 // 4027 // 4028 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4029 // CHECK7-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 4030 // CHECK7-NEXT: entry: 4031 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 4032 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 4033 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4034 // CHECK7: arraydestroy.body: 4035 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4036 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4037 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4038 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4039 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4040 // CHECK7: arraydestroy.done1: 4041 // CHECK7-NEXT: ret void 4042 // 4043 // 4044 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4045 // CHECK7-SAME: () #[[ATTR0]] { 4046 // CHECK7-NEXT: entry: 4047 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 4048 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4049 // CHECK7-NEXT: ret void 4050 // 4051 // 4052 // CHECK7-LABEL: define {{[^@]+}}@main 4053 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 4054 // CHECK7-NEXT: entry: 4055 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4056 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 4057 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4058 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4059 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4060 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 4061 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 4062 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4063 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4064 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4065 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4066 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4067 // CHECK7: omp.inner.for.cond: 4068 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4069 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 4070 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4071 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4072 // CHECK7: omp.inner.for.body: 4073 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4074 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 4075 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4076 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 4077 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !3 4078 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4079 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP5]] 4080 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3 4081 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4082 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP6]] 4083 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 4084 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false), !llvm.access.group !3 4085 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4086 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3 4087 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 4088 // CHECK7-NEXT: store i32 [[ADD2]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3 4089 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4090 // CHECK7: omp.body.continue: 4091 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4092 // CHECK7: omp.inner.for.inc: 4093 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4094 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 4095 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4096 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 4097 // CHECK7: omp.inner.for.end: 4098 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 4099 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 4100 // CHECK7-NEXT: ret i32 [[CALL]] 4101 // 4102 // 4103 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4104 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 4105 // CHECK7-NEXT: entry: 4106 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4107 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4108 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 4109 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4110 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 4111 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 4112 // CHECK7-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 4113 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4114 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4115 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4116 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4117 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 4118 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 4119 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4 4120 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4121 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 4122 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4123 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) 4124 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 4125 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) 4126 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 4127 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4128 // CHECK7-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 4129 // CHECK7-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4130 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4131 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4132 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4133 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4134 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4135 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4136 // CHECK7: omp.inner.for.cond: 4137 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 4138 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 4139 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4140 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4141 // CHECK7: omp.inner.for.body: 4142 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 4143 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4144 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4145 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 4146 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7 4147 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 4148 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 4149 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7 4150 // CHECK7-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4, !llvm.access.group !7 4151 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 4152 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 4153 // CHECK7-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* 4154 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 4155 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7 4156 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4157 // CHECK7: omp.body.continue: 4158 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4159 // CHECK7: omp.inner.for.inc: 4160 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 4161 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 4162 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 4163 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 4164 // CHECK7: omp.inner.for.end: 4165 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4 4166 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 4167 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4168 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4169 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4170 // CHECK7: arraydestroy.body: 4171 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4172 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4173 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4174 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4175 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 4176 // CHECK7: arraydestroy.done4: 4177 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 4178 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 4179 // CHECK7-NEXT: ret i32 [[TMP16]] 4180 // 4181 // 4182 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4183 // CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4184 // CHECK7-NEXT: entry: 4185 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4186 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4187 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4188 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4189 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4190 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4191 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 4192 // CHECK7-NEXT: ret void 4193 // 4194 // 4195 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4196 // CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4197 // CHECK7-NEXT: entry: 4198 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4199 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4200 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4201 // CHECK7-NEXT: ret void 4202 // 4203 // 4204 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4205 // CHECK7-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4206 // CHECK7-NEXT: entry: 4207 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4208 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4209 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4210 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4211 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4212 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4213 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4214 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4215 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4216 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4217 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 4218 // CHECK7-NEXT: ret void 4219 // 4220 // 4221 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4222 // CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4223 // CHECK7-NEXT: entry: 4224 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4225 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4226 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4227 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 4228 // CHECK7-NEXT: ret void 4229 // 4230 // 4231 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4232 // CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4233 // CHECK7-NEXT: entry: 4234 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4235 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4236 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4237 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4238 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4239 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4240 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) 4241 // CHECK7-NEXT: ret void 4242 // 4243 // 4244 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4245 // CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4246 // CHECK7-NEXT: entry: 4247 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4248 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4249 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4250 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 4251 // CHECK7-NEXT: ret void 4252 // 4253 // 4254 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4255 // CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4256 // CHECK7-NEXT: entry: 4257 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4258 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4259 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4260 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4261 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4262 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4263 // CHECK7-NEXT: ret void 4264 // 4265 // 4266 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4267 // CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4268 // CHECK7-NEXT: entry: 4269 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4270 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4271 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4272 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4273 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4274 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4275 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4276 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4277 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4278 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4279 // CHECK7-NEXT: ret void 4280 // 4281 // 4282 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4283 // CHECK7-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4284 // CHECK7-NEXT: entry: 4285 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4286 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4287 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4288 // CHECK7-NEXT: ret void 4289 // 4290 // 4291 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 4292 // CHECK7-SAME: () #[[ATTR0]] { 4293 // CHECK7-NEXT: entry: 4294 // CHECK7-NEXT: call void @__cxx_global_var_init() 4295 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 4296 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 4297 // CHECK7-NEXT: ret void 4298 // 4299 // 4300 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init 4301 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 4302 // CHECK8-NEXT: entry: 4303 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 4304 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4305 // CHECK8-NEXT: ret void 4306 // 4307 // 4308 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4309 // CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4310 // CHECK8-NEXT: entry: 4311 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4312 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4313 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4314 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 4315 // CHECK8-NEXT: ret void 4316 // 4317 // 4318 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4319 // CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4320 // CHECK8-NEXT: entry: 4321 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4322 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4323 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4324 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 4325 // CHECK8-NEXT: ret void 4326 // 4327 // 4328 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4329 // CHECK8-SAME: () #[[ATTR0]] { 4330 // CHECK8-NEXT: entry: 4331 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float noundef 1.000000e+00) 4332 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float noundef 2.000000e+00) 4333 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4334 // CHECK8-NEXT: ret void 4335 // 4336 // 4337 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4338 // CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4339 // CHECK8-NEXT: entry: 4340 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4341 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4342 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4343 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4344 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4345 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4346 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 4347 // CHECK8-NEXT: ret void 4348 // 4349 // 4350 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4351 // CHECK8-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 4352 // CHECK8-NEXT: entry: 4353 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4 4354 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4 4355 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4356 // CHECK8: arraydestroy.body: 4357 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i32 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4358 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4359 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4360 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4361 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4362 // CHECK8: arraydestroy.done1: 4363 // CHECK8-NEXT: ret void 4364 // 4365 // 4366 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4367 // CHECK8-SAME: () #[[ATTR0]] { 4368 // CHECK8-NEXT: entry: 4369 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 4370 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4371 // CHECK8-NEXT: ret void 4372 // 4373 // 4374 // CHECK8-LABEL: define {{[^@]+}}@main 4375 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] { 4376 // CHECK8-NEXT: entry: 4377 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4378 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 4379 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4380 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4381 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4382 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 4383 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 4384 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4385 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4386 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4387 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 4388 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4389 // CHECK8: omp.inner.for.cond: 4390 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4391 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 4392 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 4393 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4394 // CHECK8: omp.inner.for.body: 4395 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4396 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 4397 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4398 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 4399 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* @t_var, align 4, !llvm.access.group !3 4400 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4401 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* @vec, i32 0, i32 [[TMP5]] 4402 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3 4403 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4404 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 [[TMP6]] 4405 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* 4406 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 bitcast (%struct.S* @var to i8*), i32 4, i1 false), !llvm.access.group !3 4407 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 4408 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3 4409 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] 4410 // CHECK8-NEXT: store i32 [[ADD2]], i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group !3 4411 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4412 // CHECK8: omp.body.continue: 4413 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4414 // CHECK8: omp.inner.for.inc: 4415 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4416 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 4417 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 4418 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 4419 // CHECK8: omp.inner.for.end: 4420 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 4421 // CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 4422 // CHECK8-NEXT: ret i32 [[CALL]] 4423 // 4424 // 4425 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 4426 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat { 4427 // CHECK8-NEXT: entry: 4428 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4429 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 4430 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 4431 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 4432 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 4433 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 4434 // CHECK8-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 4435 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4436 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4437 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4438 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4439 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 4440 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef [[TEST]]) 4441 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4 4442 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 4443 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 4444 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4445 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_BEGIN]], i32 noundef 1) 4446 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 4447 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef [[ARRAYINIT_ELEMENT]], i32 noundef 2) 4448 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 4449 // CHECK8-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4450 // CHECK8-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 4451 // CHECK8-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4452 // CHECK8-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 4453 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4454 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4455 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4456 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4457 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4458 // CHECK8: omp.inner.for.cond: 4459 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 4460 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 4461 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4462 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4463 // CHECK8: omp.inner.for.body: 4464 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 4465 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4466 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4467 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 4468 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !7 4469 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 4470 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]] 4471 // CHECK8-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7 4472 // CHECK8-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4, !llvm.access.group !7 4473 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 4474 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]] 4475 // CHECK8-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* 4476 // CHECK8-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8* 4477 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false), !llvm.access.group !7 4478 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4479 // CHECK8: omp.body.continue: 4480 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4481 // CHECK8: omp.inner.for.inc: 4482 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 4483 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], 1 4484 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 4485 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 4486 // CHECK8: omp.inner.for.end: 4487 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4 4488 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 4489 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 4490 // CHECK8-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 4491 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4492 // CHECK8: arraydestroy.body: 4493 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP15]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4494 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 4495 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4496 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 4497 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 4498 // CHECK8: arraydestroy.done4: 4499 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef [[TEST]]) #[[ATTR2]] 4500 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, i32* [[RETVAL]], align 4 4501 // CHECK8-NEXT: ret i32 [[TMP16]] 4502 // 4503 // 4504 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4505 // CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4506 // CHECK8-NEXT: entry: 4507 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4508 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4509 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4510 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4511 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4512 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4513 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 4514 // CHECK8-NEXT: ret void 4515 // 4516 // 4517 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4518 // CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4519 // CHECK8-NEXT: entry: 4520 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4521 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4522 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4523 // CHECK8-NEXT: ret void 4524 // 4525 // 4526 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4527 // CHECK8-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4528 // CHECK8-NEXT: entry: 4529 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 4530 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4531 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 4532 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4533 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 4534 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4535 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4536 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4537 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4538 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4539 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 4540 // CHECK8-NEXT: ret void 4541 // 4542 // 4543 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 4544 // CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4545 // CHECK8-NEXT: entry: 4546 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4547 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4548 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4549 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef [[THIS1]]) 4550 // CHECK8-NEXT: ret void 4551 // 4552 // 4553 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 4554 // CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4555 // CHECK8-NEXT: entry: 4556 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4557 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4558 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4559 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4560 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4561 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4562 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef [[THIS1]], i32 noundef [[TMP0]]) 4563 // CHECK8-NEXT: ret void 4564 // 4565 // 4566 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 4567 // CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4568 // CHECK8-NEXT: entry: 4569 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4570 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4571 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4572 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef [[THIS1]]) #[[ATTR2]] 4573 // CHECK8-NEXT: ret void 4574 // 4575 // 4576 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 4577 // CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4578 // CHECK8-NEXT: entry: 4579 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4580 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4581 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4582 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4583 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4584 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 4585 // CHECK8-NEXT: ret void 4586 // 4587 // 4588 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 4589 // CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4590 // CHECK8-NEXT: entry: 4591 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4592 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4593 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4594 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4595 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4596 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 4597 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4598 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4599 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 4600 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4 4601 // CHECK8-NEXT: ret void 4602 // 4603 // 4604 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 4605 // CHECK8-SAME: (%struct.S.0* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4606 // CHECK8-NEXT: entry: 4607 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 4608 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 4609 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 4610 // CHECK8-NEXT: ret void 4611 // 4612 // 4613 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 4614 // CHECK8-SAME: () #[[ATTR0]] { 4615 // CHECK8-NEXT: entry: 4616 // CHECK8-NEXT: call void @__cxx_global_var_init() 4617 // CHECK8-NEXT: call void @__cxx_global_var_init.1() 4618 // CHECK8-NEXT: call void @__cxx_global_var_init.2() 4619 // CHECK8-NEXT: ret void 4620 // 4621 // 4622 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 4623 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 4624 // CHECK9-NEXT: entry: 4625 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 4626 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4627 // CHECK9-NEXT: ret void 4628 // 4629 // 4630 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4631 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4632 // CHECK9-NEXT: entry: 4633 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4634 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4635 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4636 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 4637 // CHECK9-NEXT: ret void 4638 // 4639 // 4640 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4641 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4642 // CHECK9-NEXT: entry: 4643 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4644 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4645 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4646 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 4647 // CHECK9-NEXT: ret void 4648 // 4649 // 4650 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4651 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4652 // CHECK9-NEXT: entry: 4653 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4654 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4655 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4656 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4657 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4658 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4659 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 4660 // CHECK9-NEXT: ret void 4661 // 4662 // 4663 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4664 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4665 // CHECK9-NEXT: entry: 4666 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4667 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4668 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4669 // CHECK9-NEXT: ret void 4670 // 4671 // 4672 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4673 // CHECK9-SAME: () #[[ATTR0]] { 4674 // CHECK9-NEXT: entry: 4675 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 4676 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 4677 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4678 // CHECK9-NEXT: ret void 4679 // 4680 // 4681 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4682 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4683 // CHECK9-NEXT: entry: 4684 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4685 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4686 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4687 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4688 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4689 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4690 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 4691 // CHECK9-NEXT: ret void 4692 // 4693 // 4694 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4695 // CHECK9-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 4696 // CHECK9-NEXT: entry: 4697 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4698 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4699 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4700 // CHECK9: arraydestroy.body: 4701 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4702 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4703 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4704 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4705 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4706 // CHECK9: arraydestroy.done1: 4707 // CHECK9-NEXT: ret void 4708 // 4709 // 4710 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4711 // CHECK9-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4712 // CHECK9-NEXT: entry: 4713 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4714 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4715 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4716 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4717 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4718 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4719 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4720 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4721 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4722 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4723 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 4724 // CHECK9-NEXT: ret void 4725 // 4726 // 4727 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4728 // CHECK9-SAME: () #[[ATTR0]] { 4729 // CHECK9-NEXT: entry: 4730 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 4731 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4732 // CHECK9-NEXT: ret void 4733 // 4734 // 4735 // CHECK9-LABEL: define {{[^@]+}}@main 4736 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 4737 // CHECK9-NEXT: entry: 4738 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 4739 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 4740 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 4741 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 4742 // CHECK9-NEXT: ret i32 0 4743 // 4744 // 4745 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 4746 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 4747 // CHECK9-NEXT: entry: 4748 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4749 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4750 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4751 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4752 // CHECK9-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 4753 // CHECK9-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 4754 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 4755 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4756 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4757 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4758 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4759 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4760 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4761 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 4762 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4763 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 4764 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 4765 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 4766 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 4767 // CHECK9-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 4768 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 4769 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 4770 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 4771 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4 4772 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 4773 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 4774 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 4775 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 4776 // CHECK9-NEXT: ret void 4777 // 4778 // 4779 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 4780 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR6:[0-9]+]] { 4781 // CHECK9-NEXT: entry: 4782 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4783 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4784 // CHECK9-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 4785 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 4786 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 4787 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4788 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4789 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 4790 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4791 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4792 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4793 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4794 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4795 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 4796 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4797 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4798 // CHECK9-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 4799 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 4800 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 4801 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 4802 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 4803 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 4804 // CHECK9-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 4805 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4806 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 4807 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4808 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4809 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4810 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4811 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4812 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4813 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 4814 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4815 // CHECK9: cond.true: 4816 // CHECK9-NEXT: br label [[COND_END:%.*]] 4817 // CHECK9: cond.false: 4818 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4819 // CHECK9-NEXT: br label [[COND_END]] 4820 // CHECK9: cond.end: 4821 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4822 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4823 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4824 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4825 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4826 // CHECK9: omp.inner.for.cond: 4827 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 4828 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 4829 // CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4830 // CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4831 // CHECK9: omp.inner.for.body: 4832 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 4833 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4834 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4835 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 4836 // CHECK9-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4 4837 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 4838 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 4839 // CHECK9-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4 4840 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 4841 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 4842 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 4843 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 4844 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 4845 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 4846 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 4847 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 4848 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4849 // CHECK9: omp.body.continue: 4850 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4851 // CHECK9: omp.inner.for.inc: 4852 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 4853 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 4854 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 4855 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 4856 // CHECK9: omp.inner.for.end: 4857 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4858 // CHECK9: omp.loop.exit: 4859 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4860 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4861 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 4862 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4863 // CHECK9: .omp.final.then: 4864 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4 4865 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 4866 // CHECK9: .omp.final.done: 4867 // CHECK9-NEXT: ret void 4868 // 4869 // 4870 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 4871 // CHECK9-SAME: () #[[ATTR0]] { 4872 // CHECK9-NEXT: entry: 4873 // CHECK9-NEXT: call void @__cxx_global_var_init() 4874 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 4875 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 4876 // CHECK9-NEXT: ret void 4877 // 4878 // 4879 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4880 // CHECK9-SAME: () #[[ATTR0]] { 4881 // CHECK9-NEXT: entry: 4882 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 4883 // CHECK9-NEXT: ret void 4884 // 4885 // 4886 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init 4887 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 4888 // CHECK10-NEXT: entry: 4889 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 4890 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 4891 // CHECK10-NEXT: ret void 4892 // 4893 // 4894 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 4895 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 4896 // CHECK10-NEXT: entry: 4897 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4898 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4899 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4900 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 4901 // CHECK10-NEXT: ret void 4902 // 4903 // 4904 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 4905 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4906 // CHECK10-NEXT: entry: 4907 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4908 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4909 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4910 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 4911 // CHECK10-NEXT: ret void 4912 // 4913 // 4914 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 4915 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4916 // CHECK10-NEXT: entry: 4917 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4918 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4919 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4920 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4921 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 4922 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 4923 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 4924 // CHECK10-NEXT: ret void 4925 // 4926 // 4927 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 4928 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4929 // CHECK10-NEXT: entry: 4930 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4931 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4932 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4933 // CHECK10-NEXT: ret void 4934 // 4935 // 4936 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 4937 // CHECK10-SAME: () #[[ATTR0]] { 4938 // CHECK10-NEXT: entry: 4939 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 4940 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 4941 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 4942 // CHECK10-NEXT: ret void 4943 // 4944 // 4945 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 4946 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4947 // CHECK10-NEXT: entry: 4948 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4949 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4950 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4951 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4952 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4953 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4954 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 4955 // CHECK10-NEXT: ret void 4956 // 4957 // 4958 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 4959 // CHECK10-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 4960 // CHECK10-NEXT: entry: 4961 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 4962 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 4963 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 4964 // CHECK10: arraydestroy.body: 4965 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 4966 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 4967 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 4968 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 4969 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 4970 // CHECK10: arraydestroy.done1: 4971 // CHECK10-NEXT: ret void 4972 // 4973 // 4974 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 4975 // CHECK10-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 4976 // CHECK10-NEXT: entry: 4977 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 4978 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 4979 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 4980 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 4981 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 4982 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 4983 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 4984 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 4985 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 4986 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 4987 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 4988 // CHECK10-NEXT: ret void 4989 // 4990 // 4991 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 4992 // CHECK10-SAME: () #[[ATTR0]] { 4993 // CHECK10-NEXT: entry: 4994 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 4995 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 4996 // CHECK10-NEXT: ret void 4997 // 4998 // 4999 // CHECK10-LABEL: define {{[^@]+}}@main 5000 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] { 5001 // CHECK10-NEXT: entry: 5002 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5003 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5004 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 5005 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 5006 // CHECK10-NEXT: ret i32 0 5007 // 5008 // 5009 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74 5010 // CHECK10-SAME: (i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 5011 // CHECK10-NEXT: entry: 5012 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 5013 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 5014 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 5015 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5016 // CHECK10-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 5017 // CHECK10-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8 5018 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 5019 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 5020 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 5021 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 5022 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 5023 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 5024 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 5025 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 5026 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 5027 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[G_CASTED]] to i32* 5028 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV3]], align 4 5029 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[G_CASTED]], align 8 5030 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP]], align 8 5031 // CHECK10-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 4 5032 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[G1_CASTED]] to i32* 5033 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 5034 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[G1_CASTED]], align 8 5035 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV2]], align 4 5036 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 5037 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 5038 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 5039 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]]) 5040 // CHECK10-NEXT: ret void 5041 // 5042 // 5043 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 5044 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR6:[0-9]+]] { 5045 // CHECK10-NEXT: entry: 5046 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5047 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5048 // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 5049 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 5050 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 5051 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 5052 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5053 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 5054 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5055 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5056 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5057 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5058 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 5059 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 5060 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5061 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5062 // CHECK10-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 5063 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 5064 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 5065 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to i32* 5066 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to i32* 5067 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 5068 // CHECK10-NEXT: store i32* [[CONV1]], i32** [[TMP]], align 8 5069 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5070 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 5071 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5072 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5073 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5074 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5075 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5076 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5077 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 5078 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5079 // CHECK10: cond.true: 5080 // CHECK10-NEXT: br label [[COND_END:%.*]] 5081 // CHECK10: cond.false: 5082 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5083 // CHECK10-NEXT: br label [[COND_END]] 5084 // CHECK10: cond.end: 5085 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5086 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5087 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5088 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5089 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5090 // CHECK10: omp.inner.for.cond: 5091 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 5092 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 5093 // CHECK10-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5094 // CHECK10-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5095 // CHECK10: omp.inner.for.body: 5096 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 5097 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 5098 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5099 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 5100 // CHECK10-NEXT: store i32 1, i32* [[CONV]], align 4, !llvm.access.group !4 5101 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 5102 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4, !llvm.access.group !4 5103 // CHECK10-NEXT: store i32 2, i32* [[CONV2]], align 4, !llvm.access.group !4 5104 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 5105 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP9]], align 8, !llvm.access.group !4 5106 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 5107 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[TMP]], align 8, !llvm.access.group !4 5108 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8, !llvm.access.group !4 5109 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 5110 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[TMP12]], align 8, !llvm.access.group !4 5111 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef [[REF_TMP]]), !llvm.access.group !4 5112 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5113 // CHECK10: omp.body.continue: 5114 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5115 // CHECK10: omp.inner.for.inc: 5116 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 5117 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 5118 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 5119 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 5120 // CHECK10: omp.inner.for.end: 5121 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5122 // CHECK10: omp.loop.exit: 5123 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5124 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5125 // CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 5126 // CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5127 // CHECK10: .omp.final.then: 5128 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4 5129 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] 5130 // CHECK10: .omp.final.done: 5131 // CHECK10-NEXT: ret void 5132 // 5133 // 5134 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 5135 // CHECK10-SAME: () #[[ATTR0]] { 5136 // CHECK10-NEXT: entry: 5137 // CHECK10-NEXT: call void @__cxx_global_var_init() 5138 // CHECK10-NEXT: call void @__cxx_global_var_init.1() 5139 // CHECK10-NEXT: call void @__cxx_global_var_init.2() 5140 // CHECK10-NEXT: ret void 5141 // 5142 // 5143 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5144 // CHECK10-SAME: () #[[ATTR0]] { 5145 // CHECK10-NEXT: entry: 5146 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 5147 // CHECK10-NEXT: ret void 5148 // 5149 // 5150 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 5151 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 5152 // CHECK11-NEXT: entry: 5153 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 5154 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 5155 // CHECK11-NEXT: ret void 5156 // 5157 // 5158 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 5159 // CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 5160 // CHECK11-NEXT: entry: 5161 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5162 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5163 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5164 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 5165 // CHECK11-NEXT: ret void 5166 // 5167 // 5168 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 5169 // CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5170 // CHECK11-NEXT: entry: 5171 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5172 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5173 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5174 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 5175 // CHECK11-NEXT: ret void 5176 // 5177 // 5178 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5179 // CHECK11-SAME: () #[[ATTR0]] { 5180 // CHECK11-NEXT: entry: 5181 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 5182 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 5183 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5184 // CHECK11-NEXT: ret void 5185 // 5186 // 5187 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5188 // CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5189 // CHECK11-NEXT: entry: 5190 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5191 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5192 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5193 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5194 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5195 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5196 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 5197 // CHECK11-NEXT: ret void 5198 // 5199 // 5200 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5201 // CHECK11-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 5202 // CHECK11-NEXT: entry: 5203 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 5204 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 5205 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5206 // CHECK11: arraydestroy.body: 5207 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5208 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5209 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5210 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5211 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5212 // CHECK11: arraydestroy.done1: 5213 // CHECK11-NEXT: ret void 5214 // 5215 // 5216 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5217 // CHECK11-SAME: () #[[ATTR0]] { 5218 // CHECK11-NEXT: entry: 5219 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 5220 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5221 // CHECK11-NEXT: ret void 5222 // 5223 // 5224 // CHECK11-LABEL: define {{[^@]+}}@main 5225 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 5226 // CHECK11-NEXT: entry: 5227 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5228 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5229 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 5230 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 5231 // CHECK11-NEXT: ret i32 0 5232 // 5233 // 5234 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5235 // CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5236 // CHECK11-NEXT: entry: 5237 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5238 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5239 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5240 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5241 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5242 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5243 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 5244 // CHECK11-NEXT: ret void 5245 // 5246 // 5247 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5248 // CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5249 // CHECK11-NEXT: entry: 5250 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5251 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5252 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5253 // CHECK11-NEXT: ret void 5254 // 5255 // 5256 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5257 // CHECK11-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5258 // CHECK11-NEXT: entry: 5259 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5260 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5261 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5262 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5263 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5264 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5265 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5266 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5267 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5268 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5269 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 5270 // CHECK11-NEXT: ret void 5271 // 5272 // 5273 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 5274 // CHECK11-SAME: () #[[ATTR0]] { 5275 // CHECK11-NEXT: entry: 5276 // CHECK11-NEXT: call void @__cxx_global_var_init() 5277 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 5278 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 5279 // CHECK11-NEXT: ret void 5280 // 5281 // 5282 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init 5283 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 5284 // CHECK12-NEXT: entry: 5285 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* noundef @test) 5286 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 5287 // CHECK12-NEXT: ret void 5288 // 5289 // 5290 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 5291 // CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 5292 // CHECK12-NEXT: entry: 5293 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5294 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5295 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5296 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* noundef [[THIS1]]) 5297 // CHECK12-NEXT: ret void 5298 // 5299 // 5300 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 5301 // CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5302 // CHECK12-NEXT: entry: 5303 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5304 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5305 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5306 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* noundef [[THIS1]]) #[[ATTR2]] 5307 // CHECK12-NEXT: ret void 5308 // 5309 // 5310 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 5311 // CHECK12-SAME: () #[[ATTR0]] { 5312 // CHECK12-NEXT: entry: 5313 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float noundef 1.000000e+00) 5314 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float noundef 2.000000e+00) 5315 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 5316 // CHECK12-NEXT: ret void 5317 // 5318 // 5319 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 5320 // CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5321 // CHECK12-NEXT: entry: 5322 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5323 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5324 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5325 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5326 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5327 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5328 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* noundef [[THIS1]], float noundef [[TMP0]]) 5329 // CHECK12-NEXT: ret void 5330 // 5331 // 5332 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 5333 // CHECK12-SAME: (i8* noundef [[TMP0:%.*]]) #[[ATTR0]] { 5334 // CHECK12-NEXT: entry: 5335 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 5336 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 5337 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 5338 // CHECK12: arraydestroy.body: 5339 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 1, i64 0), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 5340 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 5341 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* noundef [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 5342 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 5343 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 5344 // CHECK12: arraydestroy.done1: 5345 // CHECK12-NEXT: ret void 5346 // 5347 // 5348 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 5349 // CHECK12-SAME: () #[[ATTR0]] { 5350 // CHECK12-NEXT: entry: 5351 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* noundef @var, float noundef 3.000000e+00) 5352 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 5353 // CHECK12-NEXT: ret void 5354 // 5355 // 5356 // CHECK12-LABEL: define {{[^@]+}}@main 5357 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 5358 // CHECK12-NEXT: entry: 5359 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 5360 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 5361 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 5362 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef [[REF_TMP]]) 5363 // CHECK12-NEXT: ret i32 0 5364 // 5365 // 5366 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 5367 // CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5368 // CHECK12-NEXT: entry: 5369 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5370 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5371 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5372 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5373 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 5374 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 5375 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 5376 // CHECK12-NEXT: ret void 5377 // 5378 // 5379 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 5380 // CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5381 // CHECK12-NEXT: entry: 5382 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5383 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5384 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5385 // CHECK12-NEXT: ret void 5386 // 5387 // 5388 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 5389 // CHECK12-SAME: (%struct.S* noundef [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 5390 // CHECK12-NEXT: entry: 5391 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 5392 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 5393 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 5394 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 5395 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 5396 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 5397 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 5398 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 5399 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 5400 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 5401 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 5402 // CHECK12-NEXT: ret void 5403 // 5404 // 5405 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_firstprivate_codegen.cpp 5406 // CHECK12-SAME: () #[[ATTR0]] { 5407 // CHECK12-NEXT: entry: 5408 // CHECK12-NEXT: call void @__cxx_global_var_init() 5409 // CHECK12-NEXT: call void @__cxx_global_var_init.1() 5410 // CHECK12-NEXT: call void @__cxx_global_var_init.2() 5411 // CHECK12-NEXT: ret void 5412 // 5413