1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // expected-no-diagnostics 3 #ifndef HEADER 4 #define HEADER 5 6 // Test host codegen. 7 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 8 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 9 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 10 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 11 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 13 14 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 15 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 16 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 17 // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 18 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 20 #ifdef CK1 21 22 template <typename T, int X, long long Y> 23 struct SS{ 24 T a[X][Y]; 25 26 int foo(void) { 27 28 #pragma omp target teams distribute simd collapse(2) 29 for(int i = 0; i < X; i++) { 30 for(int j = 0; j < Y; j++) { 31 a[i][j] = (T)0; 32 } 33 } 34 35 // discard loop variables not needed here 36 37 return a[0][0]; 38 } 39 }; 40 41 int teams_template_struct(void) { 42 SS<int, 123, 456> V; 43 return V.foo(); 44 45 } 46 #endif // CK1 47 48 // Test host codegen. 49 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 50 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 51 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 52 // RUN: %clang_cc1 -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 54 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 55 56 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 58 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 59 // RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 60 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 61 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 62 #ifdef CK2 63 64 template <typename T, int n, int m> 65 int tmain(T argc) { 66 T a[n][m]; 67 #pragma omp target teams distribute simd collapse(2) 68 for(int i = 0; i < n; i++) { 69 for(int j = 0; j < m; j++) { 70 a[i][j] = (T)0; 71 } 72 } 73 return 0; 74 } 75 76 int main (int argc, char **argv) { 77 int n = 100; 78 int m = 2; 79 int a[n][m]; 80 #pragma omp target teams distribute simd collapse(2) 81 for(int i = 0; i < n; i++) { 82 for(int j = 0; j < m; j++) { 83 a[i][j] = 0; 84 } 85 } 86 return tmain<int, 10, 2>(argc); 87 } 88 89 90 91 92 93 // discard loop variables not needed here 94 95 #endif // CK2 96 #endif // #ifndef HEADER 97 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv 98 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 99 // CHECK1-NEXT: entry: 100 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 101 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 102 // CHECK1-NEXT: ret i32 [[CALL]] 103 // 104 // 105 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 106 // CHECK1-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 107 // CHECK1-NEXT: entry: 108 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 109 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 110 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 111 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 112 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 113 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 114 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 115 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 116 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 117 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 118 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 119 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 120 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 121 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 122 // CHECK1-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 123 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 124 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8 125 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 126 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 127 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 128 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 129 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 130 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 131 // CHECK1: omp_offload.failed: 132 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR3:[0-9]+]] 133 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 134 // CHECK1: omp_offload.cont: 135 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 136 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 137 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 138 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 139 // CHECK1-NEXT: ret i32 [[TMP9]] 140 // 141 // 142 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 143 // CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 144 // CHECK1-NEXT: entry: 145 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 146 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 147 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 148 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 149 // CHECK1-NEXT: ret void 150 // 151 // 152 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 153 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { 154 // CHECK1-NEXT: entry: 155 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 156 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 157 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 158 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 159 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 160 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 161 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 162 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 163 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 165 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 166 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 167 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 168 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 169 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 170 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 171 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 172 // CHECK1-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 173 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 174 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 175 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 176 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 177 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 178 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 179 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 180 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 181 // CHECK1: cond.true: 182 // CHECK1-NEXT: br label [[COND_END:%.*]] 183 // CHECK1: cond.false: 184 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 185 // CHECK1-NEXT: br label [[COND_END]] 186 // CHECK1: cond.end: 187 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 188 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 189 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 190 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 191 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 192 // CHECK1: omp.inner.for.cond: 193 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 194 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 195 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 196 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 197 // CHECK1: omp.inner.for.body: 198 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 199 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 200 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 201 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 202 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 203 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 204 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 205 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 206 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 207 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 208 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 209 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 210 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 211 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 212 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 213 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 214 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 215 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 216 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 217 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 218 // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 219 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 220 // CHECK1: omp.body.continue: 221 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 222 // CHECK1: omp.inner.for.inc: 223 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 224 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 225 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 226 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 227 // CHECK1: omp.inner.for.end: 228 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 229 // CHECK1: omp.loop.exit: 230 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 231 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 232 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 233 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 234 // CHECK1: .omp.final.then: 235 // CHECK1-NEXT: store i32 123, i32* [[I]], align 4 236 // CHECK1-NEXT: store i32 456, i32* [[J]], align 4 237 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 238 // CHECK1: .omp.final.done: 239 // CHECK1-NEXT: ret void 240 // 241 // 242 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 243 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 244 // CHECK1-NEXT: entry: 245 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 246 // CHECK1-NEXT: ret void 247 // 248 // 249 // CHECK2-LABEL: define {{[^@]+}}@_Z21teams_template_structv 250 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 251 // CHECK2-NEXT: entry: 252 // CHECK2-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 253 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 254 // CHECK2-NEXT: ret i32 [[CALL]] 255 // 256 // 257 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 258 // CHECK2-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 259 // CHECK2-NEXT: entry: 260 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 261 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 262 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 263 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 264 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 265 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 266 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 267 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 268 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 269 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 270 // CHECK2-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 271 // CHECK2-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 272 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 273 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 274 // CHECK2-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 275 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 276 // CHECK2-NEXT: store i8* null, i8** [[TMP4]], align 8 277 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 278 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 279 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 280 // CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 281 // CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 282 // CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 283 // CHECK2: omp_offload.failed: 284 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR3:[0-9]+]] 285 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 286 // CHECK2: omp_offload.cont: 287 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 288 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 289 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 290 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 291 // CHECK2-NEXT: ret i32 [[TMP9]] 292 // 293 // 294 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 295 // CHECK2-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 296 // CHECK2-NEXT: entry: 297 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 298 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 299 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 300 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 301 // CHECK2-NEXT: ret void 302 // 303 // 304 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 305 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { 306 // CHECK2-NEXT: entry: 307 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 308 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 309 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 310 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 311 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 312 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 313 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 314 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 315 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 316 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 317 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 318 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 319 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 320 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 321 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 322 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 323 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 324 // CHECK2-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 325 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 326 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 327 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 328 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 329 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 330 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 331 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 332 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 333 // CHECK2: cond.true: 334 // CHECK2-NEXT: br label [[COND_END:%.*]] 335 // CHECK2: cond.false: 336 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 337 // CHECK2-NEXT: br label [[COND_END]] 338 // CHECK2: cond.end: 339 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 340 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 341 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 342 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 343 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 344 // CHECK2: omp.inner.for.cond: 345 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 346 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 347 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 348 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 349 // CHECK2: omp.inner.for.body: 350 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 351 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 352 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 353 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 354 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 355 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 356 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 357 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 358 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 359 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 360 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 361 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 362 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 363 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 364 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 365 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 366 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 367 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 368 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 369 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 370 // CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 371 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 372 // CHECK2: omp.body.continue: 373 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 374 // CHECK2: omp.inner.for.inc: 375 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 376 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 377 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 378 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 379 // CHECK2: omp.inner.for.end: 380 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 381 // CHECK2: omp.loop.exit: 382 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 383 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 384 // CHECK2-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 385 // CHECK2-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 386 // CHECK2: .omp.final.then: 387 // CHECK2-NEXT: store i32 123, i32* [[I]], align 4 388 // CHECK2-NEXT: store i32 456, i32* [[J]], align 4 389 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]] 390 // CHECK2: .omp.final.done: 391 // CHECK2-NEXT: ret void 392 // 393 // 394 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 395 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { 396 // CHECK2-NEXT: entry: 397 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 398 // CHECK2-NEXT: ret void 399 // 400 // 401 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv 402 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 403 // CHECK3-NEXT: entry: 404 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 405 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 406 // CHECK3-NEXT: ret i32 [[CALL]] 407 // 408 // 409 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 410 // CHECK3-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 411 // CHECK3-NEXT: entry: 412 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 413 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 414 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 415 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 416 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 417 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 418 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 419 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 420 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 421 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 422 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 423 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 424 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 425 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 426 // CHECK3-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 427 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 428 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4 429 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 430 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 431 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 432 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 433 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 434 // CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 435 // CHECK3: omp_offload.failed: 436 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR3:[0-9]+]] 437 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 438 // CHECK3: omp_offload.cont: 439 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 440 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 441 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 442 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 443 // CHECK3-NEXT: ret i32 [[TMP9]] 444 // 445 // 446 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 447 // CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 448 // CHECK3-NEXT: entry: 449 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 450 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 451 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 452 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 453 // CHECK3-NEXT: ret void 454 // 455 // 456 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 457 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { 458 // CHECK3-NEXT: entry: 459 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 460 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 461 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 462 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 463 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 464 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 465 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 466 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 467 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 468 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 469 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 470 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 471 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 472 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 473 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 474 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 475 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 476 // CHECK3-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 477 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 478 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 479 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 480 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 481 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 482 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 483 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 484 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 485 // CHECK3: cond.true: 486 // CHECK3-NEXT: br label [[COND_END:%.*]] 487 // CHECK3: cond.false: 488 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 489 // CHECK3-NEXT: br label [[COND_END]] 490 // CHECK3: cond.end: 491 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 492 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 493 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 494 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 495 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 496 // CHECK3: omp.inner.for.cond: 497 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 498 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 499 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 500 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 501 // CHECK3: omp.inner.for.body: 502 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 503 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 504 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 505 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 506 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 507 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 508 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 509 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 510 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 511 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 512 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 513 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 514 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 515 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 516 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 517 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 518 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 519 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 520 // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 521 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 522 // CHECK3: omp.body.continue: 523 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 524 // CHECK3: omp.inner.for.inc: 525 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 526 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 527 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 528 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 529 // CHECK3: omp.inner.for.end: 530 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 531 // CHECK3: omp.loop.exit: 532 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 533 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 534 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 535 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 536 // CHECK3: .omp.final.then: 537 // CHECK3-NEXT: store i32 123, i32* [[I]], align 4 538 // CHECK3-NEXT: store i32 456, i32* [[J]], align 4 539 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 540 // CHECK3: .omp.final.done: 541 // CHECK3-NEXT: ret void 542 // 543 // 544 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 545 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 546 // CHECK3-NEXT: entry: 547 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 548 // CHECK3-NEXT: ret void 549 // 550 // 551 // CHECK4-LABEL: define {{[^@]+}}@_Z21teams_template_structv 552 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 553 // CHECK4-NEXT: entry: 554 // CHECK4-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 555 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 556 // CHECK4-NEXT: ret i32 [[CALL]] 557 // 558 // 559 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 560 // CHECK4-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 561 // CHECK4-NEXT: entry: 562 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 563 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 564 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 565 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 566 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 567 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 568 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 569 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 570 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 571 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 572 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 573 // CHECK4-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 574 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 575 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 576 // CHECK4-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 577 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 578 // CHECK4-NEXT: store i8* null, i8** [[TMP4]], align 4 579 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 580 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 581 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 582 // CHECK4-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 583 // CHECK4-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 584 // CHECK4-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 585 // CHECK4: omp_offload.failed: 586 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR3:[0-9]+]] 587 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 588 // CHECK4: omp_offload.cont: 589 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 590 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 591 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 592 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 593 // CHECK4-NEXT: ret i32 [[TMP9]] 594 // 595 // 596 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 597 // CHECK4-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 598 // CHECK4-NEXT: entry: 599 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 600 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 601 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 602 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 603 // CHECK4-NEXT: ret void 604 // 605 // 606 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 607 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { 608 // CHECK4-NEXT: entry: 609 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 610 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 611 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 612 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 613 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 614 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 615 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 616 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 617 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 618 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 619 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 620 // CHECK4-NEXT: [[J:%.*]] = alloca i32, align 4 621 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 622 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 623 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 624 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 625 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 626 // CHECK4-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 627 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 628 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 629 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 630 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 631 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 632 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 633 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 634 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 635 // CHECK4: cond.true: 636 // CHECK4-NEXT: br label [[COND_END:%.*]] 637 // CHECK4: cond.false: 638 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 639 // CHECK4-NEXT: br label [[COND_END]] 640 // CHECK4: cond.end: 641 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 642 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 643 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 644 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 645 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 646 // CHECK4: omp.inner.for.cond: 647 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 648 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 649 // CHECK4-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 650 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 651 // CHECK4: omp.inner.for.body: 652 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 653 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 654 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 655 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 656 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 657 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 658 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 659 // CHECK4-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 660 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 661 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 662 // CHECK4-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 663 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 664 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 665 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 666 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 667 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 668 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 669 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 670 // CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 671 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 672 // CHECK4: omp.body.continue: 673 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 674 // CHECK4: omp.inner.for.inc: 675 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 676 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 677 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 678 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 679 // CHECK4: omp.inner.for.end: 680 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 681 // CHECK4: omp.loop.exit: 682 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 683 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 684 // CHECK4-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 685 // CHECK4-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 686 // CHECK4: .omp.final.then: 687 // CHECK4-NEXT: store i32 123, i32* [[I]], align 4 688 // CHECK4-NEXT: store i32 456, i32* [[J]], align 4 689 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]] 690 // CHECK4: .omp.final.done: 691 // CHECK4-NEXT: ret void 692 // 693 // 694 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 695 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] { 696 // CHECK4-NEXT: entry: 697 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 698 // CHECK4-NEXT: ret void 699 // 700 // 701 // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv 702 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 703 // CHECK5-NEXT: entry: 704 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 705 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 706 // CHECK5-NEXT: ret i32 [[CALL]] 707 // 708 // 709 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 710 // CHECK5-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 711 // CHECK5-NEXT: entry: 712 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 713 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 714 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 715 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 716 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 717 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 718 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 719 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 720 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 721 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 722 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 723 // CHECK5-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 724 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 725 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 726 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 727 // CHECK5: omp.inner.for.cond: 728 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 729 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 730 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 731 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 732 // CHECK5: omp.inner.for.body: 733 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 734 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 735 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 736 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 737 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 738 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 739 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 740 // CHECK5-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 741 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 742 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 743 // CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 744 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 745 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !2 746 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 747 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 748 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 749 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 750 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !2 751 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 752 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 753 // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !2 754 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 755 // CHECK5: omp.body.continue: 756 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 757 // CHECK5: omp.inner.for.inc: 758 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 759 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 760 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 761 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 762 // CHECK5: omp.inner.for.end: 763 // CHECK5-NEXT: store i32 123, i32* [[I]], align 4 764 // CHECK5-NEXT: store i32 456, i32* [[J]], align 4 765 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 766 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 767 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 768 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 769 // CHECK5-NEXT: ret i32 [[TMP9]] 770 // 771 // 772 // CHECK6-LABEL: define {{[^@]+}}@_Z21teams_template_structv 773 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 774 // CHECK6-NEXT: entry: 775 // CHECK6-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 776 // CHECK6-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 777 // CHECK6-NEXT: ret i32 [[CALL]] 778 // 779 // 780 // CHECK6-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 781 // CHECK6-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 782 // CHECK6-NEXT: entry: 783 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 784 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 785 // CHECK6-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 786 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 787 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 788 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 789 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 790 // CHECK6-NEXT: [[J:%.*]] = alloca i32, align 4 791 // CHECK6-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 792 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 793 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 794 // CHECK6-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 795 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 796 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 797 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 798 // CHECK6: omp.inner.for.cond: 799 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 800 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 801 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 802 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 803 // CHECK6: omp.inner.for.body: 804 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 805 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 806 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 807 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 808 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 809 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 810 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 811 // CHECK6-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 812 // CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 813 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 814 // CHECK6-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 815 // CHECK6-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 816 // CHECK6-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !2 817 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 818 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 819 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 820 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 821 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !2 822 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 823 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 824 // CHECK6-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !2 825 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 826 // CHECK6: omp.body.continue: 827 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 828 // CHECK6: omp.inner.for.inc: 829 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 830 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 831 // CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 832 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 833 // CHECK6: omp.inner.for.end: 834 // CHECK6-NEXT: store i32 123, i32* [[I]], align 4 835 // CHECK6-NEXT: store i32 456, i32* [[J]], align 4 836 // CHECK6-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 837 // CHECK6-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 838 // CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 839 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 840 // CHECK6-NEXT: ret i32 [[TMP9]] 841 // 842 // 843 // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv 844 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 845 // CHECK7-NEXT: entry: 846 // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 847 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 848 // CHECK7-NEXT: ret i32 [[CALL]] 849 // 850 // 851 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 852 // CHECK7-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 853 // CHECK7-NEXT: entry: 854 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 855 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 856 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 857 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 858 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 859 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 860 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 861 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 862 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 863 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 864 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 865 // CHECK7-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 866 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 867 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 868 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 869 // CHECK7: omp.inner.for.cond: 870 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 871 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 872 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 873 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 874 // CHECK7: omp.inner.for.body: 875 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 876 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 877 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 878 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 879 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 880 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 881 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 882 // CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 883 // CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 884 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 885 // CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 886 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 887 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !3 888 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 889 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 890 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP6]] 891 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !3 892 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 893 // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !3 894 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 895 // CHECK7: omp.body.continue: 896 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 897 // CHECK7: omp.inner.for.inc: 898 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 899 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 900 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 901 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 902 // CHECK7: omp.inner.for.end: 903 // CHECK7-NEXT: store i32 123, i32* [[I]], align 4 904 // CHECK7-NEXT: store i32 456, i32* [[J]], align 4 905 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 906 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 907 // CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 908 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 909 // CHECK7-NEXT: ret i32 [[TMP9]] 910 // 911 // 912 // CHECK8-LABEL: define {{[^@]+}}@_Z21teams_template_structv 913 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 914 // CHECK8-NEXT: entry: 915 // CHECK8-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 916 // CHECK8-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 917 // CHECK8-NEXT: ret i32 [[CALL]] 918 // 919 // 920 // CHECK8-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 921 // CHECK8-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 922 // CHECK8-NEXT: entry: 923 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 924 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4 925 // CHECK8-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 926 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 927 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 928 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 929 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 930 // CHECK8-NEXT: [[J:%.*]] = alloca i32, align 4 931 // CHECK8-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 932 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 933 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 934 // CHECK8-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 935 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 936 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 937 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 938 // CHECK8: omp.inner.for.cond: 939 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 940 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 941 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 942 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 943 // CHECK8: omp.inner.for.body: 944 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 945 // CHECK8-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 946 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 947 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 948 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 949 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 950 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 951 // CHECK8-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 952 // CHECK8-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 953 // CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 954 // CHECK8-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 955 // CHECK8-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 956 // CHECK8-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !3 957 // CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 958 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 959 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP6]] 960 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !3 961 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 962 // CHECK8-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !3 963 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 964 // CHECK8: omp.body.continue: 965 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 966 // CHECK8: omp.inner.for.inc: 967 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 968 // CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 969 // CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 970 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 971 // CHECK8: omp.inner.for.end: 972 // CHECK8-NEXT: store i32 123, i32* [[I]], align 4 973 // CHECK8-NEXT: store i32 456, i32* [[J]], align 4 974 // CHECK8-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 975 // CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 976 // CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 977 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 978 // CHECK8-NEXT: ret i32 [[TMP9]] 979 // 980 // 981 // CHECK9-LABEL: define {{[^@]+}}@main 982 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 983 // CHECK9-NEXT: entry: 984 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 985 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 986 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 987 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 988 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 989 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 990 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 991 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 992 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 993 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 994 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 995 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 996 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 997 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 998 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 999 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1000 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1001 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 1002 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 1003 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 1004 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1005 // CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 1006 // CHECK9-NEXT: store i32 100, i32* [[N]], align 4 1007 // CHECK9-NEXT: store i32 2, i32* [[M]], align 4 1008 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1009 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1010 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 1011 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1012 // CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 1013 // CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 1014 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1015 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 1016 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1017 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 1018 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 1019 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1020 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 1021 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 1022 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 1023 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 1024 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 1025 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 1026 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1027 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 1028 // CHECK9-NEXT: [[TMP12:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1029 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP12]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes to i8*), i64 40, i1 false) 1030 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1031 // CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 1032 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP14]], align 8 1033 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1034 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 1035 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP16]], align 8 1036 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1037 // CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 1038 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1039 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1040 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 1041 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1042 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 1043 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 1044 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1045 // CHECK9-NEXT: store i8* null, i8** [[TMP22]], align 8 1046 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1047 // CHECK9-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1048 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8 1049 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1050 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 1051 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP26]], align 8 1052 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1053 // CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 1054 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1055 // CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1056 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8 1057 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1058 // CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 1059 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 1060 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1061 // CHECK9-NEXT: store i8* null, i8** [[TMP32]], align 8 1062 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1063 // CHECK9-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32** 1064 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP34]], align 8 1065 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1066 // CHECK9-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 1067 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 8 1068 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1069 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP37]], align 8 1070 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1071 // CHECK9-NEXT: store i8* null, i8** [[TMP38]], align 8 1072 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1073 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1074 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1075 // CHECK9-NEXT: [[TMP42:%.*]] = load i32, i32* [[N]], align 4 1076 // CHECK9-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 1077 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 1078 // CHECK9-NEXT: store i32 [[TMP43]], i32* [[DOTCAPTURE_EXPR_3]], align 4 1079 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1080 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP44]], 0 1081 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1082 // CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 1083 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 1084 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP45]], 0 1085 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1086 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1087 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 1088 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1089 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 1090 // CHECK9-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 1091 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP46]], 1 1092 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1093 // CHECK9-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP39]], i8** [[TMP40]], i64* [[TMP41]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1094 // CHECK9-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 1095 // CHECK9-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1096 // CHECK9: omp_offload.failed: 1097 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR4:[0-9]+]] 1098 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1099 // CHECK9: omp_offload.cont: 1100 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1101 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP49]]) 1102 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1103 // CHECK9-NEXT: [[TMP50:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1104 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP50]]) 1105 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, i32* [[RETVAL]], align 4 1106 // CHECK9-NEXT: ret i32 [[TMP51]] 1107 // 1108 // 1109 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 1110 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1111 // CHECK9-NEXT: entry: 1112 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1113 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1114 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1115 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1116 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1117 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1118 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 1119 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1120 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1121 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1122 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1123 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1124 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1125 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1126 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1127 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1128 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1129 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 1130 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1131 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 1132 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 1133 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4 1134 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* 1135 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 1136 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 1137 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 1138 // CHECK9-NEXT: ret void 1139 // 1140 // 1141 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 1142 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { 1143 // CHECK9-NEXT: entry: 1144 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1145 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1146 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1147 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1148 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1149 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1150 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1151 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1152 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1153 // CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 1154 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1155 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 1156 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 1157 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1158 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1159 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1160 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1161 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1162 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1163 // CHECK9-NEXT: [[I13:%.*]] = alloca i32, align 4 1164 // CHECK9-NEXT: [[J14:%.*]] = alloca i32, align 4 1165 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1166 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1167 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1168 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1169 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1170 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1171 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1172 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1173 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1174 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1175 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1176 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1177 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 1178 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 1179 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4 1180 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 1181 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1182 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 1183 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1184 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 1185 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1186 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 1187 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 1188 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 1189 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] 1190 // CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 1191 // CHECK9-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 1192 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4 1193 // CHECK9-NEXT: store i32 0, i32* [[J]], align 4 1194 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1195 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 1196 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1197 // CHECK9: land.lhs.true: 1198 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1199 // CHECK9-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] 1200 // CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1201 // CHECK9: omp.precond.then: 1202 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1203 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 1204 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 1205 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1206 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1207 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1208 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 1209 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1210 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1211 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 1212 // CHECK9-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 1213 // CHECK9-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1214 // CHECK9: cond.true: 1215 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 1216 // CHECK9-NEXT: br label [[COND_END:%.*]] 1217 // CHECK9: cond.false: 1218 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1219 // CHECK9-NEXT: br label [[COND_END]] 1220 // CHECK9: cond.end: 1221 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 1222 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1223 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1224 // CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 1225 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1226 // CHECK9: omp.inner.for.cond: 1227 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1228 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 1229 // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 1230 // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1231 // CHECK9: omp.inner.for.body: 1232 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1233 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 1234 // CHECK9-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 1235 // CHECK9-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 1236 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] 1237 // CHECK9-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 1238 // CHECK9-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] 1239 // CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 1240 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] 1241 // CHECK9-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 1242 // CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !5 1243 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1244 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1245 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 1246 // CHECK9-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 1247 // CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 1248 // CHECK9-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 1249 // CHECK9-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 1250 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] 1251 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 1252 // CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 1253 // CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 1254 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] 1255 // CHECK9-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 1256 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] 1257 // CHECK9-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] 1258 // CHECK9-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 1259 // CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] 1260 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 1261 // CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !5 1262 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !5 1263 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 1264 // CHECK9-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] 1265 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] 1266 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !5 1267 // CHECK9-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 1268 // CHECK9-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] 1269 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4, !llvm.access.group !5 1270 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1271 // CHECK9: omp.body.continue: 1272 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1273 // CHECK9: omp.inner.for.inc: 1274 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1275 // CHECK9-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 1276 // CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1277 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 1278 // CHECK9: omp.inner.for.end: 1279 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1280 // CHECK9: omp.loop.exit: 1281 // CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1282 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 1283 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 1284 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1285 // CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1286 // CHECK9-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1287 // CHECK9: .omp.final.then: 1288 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1289 // CHECK9-NEXT: [[SUB41:%.*]] = sub nsw i32 [[TMP33]], 0 1290 // CHECK9-NEXT: [[DIV42:%.*]] = sdiv i32 [[SUB41]], 1 1291 // CHECK9-NEXT: [[MUL43:%.*]] = mul nsw i32 [[DIV42]], 1 1292 // CHECK9-NEXT: [[ADD44:%.*]] = add nsw i32 0, [[MUL43]] 1293 // CHECK9-NEXT: store i32 [[ADD44]], i32* [[I13]], align 4 1294 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1295 // CHECK9-NEXT: [[SUB45:%.*]] = sub nsw i32 [[TMP34]], 0 1296 // CHECK9-NEXT: [[DIV46:%.*]] = sdiv i32 [[SUB45]], 1 1297 // CHECK9-NEXT: [[MUL47:%.*]] = mul nsw i32 [[DIV46]], 1 1298 // CHECK9-NEXT: [[ADD48:%.*]] = add nsw i32 0, [[MUL47]] 1299 // CHECK9-NEXT: store i32 [[ADD48]], i32* [[J14]], align 4 1300 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1301 // CHECK9: .omp.final.done: 1302 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 1303 // CHECK9: omp.precond.end: 1304 // CHECK9-NEXT: ret void 1305 // 1306 // 1307 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1308 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { 1309 // CHECK9-NEXT: entry: 1310 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1311 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1312 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1313 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1314 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1315 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1316 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1317 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1318 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1319 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1320 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 1321 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1322 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1323 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 1324 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1325 // CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 1326 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1327 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1328 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 1329 // CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1330 // CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1331 // CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1332 // CHECK9: omp_offload.failed: 1333 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR4]] 1334 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 1335 // CHECK9: omp_offload.cont: 1336 // CHECK9-NEXT: ret i32 0 1337 // 1338 // 1339 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 1340 // CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1341 // CHECK9-NEXT: entry: 1342 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1343 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1344 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1345 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1346 // CHECK9-NEXT: ret void 1347 // 1348 // 1349 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 1350 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { 1351 // CHECK9-NEXT: entry: 1352 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1353 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1354 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1355 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1356 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 1357 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1358 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1359 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1360 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1361 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1362 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 1363 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 1364 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1365 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1366 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1367 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1368 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1369 // CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1370 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1371 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1372 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1373 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1374 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1375 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1376 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1377 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1378 // CHECK9: cond.true: 1379 // CHECK9-NEXT: br label [[COND_END:%.*]] 1380 // CHECK9: cond.false: 1381 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1382 // CHECK9-NEXT: br label [[COND_END]] 1383 // CHECK9: cond.end: 1384 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1385 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1386 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1387 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1388 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1389 // CHECK9: omp.inner.for.cond: 1390 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1391 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 1392 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1393 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1394 // CHECK9: omp.inner.for.body: 1395 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1396 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1397 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1398 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1399 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 1400 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1401 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1402 // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1403 // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1404 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1405 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1406 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1407 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 1408 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1409 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1410 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 1411 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 1412 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 1413 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 1414 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 1415 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1416 // CHECK9: omp.body.continue: 1417 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1418 // CHECK9: omp.inner.for.inc: 1419 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1420 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 1421 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1422 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1423 // CHECK9: omp.inner.for.end: 1424 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1425 // CHECK9: omp.loop.exit: 1426 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1427 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1428 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1429 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1430 // CHECK9: .omp.final.then: 1431 // CHECK9-NEXT: store i32 10, i32* [[I]], align 4 1432 // CHECK9-NEXT: store i32 2, i32* [[J]], align 4 1433 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1434 // CHECK9: .omp.final.done: 1435 // CHECK9-NEXT: ret void 1436 // 1437 // 1438 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1439 // CHECK9-SAME: () #[[ATTR7:[0-9]+]] { 1440 // CHECK9-NEXT: entry: 1441 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1442 // CHECK9-NEXT: ret void 1443 // 1444 // 1445 // CHECK10-LABEL: define {{[^@]+}}@main 1446 // CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1447 // CHECK10-NEXT: entry: 1448 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1449 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1450 // CHECK10-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 1451 // CHECK10-NEXT: [[N:%.*]] = alloca i32, align 4 1452 // CHECK10-NEXT: [[M:%.*]] = alloca i32, align 4 1453 // CHECK10-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1454 // CHECK10-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1455 // CHECK10-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1456 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1457 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 1458 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1459 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1460 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1461 // CHECK10-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1462 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1463 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 1464 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1465 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 1466 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 1467 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1468 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1469 // CHECK10-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 1470 // CHECK10-NEXT: store i32 100, i32* [[N]], align 4 1471 // CHECK10-NEXT: store i32 2, i32* [[M]], align 4 1472 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1473 // CHECK10-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1474 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 1475 // CHECK10-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1476 // CHECK10-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 1477 // CHECK10-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 1478 // CHECK10-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1479 // CHECK10-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 1480 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1481 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 1482 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 1483 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1484 // CHECK10-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 1485 // CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 1486 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 1487 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 1488 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 1489 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 1490 // CHECK10-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1491 // CHECK10-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 1492 // CHECK10-NEXT: [[TMP12:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1493 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP12]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes to i8*), i64 40, i1 false) 1494 // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1495 // CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 1496 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP14]], align 8 1497 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1498 // CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 1499 // CHECK10-NEXT: store i64 [[TMP7]], i64* [[TMP16]], align 8 1500 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1501 // CHECK10-NEXT: store i8* null, i8** [[TMP17]], align 8 1502 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1503 // CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1504 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 1505 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1506 // CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 1507 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 1508 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1509 // CHECK10-NEXT: store i8* null, i8** [[TMP22]], align 8 1510 // CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1511 // CHECK10-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1512 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8 1513 // CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1514 // CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 1515 // CHECK10-NEXT: store i64 [[TMP1]], i64* [[TMP26]], align 8 1516 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1517 // CHECK10-NEXT: store i8* null, i8** [[TMP27]], align 8 1518 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1519 // CHECK10-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1520 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8 1521 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1522 // CHECK10-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 1523 // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 1524 // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1525 // CHECK10-NEXT: store i8* null, i8** [[TMP32]], align 8 1526 // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1527 // CHECK10-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32** 1528 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP34]], align 8 1529 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1530 // CHECK10-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 1531 // CHECK10-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 8 1532 // CHECK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1533 // CHECK10-NEXT: store i64 [[TMP11]], i64* [[TMP37]], align 8 1534 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1535 // CHECK10-NEXT: store i8* null, i8** [[TMP38]], align 8 1536 // CHECK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1537 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1538 // CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1539 // CHECK10-NEXT: [[TMP42:%.*]] = load i32, i32* [[N]], align 4 1540 // CHECK10-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 1541 // CHECK10-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 1542 // CHECK10-NEXT: store i32 [[TMP43]], i32* [[DOTCAPTURE_EXPR_3]], align 4 1543 // CHECK10-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1544 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP44]], 0 1545 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1546 // CHECK10-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 1547 // CHECK10-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 1548 // CHECK10-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP45]], 0 1549 // CHECK10-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1550 // CHECK10-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1551 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 1552 // CHECK10-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1553 // CHECK10-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 1554 // CHECK10-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 1555 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP46]], 1 1556 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1557 // CHECK10-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP39]], i8** [[TMP40]], i64* [[TMP41]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1558 // CHECK10-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 1559 // CHECK10-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1560 // CHECK10: omp_offload.failed: 1561 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR4:[0-9]+]] 1562 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1563 // CHECK10: omp_offload.cont: 1564 // CHECK10-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1565 // CHECK10-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP49]]) 1566 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1567 // CHECK10-NEXT: [[TMP50:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1568 // CHECK10-NEXT: call void @llvm.stackrestore(i8* [[TMP50]]) 1569 // CHECK10-NEXT: [[TMP51:%.*]] = load i32, i32* [[RETVAL]], align 4 1570 // CHECK10-NEXT: ret i32 [[TMP51]] 1571 // 1572 // 1573 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 1574 // CHECK10-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1575 // CHECK10-NEXT: entry: 1576 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1577 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1578 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1579 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1580 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1581 // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1582 // CHECK10-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 1583 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1584 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1585 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1586 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1587 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1588 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1589 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1590 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1591 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1592 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1593 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 1594 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1595 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 1596 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 1597 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4 1598 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* 1599 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 1600 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 1601 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 1602 // CHECK10-NEXT: ret void 1603 // 1604 // 1605 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 1606 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { 1607 // CHECK10-NEXT: entry: 1608 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1609 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1610 // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1611 // CHECK10-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 1612 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1613 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1614 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 1615 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1616 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1617 // CHECK10-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 1618 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1619 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 1620 // CHECK10-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 1621 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1622 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 1623 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1624 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1625 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1626 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1627 // CHECK10-NEXT: [[I13:%.*]] = alloca i32, align 4 1628 // CHECK10-NEXT: [[J14:%.*]] = alloca i32, align 4 1629 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1630 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1631 // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1632 // CHECK10-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 1633 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1634 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1635 // CHECK10-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 1636 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1637 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 1638 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1639 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1640 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 1641 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 1642 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 1643 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4 1644 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 1645 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1646 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 1647 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1648 // CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 1649 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1650 // CHECK10-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 1651 // CHECK10-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 1652 // CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 1653 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] 1654 // CHECK10-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 1655 // CHECK10-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 1656 // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 1657 // CHECK10-NEXT: store i32 0, i32* [[J]], align 4 1658 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1659 // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 1660 // CHECK10-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1661 // CHECK10: land.lhs.true: 1662 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1663 // CHECK10-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] 1664 // CHECK10-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1665 // CHECK10: omp.precond.then: 1666 // CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1667 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 1668 // CHECK10-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 1669 // CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1670 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1671 // CHECK10-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1672 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 1673 // CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1674 // CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1675 // CHECK10-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 1676 // CHECK10-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 1677 // CHECK10-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1678 // CHECK10: cond.true: 1679 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 1680 // CHECK10-NEXT: br label [[COND_END:%.*]] 1681 // CHECK10: cond.false: 1682 // CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1683 // CHECK10-NEXT: br label [[COND_END]] 1684 // CHECK10: cond.end: 1685 // CHECK10-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 1686 // CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1687 // CHECK10-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1688 // CHECK10-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 1689 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1690 // CHECK10: omp.inner.for.cond: 1691 // CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1692 // CHECK10-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 1693 // CHECK10-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 1694 // CHECK10-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1695 // CHECK10: omp.inner.for.body: 1696 // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1697 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 1698 // CHECK10-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 1699 // CHECK10-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 1700 // CHECK10-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] 1701 // CHECK10-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 1702 // CHECK10-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] 1703 // CHECK10-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 1704 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] 1705 // CHECK10-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 1706 // CHECK10-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !5 1707 // CHECK10-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1708 // CHECK10-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1709 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 1710 // CHECK10-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 1711 // CHECK10-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 1712 // CHECK10-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 1713 // CHECK10-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 1714 // CHECK10-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] 1715 // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 1716 // CHECK10-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 1717 // CHECK10-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 1718 // CHECK10-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] 1719 // CHECK10-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 1720 // CHECK10-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] 1721 // CHECK10-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] 1722 // CHECK10-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 1723 // CHECK10-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] 1724 // CHECK10-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 1725 // CHECK10-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !5 1726 // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !5 1727 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 1728 // CHECK10-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] 1729 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] 1730 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !5 1731 // CHECK10-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 1732 // CHECK10-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] 1733 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4, !llvm.access.group !5 1734 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1735 // CHECK10: omp.body.continue: 1736 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1737 // CHECK10: omp.inner.for.inc: 1738 // CHECK10-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1739 // CHECK10-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 1740 // CHECK10-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1741 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 1742 // CHECK10: omp.inner.for.end: 1743 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1744 // CHECK10: omp.loop.exit: 1745 // CHECK10-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1746 // CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 1747 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 1748 // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1749 // CHECK10-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1750 // CHECK10-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1751 // CHECK10: .omp.final.then: 1752 // CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1753 // CHECK10-NEXT: [[SUB41:%.*]] = sub nsw i32 [[TMP33]], 0 1754 // CHECK10-NEXT: [[DIV42:%.*]] = sdiv i32 [[SUB41]], 1 1755 // CHECK10-NEXT: [[MUL43:%.*]] = mul nsw i32 [[DIV42]], 1 1756 // CHECK10-NEXT: [[ADD44:%.*]] = add nsw i32 0, [[MUL43]] 1757 // CHECK10-NEXT: store i32 [[ADD44]], i32* [[I13]], align 4 1758 // CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 1759 // CHECK10-NEXT: [[SUB45:%.*]] = sub nsw i32 [[TMP34]], 0 1760 // CHECK10-NEXT: [[DIV46:%.*]] = sdiv i32 [[SUB45]], 1 1761 // CHECK10-NEXT: [[MUL47:%.*]] = mul nsw i32 [[DIV46]], 1 1762 // CHECK10-NEXT: [[ADD48:%.*]] = add nsw i32 0, [[MUL47]] 1763 // CHECK10-NEXT: store i32 [[ADD48]], i32* [[J14]], align 4 1764 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] 1765 // CHECK10: .omp.final.done: 1766 // CHECK10-NEXT: br label [[OMP_PRECOND_END]] 1767 // CHECK10: omp.precond.end: 1768 // CHECK10-NEXT: ret void 1769 // 1770 // 1771 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1772 // CHECK10-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { 1773 // CHECK10-NEXT: entry: 1774 // CHECK10-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1775 // CHECK10-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1776 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1777 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1778 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1779 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1780 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1781 // CHECK10-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1782 // CHECK10-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1783 // CHECK10-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1784 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 1785 // CHECK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1786 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1787 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 1788 // CHECK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1789 // CHECK10-NEXT: store i8* null, i8** [[TMP4]], align 8 1790 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1791 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1792 // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 1793 // CHECK10-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1794 // CHECK10-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1795 // CHECK10-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1796 // CHECK10: omp_offload.failed: 1797 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR4]] 1798 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1799 // CHECK10: omp_offload.cont: 1800 // CHECK10-NEXT: ret i32 0 1801 // 1802 // 1803 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 1804 // CHECK10-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1805 // CHECK10-NEXT: entry: 1806 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1807 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1808 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1809 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1810 // CHECK10-NEXT: ret void 1811 // 1812 // 1813 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 1814 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { 1815 // CHECK10-NEXT: entry: 1816 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1817 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1818 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 1819 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1820 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 1821 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1822 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1823 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1824 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1825 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1826 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 1827 // CHECK10-NEXT: [[J:%.*]] = alloca i32, align 4 1828 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1829 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1830 // CHECK10-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 1831 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 1832 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1833 // CHECK10-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1834 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1835 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1836 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1837 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1838 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1839 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1840 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1841 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1842 // CHECK10: cond.true: 1843 // CHECK10-NEXT: br label [[COND_END:%.*]] 1844 // CHECK10: cond.false: 1845 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1846 // CHECK10-NEXT: br label [[COND_END]] 1847 // CHECK10: cond.end: 1848 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1849 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1850 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1851 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1852 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1853 // CHECK10: omp.inner.for.cond: 1854 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1855 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 1856 // CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1857 // CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1858 // CHECK10: omp.inner.for.body: 1859 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1860 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1861 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1862 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1863 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 1864 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1865 // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1866 // CHECK10-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1867 // CHECK10-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1868 // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1869 // CHECK10-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1870 // CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1871 // CHECK10-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 1872 // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1873 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1874 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 1875 // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 1876 // CHECK10-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 1877 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 1878 // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 1879 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1880 // CHECK10: omp.body.continue: 1881 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1882 // CHECK10: omp.inner.for.inc: 1883 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1884 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 1885 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1886 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1887 // CHECK10: omp.inner.for.end: 1888 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1889 // CHECK10: omp.loop.exit: 1890 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1891 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1892 // CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1893 // CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1894 // CHECK10: .omp.final.then: 1895 // CHECK10-NEXT: store i32 10, i32* [[I]], align 4 1896 // CHECK10-NEXT: store i32 2, i32* [[J]], align 4 1897 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] 1898 // CHECK10: .omp.final.done: 1899 // CHECK10-NEXT: ret void 1900 // 1901 // 1902 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1903 // CHECK10-SAME: () #[[ATTR7:[0-9]+]] { 1904 // CHECK10-NEXT: entry: 1905 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 1906 // CHECK10-NEXT: ret void 1907 // 1908 // 1909 // CHECK11-LABEL: define {{[^@]+}}@main 1910 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1911 // CHECK11-NEXT: entry: 1912 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1913 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1914 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 1915 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 1916 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 1917 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1918 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1919 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1920 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1921 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1922 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1923 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1924 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1925 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 1926 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1927 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1928 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1929 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1930 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1931 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1932 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1933 // CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 1934 // CHECK11-NEXT: store i32 100, i32* [[N]], align 4 1935 // CHECK11-NEXT: store i32 2, i32* [[M]], align 4 1936 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1937 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 1938 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1939 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1940 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1941 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 1942 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 1943 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 1944 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 1945 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 1946 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 1947 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 1948 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 1949 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 1950 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1951 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 1952 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 1953 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1954 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes to i8*), i32 40, i1 false) 1955 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1956 // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 1957 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP13]], align 4 1958 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1959 // CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1960 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP15]], align 4 1961 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1962 // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 1963 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1964 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 1965 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 1966 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1967 // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1968 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 1969 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1970 // CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 1971 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1972 // CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 1973 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP23]], align 4 1974 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1975 // CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1976 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP25]], align 4 1977 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1978 // CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 1979 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1980 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1981 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 1982 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1983 // CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1984 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 1985 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1986 // CHECK11-NEXT: store i8* null, i8** [[TMP31]], align 4 1987 // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1988 // CHECK11-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32** 1989 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP33]], align 4 1990 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1991 // CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32** 1992 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP35]], align 4 1993 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1994 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP36]], align 4 1995 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1996 // CHECK11-NEXT: store i8* null, i8** [[TMP37]], align 4 1997 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1998 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1999 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2000 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[N]], align 4 2001 // CHECK11-NEXT: store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR_]], align 4 2002 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, i32* [[M]], align 4 2003 // CHECK11-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2004 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2005 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP43]], 0 2006 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2007 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2008 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2009 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP44]], 0 2010 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 2011 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 2012 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 2013 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 2014 // CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 2015 // CHECK11-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 2016 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP45]], 1 2017 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 2018 // CHECK11-NEXT: [[TMP46:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP38]], i8** [[TMP39]], i64* [[TMP40]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2019 // CHECK11-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 2020 // CHECK11-NEXT: br i1 [[TMP47]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2021 // CHECK11: omp_offload.failed: 2022 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR4:[0-9]+]] 2023 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2024 // CHECK11: omp_offload.cont: 2025 // CHECK11-NEXT: [[TMP48:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2026 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP48]]) 2027 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2028 // CHECK11-NEXT: [[TMP49:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2029 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP49]]) 2030 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, i32* [[RETVAL]], align 4 2031 // CHECK11-NEXT: ret i32 [[TMP50]] 2032 // 2033 // 2034 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 2035 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 2036 // CHECK11-NEXT: entry: 2037 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2038 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 2039 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2040 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2041 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2042 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2043 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 2044 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2045 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 2046 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2047 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2048 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2049 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2050 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2051 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2052 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2053 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 2054 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 2055 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 2056 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 2057 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 2058 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 2059 // CHECK11-NEXT: ret void 2060 // 2061 // 2062 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 2063 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { 2064 // CHECK11-NEXT: entry: 2065 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2066 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2067 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2068 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 2069 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2070 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2071 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2072 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2073 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 2074 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2075 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2076 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 2077 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 2078 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 2079 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 2080 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2081 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2082 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2083 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2084 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 2085 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 2086 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2087 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2088 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2089 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 2090 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2091 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2092 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2093 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2094 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2095 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2096 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2097 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 2098 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 2099 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 2100 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2101 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 2102 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2103 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2104 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2105 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 2106 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 2107 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 2108 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 2109 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 2110 // CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 2111 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 2112 // CHECK11-NEXT: store i32 0, i32* [[J]], align 4 2113 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2114 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 2115 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 2116 // CHECK11: land.lhs.true: 2117 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2118 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] 2119 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 2120 // CHECK11: omp.precond.then: 2121 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2122 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2123 // CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 2124 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2125 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2126 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2127 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 2128 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2129 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2130 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2131 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 2132 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2133 // CHECK11: cond.true: 2134 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2135 // CHECK11-NEXT: br label [[COND_END:%.*]] 2136 // CHECK11: cond.false: 2137 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2138 // CHECK11-NEXT: br label [[COND_END]] 2139 // CHECK11: cond.end: 2140 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 2141 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2142 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2143 // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 2144 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2145 // CHECK11: omp.inner.for.cond: 2146 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2147 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 2148 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 2149 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2150 // CHECK11: omp.inner.for.body: 2151 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2152 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2153 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 2154 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 2155 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 2156 // CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 2157 // CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] 2158 // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 2159 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 2160 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 2161 // CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 2162 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2163 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2164 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2165 // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 2166 // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 2167 // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 2168 // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 2169 // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] 2170 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2171 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 2172 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 2173 // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 2174 // CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 2175 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 2176 // CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] 2177 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 2178 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 2179 // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 2180 // CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 2181 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 2182 // CHECK11-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] 2183 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] 2184 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 2185 // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] 2186 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 2187 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2188 // CHECK11: omp.body.continue: 2189 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2190 // CHECK11: omp.inner.for.inc: 2191 // CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2192 // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 2193 // CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2194 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2195 // CHECK11: omp.inner.for.end: 2196 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2197 // CHECK11: omp.loop.exit: 2198 // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2199 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 2200 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 2201 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2202 // CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2203 // CHECK11-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2204 // CHECK11: .omp.final.then: 2205 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2206 // CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i32 [[TMP33]], 0 2207 // CHECK11-NEXT: [[DIV39:%.*]] = sdiv i32 [[SUB38]], 1 2208 // CHECK11-NEXT: [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 1 2209 // CHECK11-NEXT: [[ADD41:%.*]] = add nsw i32 0, [[MUL40]] 2210 // CHECK11-NEXT: store i32 [[ADD41]], i32* [[I11]], align 4 2211 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2212 // CHECK11-NEXT: [[SUB42:%.*]] = sub nsw i32 [[TMP34]], 0 2213 // CHECK11-NEXT: [[DIV43:%.*]] = sdiv i32 [[SUB42]], 1 2214 // CHECK11-NEXT: [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 1 2215 // CHECK11-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 2216 // CHECK11-NEXT: store i32 [[ADD45]], i32* [[J12]], align 4 2217 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 2218 // CHECK11: .omp.final.done: 2219 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 2220 // CHECK11: omp.precond.end: 2221 // CHECK11-NEXT: ret void 2222 // 2223 // 2224 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2225 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { 2226 // CHECK11-NEXT: entry: 2227 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2228 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2229 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2230 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2231 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2232 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 2233 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2234 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2235 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2236 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 2237 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 2238 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2239 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 2240 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 2241 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2242 // CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 2243 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2244 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2245 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 2246 // CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2247 // CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2248 // CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2249 // CHECK11: omp_offload.failed: 2250 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR4]] 2251 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2252 // CHECK11: omp_offload.cont: 2253 // CHECK11-NEXT: ret i32 0 2254 // 2255 // 2256 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 2257 // CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2258 // CHECK11-NEXT: entry: 2259 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2260 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2261 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2262 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 2263 // CHECK11-NEXT: ret void 2264 // 2265 // 2266 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2267 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { 2268 // CHECK11-NEXT: entry: 2269 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2270 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2271 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2272 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2273 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 2274 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2275 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2276 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2277 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2278 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2279 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 2280 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 2281 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2282 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2283 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2284 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2285 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2286 // CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 2287 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2288 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2289 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2290 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2291 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2292 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2293 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 2294 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2295 // CHECK11: cond.true: 2296 // CHECK11-NEXT: br label [[COND_END:%.*]] 2297 // CHECK11: cond.false: 2298 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2299 // CHECK11-NEXT: br label [[COND_END]] 2300 // CHECK11: cond.end: 2301 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2302 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2303 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2304 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2305 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2306 // CHECK11: omp.inner.for.cond: 2307 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2308 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 2309 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2310 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2311 // CHECK11: omp.inner.for.body: 2312 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2313 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 2314 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2315 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2316 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 2317 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2318 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2319 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 2320 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 2321 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 2322 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2323 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 2324 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 2325 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2326 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 2327 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 2328 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 2329 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 2330 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2331 // CHECK11: omp.body.continue: 2332 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2333 // CHECK11: omp.inner.for.inc: 2334 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2335 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 2336 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2337 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 2338 // CHECK11: omp.inner.for.end: 2339 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2340 // CHECK11: omp.loop.exit: 2341 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2342 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2343 // CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2344 // CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2345 // CHECK11: .omp.final.then: 2346 // CHECK11-NEXT: store i32 10, i32* [[I]], align 4 2347 // CHECK11-NEXT: store i32 2, i32* [[J]], align 4 2348 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 2349 // CHECK11: .omp.final.done: 2350 // CHECK11-NEXT: ret void 2351 // 2352 // 2353 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2354 // CHECK11-SAME: () #[[ATTR7:[0-9]+]] { 2355 // CHECK11-NEXT: entry: 2356 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 2357 // CHECK11-NEXT: ret void 2358 // 2359 // 2360 // CHECK12-LABEL: define {{[^@]+}}@main 2361 // CHECK12-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2362 // CHECK12-NEXT: entry: 2363 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2364 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2365 // CHECK12-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 2366 // CHECK12-NEXT: [[N:%.*]] = alloca i32, align 4 2367 // CHECK12-NEXT: [[M:%.*]] = alloca i32, align 4 2368 // CHECK12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2369 // CHECK12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2370 // CHECK12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2371 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2372 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 2373 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2374 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2375 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2376 // CHECK12-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2377 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2378 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2379 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2380 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2381 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 2382 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2383 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2384 // CHECK12-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 2385 // CHECK12-NEXT: store i32 100, i32* [[N]], align 4 2386 // CHECK12-NEXT: store i32 2, i32* [[M]], align 4 2387 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 2388 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 2389 // CHECK12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2390 // CHECK12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2391 // CHECK12-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2392 // CHECK12-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 2393 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 2394 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 2395 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 2396 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 2397 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 2398 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 2399 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 2400 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 2401 // CHECK12-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 2402 // CHECK12-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 2403 // CHECK12-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 2404 // CHECK12-NEXT: [[TMP11:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2405 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes to i8*), i32 40, i1 false) 2406 // CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2407 // CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2408 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP13]], align 4 2409 // CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2410 // CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 2411 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[TMP15]], align 4 2412 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2413 // CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 2414 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2415 // CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2416 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 2417 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2418 // CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 2419 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 2420 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2421 // CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 2422 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2423 // CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 2424 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP23]], align 4 2425 // CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2426 // CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2427 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[TMP25]], align 4 2428 // CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2429 // CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 2430 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2431 // CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 2432 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 2433 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2434 // CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 2435 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 2436 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2437 // CHECK12-NEXT: store i8* null, i8** [[TMP31]], align 4 2438 // CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2439 // CHECK12-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32** 2440 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP33]], align 4 2441 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2442 // CHECK12-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32** 2443 // CHECK12-NEXT: store i32* [[VLA]], i32** [[TMP35]], align 4 2444 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2445 // CHECK12-NEXT: store i64 [[TMP10]], i64* [[TMP36]], align 4 2446 // CHECK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2447 // CHECK12-NEXT: store i8* null, i8** [[TMP37]], align 4 2448 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2449 // CHECK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2450 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2451 // CHECK12-NEXT: [[TMP41:%.*]] = load i32, i32* [[N]], align 4 2452 // CHECK12-NEXT: store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR_]], align 4 2453 // CHECK12-NEXT: [[TMP42:%.*]] = load i32, i32* [[M]], align 4 2454 // CHECK12-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2455 // CHECK12-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2456 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP43]], 0 2457 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2458 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2459 // CHECK12-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2460 // CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP44]], 0 2461 // CHECK12-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 2462 // CHECK12-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 2463 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 2464 // CHECK12-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 2465 // CHECK12-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 2466 // CHECK12-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 2467 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP45]], 1 2468 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 2469 // CHECK12-NEXT: [[TMP46:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP38]], i8** [[TMP39]], i64* [[TMP40]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2470 // CHECK12-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 2471 // CHECK12-NEXT: br i1 [[TMP47]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2472 // CHECK12: omp_offload.failed: 2473 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR4:[0-9]+]] 2474 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2475 // CHECK12: omp_offload.cont: 2476 // CHECK12-NEXT: [[TMP48:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2477 // CHECK12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP48]]) 2478 // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2479 // CHECK12-NEXT: [[TMP49:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2480 // CHECK12-NEXT: call void @llvm.stackrestore(i8* [[TMP49]]) 2481 // CHECK12-NEXT: [[TMP50:%.*]] = load i32, i32* [[RETVAL]], align 4 2482 // CHECK12-NEXT: ret i32 [[TMP50]] 2483 // 2484 // 2485 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 2486 // CHECK12-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 2487 // CHECK12-NEXT: entry: 2488 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2489 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 2490 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2491 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2492 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2493 // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2494 // CHECK12-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 2495 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2496 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 2497 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2498 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2499 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2500 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2501 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2502 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2503 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2504 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 2505 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 2506 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 2507 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 2508 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 2509 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 2510 // CHECK12-NEXT: ret void 2511 // 2512 // 2513 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 2514 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { 2515 // CHECK12-NEXT: entry: 2516 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2517 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2518 // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2519 // CHECK12-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 2520 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2521 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2522 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 2523 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2524 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2525 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 2526 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2527 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 2528 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 2529 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 2530 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 2531 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2532 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2533 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2534 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2535 // CHECK12-NEXT: [[I11:%.*]] = alloca i32, align 4 2536 // CHECK12-NEXT: [[J12:%.*]] = alloca i32, align 4 2537 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2538 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2539 // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2540 // CHECK12-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 2541 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2542 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2543 // CHECK12-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 2544 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2545 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2546 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 2547 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2548 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 2549 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 2550 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 2551 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2552 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 2553 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2554 // CHECK12-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2555 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2556 // CHECK12-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 2557 // CHECK12-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 2558 // CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 2559 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 2560 // CHECK12-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 2561 // CHECK12-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 2562 // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 2563 // CHECK12-NEXT: store i32 0, i32* [[J]], align 4 2564 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2565 // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 2566 // CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 2567 // CHECK12: land.lhs.true: 2568 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2569 // CHECK12-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] 2570 // CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 2571 // CHECK12: omp.precond.then: 2572 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2573 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2574 // CHECK12-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 2575 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2576 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2577 // CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2578 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 2579 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2580 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2581 // CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2582 // CHECK12-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 2583 // CHECK12-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2584 // CHECK12: cond.true: 2585 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 2586 // CHECK12-NEXT: br label [[COND_END:%.*]] 2587 // CHECK12: cond.false: 2588 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2589 // CHECK12-NEXT: br label [[COND_END]] 2590 // CHECK12: cond.end: 2591 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 2592 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2593 // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2594 // CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 2595 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2596 // CHECK12: omp.inner.for.cond: 2597 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2598 // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 2599 // CHECK12-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 2600 // CHECK12-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2601 // CHECK12: omp.inner.for.body: 2602 // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2603 // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2604 // CHECK12-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 2605 // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 2606 // CHECK12-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 2607 // CHECK12-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 2608 // CHECK12-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] 2609 // CHECK12-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 2610 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 2611 // CHECK12-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 2612 // CHECK12-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 2613 // CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2614 // CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2615 // CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2616 // CHECK12-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 2617 // CHECK12-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 2618 // CHECK12-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 2619 // CHECK12-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 2620 // CHECK12-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] 2621 // CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 2622 // CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 2623 // CHECK12-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 2624 // CHECK12-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 2625 // CHECK12-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 2626 // CHECK12-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 2627 // CHECK12-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] 2628 // CHECK12-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 2629 // CHECK12-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 2630 // CHECK12-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 2631 // CHECK12-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 2632 // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 2633 // CHECK12-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] 2634 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] 2635 // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 2636 // CHECK12-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] 2637 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 2638 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2639 // CHECK12: omp.body.continue: 2640 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2641 // CHECK12: omp.inner.for.inc: 2642 // CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2643 // CHECK12-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 2644 // CHECK12-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 2645 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 2646 // CHECK12: omp.inner.for.end: 2647 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2648 // CHECK12: omp.loop.exit: 2649 // CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2650 // CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 2651 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 2652 // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2653 // CHECK12-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2654 // CHECK12-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2655 // CHECK12: .omp.final.then: 2656 // CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2657 // CHECK12-NEXT: [[SUB38:%.*]] = sub nsw i32 [[TMP33]], 0 2658 // CHECK12-NEXT: [[DIV39:%.*]] = sdiv i32 [[SUB38]], 1 2659 // CHECK12-NEXT: [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 1 2660 // CHECK12-NEXT: [[ADD41:%.*]] = add nsw i32 0, [[MUL40]] 2661 // CHECK12-NEXT: store i32 [[ADD41]], i32* [[I11]], align 4 2662 // CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 2663 // CHECK12-NEXT: [[SUB42:%.*]] = sub nsw i32 [[TMP34]], 0 2664 // CHECK12-NEXT: [[DIV43:%.*]] = sdiv i32 [[SUB42]], 1 2665 // CHECK12-NEXT: [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 1 2666 // CHECK12-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 2667 // CHECK12-NEXT: store i32 [[ADD45]], i32* [[J12]], align 4 2668 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] 2669 // CHECK12: .omp.final.done: 2670 // CHECK12-NEXT: br label [[OMP_PRECOND_END]] 2671 // CHECK12: omp.precond.end: 2672 // CHECK12-NEXT: ret void 2673 // 2674 // 2675 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2676 // CHECK12-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { 2677 // CHECK12-NEXT: entry: 2678 // CHECK12-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2679 // CHECK12-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2680 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2681 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2682 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2683 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2684 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2685 // CHECK12-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2686 // CHECK12-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2687 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 2688 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 2689 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2690 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 2691 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 2692 // CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2693 // CHECK12-NEXT: store i8* null, i8** [[TMP4]], align 4 2694 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2695 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2696 // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 2697 // CHECK12-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 2698 // CHECK12-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 2699 // CHECK12-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2700 // CHECK12: omp_offload.failed: 2701 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR4]] 2702 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2703 // CHECK12: omp_offload.cont: 2704 // CHECK12-NEXT: ret i32 0 2705 // 2706 // 2707 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 2708 // CHECK12-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 2709 // CHECK12-NEXT: entry: 2710 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2711 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2712 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2713 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 2714 // CHECK12-NEXT: ret void 2715 // 2716 // 2717 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 2718 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { 2719 // CHECK12-NEXT: entry: 2720 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2721 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2722 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 2723 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2724 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 2725 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2726 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2727 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2728 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2729 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2730 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 2731 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 2732 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2733 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2734 // CHECK12-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 2735 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 2736 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2737 // CHECK12-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 2738 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2739 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2740 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2741 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2742 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2743 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2744 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 2745 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2746 // CHECK12: cond.true: 2747 // CHECK12-NEXT: br label [[COND_END:%.*]] 2748 // CHECK12: cond.false: 2749 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2750 // CHECK12-NEXT: br label [[COND_END]] 2751 // CHECK12: cond.end: 2752 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 2753 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2754 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2755 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2756 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2757 // CHECK12: omp.inner.for.cond: 2758 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2759 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 2760 // CHECK12-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2761 // CHECK12-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2762 // CHECK12: omp.inner.for.body: 2763 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2764 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 2765 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2766 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2767 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 2768 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2769 // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2770 // CHECK12-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 2771 // CHECK12-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 2772 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 2773 // CHECK12-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 2774 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 2775 // CHECK12-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 2776 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 2777 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 2778 // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 2779 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 2780 // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 2781 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2782 // CHECK12: omp.body.continue: 2783 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2784 // CHECK12: omp.inner.for.inc: 2785 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2786 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 2787 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 2788 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 2789 // CHECK12: omp.inner.for.end: 2790 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2791 // CHECK12: omp.loop.exit: 2792 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 2793 // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2794 // CHECK12-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2795 // CHECK12-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2796 // CHECK12: .omp.final.then: 2797 // CHECK12-NEXT: store i32 10, i32* [[I]], align 4 2798 // CHECK12-NEXT: store i32 2, i32* [[J]], align 4 2799 // CHECK12-NEXT: br label [[DOTOMP_FINAL_DONE]] 2800 // CHECK12: .omp.final.done: 2801 // CHECK12-NEXT: ret void 2802 // 2803 // 2804 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2805 // CHECK12-SAME: () #[[ATTR7:[0-9]+]] { 2806 // CHECK12-NEXT: entry: 2807 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) 2808 // CHECK12-NEXT: ret void 2809 // 2810 // 2811 // CHECK13-LABEL: define {{[^@]+}}@main 2812 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 2813 // CHECK13-NEXT: entry: 2814 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2815 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2816 // CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 2817 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 2818 // CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 2819 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2820 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2821 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2822 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 2823 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2824 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2825 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 2826 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 2827 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2828 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2829 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2830 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 2831 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2832 // CHECK13-NEXT: [[I9:%.*]] = alloca i32, align 4 2833 // CHECK13-NEXT: [[J10:%.*]] = alloca i32, align 4 2834 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 2835 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2836 // CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 2837 // CHECK13-NEXT: store i32 100, i32* [[N]], align 4 2838 // CHECK13-NEXT: store i32 2, i32* [[M]], align 4 2839 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 2840 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2841 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 2842 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 2843 // CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 2844 // CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 2845 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 2846 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 2847 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 2848 // CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 2849 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 2850 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 2851 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 2852 // CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 2853 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2854 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0 2855 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 2856 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 2857 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2858 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0 2859 // CHECK13-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 2860 // CHECK13-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 2861 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 2862 // CHECK13-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 2863 // CHECK13-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 2864 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2865 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 2866 // CHECK13-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_UB]], align 8 2867 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 2868 // CHECK13-NEXT: store i32 0, i32* [[J]], align 4 2869 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2870 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]] 2871 // CHECK13-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 2872 // CHECK13: land.lhs.true: 2873 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2874 // CHECK13-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]] 2875 // CHECK13-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 2876 // CHECK13: simd.if.then: 2877 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2878 // CHECK13-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_IV]], align 8 2879 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2880 // CHECK13: omp.inner.for.cond: 2881 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2882 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !2 2883 // CHECK13-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]] 2884 // CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2885 // CHECK13: omp.inner.for.body: 2886 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2887 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 2888 // CHECK13-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0 2889 // CHECK13-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 2890 // CHECK13-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 2891 // CHECK13-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 2892 // CHECK13-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]] 2893 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 2894 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 2895 // CHECK13-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 2896 // CHECK13-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !2 2897 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2898 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2899 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 2900 // CHECK13-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0 2901 // CHECK13-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 2902 // CHECK13-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 2903 // CHECK13-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 2904 // CHECK13-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]] 2905 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 2906 // CHECK13-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0 2907 // CHECK13-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 2908 // CHECK13-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 2909 // CHECK13-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 2910 // CHECK13-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 2911 // CHECK13-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]] 2912 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 2913 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 2914 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 2915 // CHECK13-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !2 2916 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !2 2917 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 2918 // CHECK13-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 2919 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP23]] 2920 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !2 2921 // CHECK13-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64 2922 // CHECK13-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM33]] 2923 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !2 2924 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2925 // CHECK13: omp.body.continue: 2926 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2927 // CHECK13: omp.inner.for.inc: 2928 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2929 // CHECK13-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1 2930 // CHECK13-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 2931 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 2932 // CHECK13: omp.inner.for.end: 2933 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2934 // CHECK13-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0 2935 // CHECK13-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 2936 // CHECK13-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1 2937 // CHECK13-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]] 2938 // CHECK13-NEXT: store i32 [[ADD39]], i32* [[I9]], align 4 2939 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 2940 // CHECK13-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0 2941 // CHECK13-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 2942 // CHECK13-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 2943 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] 2944 // CHECK13-NEXT: store i32 [[ADD43]], i32* [[J10]], align 4 2945 // CHECK13-NEXT: br label [[SIMD_IF_END]] 2946 // CHECK13: simd.if.end: 2947 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 2948 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) 2949 // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2950 // CHECK13-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2951 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 2952 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 2953 // CHECK13-NEXT: ret i32 [[TMP30]] 2954 // 2955 // 2956 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 2957 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 2958 // CHECK13-NEXT: entry: 2959 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 2960 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 2961 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 2962 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2963 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2964 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2965 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2966 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 2967 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 2968 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 2969 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2970 // CHECK13-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 2971 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2972 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 2973 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2974 // CHECK13: omp.inner.for.cond: 2975 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2976 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 2977 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 2978 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2979 // CHECK13: omp.inner.for.body: 2980 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2981 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 2982 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2983 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2984 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 2985 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2986 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 2987 // CHECK13-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 2988 // CHECK13-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 2989 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 2990 // CHECK13-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 2991 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 2992 // CHECK13-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !6 2993 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 2994 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 2995 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 2996 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !6 2997 // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 2998 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] 2999 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !6 3000 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3001 // CHECK13: omp.body.continue: 3002 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3003 // CHECK13: omp.inner.for.inc: 3004 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3005 // CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 3006 // CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3007 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3008 // CHECK13: omp.inner.for.end: 3009 // CHECK13-NEXT: store i32 10, i32* [[I]], align 4 3010 // CHECK13-NEXT: store i32 2, i32* [[J]], align 4 3011 // CHECK13-NEXT: ret i32 0 3012 // 3013 // 3014 // CHECK14-LABEL: define {{[^@]+}}@main 3015 // CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 3016 // CHECK14-NEXT: entry: 3017 // CHECK14-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3018 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3019 // CHECK14-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 3020 // CHECK14-NEXT: [[N:%.*]] = alloca i32, align 4 3021 // CHECK14-NEXT: [[M:%.*]] = alloca i32, align 4 3022 // CHECK14-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3023 // CHECK14-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3024 // CHECK14-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3025 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 3026 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3027 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3028 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3029 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 3030 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3031 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3032 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 3033 // CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 3034 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3035 // CHECK14-NEXT: [[I9:%.*]] = alloca i32, align 4 3036 // CHECK14-NEXT: [[J10:%.*]] = alloca i32, align 4 3037 // CHECK14-NEXT: store i32 0, i32* [[RETVAL]], align 4 3038 // CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3039 // CHECK14-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 3040 // CHECK14-NEXT: store i32 100, i32* [[N]], align 4 3041 // CHECK14-NEXT: store i32 2, i32* [[M]], align 4 3042 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 3043 // CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 3044 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 3045 // CHECK14-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 3046 // CHECK14-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 3047 // CHECK14-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 3048 // CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 3049 // CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 3050 // CHECK14-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 3051 // CHECK14-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 3052 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 3053 // CHECK14-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 3054 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 3055 // CHECK14-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3056 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3057 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0 3058 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 3059 // CHECK14-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 3060 // CHECK14-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3061 // CHECK14-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0 3062 // CHECK14-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 3063 // CHECK14-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 3064 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 3065 // CHECK14-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 3066 // CHECK14-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 3067 // CHECK14-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3068 // CHECK14-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 3069 // CHECK14-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_UB]], align 8 3070 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4 3071 // CHECK14-NEXT: store i32 0, i32* [[J]], align 4 3072 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3073 // CHECK14-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]] 3074 // CHECK14-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 3075 // CHECK14: land.lhs.true: 3076 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3077 // CHECK14-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]] 3078 // CHECK14-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 3079 // CHECK14: simd.if.then: 3080 // CHECK14-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3081 // CHECK14-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_IV]], align 8 3082 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3083 // CHECK14: omp.inner.for.cond: 3084 // CHECK14-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3085 // CHECK14-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !2 3086 // CHECK14-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]] 3087 // CHECK14-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3088 // CHECK14: omp.inner.for.body: 3089 // CHECK14-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3090 // CHECK14-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 3091 // CHECK14-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0 3092 // CHECK14-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 3093 // CHECK14-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 3094 // CHECK14-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 3095 // CHECK14-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]] 3096 // CHECK14-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 3097 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 3098 // CHECK14-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 3099 // CHECK14-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !2 3100 // CHECK14-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3101 // CHECK14-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3102 // CHECK14-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 3103 // CHECK14-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0 3104 // CHECK14-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 3105 // CHECK14-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 3106 // CHECK14-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 3107 // CHECK14-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]] 3108 // CHECK14-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 3109 // CHECK14-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0 3110 // CHECK14-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 3111 // CHECK14-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 3112 // CHECK14-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 3113 // CHECK14-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 3114 // CHECK14-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]] 3115 // CHECK14-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 3116 // CHECK14-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 3117 // CHECK14-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 3118 // CHECK14-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !2 3119 // CHECK14-NEXT: [[TMP22:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !2 3120 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 3121 // CHECK14-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 3122 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP23]] 3123 // CHECK14-NEXT: [[TMP24:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !2 3124 // CHECK14-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64 3125 // CHECK14-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM33]] 3126 // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !2 3127 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3128 // CHECK14: omp.body.continue: 3129 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3130 // CHECK14: omp.inner.for.inc: 3131 // CHECK14-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3132 // CHECK14-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1 3133 // CHECK14-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 3134 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 3135 // CHECK14: omp.inner.for.end: 3136 // CHECK14-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3137 // CHECK14-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0 3138 // CHECK14-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 3139 // CHECK14-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1 3140 // CHECK14-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]] 3141 // CHECK14-NEXT: store i32 [[ADD39]], i32* [[I9]], align 4 3142 // CHECK14-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3143 // CHECK14-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0 3144 // CHECK14-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 3145 // CHECK14-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 3146 // CHECK14-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] 3147 // CHECK14-NEXT: store i32 [[ADD43]], i32* [[J10]], align 4 3148 // CHECK14-NEXT: br label [[SIMD_IF_END]] 3149 // CHECK14: simd.if.end: 3150 // CHECK14-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 3151 // CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) 3152 // CHECK14-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3153 // CHECK14-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3154 // CHECK14-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 3155 // CHECK14-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 3156 // CHECK14-NEXT: ret i32 [[TMP30]] 3157 // 3158 // 3159 // CHECK14-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 3160 // CHECK14-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 3161 // CHECK14-NEXT: entry: 3162 // CHECK14-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3163 // CHECK14-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 3164 // CHECK14-NEXT: [[TMP:%.*]] = alloca i32, align 4 3165 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3166 // CHECK14-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3167 // CHECK14-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3168 // CHECK14-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3169 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 3170 // CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 3171 // CHECK14-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3172 // CHECK14-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3173 // CHECK14-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 3174 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3175 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3176 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3177 // CHECK14: omp.inner.for.cond: 3178 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3179 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 3180 // CHECK14-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3181 // CHECK14-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3182 // CHECK14: omp.inner.for.body: 3183 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3184 // CHECK14-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 3185 // CHECK14-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 3186 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3187 // CHECK14-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 3188 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3189 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3190 // CHECK14-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 3191 // CHECK14-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 3192 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 3193 // CHECK14-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 3194 // CHECK14-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 3195 // CHECK14-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !6 3196 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 3197 // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 3198 // CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 3199 // CHECK14-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !6 3200 // CHECK14-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 3201 // CHECK14-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] 3202 // CHECK14-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !6 3203 // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3204 // CHECK14: omp.body.continue: 3205 // CHECK14-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3206 // CHECK14: omp.inner.for.inc: 3207 // CHECK14-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3208 // CHECK14-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 3209 // CHECK14-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 3210 // CHECK14-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 3211 // CHECK14: omp.inner.for.end: 3212 // CHECK14-NEXT: store i32 10, i32* [[I]], align 4 3213 // CHECK14-NEXT: store i32 2, i32* [[J]], align 4 3214 // CHECK14-NEXT: ret i32 0 3215 // 3216 // 3217 // CHECK15-LABEL: define {{[^@]+}}@main 3218 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 3219 // CHECK15-NEXT: entry: 3220 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3221 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3222 // CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 3223 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 3224 // CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 3225 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3226 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3227 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3228 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3229 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3230 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3231 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3232 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 3233 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3234 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3235 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3236 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 3237 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3238 // CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 3239 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4 3240 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 3241 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3242 // CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 3243 // CHECK15-NEXT: store i32 100, i32* [[N]], align 4 3244 // CHECK15-NEXT: store i32 2, i32* [[M]], align 4 3245 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 3246 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 3247 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3248 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3249 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 3250 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 3251 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 3252 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 3253 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 3254 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 3255 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[M]], align 4 3256 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3257 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3258 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 3259 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 3260 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 3261 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3262 // CHECK15-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0 3263 // CHECK15-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 3264 // CHECK15-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 3265 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 3266 // CHECK15-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 3267 // CHECK15-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 3268 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3269 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 3270 // CHECK15-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_UB]], align 8 3271 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4 3272 // CHECK15-NEXT: store i32 0, i32* [[J]], align 4 3273 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3274 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 3275 // CHECK15-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 3276 // CHECK15: land.lhs.true: 3277 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3278 // CHECK15-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]] 3279 // CHECK15-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 3280 // CHECK15: simd.if.then: 3281 // CHECK15-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3282 // CHECK15-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 3283 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3284 // CHECK15: omp.inner.for.cond: 3285 // CHECK15-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3286 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !3 3287 // CHECK15-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]] 3288 // CHECK15-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3289 // CHECK15: omp.inner.for.body: 3290 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3291 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3292 // CHECK15-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0 3293 // CHECK15-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 3294 // CHECK15-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 3295 // CHECK15-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 3296 // CHECK15-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]] 3297 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 3298 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 3299 // CHECK15-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 3300 // CHECK15-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !3 3301 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3302 // CHECK15-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3303 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3304 // CHECK15-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0 3305 // CHECK15-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 3306 // CHECK15-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 3307 // CHECK15-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 3308 // CHECK15-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]] 3309 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3310 // CHECK15-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0 3311 // CHECK15-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 3312 // CHECK15-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 3313 // CHECK15-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 3314 // CHECK15-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 3315 // CHECK15-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]] 3316 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 3317 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 3318 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 3319 // CHECK15-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !3 3320 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !3 3321 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]] 3322 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP21]] 3323 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !3 3324 // CHECK15-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP22]] 3325 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !3 3326 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3327 // CHECK15: omp.body.continue: 3328 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3329 // CHECK15: omp.inner.for.inc: 3330 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3331 // CHECK15-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1 3332 // CHECK15-NEXT: store i64 [[ADD34]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3333 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3334 // CHECK15: omp.inner.for.end: 3335 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3336 // CHECK15-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0 3337 // CHECK15-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1 3338 // CHECK15-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1 3339 // CHECK15-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]] 3340 // CHECK15-NEXT: store i32 [[ADD38]], i32* [[I9]], align 4 3341 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3342 // CHECK15-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0 3343 // CHECK15-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 3344 // CHECK15-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 3345 // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 3346 // CHECK15-NEXT: store i32 [[ADD42]], i32* [[J10]], align 4 3347 // CHECK15-NEXT: br label [[SIMD_IF_END]] 3348 // CHECK15: simd.if.end: 3349 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 3350 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) 3351 // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3352 // CHECK15-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3353 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) 3354 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 3355 // CHECK15-NEXT: ret i32 [[TMP28]] 3356 // 3357 // 3358 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 3359 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 3360 // CHECK15-NEXT: entry: 3361 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3362 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 3363 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 3364 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3365 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3366 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3367 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3368 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 3369 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 3370 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3371 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3372 // CHECK15-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 3373 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3374 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3375 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3376 // CHECK15: omp.inner.for.cond: 3377 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3378 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 3379 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3380 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3381 // CHECK15: omp.inner.for.body: 3382 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3383 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 3384 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 3385 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3386 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 3387 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3388 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3389 // CHECK15-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 3390 // CHECK15-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 3391 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 3392 // CHECK15-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 3393 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 3394 // CHECK15-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !7 3395 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 3396 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP6]] 3397 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !7 3398 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 3399 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !7 3400 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3401 // CHECK15: omp.body.continue: 3402 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3403 // CHECK15: omp.inner.for.inc: 3404 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3405 // CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1 3406 // CHECK15-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3407 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3408 // CHECK15: omp.inner.for.end: 3409 // CHECK15-NEXT: store i32 10, i32* [[I]], align 4 3410 // CHECK15-NEXT: store i32 2, i32* [[J]], align 4 3411 // CHECK15-NEXT: ret i32 0 3412 // 3413 // 3414 // CHECK16-LABEL: define {{[^@]+}}@main 3415 // CHECK16-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 3416 // CHECK16-NEXT: entry: 3417 // CHECK16-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3418 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3419 // CHECK16-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 3420 // CHECK16-NEXT: [[N:%.*]] = alloca i32, align 4 3421 // CHECK16-NEXT: [[M:%.*]] = alloca i32, align 4 3422 // CHECK16-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3423 // CHECK16-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3424 // CHECK16-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3425 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 3426 // CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3427 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3428 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3429 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 3430 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3431 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3432 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 3433 // CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 3434 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3435 // CHECK16-NEXT: [[I9:%.*]] = alloca i32, align 4 3436 // CHECK16-NEXT: [[J10:%.*]] = alloca i32, align 4 3437 // CHECK16-NEXT: store i32 0, i32* [[RETVAL]], align 4 3438 // CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3439 // CHECK16-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 3440 // CHECK16-NEXT: store i32 100, i32* [[N]], align 4 3441 // CHECK16-NEXT: store i32 2, i32* [[M]], align 4 3442 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 3443 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 3444 // CHECK16-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3445 // CHECK16-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3446 // CHECK16-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 3447 // CHECK16-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 3448 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 3449 // CHECK16-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 3450 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 3451 // CHECK16-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 3452 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[M]], align 4 3453 // CHECK16-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3454 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3455 // CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 3456 // CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 3457 // CHECK16-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 3458 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3459 // CHECK16-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0 3460 // CHECK16-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 3461 // CHECK16-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 3462 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 3463 // CHECK16-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 3464 // CHECK16-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 3465 // CHECK16-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3466 // CHECK16-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 3467 // CHECK16-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_UB]], align 8 3468 // CHECK16-NEXT: store i32 0, i32* [[I]], align 4 3469 // CHECK16-NEXT: store i32 0, i32* [[J]], align 4 3470 // CHECK16-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3471 // CHECK16-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 3472 // CHECK16-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 3473 // CHECK16: land.lhs.true: 3474 // CHECK16-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3475 // CHECK16-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]] 3476 // CHECK16-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 3477 // CHECK16: simd.if.then: 3478 // CHECK16-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3479 // CHECK16-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 3480 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3481 // CHECK16: omp.inner.for.cond: 3482 // CHECK16-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3483 // CHECK16-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !3 3484 // CHECK16-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]] 3485 // CHECK16-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3486 // CHECK16: omp.inner.for.body: 3487 // CHECK16-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3488 // CHECK16-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3489 // CHECK16-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0 3490 // CHECK16-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 3491 // CHECK16-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 3492 // CHECK16-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 3493 // CHECK16-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]] 3494 // CHECK16-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 3495 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 3496 // CHECK16-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 3497 // CHECK16-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !3 3498 // CHECK16-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3499 // CHECK16-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3500 // CHECK16-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3501 // CHECK16-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0 3502 // CHECK16-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 3503 // CHECK16-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 3504 // CHECK16-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 3505 // CHECK16-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]] 3506 // CHECK16-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 3507 // CHECK16-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0 3508 // CHECK16-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 3509 // CHECK16-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 3510 // CHECK16-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 3511 // CHECK16-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 3512 // CHECK16-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]] 3513 // CHECK16-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 3514 // CHECK16-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 3515 // CHECK16-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 3516 // CHECK16-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !3 3517 // CHECK16-NEXT: [[TMP20:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !3 3518 // CHECK16-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]] 3519 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP21]] 3520 // CHECK16-NEXT: [[TMP22:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !3 3521 // CHECK16-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP22]] 3522 // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !3 3523 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3524 // CHECK16: omp.body.continue: 3525 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3526 // CHECK16: omp.inner.for.inc: 3527 // CHECK16-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3528 // CHECK16-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1 3529 // CHECK16-NEXT: store i64 [[ADD34]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 3530 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 3531 // CHECK16: omp.inner.for.end: 3532 // CHECK16-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3533 // CHECK16-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0 3534 // CHECK16-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1 3535 // CHECK16-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1 3536 // CHECK16-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]] 3537 // CHECK16-NEXT: store i32 [[ADD38]], i32* [[I9]], align 4 3538 // CHECK16-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3539 // CHECK16-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0 3540 // CHECK16-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 3541 // CHECK16-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 3542 // CHECK16-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 3543 // CHECK16-NEXT: store i32 [[ADD42]], i32* [[J10]], align 4 3544 // CHECK16-NEXT: br label [[SIMD_IF_END]] 3545 // CHECK16: simd.if.end: 3546 // CHECK16-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 3547 // CHECK16-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) 3548 // CHECK16-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 3549 // CHECK16-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3550 // CHECK16-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) 3551 // CHECK16-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 3552 // CHECK16-NEXT: ret i32 [[TMP28]] 3553 // 3554 // 3555 // CHECK16-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 3556 // CHECK16-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 3557 // CHECK16-NEXT: entry: 3558 // CHECK16-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 3559 // CHECK16-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 3560 // CHECK16-NEXT: [[TMP:%.*]] = alloca i32, align 4 3561 // CHECK16-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3562 // CHECK16-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3563 // CHECK16-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3564 // CHECK16-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3565 // CHECK16-NEXT: [[I:%.*]] = alloca i32, align 4 3566 // CHECK16-NEXT: [[J:%.*]] = alloca i32, align 4 3567 // CHECK16-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 3568 // CHECK16-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3569 // CHECK16-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 3570 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3571 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 3572 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3573 // CHECK16: omp.inner.for.cond: 3574 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3575 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 3576 // CHECK16-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 3577 // CHECK16-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3578 // CHECK16: omp.inner.for.body: 3579 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3580 // CHECK16-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 3581 // CHECK16-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 3582 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3583 // CHECK16-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 3584 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3585 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3586 // CHECK16-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 3587 // CHECK16-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 3588 // CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 3589 // CHECK16-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 3590 // CHECK16-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 3591 // CHECK16-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !7 3592 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 3593 // CHECK16-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP6]] 3594 // CHECK16-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !7 3595 // CHECK16-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 3596 // CHECK16-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !7 3597 // CHECK16-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3598 // CHECK16: omp.body.continue: 3599 // CHECK16-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3600 // CHECK16: omp.inner.for.inc: 3601 // CHECK16-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3602 // CHECK16-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1 3603 // CHECK16-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 3604 // CHECK16-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3605 // CHECK16: omp.inner.for.end: 3606 // CHECK16-NEXT: store i32 10, i32* [[I]], align 4 3607 // CHECK16-NEXT: store i32 2, i32* [[J]], align 4 3608 // CHECK16-NEXT: ret i32 0 3609 // 3610