1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // expected-no-diagnostics 3 #ifndef HEADER 4 #define HEADER 5 6 // Test host codegen. 7 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 8 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 9 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 10 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 11 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 13 14 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 15 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 16 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 17 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 18 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 20 #ifdef CK1 21 22 template <typename T, int X, long long Y> 23 struct SS{ 24 T a[X][Y]; 25 26 int foo(void) { 27 28 #pragma omp target teams distribute simd collapse(2) 29 for(int i = 0; i < X; i++) { 30 for(int j = 0; j < Y; j++) { 31 a[i][j] = (T)0; 32 } 33 } 34 35 // discard loop variables not needed here 36 37 return a[0][0]; 38 } 39 }; 40 41 int teams_template_struct(void) { 42 SS<int, 123, 456> V; 43 return V.foo(); 44 45 } 46 #endif // CK1 47 48 // Test host codegen. 49 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 50 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 51 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 52 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 55 56 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 58 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 60 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 61 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 62 #ifdef CK2 63 64 template <typename T, int n, int m> 65 int tmain(T argc) { 66 T a[n][m]; 67 #pragma omp target teams distribute simd collapse(2) 68 for(int i = 0; i < n; i++) { 69 for(int j = 0; j < m; j++) { 70 a[i][j] = (T)0; 71 } 72 } 73 return 0; 74 } 75 76 int main (int argc, char **argv) { 77 int n = 100; 78 int m = 2; 79 int a[n][m]; 80 #pragma omp target teams distribute simd collapse(2) 81 for(int i = 0; i < n; i++) { 82 for(int j = 0; j < m; j++) { 83 a[i][j] = 0; 84 } 85 } 86 return tmain<int, 10, 2>(argc); 87 } 88 89 90 91 92 93 // discard loop variables not needed here 94 95 #endif // CK2 96 #endif // #ifndef HEADER 97 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv 98 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 99 // CHECK1-NEXT: entry: 100 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 101 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 102 // CHECK1-NEXT: ret i32 [[CALL]] 103 // 104 // 105 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 106 // CHECK1-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 107 // CHECK1-NEXT: entry: 108 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 109 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 110 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 111 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 112 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 113 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 114 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 115 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 116 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 117 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 118 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 119 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 120 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 121 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 122 // CHECK1-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 123 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 124 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8 125 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 126 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 127 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 128 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 129 // CHECK1-NEXT: store i32 1, i32* [[TMP7]], align 4 130 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 131 // CHECK1-NEXT: store i32 1, i32* [[TMP8]], align 4 132 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 133 // CHECK1-NEXT: store i8** [[TMP5]], i8*** [[TMP9]], align 8 134 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 135 // CHECK1-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 8 136 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 137 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP11]], align 8 138 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 139 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP12]], align 8 140 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 141 // CHECK1-NEXT: store i8** null, i8*** [[TMP13]], align 8 142 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 143 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8 144 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 145 // CHECK1-NEXT: store i64 56088, i64* [[TMP15]], align 8 146 // CHECK1-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 147 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 148 // CHECK1-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 149 // CHECK1: omp_offload.failed: 150 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR3:[0-9]+]] 151 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 152 // CHECK1: omp_offload.cont: 153 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 154 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 155 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 156 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 157 // CHECK1-NEXT: ret i32 [[TMP18]] 158 // 159 // 160 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 161 // CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 164 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 165 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 166 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 167 // CHECK1-NEXT: ret void 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 171 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 174 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 175 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 176 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 177 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 178 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 179 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 180 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 181 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 182 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 183 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 184 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 185 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 186 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 187 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 188 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 189 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 190 // CHECK1-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 191 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 192 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 193 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 194 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 195 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 196 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 197 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 198 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 199 // CHECK1: cond.true: 200 // CHECK1-NEXT: br label [[COND_END:%.*]] 201 // CHECK1: cond.false: 202 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 203 // CHECK1-NEXT: br label [[COND_END]] 204 // CHECK1: cond.end: 205 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 206 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 207 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 208 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 209 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 210 // CHECK1: omp.inner.for.cond: 211 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 212 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 213 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 214 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 215 // CHECK1: omp.inner.for.body: 216 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 217 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 218 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 219 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 220 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 221 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 222 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 223 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 224 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 225 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 226 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 227 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 228 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 229 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 230 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 231 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 232 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 233 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 234 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 235 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 236 // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 237 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 238 // CHECK1: omp.body.continue: 239 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 240 // CHECK1: omp.inner.for.inc: 241 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 242 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 243 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 244 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 245 // CHECK1: omp.inner.for.end: 246 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 247 // CHECK1: omp.loop.exit: 248 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 249 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 250 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 251 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 252 // CHECK1: .omp.final.then: 253 // CHECK1-NEXT: store i32 123, i32* [[I]], align 4 254 // CHECK1-NEXT: store i32 456, i32* [[J]], align 4 255 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 256 // CHECK1: .omp.final.done: 257 // CHECK1-NEXT: ret void 258 // 259 // 260 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 261 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 262 // CHECK1-NEXT: entry: 263 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 264 // CHECK1-NEXT: ret void 265 // 266 // 267 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv 268 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 269 // CHECK3-NEXT: entry: 270 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 271 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 272 // CHECK3-NEXT: ret i32 [[CALL]] 273 // 274 // 275 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 276 // CHECK3-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 277 // CHECK3-NEXT: entry: 278 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 279 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 280 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 281 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 282 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 283 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 284 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 285 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 286 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 287 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 288 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 289 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 290 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 291 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 292 // CHECK3-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 293 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 294 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4 295 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 296 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 297 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 298 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 299 // CHECK3-NEXT: store i32 1, i32* [[TMP7]], align 4 300 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 301 // CHECK3-NEXT: store i32 1, i32* [[TMP8]], align 4 302 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 303 // CHECK3-NEXT: store i8** [[TMP5]], i8*** [[TMP9]], align 4 304 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 305 // CHECK3-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 4 306 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 307 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP11]], align 4 308 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 309 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP12]], align 4 310 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 311 // CHECK3-NEXT: store i8** null, i8*** [[TMP13]], align 4 312 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 313 // CHECK3-NEXT: store i8** null, i8*** [[TMP14]], align 4 314 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 315 // CHECK3-NEXT: store i64 56088, i64* [[TMP15]], align 8 316 // CHECK3-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 317 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 318 // CHECK3-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 319 // CHECK3: omp_offload.failed: 320 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR3:[0-9]+]] 321 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 322 // CHECK3: omp_offload.cont: 323 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 324 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 325 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 326 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 327 // CHECK3-NEXT: ret i32 [[TMP18]] 328 // 329 // 330 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 331 // CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 332 // CHECK3-NEXT: entry: 333 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 334 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 335 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 336 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 337 // CHECK3-NEXT: ret void 338 // 339 // 340 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 341 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { 342 // CHECK3-NEXT: entry: 343 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 344 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 345 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 346 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 347 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 348 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 349 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 350 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 351 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 352 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 353 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 354 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 355 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 356 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 357 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 358 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 359 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 360 // CHECK3-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 361 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 362 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 363 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 364 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 365 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 366 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 367 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 368 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 369 // CHECK3: cond.true: 370 // CHECK3-NEXT: br label [[COND_END:%.*]] 371 // CHECK3: cond.false: 372 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 373 // CHECK3-NEXT: br label [[COND_END]] 374 // CHECK3: cond.end: 375 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 376 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 377 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 378 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 379 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 380 // CHECK3: omp.inner.for.cond: 381 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 382 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 383 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 384 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 385 // CHECK3: omp.inner.for.body: 386 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 387 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 388 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 389 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 390 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 391 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 392 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 393 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 394 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 395 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 396 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 397 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 398 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 399 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 400 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 401 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 402 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 403 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 404 // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 405 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 406 // CHECK3: omp.body.continue: 407 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 408 // CHECK3: omp.inner.for.inc: 409 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 410 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 411 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 412 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 413 // CHECK3: omp.inner.for.end: 414 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 415 // CHECK3: omp.loop.exit: 416 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 417 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 418 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 419 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 420 // CHECK3: .omp.final.then: 421 // CHECK3-NEXT: store i32 123, i32* [[I]], align 4 422 // CHECK3-NEXT: store i32 456, i32* [[J]], align 4 423 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 424 // CHECK3: .omp.final.done: 425 // CHECK3-NEXT: ret void 426 // 427 // 428 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 429 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 430 // CHECK3-NEXT: entry: 431 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 432 // CHECK3-NEXT: ret void 433 // 434 // 435 // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv 436 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 437 // CHECK5-NEXT: entry: 438 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 439 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 440 // CHECK5-NEXT: ret i32 [[CALL]] 441 // 442 // 443 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 444 // CHECK5-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 445 // CHECK5-NEXT: entry: 446 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 447 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 448 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 449 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 450 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 451 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 452 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 453 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 454 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 455 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 456 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 457 // CHECK5-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 458 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 459 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 460 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 461 // CHECK5: omp.inner.for.cond: 462 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 463 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 464 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 465 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 466 // CHECK5: omp.inner.for.body: 467 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 468 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 469 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 470 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 471 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 472 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 473 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 474 // CHECK5-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 475 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 476 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 477 // CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 478 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 479 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !2 480 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 481 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 482 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 483 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 484 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !2 485 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 486 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 487 // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !2 488 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 489 // CHECK5: omp.body.continue: 490 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 491 // CHECK5: omp.inner.for.inc: 492 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 493 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 494 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 495 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 496 // CHECK5: omp.inner.for.end: 497 // CHECK5-NEXT: store i32 123, i32* [[I]], align 4 498 // CHECK5-NEXT: store i32 456, i32* [[J]], align 4 499 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 500 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 501 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 502 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 503 // CHECK5-NEXT: ret i32 [[TMP9]] 504 // 505 // 506 // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv 507 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 508 // CHECK7-NEXT: entry: 509 // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 510 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 511 // CHECK7-NEXT: ret i32 [[CALL]] 512 // 513 // 514 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 515 // CHECK7-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 516 // CHECK7-NEXT: entry: 517 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 518 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 519 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 520 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 521 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 522 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 523 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 524 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 525 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 526 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 527 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 528 // CHECK7-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 529 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 530 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 531 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 532 // CHECK7: omp.inner.for.cond: 533 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 534 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 535 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 536 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 537 // CHECK7: omp.inner.for.body: 538 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 539 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 540 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 541 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 542 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 543 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 544 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 545 // CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 546 // CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 547 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 548 // CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 549 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 550 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !3 551 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 552 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 553 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP6]] 554 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !3 555 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 556 // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !3 557 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 558 // CHECK7: omp.body.continue: 559 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 560 // CHECK7: omp.inner.for.inc: 561 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 562 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 563 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 564 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 565 // CHECK7: omp.inner.for.end: 566 // CHECK7-NEXT: store i32 123, i32* [[I]], align 4 567 // CHECK7-NEXT: store i32 456, i32* [[J]], align 4 568 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 569 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 570 // CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 571 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 572 // CHECK7-NEXT: ret i32 [[TMP9]] 573 // 574 // 575 // CHECK9-LABEL: define {{[^@]+}}@main 576 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 577 // CHECK9-NEXT: entry: 578 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 579 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 580 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 581 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 582 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 583 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 584 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 585 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 586 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 587 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 588 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 589 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 590 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 591 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 592 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 593 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 594 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 595 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 596 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 597 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 598 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 599 // CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 600 // CHECK9-NEXT: store i32 100, i32* [[N]], align 4 601 // CHECK9-NEXT: store i32 2, i32* [[M]], align 4 602 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 603 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 604 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 605 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 606 // CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 607 // CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 608 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 609 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 610 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 611 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 612 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 613 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 614 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 615 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 616 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 617 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 618 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 619 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 620 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 621 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 622 // CHECK9-NEXT: [[TMP12:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 623 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP12]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes to i8*), i64 40, i1 false) 624 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 625 // CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 626 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP14]], align 8 627 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 628 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 629 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP16]], align 8 630 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 631 // CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 632 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 633 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 634 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 635 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 636 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 637 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 638 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 639 // CHECK9-NEXT: store i8* null, i8** [[TMP22]], align 8 640 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 641 // CHECK9-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 642 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8 643 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 644 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 645 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP26]], align 8 646 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 647 // CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 648 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 649 // CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 650 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8 651 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 652 // CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 653 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 654 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 655 // CHECK9-NEXT: store i8* null, i8** [[TMP32]], align 8 656 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 657 // CHECK9-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32** 658 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP34]], align 8 659 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 660 // CHECK9-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 661 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 8 662 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 663 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP37]], align 8 664 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 665 // CHECK9-NEXT: store i8* null, i8** [[TMP38]], align 8 666 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 667 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 668 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 669 // CHECK9-NEXT: [[TMP42:%.*]] = load i32, i32* [[N]], align 4 670 // CHECK9-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 671 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 672 // CHECK9-NEXT: store i32 [[TMP43]], i32* [[DOTCAPTURE_EXPR_3]], align 4 673 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 674 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP44]], 0 675 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 676 // CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 677 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 678 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP45]], 0 679 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 680 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 681 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 682 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 683 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 684 // CHECK9-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 685 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP46]], 1 686 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 687 // CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 688 // CHECK9-NEXT: store i32 1, i32* [[TMP47]], align 4 689 // CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 690 // CHECK9-NEXT: store i32 5, i32* [[TMP48]], align 4 691 // CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 692 // CHECK9-NEXT: store i8** [[TMP39]], i8*** [[TMP49]], align 8 693 // CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 694 // CHECK9-NEXT: store i8** [[TMP40]], i8*** [[TMP50]], align 8 695 // CHECK9-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 696 // CHECK9-NEXT: store i64* [[TMP41]], i64** [[TMP51]], align 8 697 // CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 698 // CHECK9-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP52]], align 8 699 // CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 700 // CHECK9-NEXT: store i8** null, i8*** [[TMP53]], align 8 701 // CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 702 // CHECK9-NEXT: store i8** null, i8*** [[TMP54]], align 8 703 // CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 704 // CHECK9-NEXT: store i64 [[ADD]], i64* [[TMP55]], align 8 705 // CHECK9-NEXT: [[TMP56:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 706 // CHECK9-NEXT: [[TMP57:%.*]] = icmp ne i32 [[TMP56]], 0 707 // CHECK9-NEXT: br i1 [[TMP57]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 708 // CHECK9: omp_offload.failed: 709 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR4:[0-9]+]] 710 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 711 // CHECK9: omp_offload.cont: 712 // CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 713 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP58]]) 714 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 715 // CHECK9-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 716 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP59]]) 717 // CHECK9-NEXT: [[TMP60:%.*]] = load i32, i32* [[RETVAL]], align 4 718 // CHECK9-NEXT: ret i32 [[TMP60]] 719 // 720 // 721 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 722 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 723 // CHECK9-NEXT: entry: 724 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 725 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 726 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 727 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 728 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 729 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 730 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 731 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 732 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 733 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 734 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 735 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 736 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 737 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 738 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 739 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 740 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 741 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 742 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* 743 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 744 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 745 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4 746 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* 747 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 748 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 749 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 750 // CHECK9-NEXT: ret void 751 // 752 // 753 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 754 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { 755 // CHECK9-NEXT: entry: 756 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 757 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 758 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 759 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 760 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 761 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 762 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 763 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 764 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 765 // CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 766 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 767 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 768 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 769 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 770 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 771 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 772 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 773 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 774 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 775 // CHECK9-NEXT: [[I13:%.*]] = alloca i32, align 4 776 // CHECK9-NEXT: [[J14:%.*]] = alloca i32, align 4 777 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 778 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 779 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 780 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 781 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 782 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 783 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 784 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 785 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 786 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 787 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 788 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 789 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 790 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 791 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4 792 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 793 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 794 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 795 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 796 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 797 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 798 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 799 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 800 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 801 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] 802 // CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 803 // CHECK9-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 804 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4 805 // CHECK9-NEXT: store i32 0, i32* [[J]], align 4 806 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 807 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 808 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 809 // CHECK9: land.lhs.true: 810 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 811 // CHECK9-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] 812 // CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 813 // CHECK9: omp.precond.then: 814 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 815 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 816 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 817 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 818 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 819 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 820 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 821 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 822 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 823 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 824 // CHECK9-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 825 // CHECK9-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 826 // CHECK9: cond.true: 827 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 828 // CHECK9-NEXT: br label [[COND_END:%.*]] 829 // CHECK9: cond.false: 830 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 831 // CHECK9-NEXT: br label [[COND_END]] 832 // CHECK9: cond.end: 833 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 834 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 835 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 836 // CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 837 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 838 // CHECK9: omp.inner.for.cond: 839 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 840 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 841 // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 842 // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 843 // CHECK9: omp.inner.for.body: 844 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 845 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 846 // CHECK9-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 847 // CHECK9-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 848 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] 849 // CHECK9-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 850 // CHECK9-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] 851 // CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 852 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] 853 // CHECK9-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 854 // CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !5 855 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 856 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 857 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 858 // CHECK9-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 859 // CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 860 // CHECK9-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 861 // CHECK9-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 862 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] 863 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 864 // CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 865 // CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 866 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] 867 // CHECK9-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 868 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] 869 // CHECK9-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] 870 // CHECK9-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 871 // CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] 872 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 873 // CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !5 874 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !5 875 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 876 // CHECK9-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] 877 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] 878 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !5 879 // CHECK9-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 880 // CHECK9-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] 881 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4, !llvm.access.group !5 882 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 883 // CHECK9: omp.body.continue: 884 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 885 // CHECK9: omp.inner.for.inc: 886 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 887 // CHECK9-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 888 // CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 889 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 890 // CHECK9: omp.inner.for.end: 891 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 892 // CHECK9: omp.loop.exit: 893 // CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 894 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 895 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 896 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 897 // CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 898 // CHECK9-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 899 // CHECK9: .omp.final.then: 900 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 901 // CHECK9-NEXT: [[SUB41:%.*]] = sub nsw i32 [[TMP33]], 0 902 // CHECK9-NEXT: [[DIV42:%.*]] = sdiv i32 [[SUB41]], 1 903 // CHECK9-NEXT: [[MUL43:%.*]] = mul nsw i32 [[DIV42]], 1 904 // CHECK9-NEXT: [[ADD44:%.*]] = add nsw i32 0, [[MUL43]] 905 // CHECK9-NEXT: store i32 [[ADD44]], i32* [[I13]], align 4 906 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 907 // CHECK9-NEXT: [[SUB45:%.*]] = sub nsw i32 [[TMP34]], 0 908 // CHECK9-NEXT: [[DIV46:%.*]] = sdiv i32 [[SUB45]], 1 909 // CHECK9-NEXT: [[MUL47:%.*]] = mul nsw i32 [[DIV46]], 1 910 // CHECK9-NEXT: [[ADD48:%.*]] = add nsw i32 0, [[MUL47]] 911 // CHECK9-NEXT: store i32 [[ADD48]], i32* [[J14]], align 4 912 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 913 // CHECK9: .omp.final.done: 914 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 915 // CHECK9: omp.precond.end: 916 // CHECK9-NEXT: ret void 917 // 918 // 919 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 920 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { 921 // CHECK9-NEXT: entry: 922 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 923 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 924 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 925 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 926 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 927 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 928 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 929 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 930 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 931 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 932 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 933 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 934 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 935 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 936 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 937 // CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 938 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 939 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 940 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 941 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 942 // CHECK9-NEXT: store i32 1, i32* [[TMP7]], align 4 943 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 944 // CHECK9-NEXT: store i32 1, i32* [[TMP8]], align 4 945 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 946 // CHECK9-NEXT: store i8** [[TMP5]], i8*** [[TMP9]], align 8 947 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 948 // CHECK9-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 8 949 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 950 // CHECK9-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP11]], align 8 951 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 952 // CHECK9-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP12]], align 8 953 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 954 // CHECK9-NEXT: store i8** null, i8*** [[TMP13]], align 8 955 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 956 // CHECK9-NEXT: store i8** null, i8*** [[TMP14]], align 8 957 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 958 // CHECK9-NEXT: store i64 20, i64* [[TMP15]], align 8 959 // CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 960 // CHECK9-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 961 // CHECK9-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 962 // CHECK9: omp_offload.failed: 963 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR4]] 964 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 965 // CHECK9: omp_offload.cont: 966 // CHECK9-NEXT: ret i32 0 967 // 968 // 969 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 970 // CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 971 // CHECK9-NEXT: entry: 972 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 973 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 974 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 975 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 976 // CHECK9-NEXT: ret void 977 // 978 // 979 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 980 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { 981 // CHECK9-NEXT: entry: 982 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 983 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 984 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 985 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 986 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 987 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 988 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 989 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 990 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 991 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 992 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 993 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 994 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 995 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 996 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 997 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 998 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 999 // CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1000 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1001 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1002 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1003 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1004 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1005 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1006 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1007 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1008 // CHECK9: cond.true: 1009 // CHECK9-NEXT: br label [[COND_END:%.*]] 1010 // CHECK9: cond.false: 1011 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1012 // CHECK9-NEXT: br label [[COND_END]] 1013 // CHECK9: cond.end: 1014 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1015 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1016 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1017 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1018 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1019 // CHECK9: omp.inner.for.cond: 1020 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1021 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 1022 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1023 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1024 // CHECK9: omp.inner.for.body: 1025 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1026 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1027 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1028 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1029 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 1030 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1031 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1032 // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1033 // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1034 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1035 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1036 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1037 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 1038 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 1039 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 1040 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 1041 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 1042 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 1043 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 1044 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 1045 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1046 // CHECK9: omp.body.continue: 1047 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1048 // CHECK9: omp.inner.for.inc: 1049 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1050 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 1051 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 1052 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1053 // CHECK9: omp.inner.for.end: 1054 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1055 // CHECK9: omp.loop.exit: 1056 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1057 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1058 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1059 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1060 // CHECK9: .omp.final.then: 1061 // CHECK9-NEXT: store i32 10, i32* [[I]], align 4 1062 // CHECK9-NEXT: store i32 2, i32* [[J]], align 4 1063 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 1064 // CHECK9: .omp.final.done: 1065 // CHECK9-NEXT: ret void 1066 // 1067 // 1068 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1069 // CHECK9-SAME: () #[[ATTR7:[0-9]+]] { 1070 // CHECK9-NEXT: entry: 1071 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1072 // CHECK9-NEXT: ret void 1073 // 1074 // 1075 // CHECK11-LABEL: define {{[^@]+}}@main 1076 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1077 // CHECK11-NEXT: entry: 1078 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1079 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1080 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 1081 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 1082 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 1083 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1084 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1085 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1086 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1087 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1088 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1089 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1090 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1091 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 1092 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1093 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1094 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1095 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1096 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1097 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1098 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1099 // CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 1100 // CHECK11-NEXT: store i32 100, i32* [[N]], align 4 1101 // CHECK11-NEXT: store i32 2, i32* [[M]], align 4 1102 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1103 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 1104 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1105 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1106 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1107 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 1108 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 1109 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 1110 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 1111 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 1112 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 1113 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 1114 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 1115 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 1116 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1117 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 1118 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 1119 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1120 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes to i8*), i32 40, i1 false) 1121 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1122 // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 1123 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP13]], align 4 1124 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1125 // CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1126 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP15]], align 4 1127 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1128 // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 1129 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1130 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 1131 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 1132 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1133 // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1134 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 1135 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1136 // CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 1137 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1138 // CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 1139 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP23]], align 4 1140 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1141 // CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1142 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP25]], align 4 1143 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1144 // CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 1145 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1146 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1147 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 1148 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1149 // CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1150 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 1151 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1152 // CHECK11-NEXT: store i8* null, i8** [[TMP31]], align 4 1153 // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1154 // CHECK11-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32** 1155 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP33]], align 4 1156 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1157 // CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32** 1158 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP35]], align 4 1159 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1160 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP36]], align 4 1161 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1162 // CHECK11-NEXT: store i8* null, i8** [[TMP37]], align 4 1163 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1164 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1165 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1166 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[N]], align 4 1167 // CHECK11-NEXT: store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR_]], align 4 1168 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, i32* [[M]], align 4 1169 // CHECK11-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1170 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1171 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP43]], 0 1172 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1173 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1174 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1175 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP44]], 0 1176 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1177 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1178 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1179 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1180 // CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 1181 // CHECK11-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 1182 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP45]], 1 1183 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1184 // CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1185 // CHECK11-NEXT: store i32 1, i32* [[TMP46]], align 4 1186 // CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1187 // CHECK11-NEXT: store i32 5, i32* [[TMP47]], align 4 1188 // CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1189 // CHECK11-NEXT: store i8** [[TMP38]], i8*** [[TMP48]], align 4 1190 // CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1191 // CHECK11-NEXT: store i8** [[TMP39]], i8*** [[TMP49]], align 4 1192 // CHECK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1193 // CHECK11-NEXT: store i64* [[TMP40]], i64** [[TMP50]], align 4 1194 // CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1195 // CHECK11-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP51]], align 4 1196 // CHECK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1197 // CHECK11-NEXT: store i8** null, i8*** [[TMP52]], align 4 1198 // CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1199 // CHECK11-NEXT: store i8** null, i8*** [[TMP53]], align 4 1200 // CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1201 // CHECK11-NEXT: store i64 [[ADD]], i64* [[TMP54]], align 8 1202 // CHECK11-NEXT: [[TMP55:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1203 // CHECK11-NEXT: [[TMP56:%.*]] = icmp ne i32 [[TMP55]], 0 1204 // CHECK11-NEXT: br i1 [[TMP56]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1205 // CHECK11: omp_offload.failed: 1206 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR4:[0-9]+]] 1207 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1208 // CHECK11: omp_offload.cont: 1209 // CHECK11-NEXT: [[TMP57:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1210 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP57]]) 1211 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1212 // CHECK11-NEXT: [[TMP58:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 1213 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP58]]) 1214 // CHECK11-NEXT: [[TMP59:%.*]] = load i32, i32* [[RETVAL]], align 4 1215 // CHECK11-NEXT: ret i32 [[TMP59]] 1216 // 1217 // 1218 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 1219 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1220 // CHECK11-NEXT: entry: 1221 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1222 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 1223 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1224 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1225 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 1226 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1227 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1228 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1229 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 1230 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1231 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1232 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 1233 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1234 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1235 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 1236 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1237 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 1238 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 1239 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 1240 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 1241 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 1242 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 1243 // CHECK11-NEXT: ret void 1244 // 1245 // 1246 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 1247 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { 1248 // CHECK11-NEXT: entry: 1249 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1250 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1251 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1252 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 1253 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1254 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1255 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 1256 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1257 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1258 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1259 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1260 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1261 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1262 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1263 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1264 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1265 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1266 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1267 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1268 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 1269 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 1270 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1271 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1272 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1273 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 1274 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1275 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1276 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 1277 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1278 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1279 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 1280 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1281 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 1282 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 1283 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1284 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1285 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 1286 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1287 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1288 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1289 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 1290 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1291 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1292 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1293 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1294 // CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 1295 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 1296 // CHECK11-NEXT: store i32 0, i32* [[J]], align 4 1297 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1298 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 1299 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1300 // CHECK11: land.lhs.true: 1301 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1302 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] 1303 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1304 // CHECK11: omp.precond.then: 1305 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1306 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1307 // CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 1308 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1309 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1310 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1311 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 1312 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1313 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1314 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1315 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 1316 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1317 // CHECK11: cond.true: 1318 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1319 // CHECK11-NEXT: br label [[COND_END:%.*]] 1320 // CHECK11: cond.false: 1321 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1322 // CHECK11-NEXT: br label [[COND_END]] 1323 // CHECK11: cond.end: 1324 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 1325 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1326 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1327 // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 1328 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1329 // CHECK11: omp.inner.for.cond: 1330 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1331 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 1332 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 1333 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1334 // CHECK11: omp.inner.for.body: 1335 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1336 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 1337 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 1338 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1339 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 1340 // CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 1341 // CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] 1342 // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 1343 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 1344 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 1345 // CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 1346 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1347 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1348 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 1349 // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 1350 // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 1351 // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 1352 // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 1353 // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] 1354 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 1355 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 1356 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 1357 // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 1358 // CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 1359 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 1360 // CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] 1361 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 1362 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 1363 // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 1364 // CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 1365 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 1366 // CHECK11-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] 1367 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] 1368 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 1369 // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] 1370 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 1371 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1372 // CHECK11: omp.body.continue: 1373 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1374 // CHECK11: omp.inner.for.inc: 1375 // CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1376 // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 1377 // CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1378 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1379 // CHECK11: omp.inner.for.end: 1380 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1381 // CHECK11: omp.loop.exit: 1382 // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1383 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 1384 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 1385 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1386 // CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1387 // CHECK11-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1388 // CHECK11: .omp.final.then: 1389 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1390 // CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i32 [[TMP33]], 0 1391 // CHECK11-NEXT: [[DIV39:%.*]] = sdiv i32 [[SUB38]], 1 1392 // CHECK11-NEXT: [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 1 1393 // CHECK11-NEXT: [[ADD41:%.*]] = add nsw i32 0, [[MUL40]] 1394 // CHECK11-NEXT: store i32 [[ADD41]], i32* [[I11]], align 4 1395 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1396 // CHECK11-NEXT: [[SUB42:%.*]] = sub nsw i32 [[TMP34]], 0 1397 // CHECK11-NEXT: [[DIV43:%.*]] = sdiv i32 [[SUB42]], 1 1398 // CHECK11-NEXT: [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 1 1399 // CHECK11-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 1400 // CHECK11-NEXT: store i32 [[ADD45]], i32* [[J12]], align 4 1401 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 1402 // CHECK11: .omp.final.done: 1403 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 1404 // CHECK11: omp.precond.end: 1405 // CHECK11-NEXT: ret void 1406 // 1407 // 1408 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1409 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { 1410 // CHECK11-NEXT: entry: 1411 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1412 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1413 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1414 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1415 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1416 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1417 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1418 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1419 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1420 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1421 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 1422 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1423 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1424 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 1425 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1426 // CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 1427 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1428 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1429 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1430 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1431 // CHECK11-NEXT: store i32 1, i32* [[TMP7]], align 4 1432 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1433 // CHECK11-NEXT: store i32 1, i32* [[TMP8]], align 4 1434 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1435 // CHECK11-NEXT: store i8** [[TMP5]], i8*** [[TMP9]], align 4 1436 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1437 // CHECK11-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 4 1438 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1439 // CHECK11-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64** [[TMP11]], align 4 1440 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1441 // CHECK11-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i64** [[TMP12]], align 4 1442 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1443 // CHECK11-NEXT: store i8** null, i8*** [[TMP13]], align 4 1444 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1445 // CHECK11-NEXT: store i8** null, i8*** [[TMP14]], align 4 1446 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1447 // CHECK11-NEXT: store i64 20, i64* [[TMP15]], align 8 1448 // CHECK11-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 0, i32 1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1449 // CHECK11-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 1450 // CHECK11-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1451 // CHECK11: omp_offload.failed: 1452 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR4]] 1453 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1454 // CHECK11: omp_offload.cont: 1455 // CHECK11-NEXT: ret i32 0 1456 // 1457 // 1458 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 1459 // CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1460 // CHECK11-NEXT: entry: 1461 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 1462 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 1463 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 1464 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1465 // CHECK11-NEXT: ret void 1466 // 1467 // 1468 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 1469 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { 1470 // CHECK11-NEXT: entry: 1471 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1472 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1473 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 1474 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1475 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1476 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1477 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1478 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1479 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1480 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1481 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1482 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1483 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1484 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1485 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 1486 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 1487 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1488 // CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1489 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1490 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1491 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1492 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1493 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1494 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1495 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1496 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1497 // CHECK11: cond.true: 1498 // CHECK11-NEXT: br label [[COND_END:%.*]] 1499 // CHECK11: cond.false: 1500 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1501 // CHECK11-NEXT: br label [[COND_END]] 1502 // CHECK11: cond.end: 1503 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1504 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1505 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1506 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1507 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1508 // CHECK11: omp.inner.for.cond: 1509 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1510 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 1511 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1512 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1513 // CHECK11: omp.inner.for.body: 1514 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1515 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1516 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1517 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1518 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 1519 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1520 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1521 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1522 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1523 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1524 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1525 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1526 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 1527 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1528 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 1529 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 1530 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 1531 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 1532 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1533 // CHECK11: omp.body.continue: 1534 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1535 // CHECK11: omp.inner.for.inc: 1536 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1537 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 1538 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1539 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1540 // CHECK11: omp.inner.for.end: 1541 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1542 // CHECK11: omp.loop.exit: 1543 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1544 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1545 // CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1546 // CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1547 // CHECK11: .omp.final.then: 1548 // CHECK11-NEXT: store i32 10, i32* [[I]], align 4 1549 // CHECK11-NEXT: store i32 2, i32* [[J]], align 4 1550 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 1551 // CHECK11: .omp.final.done: 1552 // CHECK11-NEXT: ret void 1553 // 1554 // 1555 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1556 // CHECK11-SAME: () #[[ATTR7:[0-9]+]] { 1557 // CHECK11-NEXT: entry: 1558 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 1559 // CHECK11-NEXT: ret void 1560 // 1561 // 1562 // CHECK13-LABEL: define {{[^@]+}}@main 1563 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1564 // CHECK13-NEXT: entry: 1565 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1566 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1567 // CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 1568 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 1569 // CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 1570 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1571 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1572 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1573 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 1574 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1575 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1576 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1577 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1578 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1579 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1580 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 1581 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 1582 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1583 // CHECK13-NEXT: [[I9:%.*]] = alloca i32, align 4 1584 // CHECK13-NEXT: [[J10:%.*]] = alloca i32, align 4 1585 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 1586 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1587 // CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 1588 // CHECK13-NEXT: store i32 100, i32* [[N]], align 4 1589 // CHECK13-NEXT: store i32 2, i32* [[M]], align 4 1590 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1591 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1592 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 1593 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1594 // CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 1595 // CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 1596 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1597 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 1598 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1599 // CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 1600 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 1601 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 1602 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 1603 // CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1604 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1605 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0 1606 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1607 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1608 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1609 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0 1610 // CHECK13-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1611 // CHECK13-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1612 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1613 // CHECK13-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1614 // CHECK13-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 1615 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1616 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 1617 // CHECK13-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_UB]], align 8 1618 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 1619 // CHECK13-NEXT: store i32 0, i32* [[J]], align 4 1620 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1621 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]] 1622 // CHECK13-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 1623 // CHECK13: land.lhs.true: 1624 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1625 // CHECK13-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]] 1626 // CHECK13-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 1627 // CHECK13: simd.if.then: 1628 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1629 // CHECK13-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_IV]], align 8 1630 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1631 // CHECK13: omp.inner.for.cond: 1632 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1633 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !2 1634 // CHECK13-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]] 1635 // CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1636 // CHECK13: omp.inner.for.body: 1637 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1638 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 1639 // CHECK13-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0 1640 // CHECK13-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 1641 // CHECK13-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 1642 // CHECK13-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 1643 // CHECK13-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]] 1644 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 1645 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 1646 // CHECK13-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 1647 // CHECK13-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !2 1648 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1649 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1650 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 1651 // CHECK13-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0 1652 // CHECK13-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 1653 // CHECK13-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 1654 // CHECK13-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 1655 // CHECK13-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]] 1656 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 1657 // CHECK13-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0 1658 // CHECK13-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 1659 // CHECK13-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 1660 // CHECK13-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 1661 // CHECK13-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 1662 // CHECK13-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]] 1663 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 1664 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 1665 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 1666 // CHECK13-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !2 1667 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !2 1668 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 1669 // CHECK13-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 1670 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP23]] 1671 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !2 1672 // CHECK13-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64 1673 // CHECK13-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM33]] 1674 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !2 1675 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1676 // CHECK13: omp.body.continue: 1677 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1678 // CHECK13: omp.inner.for.inc: 1679 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1680 // CHECK13-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1 1681 // CHECK13-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1682 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1683 // CHECK13: omp.inner.for.end: 1684 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1685 // CHECK13-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0 1686 // CHECK13-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 1687 // CHECK13-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1 1688 // CHECK13-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]] 1689 // CHECK13-NEXT: store i32 [[ADD39]], i32* [[I9]], align 4 1690 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1691 // CHECK13-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0 1692 // CHECK13-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 1693 // CHECK13-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 1694 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] 1695 // CHECK13-NEXT: store i32 [[ADD43]], i32* [[J10]], align 4 1696 // CHECK13-NEXT: br label [[SIMD_IF_END]] 1697 // CHECK13: simd.if.end: 1698 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1699 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) 1700 // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1701 // CHECK13-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1702 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 1703 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 1704 // CHECK13-NEXT: ret i32 [[TMP30]] 1705 // 1706 // 1707 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1708 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 1709 // CHECK13-NEXT: entry: 1710 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1711 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1712 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 1713 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1714 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1715 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1716 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1717 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 1718 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 1719 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1720 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1721 // CHECK13-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1722 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1723 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1724 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1725 // CHECK13: omp.inner.for.cond: 1726 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1727 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1728 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1729 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1730 // CHECK13: omp.inner.for.body: 1731 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1732 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 1733 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1734 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1735 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1736 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1737 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1738 // CHECK13-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 1739 // CHECK13-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 1740 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 1741 // CHECK13-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 1742 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 1743 // CHECK13-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !6 1744 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1745 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 1746 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 1747 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !6 1748 // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 1749 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] 1750 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !6 1751 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1752 // CHECK13: omp.body.continue: 1753 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1754 // CHECK13: omp.inner.for.inc: 1755 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1756 // CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 1757 // CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1758 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1759 // CHECK13: omp.inner.for.end: 1760 // CHECK13-NEXT: store i32 10, i32* [[I]], align 4 1761 // CHECK13-NEXT: store i32 2, i32* [[J]], align 4 1762 // CHECK13-NEXT: ret i32 0 1763 // 1764 // 1765 // CHECK15-LABEL: define {{[^@]+}}@main 1766 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1767 // CHECK15-NEXT: entry: 1768 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1769 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1770 // CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 1771 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 1772 // CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 1773 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1774 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1775 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1776 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 1777 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1778 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1779 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1780 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1781 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1782 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1783 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 1784 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 1785 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1786 // CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 1787 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4 1788 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 1789 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1790 // CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 1791 // CHECK15-NEXT: store i32 100, i32* [[N]], align 4 1792 // CHECK15-NEXT: store i32 2, i32* [[M]], align 4 1793 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1794 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 1795 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1796 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1797 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1798 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 1799 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 1800 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 1801 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 1802 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 1803 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[M]], align 4 1804 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1805 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1806 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 1807 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1808 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1809 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1810 // CHECK15-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0 1811 // CHECK15-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1812 // CHECK15-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1813 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1814 // CHECK15-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1815 // CHECK15-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 1816 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1817 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 1818 // CHECK15-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_UB]], align 8 1819 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4 1820 // CHECK15-NEXT: store i32 0, i32* [[J]], align 4 1821 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1822 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1823 // CHECK15-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 1824 // CHECK15: land.lhs.true: 1825 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1826 // CHECK15-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]] 1827 // CHECK15-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 1828 // CHECK15: simd.if.then: 1829 // CHECK15-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1830 // CHECK15-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 1831 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1832 // CHECK15: omp.inner.for.cond: 1833 // CHECK15-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1834 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !3 1835 // CHECK15-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]] 1836 // CHECK15-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1837 // CHECK15: omp.inner.for.body: 1838 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1839 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1840 // CHECK15-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0 1841 // CHECK15-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 1842 // CHECK15-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 1843 // CHECK15-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 1844 // CHECK15-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]] 1845 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 1846 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 1847 // CHECK15-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 1848 // CHECK15-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !3 1849 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1850 // CHECK15-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1851 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1852 // CHECK15-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0 1853 // CHECK15-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 1854 // CHECK15-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 1855 // CHECK15-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 1856 // CHECK15-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]] 1857 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1858 // CHECK15-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0 1859 // CHECK15-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 1860 // CHECK15-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 1861 // CHECK15-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 1862 // CHECK15-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 1863 // CHECK15-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]] 1864 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 1865 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 1866 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 1867 // CHECK15-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !3 1868 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !3 1869 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]] 1870 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP21]] 1871 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !3 1872 // CHECK15-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP22]] 1873 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !3 1874 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1875 // CHECK15: omp.body.continue: 1876 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1877 // CHECK15: omp.inner.for.inc: 1878 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1879 // CHECK15-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1 1880 // CHECK15-NEXT: store i64 [[ADD34]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1881 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1882 // CHECK15: omp.inner.for.end: 1883 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1884 // CHECK15-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0 1885 // CHECK15-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1 1886 // CHECK15-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1 1887 // CHECK15-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]] 1888 // CHECK15-NEXT: store i32 [[ADD38]], i32* [[I9]], align 4 1889 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1890 // CHECK15-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0 1891 // CHECK15-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 1892 // CHECK15-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 1893 // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 1894 // CHECK15-NEXT: store i32 [[ADD42]], i32* [[J10]], align 4 1895 // CHECK15-NEXT: br label [[SIMD_IF_END]] 1896 // CHECK15: simd.if.end: 1897 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1898 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) 1899 // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1900 // CHECK15-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 1901 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) 1902 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 1903 // CHECK15-NEXT: ret i32 [[TMP28]] 1904 // 1905 // 1906 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1907 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 1908 // CHECK15-NEXT: entry: 1909 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1910 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1911 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 1912 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1913 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1914 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1915 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1916 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 1917 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 1918 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1919 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1920 // CHECK15-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1921 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1922 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1923 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1924 // CHECK15: omp.inner.for.cond: 1925 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1926 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1927 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1928 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1929 // CHECK15: omp.inner.for.body: 1930 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1931 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 1932 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1933 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1934 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 1935 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1936 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1937 // CHECK15-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 1938 // CHECK15-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 1939 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 1940 // CHECK15-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 1941 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 1942 // CHECK15-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !7 1943 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1944 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP6]] 1945 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !7 1946 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 1947 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !7 1948 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1949 // CHECK15: omp.body.continue: 1950 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1951 // CHECK15: omp.inner.for.inc: 1952 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1953 // CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1 1954 // CHECK15-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1955 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1956 // CHECK15: omp.inner.for.end: 1957 // CHECK15-NEXT: store i32 10, i32* [[I]], align 4 1958 // CHECK15-NEXT: store i32 2, i32* [[J]], align 4 1959 // CHECK15-NEXT: ret i32 0 1960 // 1961