1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // expected-no-diagnostics 3 #ifndef HEADER 4 #define HEADER 5 6 // Test host codegen. 7 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 8 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 9 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 10 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 11 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 13 14 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 15 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 16 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 17 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 18 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 19 // RUN: %clang_cc1 -no-opaque-pointers -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 20 #ifdef CK1 21 22 template <typename T, int X, long long Y> 23 struct SS{ 24 T a[X][Y]; 25 26 int foo(void) { 27 28 #pragma omp target teams distribute simd collapse(2) 29 for(int i = 0; i < X; i++) { 30 for(int j = 0; j < Y; j++) { 31 a[i][j] = (T)0; 32 } 33 } 34 35 // discard loop variables not needed here 36 37 return a[0][0]; 38 } 39 }; 40 41 int teams_template_struct(void) { 42 SS<int, 123, 456> V; 43 return V.foo(); 44 45 } 46 #endif // CK1 47 48 // Test host codegen. 49 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 50 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 51 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 52 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 55 56 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 58 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15 60 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 61 // RUN: %clang_cc1 -no-opaque-pointers -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15 62 #ifdef CK2 63 64 template <typename T, int n, int m> 65 int tmain(T argc) { 66 T a[n][m]; 67 #pragma omp target teams distribute simd collapse(2) 68 for(int i = 0; i < n; i++) { 69 for(int j = 0; j < m; j++) { 70 a[i][j] = (T)0; 71 } 72 } 73 return 0; 74 } 75 76 int main (int argc, char **argv) { 77 int n = 100; 78 int m = 2; 79 int a[n][m]; 80 #pragma omp target teams distribute simd collapse(2) 81 for(int i = 0; i < n; i++) { 82 for(int j = 0; j < m; j++) { 83 a[i][j] = 0; 84 } 85 } 86 return tmain<int, 10, 2>(argc); 87 } 88 89 90 91 92 93 // discard loop variables not needed here 94 95 #endif // CK2 96 #endif // #ifndef HEADER 97 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv 98 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 99 // CHECK1-NEXT: entry: 100 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 101 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 102 // CHECK1-NEXT: ret i32 [[CALL]] 103 // 104 // 105 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 106 // CHECK1-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 107 // CHECK1-NEXT: entry: 108 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 109 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 110 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 111 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 112 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 113 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 114 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 115 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 116 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 117 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 118 // CHECK1-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 119 // CHECK1-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 8 120 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 121 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 122 // CHECK1-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 8 123 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 124 // CHECK1-NEXT: store i8* null, i8** [[TMP4]], align 8 125 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 126 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 127 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 128 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 129 // CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 130 // CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 131 // CHECK1: omp_offload.failed: 132 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR3:[0-9]+]] 133 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 134 // CHECK1: omp_offload.cont: 135 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 136 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i64 0, i64 0 137 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 0 138 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 139 // CHECK1-NEXT: ret i32 [[TMP9]] 140 // 141 // 142 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 143 // CHECK1-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 144 // CHECK1-NEXT: entry: 145 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 146 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 147 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 148 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 149 // CHECK1-NEXT: ret void 150 // 151 // 152 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 153 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { 154 // CHECK1-NEXT: entry: 155 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 156 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 157 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 158 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 159 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 160 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 161 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 162 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 163 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 165 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 166 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 167 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 168 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 169 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 170 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 171 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 172 // CHECK1-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 173 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 174 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 175 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 176 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 177 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 178 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 179 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 180 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 181 // CHECK1: cond.true: 182 // CHECK1-NEXT: br label [[COND_END:%.*]] 183 // CHECK1: cond.false: 184 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 185 // CHECK1-NEXT: br label [[COND_END]] 186 // CHECK1: cond.end: 187 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 188 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 189 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 190 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 191 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 192 // CHECK1: omp.inner.for.cond: 193 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 194 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !4 195 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 196 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 197 // CHECK1: omp.inner.for.body: 198 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 199 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 200 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 201 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 202 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !4 203 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 204 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 205 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 206 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 207 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 208 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 209 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 210 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !4 211 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 212 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !4 213 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 214 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 215 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !4 216 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 217 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 218 // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !4 219 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 220 // CHECK1: omp.body.continue: 221 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 222 // CHECK1: omp.inner.for.inc: 223 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 224 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 225 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !4 226 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 227 // CHECK1: omp.inner.for.end: 228 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 229 // CHECK1: omp.loop.exit: 230 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 231 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 232 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 233 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 234 // CHECK1: .omp.final.then: 235 // CHECK1-NEXT: store i32 123, i32* [[I]], align 4 236 // CHECK1-NEXT: store i32 456, i32* [[J]], align 4 237 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 238 // CHECK1: .omp.final.done: 239 // CHECK1-NEXT: ret void 240 // 241 // 242 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 243 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 244 // CHECK1-NEXT: entry: 245 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 246 // CHECK1-NEXT: ret void 247 // 248 // 249 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv 250 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 251 // CHECK3-NEXT: entry: 252 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 253 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 254 // CHECK3-NEXT: ret i32 [[CALL]] 255 // 256 // 257 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 258 // CHECK3-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 259 // CHECK3-NEXT: entry: 260 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 261 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 262 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 263 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 264 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 265 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 266 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 267 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 268 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 269 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 270 // CHECK3-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to %struct.SS** 271 // CHECK3-NEXT: store %struct.SS* [[THIS1]], %struct.SS** [[TMP1]], align 4 272 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 273 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [123 x [456 x i32]]** 274 // CHECK3-NEXT: store [123 x [456 x i32]]* [[A]], [123 x [456 x i32]]** [[TMP3]], align 4 275 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 276 // CHECK3-NEXT: store i8* null, i8** [[TMP4]], align 4 277 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 278 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 279 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 56088) 280 // CHECK3-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 281 // CHECK3-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 282 // CHECK3-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 283 // CHECK3: omp_offload.failed: 284 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(%struct.SS* [[THIS1]]) #[[ATTR3:[0-9]+]] 285 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 286 // CHECK3: omp_offload.cont: 287 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 288 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A3]], i32 0, i32 0 289 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 0 290 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4 291 // CHECK3-NEXT: ret i32 [[TMP9]] 292 // 293 // 294 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28 295 // CHECK3-SAME: (%struct.SS* noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] { 296 // CHECK3-NEXT: entry: 297 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 298 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 299 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 300 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[TMP0]]) 301 // CHECK3-NEXT: ret void 302 // 303 // 304 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 305 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.SS* noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] { 306 // CHECK3-NEXT: entry: 307 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 308 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 309 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 310 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 311 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 312 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 313 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 314 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 315 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 316 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 317 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 318 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 319 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 320 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 321 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 322 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 323 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 324 // CHECK3-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 325 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 326 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 327 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 328 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 329 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 330 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 331 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087 332 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 333 // CHECK3: cond.true: 334 // CHECK3-NEXT: br label [[COND_END:%.*]] 335 // CHECK3: cond.false: 336 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 337 // CHECK3-NEXT: br label [[COND_END]] 338 // CHECK3: cond.end: 339 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 340 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 341 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 342 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 343 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 344 // CHECK3: omp.inner.for.cond: 345 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 346 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !5 347 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 348 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 349 // CHECK3: omp.inner.for.body: 350 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 351 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 352 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 353 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 354 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !5 355 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 356 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 357 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 358 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 359 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 360 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 361 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 362 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !5 363 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[TMP0]], i32 0, i32 0 364 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !5 365 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP11]] 366 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !5 367 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 368 // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !5 369 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 370 // CHECK3: omp.body.continue: 371 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 372 // CHECK3: omp.inner.for.inc: 373 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 374 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 375 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !5 376 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 377 // CHECK3: omp.inner.for.end: 378 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 379 // CHECK3: omp.loop.exit: 380 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 381 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 382 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 383 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 384 // CHECK3: .omp.final.then: 385 // CHECK3-NEXT: store i32 123, i32* [[I]], align 4 386 // CHECK3-NEXT: store i32 456, i32* [[J]], align 4 387 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 388 // CHECK3: .omp.final.done: 389 // CHECK3-NEXT: ret void 390 // 391 // 392 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 393 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 394 // CHECK3-NEXT: entry: 395 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 396 // CHECK3-NEXT: ret void 397 // 398 // 399 // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv 400 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 401 // CHECK5-NEXT: entry: 402 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 403 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 404 // CHECK5-NEXT: ret i32 [[CALL]] 405 // 406 // 407 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 408 // CHECK5-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 409 // CHECK5-NEXT: entry: 410 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 411 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 412 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 413 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 414 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 415 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 416 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 417 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4 418 // CHECK5-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 419 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 420 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 421 // CHECK5-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 422 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 423 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 424 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 425 // CHECK5: omp.inner.for.cond: 426 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 427 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 428 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 429 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 430 // CHECK5: omp.inner.for.body: 431 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 432 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 433 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 434 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 435 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 436 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 437 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 438 // CHECK5-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 439 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 440 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 441 // CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 442 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 443 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !2 444 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 445 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2 446 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 447 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 448 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !2 449 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 450 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 451 // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !2 452 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 453 // CHECK5: omp.body.continue: 454 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 455 // CHECK5: omp.inner.for.inc: 456 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 457 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 458 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 459 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 460 // CHECK5: omp.inner.for.end: 461 // CHECK5-NEXT: store i32 123, i32* [[I]], align 4 462 // CHECK5-NEXT: store i32 456, i32* [[J]], align 4 463 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 464 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A10]], i64 0, i64 0 465 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX11]], i64 0, i64 0 466 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX12]], align 4 467 // CHECK5-NEXT: ret i32 [[TMP9]] 468 // 469 // 470 // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv 471 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 472 // CHECK7-NEXT: entry: 473 // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 474 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[V]]) 475 // CHECK7-NEXT: ret i32 [[CALL]] 476 // 477 // 478 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv 479 // CHECK7-SAME: (%struct.SS* noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 { 480 // CHECK7-NEXT: entry: 481 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 482 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 483 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 484 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 485 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 486 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 487 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 488 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4 489 // CHECK7-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 490 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 491 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 492 // CHECK7-NEXT: store i32 56087, i32* [[DOTOMP_UB]], align 4 493 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 494 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 495 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 496 // CHECK7: omp.inner.for.cond: 497 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 498 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 499 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 500 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 501 // CHECK7: omp.inner.for.body: 502 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 503 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456 504 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 505 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 506 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 507 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 508 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 509 // CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456 510 // CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 511 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]] 512 // CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 513 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 514 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !3 515 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 516 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3 517 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A]], i32 0, i32 [[TMP6]] 518 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !3 519 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 520 // CHECK7-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !3 521 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 522 // CHECK7: omp.body.continue: 523 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 524 // CHECK7: omp.inner.for.inc: 525 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 526 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 527 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 528 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 529 // CHECK7: omp.inner.for.end: 530 // CHECK7-NEXT: store i32 123, i32* [[I]], align 4 531 // CHECK7-NEXT: store i32 456, i32* [[J]], align 4 532 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 533 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], [123 x [456 x i32]]* [[A9]], i32 0, i32 0 534 // CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], [456 x i32]* [[ARRAYIDX10]], i32 0, i32 0 535 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[ARRAYIDX11]], align 4 536 // CHECK7-NEXT: ret i32 [[TMP9]] 537 // 538 // 539 // CHECK9-LABEL: define {{[^@]+}}@main 540 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 541 // CHECK9-NEXT: entry: 542 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 543 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 544 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 545 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4 546 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4 547 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 548 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 549 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 550 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 551 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 552 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 553 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 554 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 555 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 556 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 557 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 558 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 559 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 560 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i64, align 8 561 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 562 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 563 // CHECK9-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 564 // CHECK9-NEXT: store i32 100, i32* [[N]], align 4 565 // CHECK9-NEXT: store i32 2, i32* [[M]], align 4 566 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 567 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 568 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 569 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 570 // CHECK9-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 571 // CHECK9-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 572 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 573 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 574 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 575 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 576 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 577 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 578 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 579 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[N_CASTED]], align 8 580 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[M]], align 4 581 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[M_CASTED]] to i32* 582 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV1]], align 4 583 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[M_CASTED]], align 8 584 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 585 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4 586 // CHECK9-NEXT: [[TMP12:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 587 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP12]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes to i8*), i64 40, i1 false) 588 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 589 // CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 590 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP14]], align 8 591 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 592 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 593 // CHECK9-NEXT: store i64 [[TMP7]], i64* [[TMP16]], align 8 594 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 595 // CHECK9-NEXT: store i8* null, i8** [[TMP17]], align 8 596 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 597 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 598 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP19]], align 8 599 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 600 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 601 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[TMP21]], align 8 602 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 603 // CHECK9-NEXT: store i8* null, i8** [[TMP22]], align 8 604 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 605 // CHECK9-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 606 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP24]], align 8 607 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 608 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 609 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[TMP26]], align 8 610 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 611 // CHECK9-NEXT: store i8* null, i8** [[TMP27]], align 8 612 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 613 // CHECK9-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 614 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP29]], align 8 615 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 616 // CHECK9-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 617 // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP31]], align 8 618 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 619 // CHECK9-NEXT: store i8* null, i8** [[TMP32]], align 8 620 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 621 // CHECK9-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i32** 622 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP34]], align 8 623 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 624 // CHECK9-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32** 625 // CHECK9-NEXT: store i32* [[VLA]], i32** [[TMP36]], align 8 626 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 627 // CHECK9-NEXT: store i64 [[TMP11]], i64* [[TMP37]], align 8 628 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 629 // CHECK9-NEXT: store i8* null, i8** [[TMP38]], align 8 630 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 631 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 632 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 633 // CHECK9-NEXT: [[TMP42:%.*]] = load i32, i32* [[N]], align 4 634 // CHECK9-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 635 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[M]], align 4 636 // CHECK9-NEXT: store i32 [[TMP43]], i32* [[DOTCAPTURE_EXPR_3]], align 4 637 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 638 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP44]], 0 639 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 640 // CHECK9-NEXT: [[CONV5:%.*]] = sext i32 [[DIV]] to i64 641 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 642 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP45]], 0 643 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 644 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 645 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV5]], [[CONV8]] 646 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 647 // CHECK9-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_4]], align 8 648 // CHECK9-NEXT: [[TMP46:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_4]], align 8 649 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP46]], 1 650 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 651 // CHECK9-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP39]], i8** [[TMP40]], i64* [[TMP41]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 652 // CHECK9-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 653 // CHECK9-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 654 // CHECK9: omp_offload.failed: 655 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], i32* [[VLA]]) #[[ATTR4:[0-9]+]] 656 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 657 // CHECK9: omp_offload.cont: 658 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 659 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP49]]) 660 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 661 // CHECK9-NEXT: [[TMP50:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 662 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP50]]) 663 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, i32* [[RETVAL]], align 4 664 // CHECK9-NEXT: ret i32 [[TMP51]] 665 // 666 // 667 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 668 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 669 // CHECK9-NEXT: entry: 670 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 671 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 672 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 673 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 674 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 675 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 676 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8 677 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 678 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 679 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 680 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 681 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 682 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 683 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 684 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 685 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 686 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 687 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 688 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[N_CASTED]] to i32* 689 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV4]], align 4 690 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 691 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV3]], align 4 692 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[M_CASTED]] to i32* 693 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV5]], align 4 694 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[M_CASTED]], align 8 695 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i64, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], i32* [[TMP2]]) 696 // CHECK9-NEXT: ret void 697 // 698 // 699 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 700 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { 701 // CHECK9-NEXT: entry: 702 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 703 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 704 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 705 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8 706 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 707 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 708 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 709 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 710 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 711 // CHECK9-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 712 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 713 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 714 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i64, align 8 715 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 716 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 717 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 718 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 719 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 720 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 721 // CHECK9-NEXT: [[I13:%.*]] = alloca i32, align 4 722 // CHECK9-NEXT: [[J14:%.*]] = alloca i32, align 4 723 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 724 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 725 // CHECK9-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 726 // CHECK9-NEXT: store i64 [[M]], i64* [[M_ADDR]], align 8 727 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 728 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 729 // CHECK9-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 730 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 731 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[M_ADDR]] to i32* 732 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 733 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 734 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 8 735 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 736 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 737 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV3]], align 4 738 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_5]], align 4 739 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 740 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 741 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 742 // CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[DIV]] to i64 743 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 744 // CHECK9-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP6]], 0 745 // CHECK9-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1 746 // CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[DIV9]] to i64 747 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV7]], [[CONV10]] 748 // CHECK9-NEXT: [[SUB11:%.*]] = sub nsw i64 [[MUL]], 1 749 // CHECK9-NEXT: store i64 [[SUB11]], i64* [[DOTCAPTURE_EXPR_6]], align 8 750 // CHECK9-NEXT: store i32 0, i32* [[I]], align 4 751 // CHECK9-NEXT: store i32 0, i32* [[J]], align 4 752 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 753 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 754 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 755 // CHECK9: land.lhs.true: 756 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 757 // CHECK9-NEXT: [[CMP12:%.*]] = icmp slt i32 0, [[TMP8]] 758 // CHECK9-NEXT: br i1 [[CMP12]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 759 // CHECK9: omp.precond.then: 760 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 761 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 762 // CHECK9-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 763 // CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 764 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 765 // CHECK9-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 766 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 767 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 768 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 769 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 770 // CHECK9-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 771 // CHECK9-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 772 // CHECK9: cond.true: 773 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_6]], align 8 774 // CHECK9-NEXT: br label [[COND_END:%.*]] 775 // CHECK9: cond.false: 776 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 777 // CHECK9-NEXT: br label [[COND_END]] 778 // CHECK9: cond.end: 779 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 780 // CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 781 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 782 // CHECK9-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 783 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 784 // CHECK9: omp.inner.for.cond: 785 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 786 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 787 // CHECK9-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 788 // CHECK9-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 789 // CHECK9: omp.inner.for.body: 790 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 791 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 792 // CHECK9-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP20]], 0 793 // CHECK9-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 794 // CHECK9-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] 795 // CHECK9-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 796 // CHECK9-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP19]], [[CONV20]] 797 // CHECK9-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 798 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] 799 // CHECK9-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 800 // CHECK9-NEXT: store i32 [[CONV23]], i32* [[I13]], align 4, !llvm.access.group !5 801 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 802 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 803 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 804 // CHECK9-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP23]], 0 805 // CHECK9-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 806 // CHECK9-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 807 // CHECK9-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 808 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP22]], [[CONV27]] 809 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4, !llvm.access.group !5 810 // CHECK9-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP24]], 0 811 // CHECK9-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 812 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] 813 // CHECK9-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 814 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] 815 // CHECK9-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP21]], [[MUL33]] 816 // CHECK9-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 817 // CHECK9-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] 818 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 819 // CHECK9-NEXT: store i32 [[CONV37]], i32* [[J14]], align 4, !llvm.access.group !5 820 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[I13]], align 4, !llvm.access.group !5 821 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64 822 // CHECK9-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]] 823 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i64 [[TMP26]] 824 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[J14]], align 4, !llvm.access.group !5 825 // CHECK9-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP27]] to i64 826 // CHECK9-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM38]] 827 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX39]], align 4, !llvm.access.group !5 828 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 829 // CHECK9: omp.body.continue: 830 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 831 // CHECK9: omp.inner.for.inc: 832 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 833 // CHECK9-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP28]], 1 834 // CHECK9-NEXT: store i64 [[ADD40]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 835 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 836 // CHECK9: omp.inner.for.end: 837 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 838 // CHECK9: omp.loop.exit: 839 // CHECK9-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 840 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 841 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 842 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 843 // CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 844 // CHECK9-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 845 // CHECK9: .omp.final.then: 846 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 847 // CHECK9-NEXT: [[SUB41:%.*]] = sub nsw i32 [[TMP33]], 0 848 // CHECK9-NEXT: [[DIV42:%.*]] = sdiv i32 [[SUB41]], 1 849 // CHECK9-NEXT: [[MUL43:%.*]] = mul nsw i32 [[DIV42]], 1 850 // CHECK9-NEXT: [[ADD44:%.*]] = add nsw i32 0, [[MUL43]] 851 // CHECK9-NEXT: store i32 [[ADD44]], i32* [[I13]], align 4 852 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 853 // CHECK9-NEXT: [[SUB45:%.*]] = sub nsw i32 [[TMP34]], 0 854 // CHECK9-NEXT: [[DIV46:%.*]] = sdiv i32 [[SUB45]], 1 855 // CHECK9-NEXT: [[MUL47:%.*]] = mul nsw i32 [[DIV46]], 1 856 // CHECK9-NEXT: [[ADD48:%.*]] = add nsw i32 0, [[MUL47]] 857 // CHECK9-NEXT: store i32 [[ADD48]], i32* [[J14]], align 4 858 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 859 // CHECK9: .omp.final.done: 860 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 861 // CHECK9: omp.precond.end: 862 // CHECK9-NEXT: ret void 863 // 864 // 865 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 866 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { 867 // CHECK9-NEXT: entry: 868 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 869 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 870 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 871 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 872 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 873 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 874 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 875 // CHECK9-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 876 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 877 // CHECK9-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 878 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 8 879 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 880 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 881 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 8 882 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 883 // CHECK9-NEXT: store i8* null, i8** [[TMP4]], align 8 884 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 885 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 886 // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 887 // CHECK9-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 888 // CHECK9-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 889 // CHECK9-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 890 // CHECK9: omp_offload.failed: 891 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR4]] 892 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 893 // CHECK9: omp_offload.cont: 894 // CHECK9-NEXT: ret i32 0 895 // 896 // 897 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 898 // CHECK9-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 899 // CHECK9-NEXT: entry: 900 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 901 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 902 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 903 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 904 // CHECK9-NEXT: ret void 905 // 906 // 907 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 908 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { 909 // CHECK9-NEXT: entry: 910 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 911 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 912 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 8 913 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 914 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 915 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 916 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 917 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 918 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 919 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 920 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 921 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 922 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 923 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 924 // CHECK9-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 8 925 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 8 926 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 927 // CHECK9-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 928 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 929 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 930 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 931 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 932 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 933 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 934 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 935 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 936 // CHECK9: cond.true: 937 // CHECK9-NEXT: br label [[COND_END:%.*]] 938 // CHECK9: cond.false: 939 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 940 // CHECK9-NEXT: br label [[COND_END]] 941 // CHECK9: cond.end: 942 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 943 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 944 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 945 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 946 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 947 // CHECK9: omp.inner.for.cond: 948 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 949 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 950 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 951 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 952 // CHECK9: omp.inner.for.body: 953 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 954 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 955 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 956 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 957 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 958 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 959 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 960 // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 961 // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 962 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 963 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 964 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 965 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !11 966 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !11 967 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 968 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i64 0, i64 [[IDXPROM]] 969 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !11 970 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 971 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] 972 // CHECK9-NEXT: store i32 0, i32* [[ARRAYIDX8]], align 4, !llvm.access.group !11 973 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 974 // CHECK9: omp.body.continue: 975 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 976 // CHECK9: omp.inner.for.inc: 977 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 978 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 979 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 980 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 981 // CHECK9: omp.inner.for.end: 982 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 983 // CHECK9: omp.loop.exit: 984 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 985 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 986 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 987 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 988 // CHECK9: .omp.final.then: 989 // CHECK9-NEXT: store i32 10, i32* [[I]], align 4 990 // CHECK9-NEXT: store i32 2, i32* [[J]], align 4 991 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 992 // CHECK9: .omp.final.done: 993 // CHECK9-NEXT: ret void 994 // 995 // 996 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 997 // CHECK9-SAME: () #[[ATTR7:[0-9]+]] { 998 // CHECK9-NEXT: entry: 999 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1000 // CHECK9-NEXT: ret void 1001 // 1002 // 1003 // CHECK11-LABEL: define {{[^@]+}}@main 1004 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1005 // CHECK11-NEXT: entry: 1006 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1007 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1008 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 1009 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4 1010 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4 1011 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1012 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1013 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1014 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1015 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1016 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1017 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1018 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1019 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 1020 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1021 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1022 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1023 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1024 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1025 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1026 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1027 // CHECK11-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 1028 // CHECK11-NEXT: store i32 100, i32* [[N]], align 4 1029 // CHECK11-NEXT: store i32 2, i32* [[M]], align 4 1030 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1031 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 1032 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1033 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1034 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1035 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 1036 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 1037 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 1038 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 1039 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 1040 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 1041 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M]], align 4 1042 // CHECK11-NEXT: store i32 [[TMP6]], i32* [[M_CASTED]], align 4 1043 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[M_CASTED]], align 4 1044 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1045 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4 1046 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64 1047 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1048 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes to i8*), i32 40, i1 false) 1049 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1050 // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 1051 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP13]], align 4 1052 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1053 // CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1054 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[TMP15]], align 4 1055 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1056 // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 1057 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1058 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 1059 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP18]], align 4 1060 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1061 // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1062 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[TMP20]], align 4 1063 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1064 // CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 1065 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1066 // CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 1067 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP23]], align 4 1068 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1069 // CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1070 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[TMP25]], align 4 1071 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1072 // CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 1073 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1074 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1075 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4 1076 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1077 // CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1078 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 1079 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1080 // CHECK11-NEXT: store i8* null, i8** [[TMP31]], align 4 1081 // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1082 // CHECK11-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32** 1083 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP33]], align 4 1084 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1085 // CHECK11-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32** 1086 // CHECK11-NEXT: store i32* [[VLA]], i32** [[TMP35]], align 4 1087 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1088 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[TMP36]], align 4 1089 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1090 // CHECK11-NEXT: store i8* null, i8** [[TMP37]], align 4 1091 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1092 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1093 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1094 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[N]], align 4 1095 // CHECK11-NEXT: store i32 [[TMP41]], i32* [[DOTCAPTURE_EXPR_]], align 4 1096 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, i32* [[M]], align 4 1097 // CHECK11-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1098 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1099 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP43]], 0 1100 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1101 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1102 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1103 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP44]], 0 1104 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1105 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1106 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1107 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1108 // CHECK11-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 1109 // CHECK11-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 1110 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP45]], 1 1111 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 [[ADD]]) 1112 // CHECK11-NEXT: [[TMP46:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, i32 5, i8** [[TMP38]], i8** [[TMP39]], i64* [[TMP40]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1113 // CHECK11-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 1114 // CHECK11-NEXT: br i1 [[TMP47]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1115 // CHECK11: omp_offload.failed: 1116 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], i32* [[VLA]]) #[[ATTR4:[0-9]+]] 1117 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1118 // CHECK11: omp_offload.cont: 1119 // CHECK11-NEXT: [[TMP48:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1120 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP48]]) 1121 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1122 // CHECK11-NEXT: [[TMP49:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 1123 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP49]]) 1124 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, i32* [[RETVAL]], align 4 1125 // CHECK11-NEXT: ret i32 [[TMP50]] 1126 // 1127 // 1128 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 1129 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { 1130 // CHECK11-NEXT: entry: 1131 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1132 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 1133 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1134 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1135 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 1136 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 1137 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4 1138 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1139 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 1140 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1141 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1142 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 1143 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1144 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1145 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 1146 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1147 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 1148 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 1149 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[M_ADDR]], align 4 1150 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[M_CASTED]], align 4 1151 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[M_CASTED]], align 4 1152 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, i32, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], i32* [[TMP2]]) 1153 // CHECK11-NEXT: ret void 1154 // 1155 // 1156 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 1157 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] { 1158 // CHECK11-NEXT: entry: 1159 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1160 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1161 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1162 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4 1163 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1164 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1165 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 4 1166 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1167 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1168 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 1169 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1170 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 1171 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 1172 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1173 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1174 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1175 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1176 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1177 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1178 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4 1179 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4 1180 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1181 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1182 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1183 // CHECK11-NEXT: store i32 [[M]], i32* [[M_ADDR]], align 4 1184 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1185 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1186 // CHECK11-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 4 1187 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1188 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1189 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A_ADDR]], align 4 1190 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1191 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTCAPTURE_EXPR_]], align 4 1192 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[M_ADDR]], align 4 1193 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_4]], align 4 1194 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1195 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 1196 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1197 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1198 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1199 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0 1200 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 1201 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 1202 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] 1203 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 1204 // CHECK11-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8 1205 // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 1206 // CHECK11-NEXT: store i32 0, i32* [[J]], align 4 1207 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1208 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]] 1209 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 1210 // CHECK11: land.lhs.true: 1211 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1212 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]] 1213 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 1214 // CHECK11: omp.precond.then: 1215 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1216 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1217 // CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 1218 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1219 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1220 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1221 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 1222 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1223 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1224 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1225 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 1226 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1227 // CHECK11: cond.true: 1228 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8 1229 // CHECK11-NEXT: br label [[COND_END:%.*]] 1230 // CHECK11: cond.false: 1231 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1232 // CHECK11-NEXT: br label [[COND_END]] 1233 // CHECK11: cond.end: 1234 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 1235 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1236 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1237 // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 1238 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1239 // CHECK11: omp.inner.for.cond: 1240 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1241 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !6 1242 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 1243 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1244 // CHECK11: omp.inner.for.body: 1245 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1246 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 1247 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0 1248 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 1249 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] 1250 // CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 1251 // CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]] 1252 // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 1253 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] 1254 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 1255 // CHECK11-NEXT: store i32 [[CONV21]], i32* [[I11]], align 4, !llvm.access.group !6 1256 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1257 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1258 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 1259 // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0 1260 // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 1261 // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] 1262 // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 1263 // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]] 1264 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group !6 1265 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0 1266 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 1267 // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] 1268 // CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 1269 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] 1270 // CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]] 1271 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 1272 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] 1273 // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 1274 // CHECK11-NEXT: store i32 [[CONV35]], i32* [[J12]], align 4, !llvm.access.group !6 1275 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[I11]], align 4, !llvm.access.group !6 1276 // CHECK11-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]] 1277 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 [[TMP26]] 1278 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[J12]], align 4, !llvm.access.group !6 1279 // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP27]] 1280 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX36]], align 4, !llvm.access.group !6 1281 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1282 // CHECK11: omp.body.continue: 1283 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1284 // CHECK11: omp.inner.for.inc: 1285 // CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1286 // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1 1287 // CHECK11-NEXT: store i64 [[ADD37]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !6 1288 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1289 // CHECK11: omp.inner.for.end: 1290 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1291 // CHECK11: omp.loop.exit: 1292 // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1293 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 1294 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 1295 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1296 // CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1297 // CHECK11-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1298 // CHECK11: .omp.final.then: 1299 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1300 // CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i32 [[TMP33]], 0 1301 // CHECK11-NEXT: [[DIV39:%.*]] = sdiv i32 [[SUB38]], 1 1302 // CHECK11-NEXT: [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 1 1303 // CHECK11-NEXT: [[ADD41:%.*]] = add nsw i32 0, [[MUL40]] 1304 // CHECK11-NEXT: store i32 [[ADD41]], i32* [[I11]], align 4 1305 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 1306 // CHECK11-NEXT: [[SUB42:%.*]] = sub nsw i32 [[TMP34]], 0 1307 // CHECK11-NEXT: [[DIV43:%.*]] = sdiv i32 [[SUB42]], 1 1308 // CHECK11-NEXT: [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 1 1309 // CHECK11-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]] 1310 // CHECK11-NEXT: store i32 [[ADD45]], i32* [[J12]], align 4 1311 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 1312 // CHECK11: .omp.final.done: 1313 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 1314 // CHECK11: omp.precond.end: 1315 // CHECK11-NEXT: ret void 1316 // 1317 // 1318 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1319 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR6:[0-9]+]] comdat { 1320 // CHECK11-NEXT: entry: 1321 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1322 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1323 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1324 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1325 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1326 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1327 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1328 // CHECK11-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1329 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1330 // CHECK11-NEXT: [[TMP1:%.*]] = bitcast i8** [[TMP0]] to [10 x [2 x i32]]** 1331 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP1]], align 4 1332 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1333 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to [10 x [2 x i32]]** 1334 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[TMP3]], align 4 1335 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1336 // CHECK11-NEXT: store i8* null, i8** [[TMP4]], align 4 1337 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1338 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1339 // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 20) 1340 // CHECK11-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, i32 1, i8** [[TMP5]], i8** [[TMP6]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 1) 1341 // CHECK11-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0 1342 // CHECK11-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1343 // CHECK11: omp_offload.failed: 1344 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67([10 x [2 x i32]]* [[A]]) #[[ATTR4]] 1345 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1346 // CHECK11: omp_offload.cont: 1347 // CHECK11-NEXT: ret i32 0 1348 // 1349 // 1350 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67 1351 // CHECK11-SAME: ([10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { 1352 // CHECK11-NEXT: entry: 1353 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 1354 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 1355 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 1356 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x [2 x i32]]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x [2 x i32]]* [[TMP0]]) 1357 // CHECK11-NEXT: ret void 1358 // 1359 // 1360 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 1361 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x [2 x i32]]* noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR3]] { 1362 // CHECK11-NEXT: entry: 1363 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1364 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1365 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [10 x [2 x i32]]*, align 4 1366 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1367 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 1368 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1369 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1370 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1371 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1372 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1373 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 1374 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 1375 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1376 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1377 // CHECK11-NEXT: store [10 x [2 x i32]]* [[A]], [10 x [2 x i32]]** [[A_ADDR]], align 4 1378 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x [2 x i32]]*, [10 x [2 x i32]]** [[A_ADDR]], align 4 1379 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1380 // CHECK11-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1381 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1382 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1383 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1384 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1385 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1386 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1387 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19 1388 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1389 // CHECK11: cond.true: 1390 // CHECK11-NEXT: br label [[COND_END:%.*]] 1391 // CHECK11: cond.false: 1392 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1393 // CHECK11-NEXT: br label [[COND_END]] 1394 // CHECK11: cond.end: 1395 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1396 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1397 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1398 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 1399 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1400 // CHECK11: omp.inner.for.cond: 1401 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1402 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 1403 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1404 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1405 // CHECK11: omp.inner.for.body: 1406 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1407 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 1408 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1409 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1410 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 1411 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1412 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1413 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 1414 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 1415 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] 1416 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 1417 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] 1418 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[J]], align 4, !llvm.access.group !12 1419 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !12 1420 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[TMP0]], i32 0, i32 [[TMP11]] 1421 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !12 1422 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP12]] 1423 // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !12 1424 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1425 // CHECK11: omp.body.continue: 1426 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1427 // CHECK11: omp.inner.for.inc: 1428 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1429 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 1430 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 1431 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1432 // CHECK11: omp.inner.for.end: 1433 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1434 // CHECK11: omp.loop.exit: 1435 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1436 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1437 // CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 1438 // CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1439 // CHECK11: .omp.final.then: 1440 // CHECK11-NEXT: store i32 10, i32* [[I]], align 4 1441 // CHECK11-NEXT: store i32 2, i32* [[J]], align 4 1442 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] 1443 // CHECK11: .omp.final.done: 1444 // CHECK11-NEXT: ret void 1445 // 1446 // 1447 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1448 // CHECK11-SAME: () #[[ATTR7:[0-9]+]] { 1449 // CHECK11-NEXT: entry: 1450 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 1451 // CHECK11-NEXT: ret void 1452 // 1453 // 1454 // CHECK13-LABEL: define {{[^@]+}}@main 1455 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1456 // CHECK13-NEXT: entry: 1457 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1458 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1459 // CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 8 1460 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4 1461 // CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4 1462 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1463 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1464 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1465 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 1466 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1467 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1468 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1469 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1470 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1471 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1472 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 1473 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 1474 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1475 // CHECK13-NEXT: [[I9:%.*]] = alloca i32, align 4 1476 // CHECK13-NEXT: [[J10:%.*]] = alloca i32, align 4 1477 // CHECK13-NEXT: store i32 0, i32* [[RETVAL]], align 4 1478 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1479 // CHECK13-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 8 1480 // CHECK13-NEXT: store i32 100, i32* [[N]], align 4 1481 // CHECK13-NEXT: store i32 2, i32* [[M]], align 4 1482 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1483 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1484 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[M]], align 4 1485 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1486 // CHECK13-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 1487 // CHECK13-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8 1488 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] 1489 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 1490 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1491 // CHECK13-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 1492 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N]], align 4 1493 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_]], align 4 1494 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[M]], align 4 1495 // CHECK13-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1496 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1497 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0 1498 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1499 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1500 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1501 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0 1502 // CHECK13-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1503 // CHECK13-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1504 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1505 // CHECK13-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1506 // CHECK13-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 1507 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1508 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 1509 // CHECK13-NEXT: store i64 [[TMP10]], i64* [[DOTOMP_UB]], align 8 1510 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 1511 // CHECK13-NEXT: store i32 0, i32* [[J]], align 4 1512 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1513 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]] 1514 // CHECK13-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 1515 // CHECK13: land.lhs.true: 1516 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1517 // CHECK13-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]] 1518 // CHECK13-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 1519 // CHECK13: simd.if.then: 1520 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1521 // CHECK13-NEXT: store i64 [[TMP13]], i64* [[DOTOMP_IV]], align 8 1522 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1523 // CHECK13: omp.inner.for.cond: 1524 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1525 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !2 1526 // CHECK13-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]] 1527 // CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1528 // CHECK13: omp.inner.for.body: 1529 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1530 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 1531 // CHECK13-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0 1532 // CHECK13-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 1533 // CHECK13-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 1534 // CHECK13-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 1535 // CHECK13-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]] 1536 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 1537 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 1538 // CHECK13-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 1539 // CHECK13-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !2 1540 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1541 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1542 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 1543 // CHECK13-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0 1544 // CHECK13-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 1545 // CHECK13-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 1546 // CHECK13-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 1547 // CHECK13-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]] 1548 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !2 1549 // CHECK13-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0 1550 // CHECK13-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 1551 // CHECK13-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 1552 // CHECK13-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 1553 // CHECK13-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 1554 // CHECK13-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]] 1555 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 1556 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 1557 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 1558 // CHECK13-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !2 1559 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !2 1560 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 1561 // CHECK13-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] 1562 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i64 [[TMP23]] 1563 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !2 1564 // CHECK13-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64 1565 // CHECK13-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i64 [[IDXPROM33]] 1566 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX34]], align 4, !llvm.access.group !2 1567 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1568 // CHECK13: omp.body.continue: 1569 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1570 // CHECK13: omp.inner.for.inc: 1571 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1572 // CHECK13-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1 1573 // CHECK13-NEXT: store i64 [[ADD35]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !2 1574 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1575 // CHECK13: omp.inner.for.end: 1576 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1577 // CHECK13-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0 1578 // CHECK13-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1 1579 // CHECK13-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1 1580 // CHECK13-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]] 1581 // CHECK13-NEXT: store i32 [[ADD39]], i32* [[I9]], align 4 1582 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1583 // CHECK13-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0 1584 // CHECK13-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1 1585 // CHECK13-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1 1586 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] 1587 // CHECK13-NEXT: store i32 [[ADD43]], i32* [[J10]], align 4 1588 // CHECK13-NEXT: br label [[SIMD_IF_END]] 1589 // CHECK13: simd.if.end: 1590 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1591 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) 1592 // CHECK13-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1593 // CHECK13-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1594 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 1595 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[RETVAL]], align 4 1596 // CHECK13-NEXT: ret i32 [[TMP30]] 1597 // 1598 // 1599 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1600 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 1601 // CHECK13-NEXT: entry: 1602 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1603 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1604 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 1605 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1606 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1607 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1608 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1609 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 1610 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 1611 // CHECK13-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1612 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1613 // CHECK13-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1614 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1615 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1616 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1617 // CHECK13: omp.inner.for.cond: 1618 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1619 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6 1620 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1621 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1622 // CHECK13: omp.inner.for.body: 1623 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1624 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 1625 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1626 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1627 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6 1628 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1629 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1630 // CHECK13-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 1631 // CHECK13-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 1632 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 1633 // CHECK13-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 1634 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 1635 // CHECK13-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !6 1636 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6 1637 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 1638 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i64 0, i64 [[IDXPROM]] 1639 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !6 1640 // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 1641 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] 1642 // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX7]], align 4, !llvm.access.group !6 1643 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1644 // CHECK13: omp.body.continue: 1645 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1646 // CHECK13: omp.inner.for.inc: 1647 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1648 // CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 1649 // CHECK13-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6 1650 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1651 // CHECK13: omp.inner.for.end: 1652 // CHECK13-NEXT: store i32 10, i32* [[I]], align 4 1653 // CHECK13-NEXT: store i32 2, i32* [[J]], align 4 1654 // CHECK13-NEXT: ret i32 0 1655 // 1656 // 1657 // CHECK15-LABEL: define {{[^@]+}}@main 1658 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]], i8** noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] { 1659 // CHECK15-NEXT: entry: 1660 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1661 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1662 // CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca i8**, align 4 1663 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 1664 // CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4 1665 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1666 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1667 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1668 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 1669 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1670 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1671 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1672 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 1673 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1674 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1675 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 1676 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 1677 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1678 // CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4 1679 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4 1680 // CHECK15-NEXT: store i32 0, i32* [[RETVAL]], align 4 1681 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1682 // CHECK15-NEXT: store i8** [[ARGV]], i8*** [[ARGV_ADDR]], align 4 1683 // CHECK15-NEXT: store i32 100, i32* [[N]], align 4 1684 // CHECK15-NEXT: store i32 2, i32* [[M]], align 4 1685 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 1686 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[M]], align 4 1687 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1688 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1689 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] 1690 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 1691 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 1692 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR1]], align 4 1693 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N]], align 4 1694 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR_]], align 4 1695 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[M]], align 4 1696 // CHECK15-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1697 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1698 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 1699 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 1700 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 1701 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1702 // CHECK15-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0 1703 // CHECK15-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1 1704 // CHECK15-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64 1705 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]] 1706 // CHECK15-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1 1707 // CHECK15-NEXT: store i64 [[SUB7]], i64* [[DOTCAPTURE_EXPR_3]], align 8 1708 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1709 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 1710 // CHECK15-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_UB]], align 8 1711 // CHECK15-NEXT: store i32 0, i32* [[I]], align 4 1712 // CHECK15-NEXT: store i32 0, i32* [[J]], align 4 1713 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1714 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] 1715 // CHECK15-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]] 1716 // CHECK15: land.lhs.true: 1717 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1718 // CHECK15-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]] 1719 // CHECK15-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]] 1720 // CHECK15: simd.if.then: 1721 // CHECK15-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1722 // CHECK15-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 1723 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1724 // CHECK15: omp.inner.for.cond: 1725 // CHECK15-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1726 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !3 1727 // CHECK15-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]] 1728 // CHECK15-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1729 // CHECK15: omp.inner.for.body: 1730 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1731 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1732 // CHECK15-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0 1733 // CHECK15-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1 1734 // CHECK15-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]] 1735 // CHECK15-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64 1736 // CHECK15-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]] 1737 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1 1738 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]] 1739 // CHECK15-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32 1740 // CHECK15-NEXT: store i32 [[CONV18]], i32* [[I9]], align 4, !llvm.access.group !3 1741 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1742 // CHECK15-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1743 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1744 // CHECK15-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0 1745 // CHECK15-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1 1746 // CHECK15-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]] 1747 // CHECK15-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64 1748 // CHECK15-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]] 1749 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group !3 1750 // CHECK15-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0 1751 // CHECK15-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 1752 // CHECK15-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] 1753 // CHECK15-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 1754 // CHECK15-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]] 1755 // CHECK15-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]] 1756 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1 1757 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]] 1758 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32 1759 // CHECK15-NEXT: store i32 [[CONV32]], i32* [[J10]], align 4, !llvm.access.group !3 1760 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[I9]], align 4, !llvm.access.group !3 1761 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]] 1762 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[VLA]], i32 [[TMP21]] 1763 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, i32* [[J10]], align 4, !llvm.access.group !3 1764 // CHECK15-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX]], i32 [[TMP22]] 1765 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX33]], align 4, !llvm.access.group !3 1766 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1767 // CHECK15: omp.body.continue: 1768 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1769 // CHECK15: omp.inner.for.inc: 1770 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1771 // CHECK15-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1 1772 // CHECK15-NEXT: store i64 [[ADD34]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !3 1773 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1774 // CHECK15: omp.inner.for.end: 1775 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1776 // CHECK15-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0 1777 // CHECK15-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1 1778 // CHECK15-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1 1779 // CHECK15-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]] 1780 // CHECK15-NEXT: store i32 [[ADD38]], i32* [[I9]], align 4 1781 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1782 // CHECK15-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0 1783 // CHECK15-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1 1784 // CHECK15-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1 1785 // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] 1786 // CHECK15-NEXT: store i32 [[ADD42]], i32* [[J10]], align 4 1787 // CHECK15-NEXT: br label [[SIMD_IF_END]] 1788 // CHECK15: simd.if.end: 1789 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARGC_ADDR]], align 4 1790 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) 1791 // CHECK15-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1792 // CHECK15-NEXT: [[TMP27:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 1793 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP27]]) 1794 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[RETVAL]], align 4 1795 // CHECK15-NEXT: ret i32 [[TMP28]] 1796 // 1797 // 1798 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ 1799 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { 1800 // CHECK15-NEXT: entry: 1801 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 1802 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4 1803 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 1804 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1805 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1806 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1807 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1808 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 1809 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4 1810 // CHECK15-NEXT: store i32 [[ARGC]], i32* [[ARGC_ADDR]], align 4 1811 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1812 // CHECK15-NEXT: store i32 19, i32* [[DOTOMP_UB]], align 4 1813 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1814 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4 1815 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1816 // CHECK15: omp.inner.for.cond: 1817 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1818 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7 1819 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1820 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1821 // CHECK15: omp.inner.for.body: 1822 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1823 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2 1824 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1825 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1826 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7 1827 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1828 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1829 // CHECK15-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2 1830 // CHECK15-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2 1831 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]] 1832 // CHECK15-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 1833 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] 1834 // CHECK15-NEXT: store i32 [[ADD5]], i32* [[J]], align 4, !llvm.access.group !7 1835 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7 1836 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], [10 x [2 x i32]]* [[A]], i32 0, i32 [[TMP6]] 1837 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group !7 1838 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[ARRAYIDX]], i32 0, i32 [[TMP7]] 1839 // CHECK15-NEXT: store i32 0, i32* [[ARRAYIDX6]], align 4, !llvm.access.group !7 1840 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1841 // CHECK15: omp.body.continue: 1842 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1843 // CHECK15: omp.inner.for.inc: 1844 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1845 // CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1 1846 // CHECK15-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7 1847 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1848 // CHECK15: omp.inner.for.end: 1849 // CHECK15-NEXT: store i32 10, i32* [[I]], align 4 1850 // CHECK15-NEXT: store i32 2, i32* [[J]], align 4 1851 // CHECK15-NEXT: ret i32 0 1852 // 1853